IXDF502PI [IXYS]
2 Ampere Dual Low-Side Ultrafast MOSFET Drivers; 2安培双低侧超快MOSFET驱动器
| 型号： | IXDF502PI |
| 厂家： | 
IXYS CORPORATION |
| 描述： | 2 Ampere Dual Low-Side Ultrafast MOSFET Drivers |
| 文件： | 总12页 (文件大小：409K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IXDF502 / IXDI502 / IXDN502
2 Ampere Dual Low-Side Ultrafast MOSFET Drivers
General Description
Features
• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes
• Latch-Up Protected up to 2 Amps
• High 2A Peak Output Current
• Wide Operating Range: 4.5V to 30V
• -55°Cto+125°CExtendedOperating
Temperature
TheIXDF502,IXDI502andIXDN502eachconsistoftwo2-
AmpCMOShighspeedMOSFETGateDriversfordriving
the latest IXYS MOSFETs & IGBTs. Each of the Dual
Outputs can source and sink 2 Amps of Peak Current while
producing voltage rise and fall times of less than 15ns. The
input of each Driver is TTL or CMOS compatible and is
virtually immune to latch up. Patented* design innovations
eliminate cross conduction and current "shoot-through".
Improvedspeedanddrivecapabilitiesarefurtherenhanced
by very quick & matched rise and fall times.
• High Capacitive Load
DriveCapability:1000pFin<10ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
• LowOutputImpedance
• LowSupplyCurrent
• TwoDriversinSingleChip
TheIXDF502isconfiguredwithoneGateDriverInverting
plusoneGateDriverNon-Inverting.TheIXDI502isconfig-
uredasaDualInvertingGateDriver, andtheIXDN502is
configuredasaDualNon-InvertingGateDriver.
Applications
• DrivingMOSFETsandIGBTs
• MotorControls
• LineDrivers
• PulseGenerators
TheIXDF502,IXDI502andIXDN502areeachavailablein
the 8-Pin P-DIP (PI) package, the 8-Pin SOIC (SIA) pack-
age, and the 6-Lead DFN (D1) package, (which occupies
less than 65% of the board area of the 8-Pin SOIC).
• Local Power ON/OFF Switch
• Switch Mode Power Supplies (SMPS)
• DCtoDCConverters
• PulseTransformerDriver
• Class D Switching Amplifiers
• PowerChargePumps
*United States Patent 6,917,227
Ordering Information
Part Number
Description
Package
Type
PackingStyle
Pack Configuration
Qty
50
IXDF502PI
IXDF502SIA
2ALowSideGateDriver I.C. 8-PinPDIP
2ALowSideGateDriver I.C. 8-PinSOIC
Tube
Tube
Dual, withone
94
Driver Inverting
andoneDriver
Non-Inverting
IXDF502SIAT/R 2ALowSideGateDriver I.C. 8-PinSOIC 13” TapeandReel 2500
IXDF502D1 56
IXDF502D1T/R 2ALowSideGateDriver I.C. 6-LeadDFN 13” TapeandReel 2500
2ALowSideGateDriver I.C. 6-LeadDFN 2” x 2” WafflePack
IXDI502PI
IXDI502SIA
2ALowSideGateDriver I.C. 8-PinPDIP
2ALowSideGateDriver I.C. 8-PinSOIC
IXDI502SIAT/R 2ALowSideGateDriver I.C. 8-PinSOIC
Tube
Tube
50
94
Dual, withboth
Drivers
Inverting
13” TapeandReel 2500
IXDI502D1
2ALowSideGateDriver I.C. 6-LeadDFN 2” x 2” WafflePack 56
2ALowSideGateDriver I.C. 6-LeadDFN 13” TapeandReel 2500
2ALowSideGateDriver I.C. 8-PinPDIP
2ALowSideGateDriver I.C. 8-PinSOIC
IXDI502D1T/R
IXDN502PI
IXDN502SIA
Tube
Tube
50
94
Dual, withboth
DriversNon-
Inverting
IXDN502SIAT/R 2ALowSideGateDriver I.C. 8-PinSOIC 13” TapeandReel 2500
IXDN502D1 56
IXDN502D1T/R 2ALowSideGateDriver I.C. 6-LeadDFN 13” TapeandReel 2500
2ALowSideGateDriver I.C. 6-LeadDFN 2” x 2” WafflePack
NOTE: All parts are lead-free and RoHS Compliant
DS99573B(03/10)
Copyright © 2007 IXYS CORPORATION All rights reserved
First Release
IXDF502 / IXDI502 / IXDN502
Figure 1 - IXDF502 Inverting + Non-Inverting 2A Gate Driver Functional Block Diagram
Vcc
P
ANTI-CROSS
CONDUCTION
CIRCUIT *
IN A
OUT A
*
N
P
N
ANTI-CROSS
CONDUCTION
CIRCUIT *
OUT B
IN B
*
GND
Figure 2 - IXDI502 Dual Inverting 2A Gate Driver Functional Block Diagram
Vcc
P
ANTI-CROSS
CONDUCTION
CIRCUIT *
IN A
OUT A
*
N
P
ANTI-CROSS
CONDUCTION
CIRCUIT *
OUT B
IN B
*
N
GND
Figure 3 - IXDN502 Dual 2A Non-Inverting Gate Driver Functional Block Diagram
Vcc
P
ANTI-CROSS
CONDUCTION
CIRCUIT *
IN A
OUT A
N
P
ANTI-CROSS
CONDUCTION
CIRCUIT *
OUT B
IN B
N
GND
* United States Patent 6,917,227
2
Copyright © 2007 IXYS CORPORATION All rights reserved
IXDF502 / IXDI502 / IXDN502
Operating Ratings (2)
Absolute Maximum Ratings (1)
Parameter
Supply Voltage
AllOtherPins
Value
35V
-0.3 V to VCC + 0.3V
150 °C
Parameter
Value
4.5V to 30V
-55 °C to 125°C
Operating Supply Voltage
OperatingTemperatureRange
PackageThermalResistance*
JunctionTemperature
StorageTemperature
LeadTemperature(10Sec)
-65 °C to 150 °C
300°C
8-PinPDIP
(PI)
θJ-A (typ) 125°C/W
8-PinSOIC
6-LeadDFN
6-LeadDFN
6-LeadDFN
(SIA)
(D1)
(D1)
(D1)
θJ-A(typ) 200°C/W
θJ-A(typ) 125-200°C/W
θJ-C(max) 3.3°C/W
θJ-S(typ) 7.3°C/W
Electrical Characteristics @ TA = 25 oC (3)
Unless otherwise noted, 4.5V ≤ VCC ≤ 30V .
All voltage measurements with respect to GND. IXD_502 configured as described in Test Conditions. All specifications are for one channel.
(4)
Symbol Parameter
Test Conditions
Min
Typ
Max
Units
V
3.0
4.5V ≤ VCC ≤ 18V
4.5V ≤ VCC ≤ 18V
VIH
VIL
VIN
IIN
High input voltage
0.8
VCC + 0.3
10
V
Low input voltage
Input voltage range
Input current
-5
-10
V
0V ≤ VIN ≤ VCC
µA
V
VCC - 0.025
VOH
VOL
High output voltage
Low output voltage
0.025
4
V
High state output
resistance
ROH
ROL
VCC = 15V
2.5
Ω
Ω
Low state output
resistance
VCC = 15V
VCC = 15V
2
2
3
A
A
IPEAK
IDC
Peak output current
Continuous output current
Rise time
1
CLOAD =1000pF VCC =15V
CLOAD =1000pF VCC =15V
CLOAD =1000pF VCC =15V
CLOAD =1000pF VCC =15V
7.5
6.5
25
20
15
10
9
ns
ns
ns
ns
V
tR
tF
Fall time
32
30
30
tONDLY
tOFFDLY
VCC
On-time propagation delay
Off-time propagation delay
Power supply voltage
4.5
VIN = 3.5V
VIN = 0V
VIN = +VCC
1
0
3
15
15
mA
µA
µA
ICC
Power supply current
IXYS reserves the right to change limits, test conditions, and dimensions.
3
IXDF502 / IXDI502 / IXDN502
Electrical Characteristics @ temperatures over -55 oC to 125 oC (3)
Unless otherwise noted, 4.5V ≤ VCC ≤ 30V , Tj < 150oC
All voltage measurements with respect to GND. IXD_502 configured as described in Test Conditions. All specifications are for one channel.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
V
High input voltage
Low input voltage
Input voltage range
Input current
3.1
4.5V ≤ VCC ≤ 15V
4.5V ≤ VCC ≤ 15V
VIH
VIL
VIN
IIN
0.8
VCC + 0.3
10
V
-5
-10
V
0V ≤ VIN ≤ VCC
µA
V
High output voltage
Low output voltage
VCC - 0.025
VOH
VOL
0.025
6
V
High state output
resistance
VCC = 15V
VCC = 15V
ROH
ROL
IDC
Ω
Ω
A
Low state output
resistance
5
1
Continuous output
current
Rise time
CLOAD =1000pF VCC=15V
CLOAD =1000pF VCC =15V
11
10
40
ns
ns
ns
tR
tF
Fall time
On-time propagation
delay
tONDLY
CLOAD =1000pF VCC =15V
CLOAD =1000pF VCC =15V
Off-time propagation
delay
Power supply voltage
38
ns
tOFFDLY
VCC
4.5
15
30
V
VIN = 3.5V
VIN = 0V
VIN = + VCC
1
0
3
40
40
mA
µA
µA
ICC
Power supply current
Notes:
1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanent
damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
2. The device is not intended to be operated outside of the Operating Ratings.
3. Electrical Characteristics provided are associated with the stated Test Conditions.
4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily
to highlight any specific performance limits within which the device is guaranteed to function.
* The following notes are meant to define the conditions for the θJ-A, θJ-C and θJ-S values:
1) TheθJ-A (typ)isdefinedasjunctiontoambient. TheθJ-A ofthestandardsingledie8-LeadPDIPand8-LeadSOICaredominatedbythe
resistanceofthepackage,andtheIXD_5XXaretypical. Thevaluesforthesepackagesarenaturalconvectionvalueswithverticalboards
and the values would be lower with forced convection. For the 6-Lead DFN package, the θJ-A value supposes the DFN package is
soldered on a PCB. The θJ-A (typ) is 200 °C/W with no special provisions on the PCB, but because the center pad provides a low
thermal resistance to the die, it is easy to reduce the θJ-A by adding connected copper pads or traces on the PCB. These can reduce
the θJ-A (typ) to 125 °C/W easily, and potentially even lower. The θJ-A for DFN on PCB without heatsink or thermal management will
vary significantly with size, construction, layout, materials, etc. This typical range tells the user what he is likely to get if he does no
thermalmanagement.
2) θJ-C (max) is defined as juction to case, where case is the large pad on the back of the DFN package. The θJ-C values are generally not
publishedforthePDIPandSOICpackages. TheθJ-CfortheDFNpackagesareimportanttoshowthelowthermalresistancefromjunctionto
thedieattachpadonthebackoftheDFN, --andaguardbandhasbeenaddedtobesafe.
3) TheθJ-S (typ)isdefinedasjunctiontoheatsink,wheretheDFNpackageissolderedtoathermalsubstratethatismountedonaheatsink.
Thevaluemustbetypicalbecausethereareavarietyofthermalsubstrates. ThisvaluewascalculatedbasedoneasilyavailableIMSinthe
U.S.orEurope,andnotapremiumJapaneseIMS. A4mildialectricwithathermalconductivityof2.2W/mCwasassumed. Theresultwas
given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the
DFNpackage.
4
Copyright © 2007 IXYS CORPORATION All rights reserved
IXDF502 / IXDI502 / IXDN502
Pin Description
PIN
PACKAGE
SYMBOL
FUNCTION
DESCRIPTION
2
1
SOIC, DIP
DFN
IN A
A Channel Input
A Channel Input signal-TTL or CMOS compatible.
The system ground pin. Internally connected to all circuitry,
this pin provides ground reference for the entire chip. This pin
should be connected to a low noise analog ground plane for
optimum performance.
3
2
SOIC, DIP
DFN
GND
Ground
4
3
SOIC, DIP
DFN
IN B
B Channel Input
B Channel Input signal-TTL or CMOS compatible.
5
4
SOIC, DIP
DFN
B Channel Driver output. For application purposes, this pin is
connected via a resistor to a gate of a MOSFET/IGBT.
OUT B
B Channel Output
Positive power-supply voltage input. This pin provides power
to the entire chip. The range for this voltage is from 4.5V to
30V.
6
5
SOIC, DIP
DFN
Supply Voltage
V
CC
7
6
SOIC, DIP
DFN
A Channel Driver output. For application purposes, this pin is
connected via a resistor to a gate of a MOSFET/IGBT.
OUT A
A Channel Output
CAUTION: Follow proper ESD procedures when handling and assembling this component.
PinConfiguration
IXDN502
IXDF502
IXDI502
1
2
3
4
NC
OUT A
VS
NC
8
7
6
5
1
2
3
4
NC
OUT A
VS
NC
8
7
6
5
1
2
3
4
NC
OUT A
VS
NC
8
7
6
5
IN A
GND
INB
IN A
GND
INB
IN A
GND
INB
OUT B
OUT B
OUT B
8 Lead PDIP (PI)
8 Pin SOIC (
8 Lead PDIP (PI)
8 Pin SOIC
8 Lead PDIP (PI)
8 Pin SOIC (SI)
(SIA)
(SIA)
(SIA)
6LeadDFN(D1)
(BottomView)
6LeadDFN(D1)
(BottomView)
6LeadDFN(D1)
(BottomView)
6
6
IN A
GND
IN B
6
5
4
OUTA IN A 1
OUTA
Vcc
1
2
IN A 1
OUTA
Vcc
2
5
4
GND
5
4
2
Vcc
GND
IN B 3
3
IN B
3
OUTB
OUTB
OUTB
NOTE: Solder tabs on bottoms of DFN packages are grounded
Figure 4 - Characteristics Test Diagram
Vcc
1
2
3
4
8
7
6
5
NC
NC
In A
Gnd
In B
Out A
Vcc
0.01uF
10uF
Out B
Agilent 1147A
Current Probe
Agilent 1147A
Current Probe
1000 pF
1000 pF
IXYS reserves the right to change limits, test conditions, and dimensions.
5
IXDF502 / IXDI502 / IXDN502
Typical Performance Characteristics
Fig. 6
Fig. 5
Rise Time vs. Supply Voltage
Fall Time vs. Supply Voltage
80
70
70
60
50
40
30
20
10
0
60
50
40
30
20
10
0
10000pF
10000pF
5400pF
5400pF
1000pF
560pF
1000pF
560pF
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Supply Voltage (V)
Supply Voltage (V)
Fig. 7
Fig. 8
Rise / Fall Time vs. Temperature
VSUPPLY = 15V CLOAD = 1000pF
Rise Time vs. Capacitive Load
90
80
70
60
50
40
30
20
10
12
10
8
5V
Rise time
Fall time
10V
15V
20V
6
4
2
0
0
100
1000
10000
-50
0
50
100
150
Load Capacitance (pF)
Temperature (C)
Fig. 10
Fig. 9
Fall Time vs. Capacitive Load
Input Threshold Levels vs. Supply Voltage
70
60
50
40
30
20
10
0
2.5
5V
2
1.5
1
10V
Positive going
15V
20V
Negative going
0.5
0
0
10
20
30
40
100
1000
10000
Supply Voltage (V)
Load Capacitance (pF)
6
Copyright © 2007 IXYS CORPORATION All rights reserved
IXDF502 / IXDI502 / IXDN502
Fig. 12
Fig. 11
Propagation Delay vs. Supply Voltage
Rising Input, CLOAD = 1000pF
Input Threshold Levels vs. Temperature
3
40
35
30
2.5
2
Non-Inverting
25
Positive going input
Negative going input
1.5
1
20
Inverting
15
10
5
0.5
0
0
0
5
10
15
20
25
30
35
40
-50
0
50
100
150
Supply Voltage (V)
Temperature (C)
Fig. 13
Fig. 14
Propagation Delay vs. Supply Voltage
Falling Input, CLOAD = 1000pF
Propagation Delay vs. Temperature
VSUPPLY = 15V CLOAD = 1000pF
45
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
Negative going input
Positve going input
Inverting
Non-Inverting
0
0
-50
0
50
100
150
0
5
10
15
20
25
30
35
40
Temeprature (C)
Supply Voltage (V)
Quiescent current vs Temperature
Vsupply = 15V
Fig. 16
Fig. 15
Quiescent Current vs Supply Voltage
35
30
25
20
15
10
5
90
80
70
60
50
40
30
20
10
inverting input=gnd
non-inverting input=vcc
inverting input=gnd
non-inverting input=vcc
0
0
-55
-25
0
25
50
75
100
125
0V
5V
10V
15V
20V
25V
30V
35V
Temperature (C)
Supply Voltage (V)
7
IXDF502 / IXDI502 / IXDN502
Fig. 18
Fig. 17
SupplyCurrent vs. CapacitiveLoad
VSUPPLY =5V
SupplyCurrent vs. Frequency
VSUPPLY =5V
100
90
80
70
60
50
40
30
20
10
0
100
10000pF
2MHz
90
80
70
60
5400pF
50
40
30
1MHz
20
1000pF
10
560pF
100kHz
0
100
1000
10000
100
1000
10000
Frequency(kHz)
Load Capacitance(pF)
Supply Current vs. Capacitive Load
VSUPPLY = 10V
Fig. 19
Fig. 20
SupplyCurrent vs. Frequency
VSUPPLY = 10V
200
180
160
140
120
100
80
200
10000pF
2MHz
180
160
140
120
100
80
5400pF
1MHz
60
60
40
40
1000pF
560pF
20
20
100kHz
0
0
100
1000
10000
100
1000
10000
Frequency(kHz)
Load Capacitance (pF)
Fig. 21
SupplyCurrent vs. CapacitiveLoad
VSUPPLY =15V
SupplyCurrent vs. Frequency
VSUPPLY =15V
Fig. 22
300
250
200
150
100
50
300
2MHz
10000pF
250
200
150
100
50
5400pF
1MHz
1000pF
560pF
100kHz
0
0
100
1000
10000
100
1000
10000
Load Capacitance(pF)
Frequency(kHz)
8
Copyright © 2007 IXYS CORPORATION All rights reserved
IXDF502 / IXDI502 / IXDN502
Fig. 24
Fig. 23
SupplyCurrent vs. CapacitiveLoad
VSUPPLY =20V
SupplyCurrent vs. Frequency
VSUPPLY=20V
400
400
10000pF
2MHz
1MHz
350
300
250
200
150
100
50
350
300
250
5400pF
200
150
100
1000pF
50
560pF
100kHz
0
0
100
1000
10000
100
1000
10000
LoadCapacitance(pF)
Frequency(kHz)
Fig. 25
Fig. 26
Output Source Current vs. Supply Voltage
Output Sink Current vs. Supply Voltage
7
6
5
4
3
2
1
0
0
-1
-2
-3
-4
-5
-6
-7
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Supply Voltage (V)
Supply Voltage (V)
Output Sink Current vs. Temperature
VSUPPLY = 15V
Output Source Current vs. Temperature
VSUPPLY = 15V
Fig. 28
Fig. 27
3.5
3
0
-0.5
-1
2.5
2
-1.5
-2
1.5
1
-2.5
-3
0.5
0
-3.5
-50
0
50
100
150
-50
0
50
100
150
Temperature (C)
Temperature (C)
9
IXDF502 / IXDI502 / IXDN502
Fig. 30
Fig. 29
Low State Output Resistance vs. Supply Voltage
4.5
High State Output Resistance vs. Supply Voltage
6
4
5
4
3
2
1
0
3.5
3
2.5
2
1.5
1
0.5
0
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
Supply Voltage (V)
Supply Voltage (V)
10
Copyright © 2007 IXYS CORPORATION All rights reserved
IXDF502 / IXDI502 / IXDN502
Supply Bypassing, Grounding Practices And
Output Lead inductance
WhendesigningacircuittodriveahighspeedMOSFETutilizing
theIXD_502,itisveryimportanttoobservecertaindesigncriteria
inordertooptimizeperformanceofthedriver. Particularattention
needs to be paid to Supply Bypassing, Grounding, and
minimizing the Output Lead Inductance.
Say,forexample,weareusingtheIXD_502tochargea1500pF
capacitive load from 0 to 25 volts in 25ns.
Using the formula: I = C ∆V/∆t, where ∆V=25V C=1500pF &
∆t=25ns, we can determine that to charge 1500pF to 25 volts in
25nswilltakeaconstantcurrentof1.5A.(Inreality,thecharging
currentwon’tbeconstant,andwillpeaksomewherearound2A).
SUPPLY BYPASSING
In order for our design to turn the load on properly, the IXD_502
must be able to draw this 1.5A of current from the power supply
inthe25ns. Thismeansthattheremustbeverylowimpedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the power
supply at the driver with a capacitance value that is an order of
magnitudelargerthantheloadcapacitance. Usually,thiswould
beachievedbyplacingtwodifferenttypesofbypassingcapacitors,
withcomplementaryimpedancecurves, veryclosetothedriver
itself.(Thesecapacitorsshouldbecarefullyselectedandshould
have low inductance, low resistance and high-pulse current-
serviceratings). Leadlengthsmayradiateathighfrequencydue
toinductance,socareshouldbetakentokeepthelengthsofthe
leads between these bypass capacitors and the IXD_502 to an
absoluteminimum.
GROUNDING
In order for the design to turn the load off properly, the IXD_502
must be able to drain this 1.5A of current into an adequate
groundingsystem. Therearethreepathsforreturningcurrentthat
need to be considered: Path #1 is between the IXD_502 and its
load. Path#2isbetweentheIXD_502anditspowersupply. Path
#3isbetweentheIXD_502andwhateverlogicisdrivingit. Allthree
of these paths should be as low in resistance and inductance as
possible, and thus as short as practical. In addition, every effort
should be made to keep these three ground paths distinctly
separate. Otherwise, the returning ground current from the load
maydevelopavoltagethatwouldhaveadetrimentaleffectonthe
logiclinedrivingtheIXD_502.
OUTPUT LEAD INDUCTANCE
Of equal importance to Supply Bypassing and Grounding are
issuesrelatedtotheOutputLeadInductance.Everyeffortshould
bemadetokeeptheleadsbetweenthedriveranditsloadasshort
andwideaspossible. Ifthedrivermustbeplacedfartherthan0.2”
(5mm) from the load, then the output leads should be treated as
transmission lines. In this case, a twisted-pair should be
considered, and the return line of each twisted pair should be
placed as close as possible to the ground pin of the driver, and
connected directly to the ground terminal of the load.
11
IXDF502 / IXDI502 / IXDN502
A2
b
b2
b3
c
D
D1
E
E1
e
eA
eB
L
E
H
B
C
D
E
e
D
H
h
A
L
A1
M
N
e
B
h X45
N
L
C
M
0.035 [0.90]
0.137 [3.48]
0.197 0.005 [5.00 0.13]
IXYSCorporation
3540 Bassett St; Santa Clara, CA 95054
Tel:408-982-0700;Fax:408-496-0670
e-mail: sales@ixys.net
www.ixys.com
S0.002^ 0.000;
o
[S0.05^ 0.00;o
]
0.018 [0.47]
0.100 [2.54]
IXYSSemiconductorGmbH
Edisonstrasse15;D-68623;Lampertheim
Tel:+49-6206-503-0;Fax:+49-6206-503627
e-mail:marcom@ixys.de
12
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