IXDI504_技术文档

IXDF504 / IXDI504 / IXDN504

4 Ampere Dual Low-Side Ultrafast MOSFET Drivers

General Description

Features

• Built using the advantages and compatibility

of CMOS and IXYS HDMOS^TMprocesses

• Latch-Up Protected up to 4 Amps

• High Peak Output Current: 4A Peak

• Wide Operating Range: 4.5V to 30V

• -55°Cto+125°CExtendedOperating

Temperature

TheIXDF504,IXDI504andIXDN504eachconsistoftwo4-

AmpCMOShighspeedMOSFETGateDriversfordriving

the latest IXYS MOSFETs & IGBTs. Each of the outputs

can source and sink 4 Amps of Peak Current while produc-

ing voltage rise and fall times of less than 15ns. The input

of each driver is TTL or CMOS compatible and is virtually

immune to latch up. Patented* design innovations eliminate

crossconductionandcurrent"shoot-through".Improved

speedanddrivecapabilitiesarefurtherenhancedbyvery

fast, matched rise and fall times.

• High Capacitive Load

DriveCapability:1800pFin<15ns

• Matched Rise And Fall Times

• Low Propagation Delay Time

• LowOutputImpedance

• LowSupplyCurrent

• TwoDriversinSingleChip

TheIXDF504isconfiguredwithoneGateDriverInverting+

oneGateDriverNon-Inverting.TheIXDI504isconfiguredas

aDualInvertingGateDriver,andtheIXDN504isconfigured

asaDualNon-InvertingGateDriver.

Applications

• DrivingMOSFETsandIGBTs

• MotorControls

• LineDrivers

• PulseGenerators

TheIXDF504,IXDI504andIXDN504areeachavailablein

the 8-Pin P-DIP (PI) package, the 8-Pin SOIC (SIA) pack-

age, and the 6-Lead DFN (D1) package, (which occupies

less than 65% of the board area of the 8-Pin SOIC).

• Local Power ON/OFF Switch

• Switch Mode Power Supplies (SMPS)

• DCtoDCConverters

• PulseTransformerDriver

• Class D Switching Amplifiers

• PowerChargePumps

*United States Patent 6,917,227

Ordering Information

Package

Type

Pack

Qty

50

94

2500

56

2500

50

94

2500

56

2500

50

Part Number

Description

Packing Style

Tube

Configuration

IXDF504PI

IXDF504SIA

IXDF504SIAT/R 4A Low Side Gate Driver I.C.

4A Low Side Gate Driver I.C.

8-Pin PDIP

8-Pin SOIC

6-Lead DFN

8-Pin PDIP

8-Pin SOIC

6-Lead DFN

8-Pin PDIP

8-Pin SOIC

6-Lead DFN

Dual Drivers,

one Inverting

and one Non-

Inverting

Tube

13” Tape and Reel

2” x 2” Waffle Pack

13” Tape and Reel

Tube

IXDF504D1

IXDF504D1T/R

IXDI504PI

IXDI504SIA

IXDI504SIAT/R

IXDI504D1

IXDI504D1T/R

IXDN504PI

IXDN504SIA

4A Low Side Gate Driver I.C.

Tube

Dual Inverting

Drivers

13” Tape and Reel

2” x 2” Waffle Pack

13” Tape and Reel

Tube

Dual Non-

Inverting

Drivers

Tube

94

2500

56

IXDN504SIAT/R 4A Low Side Gate Driver I.C.

IXDN504D1 4A Low Side Gate Driver I.C.

IXDN504D1T/R 4A Low Side Gate Driver I.C.

13” Tape and Reel

2” x 2” Waffle Pack

13” Tape and Reel

2500

NOTE: All parts are lead-free and RoHS Compliant

DS99567A(10/07)

First Release

IXDF504 / IXDI504 / IXDN504

Figure 1 - IXDF504 Inverting + Non-Inverting 4A Gate Driver Functional Block Diagram

Vcc

P

ANTI-CROSS

IN A

OUT A

CONDUCTION

CIRCUIT *

*

N

P

N

ANTI-CROSS

CONDUCTION

OUT B

IN B

CIRCUIT *

*

GND

Figure 2 - IXDI504 Dual Inverting 4A Gate Driver Functional Block Diagram

Vcc

P

ANTI-CROSS

IN A

OUT A

CONDUCTION

CIRCUIT *

*

N

P

ANTI-CROSS

OUT B

IN B

CONDUCTION

CIRCUIT *

*

N

GND

Figure 3 - IXDN504 Dual 4A Non-Inverting Gate Driver Functional Block Diagram

Vcc

P

ANTI-CROSS

IN A

OUT A

CONDUCTION

CIRCUIT *

*

N

P

N

ANTI-CROSS

CONDUCTION

IN B

OUT B

CIRCUIT *

*

GND

* United States Patent 6,917,227

2

IXDF504 / IXDI504 / IXDN504

Operating Ratings ⁽²⁾

Absolute Maximum Ratings ⁽¹⁾

Parameter

Value

Parameter

Value

Supply Voltage

AllOtherPins(Unlessspecified

otherwise)

35 V

Operating Supply Voltage

OperatingTemperatureRange

PackageThermalResistance*

4.5V to 30V

-55 °C to 125°C

-0.3 V to V_CC+ 0.3V

JunctionTemperature

StorageTemperature

LeadTemperature(10Sec)

150 °C

-65 °C to 150 °C

300°C

8-PinPDIP

(PI)

θ

(typ) 125°C/W

8-PinSOIC

6-LeadDFN

(SIA)

(D1)

θ_J^J_-^-A_A(typ) 200°C/W

θ

(typ) 125-200°C/W

θ^J-A(max) 2.1°C/W

θ^J_J^-_-^C_S(typ) 6.4°C/W

Electrical Characteristics @ T_A= 25 ^oC ⁽³⁾

Unless otherwise noted, 4.5V ≤ V_CC≤ 30V .

All voltage measurements with respect to GND. IXD_504 configured as described in Test Conditions. All specifications are for one channel.

(4)

Symbol

V_IH

Parameter

Test Conditions

Min

Typ

Max

Units

4.5V ≤ V_IN≤ 18V

High input voltage

Low input voltage

Input voltage range

Input current

3

V

V_IL

0.8

V_CC+ 0.3

10

V_IN

-5

-10

V

I_IN

0V ≤ V_IN≤ V_CC

µA

V

V_OH

V_OL

High output voltage

Low output voltage

V_CC- 0.025

0.025

2.5

V

V_CC= 18V

R_OH

High state output resistance

1.5

Ω

I

_OUT= 10mA

V_CC= 18V

_OUT= 10mA

R_OL

Low state output resistance

Peak output current

1.2

4

2

1

I

I_PEAK

V_CC= 15V

A

Limited by package

dissipation

I_DC

t_R

Continuous output current

C_LOAD=1000pF

Rise time

9

8

16

14

40

ns

V_CC=18V

C_LOAD=1000pF

t_F

Fall time

V_CC=18V

C_LOAD=1000pF

t_ONDLY

On-time propagation delay

19

18

V_CC=18V

C_LOAD=1000pF

t_OFFDLY

V_CC

Off-time propagation delay

Power supply voltage

35

30

ns

V

V_CC=18V

4.5

18

V_CC= 18V, V_IN= 0V

V_IN= 3.5V

0.25

10

3

10

µA

mA

I_CC

Power supply current

V_IN= V_CC

IXYS reserves the right to change limits, test conditions, and dimensions.

3

IXDF504 / IXDI504 / IXDN504

Electrical Characteristics @ temperatures over -55 ^oC to 125 ^oC ⁽³⁾

Unless otherwise noted, 4.5V ≤ V_CC≤ 30V , Tj < 150^oC

All voltage measurements with respect to GND. IXD_504 configured as described in Test Conditions. All specifications are for one channel.

Symbol

V_IH

Parameter

Test Conditions

Min

Typ

Max

Units

V

High input voltage

Low input voltage

Input voltage range

Input current

3

4.5V ≤ V_CC≤ 18V

V_IL

0.8

V_CC+ 0.3

10

V

V_IN

-5

-10

V

I_IN

0V ≤ V_IN≤ V_CC

µA

V

V_OH

V_OL

R_OH

High output voltage

Low output voltage

V_CC- 0.025

0.025

3

V

High state output

resistance

Low state output

resistance

V_CC= 18V, I_OUT= 10mA

Ω

R_OL

2.5

Ω

I_DC

Continuous output current

1

A

t_R

Rise time

Fall time

C_LOAD=1000pF V_CC=18V

20

15

60

50

30

ns

V

t_F

t_ONDLY

t_OFFDLY

V_CC

I_CC

On-time propagation delay C_LOAD=1000pF V_CC=18V

Off-time propagation delay C_LOAD=1000pF V_CC=18V

Power supply voltage

4.5

18

Power supply current

V_CC= 18V, V_IN= 0V

V_IN= 3.5V

150

3

150

µA

mA

V_IN= V_CC

Notes:

1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanent

damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device

reliability.

2. The device is not intended to be operated outside of the Operating Ratings.

3. Electrical Characteristics provided are associated with the stated Test Conditions.

4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily

to highlight any specific performance limits within which the device is guaranteed to function.

* The following notes are meant to define the conditions for the θ_J-A, θ_J-Cand θ_J-Svalues:

1) Theθ_J-A(typ)isdefinedasjunctiontoambient. Theθ_J-Aofthestandardsingledie8-LeadPDIPand8-LeadSOICaredominatedbythe

resistanceofthepackage,andtheIXD_5XXaretypical. Thevaluesforthesepackagesarenaturalconvectionvalueswithverticalboards

andthevalueswouldbelowerwithforcedconvection. Forthe6-LeadDFNpackage, theθ_J-AvaluesupposestheDFNpackageissoldered

onaPCB. Theθ_J-A(typ)is200°C/W with no special provisions on the PCB, but because the center pad provides a low thermal resistance

to the die, it is easy to reduce the θ_J-Aby adding connected copper pads or traces on the PCB. These can reduce the θ_J-A(typ) to 125 °C/W

easily, andpotentiallyevenlower. The θ_J-AforDFNonPCBwithoutheatsinkorthermalmanagementwillvarysignificantlywithsize,

construction, layout, materials, etc. Thistypicalrangetellstheuserwhatheislikelytogetifhedoesnothermalmanagement.

2) θ_J-C(max) is defined as juction to case, where case is the large pad on the back of the DFN package. The θ_J-Cvalues are generally not

publishedforthePDIPandSOICpackages. Theθ_J-CfortheDFNpackagesareimportanttoshowthelowthermalresistancefromjunctionto

thedieattachpadonthebackoftheDFN, --andaguardbandhasbeenaddedtobesafe.

3) Theθ_J-S(typ)isdefinedasjunctiontoheatsink,wheretheDFNpackageissolderedtoathermalsubstratethatismountedonaheatsink.

Thevaluemustbetypicalbecausethereareavarietyofthermalsubstrates. ThisvaluewascalculatedbasedoneasilyavailableIMSinthe

U.S.orEurope,andnotapremiumJapaneseIMS. A4mildialectricwithathermalconductivityof2.2W/mCwasassumed. Theresultwas

given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the

DFNpackage.

4

IXDF504 / IXDI504 / IXDN504

Pin Description

SYMBOL

FUNCTION

DESCRIPTION

IN A

A Channel Input

Ground

A channel input signal-TTL or CMOS compatible.

The system ground pin. Internally connected to all circuitry, this pin provides

ground reference for the entire device. This pin should be connected to a

low noise analog ground plane for optimum performance.

B channel input signal-TTL or CMOS compatible.

GND

IN B

B Channel Input

B channel driver output. For application purposes, this pin is connected via a

resistor to the gate of a MOSFET/IGBT.

OUT B

B Channel Output

Positive power-supply voltage input. This pin provides power to the entire

device. The range for this voltage is from 4.5V to 30V.

VCC

Supply Voltage

A channel criver output. For application purposes, this pin is connected via a

resistor to the gate of a MOSFET/IGBT.

OUT A

A Channel Output

CAUTION: Follow proper ESD procedures when handling and assembling this component.

PinConfigurations

IXDN504

IXDF504

IXDI504

1

2

3

4

NC

OUT A

V_S

NC

8

7

6

5

1

2

3

4

NC

OUT A

V_S

NC

8

7

6

5

1

2

3

4

NC

OUT A

V_S

NC

8

7

6

5

IN A

GND

INB

IN A

GND

INB

IN A

GND

INB

OUT B

8 Lead PDIP (PI)

(SIA)

8 Pin SOIC (SI)

IXDN402

8 Lead PDIP (PI)

8 Pin SOIC (SI)

8 Lead PDIP (PI)

8 Pin SOIC (SI)

(SIA)

IXDF402

IXDI402

6LeadDFN(D1)

(BottomView)

6LeadDFN(D1)

(BottomView)

6LeadDFN(D1)

(BottomView)

6

IN A

GND

IN B

OUT A

Vcc

6

5

4

OUT A IN A 1

1

IN A 1

OUT A

Vcc

2

3

5

4

GND

IN B

2

3

2

5

4

Vcc

GND

IN B

3

OUT B

NOTE: Solder tabs on bottoms of DFN packages are grounded

Figure 4 - Characteristics Test Diagram

Vcc

IXD_504

1

8

7

6

5

NC

2

3

4

In A

Gnd

In B

Out A

Vcc

0.01uF

10uF

Out B

Agilent 1147A

Current Probe

Agilent 1147A

Current Probe

C_LOAD

IXYS reserves the right to change limits, test conditions, and dimensions.

5

IXDF504 / IXDI504 / IXDN504

Typical Performance Characteristics

Fig. 5

Fig. 6

Rise Times vs. Supply Voltage

Fall Times vs. Supply Voltage

90

80

70

60

50

40

30

20

10

70

60

50

40

30

20

10

0

10000pF

5400pF

10000pF

5400pF

1000pF

100pF

1000pF

100pF

0

5

10

15

20

25

30

35

5

10

15

20

25

30

35

Supply Voltage (V)

Fig. 7

Fig. 8

Rise / Fall Time vs. Temperature

_SUPPLY= 15V C_LOAD= 1000pF

Rise Time vs. Capacitive Load

V

70

60

50

40

30

20

10

0

10

9

8

7

6

5

4

3

2

1

5V

15V

30V

0

-50

-30

-10

10

30

50

70

90

110

130

150

100

1000

10000

Load Capacitance (pF)

Temperature (C)

Fig. 9

Fig. 10

Fall Time vs. Capacitive Load

Input Threshold Levels vs. Supply Voltage

70

2.5

60

50

40

30

20

10

5V

2

1.5

1

Positive going input

15V

30V

Negative going input

0.5

0

100

1000

10000

0

5

10

15

20

25

30

35

Load Capacitance (pF)

Supply Voltage (V)

6

IXDF504 / IXDI504 / IXDN504

Propagation Delay vs. Supply Voltage

Fig. 11

Input Threshold Levels vs. Temperature

Fig. 12

Rising Input, C_LOAD= 1000pF

V_SUPPLY= 15V

3

35

30

25

20

15

10

5

2.5

2

Positive going input

Negative going input

1.5

1

0.5

0

5

10

15

20

25

30

35

-50

0

50

100

150

Temperature (C)

Supply Voltage (V)

Fig. 14

Fig. 13

Propagation Delay vs. Temperature

_SUPPLY= 15V C_LOAD= 1000pF

Propagation Delay vs. Supply Voltage

Falling Input, C_LOAD= 1000pF

V

45

35

40

35

30

25

20

15

10

5

30

25

20

15

10

5

Negative going input

Positve going input

0

5

10

15

20

25

30

35

-50

0

50

100

150

Supply Voltage (V)

Temeprature (C)

Fig. 15

Fig. 16

Quiescent Current vs. Temperature

Quiescent Current vs. Supply Voltage

V_SUPPLY= 15V

V = 0V

IN

1000

100

10

1

0.1

Non-inverting, Input= "0"

Inverting Input = "1"

0.1

0.01

0

5

10

15

20

25

30

35

-50

-30

-10

10

30

50

70

90

110

130

150

Supply Voltage (V)

Temperature (C)

7

IXDF504 / IXDI504 / IXDN504

Fig. 18

Fig. 17

Supply Current vs. Frequency

Supply Current vs. Capacitive Load

_SUPPLY= 5V

V_SUPPLY= 5V

V

100

10

2MHz

1MHz

100

10000pF

5400pF

1000pF

100pF

10

1

100kHz

10kHz

1

0.1

0.01

0.1

0.01

10

100

1000

10000

100

1000

10000

Frequency (kHz)

Load Capacitance (pF)

Fig. 19

Fig. 20

Supply Current vs. Frequency

_SUPPLY= 15V

Supply Current vs. Capacitive Load

V

V_SUPPLY= 15V

1000

100

10

1000

100

10

10000pF

5400pF

2MHz

1MHz

1000pF

100pF

100kHz

10kHz

1

0.1

0.01

10

100

1000

10000

100

1000

10000

Load Capacitance (pF)

Frequency (kHz)

Fig. 22

Fig. 21

Supply Current vs. Capacitive Load

Supply Current vs. Frequency

_SUPPLY= 30V

V_SUPPLY= 30V

V

1000

100

10

10000pF

5400pF

2MHz

1MHz

1000pF

100pF

100

10

1

100kHz

10kHz

1

0.1

10

100

1000

10000

100

1000

10000

Load Capacitance (pF)

Frequency (kHz)

8

IXDF504 / IXDI504 / IXDN504

Fig. 24

Fig. 23

Output Source Current vs. Supply Voltage

Output Sink Current vs. Supply Voltage

12

10

8

0

-2

-4

-6

6

-8

4

-10

-12

-14

2

0

5

10

15

20

25

30

35

0

5

10

15

20

25

30

35

Supply Voltage (V)

Fig. 26

Output Sink Current vs. Temperature

V_SUPPLY= 15V

Fig. 25

Output Source Current vs. Temperature

V_SUPPLY= 15V

0

-1

-2

-3

-4

-5

-6

6

5

4

3

2

1

0

-50

0

50

100

150

-50

0

50

100

150

Temperature (C)

Fig. 28

^{Fig. 27}High State Output Resistance vs. Supply Voltage

Low State Output Resistance vs. Supply Voltage

3

2.5

2

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

5

10

15

20

25

30

35

0

5

10

15

20

25

30

35

Supply Voltage (V)

9

IXDF504 / IXDI504 / IXDN504

Supply Bypassing, Grounding Practices And Output Lead inductance

When designing a circuit to drive a high speed MOSFET

utilizing the IXD_504, it is very important to observe certain

design criteria in order to optimize performance of the driver.

Particular attention needs to be paid to Supply Bypassing,

Grounding, and minimizing the Output Lead Inductance.

Say, forexample, weareusingtheIXD_504tochargea2500pF

capacitive load from 0 to 25 volts in 25ns.

Using the formula: I_C= C (∆V/∆t), where ∆V=25V C=2500pF &

∆t=25ns, we can determine that to charge 2500pF to 25 volts

in 25ns will take a constant current of 2.5A. (In reality, the

charging current won’t be constant and will peak somewhere

around 4A).

SUPPLYBYPASSING

In order for our design to turn the load on properly, the IXD_504

must be able to draw this 2.5A of current from the power supply

in the 25ns. This means that there must be very low impedance

between the driver and the power supply. The most common

method of achieving this low impedance is to bypass the power

supply at the driver with a capacitance value that is an order of

magnitude larger than the load capacitance. Usually, this

would be achieved by placing two different types of bypassing

capacitors, with complementary impedance curves, very close

to the driver itself. (These capacitors should be carefully

selected and should have low inductance, low resistance and

high-pulse current-service ratings). Lead lengths may radiate

at high frequency due to inductance, so care should be taken

to keep the lengths of the leads between these bypass

capacitors and the IXD_504 to an absolute minimum.

GROUNDING

In order for the design to turn the load off properly, the IXD_504

must be able to drain this 2.5A of current into an adequate

grounding system. There are three paths for returning current

that need to be considered: Path #1 is between the IXD_504

and its load. Path #2 is between the IXD_504 and its power

supply. Path #3 is between the IXD_504 and whatever logic is

driving it. All three of these paths should be as low in resistance

and inductance as possible, and thus as short as practical. In

addition, every effort should be made to keep these three

ground paths distinctly separate. Otherwise, the returning

ground current from the load may develop a voltage that would

have a detrimental effect on the logic line driving the IXD_504.

OUTPUTLEADINDUCTANCE

Of equal importance to Supply Bypassing and Grounding are

issues related to the Output Lead Inductance. Every effort

should be made to keep the leads between the driver and its

load as short and wide as possible. If the driver must be placed

farther than 0.2” (5mm) from the load, then the output leads

should be treated as transmission lines. In this case, a twisted-

pair should be considered, and the return line of each twisted

pair should be placed as close as possible to the ground pin

of the driver, and connected directly to the ground terminal of the

load.

10

IXDF504 / IXDI504 / IXDN504

A2

b

b2

b3

c

D

D1

E

E1

e

eA

eB

L

E

H

B

C

D

E

e

H

h

L

M

N

D

A

A1

e

B

h X 45

N

L

C

M

0.035 [0.90]

0.137 [3.48]

0.197±0.005 [5.00±0.13]

IXYS Corporation

3540 Bassett St; Santa Clara, CA 95054

Tel: 408-982-0700; Fax: 408-496-0670

e-mail: sales@ixys.net

www.ixys.com

S0.002^0.000;

o

[S0.05^0.00;o

]

0.018 [0.47]

0.100 [2.54]

IXYS Semiconductor GmbH

Edisonstrasse15 ; D-68623; Lampertheim

Tel: +49-6206-503-0; Fax: +49-6206-503627

e-mail: marcom@ixys.de

11


型号：	IXDI504
厂家：	IXYS CORPORATION
描述：	4 Ampere Dual Low-Side Ultrafast MOSFET Drivers
文件：	总11页 (文件大小：415K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IXDI504 [IXYS]

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