M-8870-01 [IXYS]
DTMF Signaling Circuit, CMOS, PDIP18,;
| 型号： | M-8870-01 |
| 厂家： | 
IXYS CORPORATION |
| 描述： | DTMF Signaling Circuit, CMOS, PDIP18, 电信 光电二极管 电信集成电路 |
| 文件： | 总9页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M-8870
DTMF Receiver
Features
Description
• Low Power Consumption
The M-8870 is a full DTMF Receiver that integrates
both bandsplit filter and decoder functions into a single
18-pin DIP or SOIC package. Manufactured using
CMOS process technology, the M-8870 offers low
power consumption (35 mW max) and precise data
handling. Its filter section uses switched capacitor
technology for both the high and low group filters and
for dial tone rejection. Its decoder uses digital counting
techniques to detect and decode all 16 DTMF tone
pairs into a 4-bit code. External component count is
minimized by provision of an on-chip differential input
amplifier, clock generator, and latched tri-state inter-
face bus. Minimal external components required
include a low-cost 3.579545 MHz color burst crystal, a
timing resistor, and a timing capacitor.
• Adjustable Acquisition and Release Times
• Central Office Quality and Performance
• Power-down and Inhibit Modes (-02 only)
• Inexpensive 3.58 MHz Time Base
• Single 5 Volt Power Supply
• Dial Tone Suppression
Applications
• Telephone switch equipment
• Remote data entry
• Paging systems
• Personal computers
• Credit card systems
The M-8870-02 provides a “power-down” option
which, when enabled, drops consumption to less
than 0.5 mW. The M-8870-02 can also inhibit the
decoding of fourth column digits (see Tone Decoding
table on page 5).
Pin Configuration
Ordering Information
Part #
Description
M-8870-01
18-pin plastic DIP
M-8870-01SM
18-pin plastic SOIC
M-8870-01SMTR 18-pin plastic SOIC, tape and reel
M-8870-02
18-pin plastic DIP, power-down,
option
M-8870-02SM
M-8870-02T
18-pin plastic SOIC, power-down,
option
18-pin plastic SOIC, power-down
option, tape and reel
Block Diagram
DS-M8870-R3
1
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M-8870
Absolute Maximum Ratings
Absolute Maximum Ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at these or
any other conditions beyond those indicated in the opera-
tional sections of this data sheet is not implied. Exposure of
the device to the absolute maximum ratings for an extend-
ed period may degrade the device and effect its reliability.
Parameter
Symbol
Value
Power supply voltage (VDD - VSS)
Voltage on any pin
VDD
VDC
IDD
TA
6.0 V max
VSS -0.3, VDD +0.3
10 mA max
Current on any pin
Operating temperature
-40°C to + 85°C
-65°C to + 150°C
Storage temperature
TS
Note:
Exceeding these ratings may cause permanent damage. Functional operation under
these conditions is not implied.
DC Characteristics
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Operating supply voltage
Operating supply current
Standby supply current (see Note 3)
Power consumption
VDD
IDD
4.75
-
3.0
-
5.25
7.0
100
35
1.5
-
V
mA
µA
mW
V
-
-
-
IDDQ
-
PD=VDD
PO
VIL
-
15
-
f = 3.579 MHz, VDD = 5.0 V
Low level input voltage
-
-
High level input voltage
Input leakage current
VIH
3.5
-
V
-
IIH/IIL
ISO
-
0.1
6.5
10
-
-
µA
µA
mΩ
V
VIN = VSS or VDD (see Note 2)
Pullup (source) current on OE
Input impedance, signal inputs 1, 2
Steering threshold voltage
Low level output voltage
High level output voltage
Output low (sink) current
Output high (source) current
Output voltage VREF
-
15.0
-
OE = 0 V
@ 1 kHz
-
RIN
VTSt
VOL
VOH
IOL
8
2.2
2.5
0.03
-
-
-
V
No load
VDD - 0.03
-
V
No load
1.0
0.4
2.4
-
2.5
0.8
-
-
mA
mA
V
VOUT = 0.4 V
VOUT = VDD - 0.4 V
No load
IOH
-
VREF
ROR
2.7
-
Output resistance VREF
10
kΩ
-
*Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Operating Characteristics - Gain Setting Amplifier
Parameter
Symbol
IN
Min
-
Typ
Max
Units
nA
Test Conditions
Input leakage current
Input resistance
100
-
VSS < VIN < VDD
RIN
4
-
25
-
-
MΩ
mV
dB
-
Input offset voltage
VOS
-
-
-
Power supply rejection
Common mode rejection
DC open loop voltage gain
Open loop unity gain bandwidth
Output voltage swing
Tolerable capacitive load (GS)
Tolerable resistive load (GS)
Common mode range
PSRR
CMRR
AVOL
fC
50
55
60
1.2
3.5
-
-
1 KHz
-
-
-
dB
-3.0V < VIN < 3.0V
-
dB
-
1.5
-
-
MHz
VP-P
pF
-
VO
-
RL ≈ 100 KΩ to VSS
CL
-
100
50
-
-
RL
-
-
kΩ
VP-P
-
VCM
2.5
-
No load
*Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Notes:
1. All voltages referenced to VSS unless otherwise noted. For typical values, VDD = 5.0V, VSS = 0V, TA = 25°C.
Rev. 3
2
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M-8870
Steering Circuit
Functional Description
Before a decoded tone pair is registered, the receiver
checks for a valid signal duration (referred to as char-
acter-recognition-condition). This check is performed
by an external RC time constant driven by ESt. A logic
high on ESt causes VC (see block diagram on page 1)
to rise as the capacitor discharges. Provided that sig-
nal condition is maintained (ESt remains high) for the
M-8870 operating functions (see block diagram on
page 1) include a bandsplit filter that separates the
high and low tones of the received pair, and a digital
decoder that verifies both the frequency and duration
of the received tones before passing the resulting 4-bit
code to the output bus.
validation period (tGTF), VC reaches the threshold (VTSt
)
Filter
of the steering logic to register the tone pair, thus latch-
ing its corresponding 4-bit code (see DC
Characteristics on page 2) into the output latch. At this
The low and high group tones are separated by apply-
ing the dual-tone signal to the inputs of two 6th order
switched capacitor bandpass filters with bandwidths
that correspond to the bands enclosing the low and
high group tones. The filter also incorporates notches
at 350 and 440 Hz, providing excellent dial tone rejec-
tion. Each filter output is followed by a single-order
switched capacitor section that smooths the signals
prior to limiting. Signal limiting is performed by high-
gain comparators provided with hysteresis to prevent
detection of unwanted low-level signals and noise.
The comparator outputs provide full-rail logic swings
at the frequencies of the incoming tones.
point, the GT output is activated and drives VC to VDD
.
GT continues to drive high as long as ESt remains
high. Finally, after a short delay to allow the output
latch to settle, the delayed steering output flag (StD)
goes high, signaling that a received tone pair has been
registered. The contents of the output latch are made
available on the 4-bit output bus by raising the three-
state control input (OE) to a logic high. The steering
circuit works in reverse to validate the interdigit pause
between signals. Thus, as well as rejecting signals too
short to be considered valid, the receiver will tolerate
signal interruptions (dropouts) too short to be consid-
ered a valid pause. This capability, together with the
ability to select the steering time constants externally,
allows the designer to tailor performance to meet a
wide variety of system requirements.
Decoder
The M-8870 decoder uses a digital counting tech-
nique to determine the frequencies of the limited tones
and to verify that they correspond to standard DTMF
frequencies. A complex averaging algorithm is used to
protect against tone simulation by extraneous signals
(such as voice) while tolerating small frequency varia-
tions. The algorithm ensures an optimum combination
of immunity to talkoff and tolerance to interfering sig-
nals (third tones) and noise. When the detector rec-
ognizes the simultaneous presence of two valid tones
(known as signal condition), it raises the Early
Steering flag (ESt). Any subsequent loss of signal
condition will cause ESt to fall.
Single-Ended Input Configuration
Basic Steering Circuit
Rev. 3
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3
M-8870
Pin Functions
Pin
1
Name
IN+
Description
Non-inverting input
Inverting input
Connections to the front-end differential amplifier.
2
IN-
3
GS
Gain select. Gives access to output of front-end amplifier for connection of feedback resistor.
Reference voltage output (nominally VDD/2). May be used to bias the inputs at mid-rail.
4
VREF
5
INH* Inhibits detection of tones representing keys A, B, C, and D.
PD* Power down. Logic high powers down the device and inhibits the oscillator. Internal pulldown.
6
7
OSC1 Clock input
OSC2 Clock output
3.579545 MHz crystal connected between these pins completes the internal oscillator.
8
9
VSS
OE
Negative power supply (normally connected to 0 V).
Tri-statable output enable (input). Logic high enables the outputs Q1 - Q4. Internal pullup.
10
11-14 Q1, Q2, Tri-statable data outputs. When enabled by OE, provides the code corresponding to the last valid tone pair
Q3, Q4 received (see Tone Decoding table on page 5).
15
16
17
StD
Delayed steering output. Presents a logic high when a received tone pair has been registered and the output latch is
updated. Returns to logic low when the voltage on St/GT falls below VTSt.
ESt
Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone pair (signal
condition). Any momentary loss of signal condition will cause ESt to return to a logic low.
St/GT Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the
detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT
output acts to reset the external steering time constant, and its state is a function of ESt and the voltage on St. (See
Common Crystal Connection on page 5).
18
VDD
Positive power supply. (Normally connected to +5V.)
* -02 only. Connect to VSS for -01 version
Guard Time Adjustment
registered. On the other hand, a relatively short tREC
with a long tDO would be appropriate for extremely
noisy environments where fast acquisition time and
immunity to dropouts would be required. Design infor-
mation for guard time adjustment is shown in the
Guard Time Adjustment below.
Where independent selection of signal duration and
interdigit pause are not required, the simple steering
circuit of Basic Steering Circuit is applicable.
Component values are chosenaccording to the formu-
la:
Power-down and Inhibit Mode (-02 only)
tREC = tDP + tGTP
tGTP @ 0.67 RC
A logic high applied to pin 6 (PD) will place the device
into standby mode to minimize power consumption. It
The value of tDP is a parameter of the device and
tREC is the minimum signal duration to be recognized
by the receiver. A value for C of 0.1 µF is recommend-
ed for most applications, leaving R to be selected by
the designer. For example, a suitable value of R for a
tREC of 40 ms would be 300 kΩ. A typical circuit using
this steering configuration is shown in the Single -
Ended Input Configuration on page 4. The timing
requirements for most telecommunication applications
are satisfied with this circuit. Different steering arrange-
ments may be used to select independently the guard
times for tone-present (tGTP) and tone-absent (tGTA).
This may be necessary to meet system specifications
that place both accept and reject limits on both tone
duration and interdigit pause.
Figure 5 Guard Time Adjustment
Guard time adjustment also allows the designer to tai-
lor system parameters such as talkoff and noise immu-
nity. Increasing tREC improves talkoff performance,
since it reduces the probability that tones simulated by
speech will maintain signal condition long enough to be
Rev. 3
4
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M-8870
In a single-ended configuration, the input pins are
connected as shown in the Single - Ended Input
Configuration on page 3 with the op-amp connected
stops the oscillator and the functioning of the filters.
On the M-8870-01 models, this pin is tied to ground
(logic low).
for unity gain and VREF biasing the input at 1/2VDD
The Differential Input Configuration bellow permits
gain adjustment with the feedback resistor R5.
.
Inhibit mode is enabled by a logic high input to pin 5
(INH). It inhibits the detection of 1633 Hz. The output
code will remain the same as the previous detected
code (see Pin functions table on page 4). On the M-
8870-01 models, this pin is tied to ground (logic low).
DTMF Clock Circuit
The internal clock circuit is completed with the addition
of a standard 3.579545 MHz television color burst crys-
tal. The crystal can be connected to a single M-8870 as
shown in the Single - Ended Input Configuration on
page 3, or to a series of M-8870s. As illustrated in the
Common Crystal Connection below, a single crystal
can be used to connect a series of M-8870s by cou-
pling the oscillator output of each M-8870 through a 30
pF capacitor to the oscillator input of the next M-8870.
Input Configuration
The input arrangement of the M-8870 provides a dif-
ferential input operational amplifier as well as a bias
source (VREF) to bias the inputs at mid-rail. Provision
is made for connection of a feedback resistor to the
op-amp output (GS) for gain adjustment.
Tone Decoding
FLOW
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
ANY
FHIGH
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
ANY
Key (ref.)
OE
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
Q4
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
Z
Q3
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
Z
Q2
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
Z
Q1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Z
1
2
3
4
5
6
7
8
9
0
S
#
A
B
C
D
ANY
L = logic low, H = logic high, Z = high impedance
Common Crystal Connection
Differential Input Configuration
Rev. 3
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5
M-8870
AC Characteristics
Parameter
Symbol
Min
Typ*
Max
Units
dBm
mVRMS
dB
Notes
Valid input signal levels (each tone
of composite signal)
-
-
-29
-
+1
1,2,3,4,5,8
27.5
-
869
Positive twist accept
-
-
-
10
2,3,4,8
Negative twist accept
-
-
-
10
dB
Frequency deviation accept limit
Frequency deviation reject limit
Third tone tolerance
-
-
-
1.5% + 2 Hz
Nom.
Nom.
dB
2,3,5,8,10
2,3,5
-
3.5%
-
-
-
-25
-16
-
2,3,4,5,8,9,13,14
2,3,4,5,6,8,9
Noise tolerance
-
-
-12
-
-
dB
Dial tone tolerance
-
+18
+22
dB
2,3,4,5,7,8,9
Tone present detection time
Tone absent detection time
Minimum tone duration accept
Maximum tone duration reject
Minimum interdigit pause accept
Maximum interdigit pause reject
Propagation delay (St to Q)
Propagation delay (St to StD)
Output data setup (Q to StD)
Propagation delay (OE to Q), enable
Propagation delay (OE to Q), disable
Crystal clock frequency
tDP
tDA
tREC
tREC
tID
tDO
tPQ
tPStD
tQStD
tPTE
tPTD
fCLK
CLO
5
8
14
8.5
40
-
ms
See Timing Diagram on page 7
0.5
3
ms
-
-
ms
User adjustable (see Basic Steering
Circuit and Guard Time Adjustment
on pages 3 and 4.)
20
-
ms
-
-
40
-
ms
20
-
6
ms
-
11
16
-
µs
OE = VDD
-
9
µs
-
4.0
50
µs
-
60
-
ns
RL = 10 kΩ, CL = 50 pF
-
3.5759
-
300
3.5795
-
ns
3.5831
30
MHz
pF
-
-
Clock output (OSC2), capacitive load
All voltages referenced to VSS unless otherwise noted. For typical values VDD = 5.0 V, VSS = 0 V, TA = 25°C, fCLK = 3.579545 MHz.
*Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Notes:
1. dBm = decibels above or below a reference power of 1 mW into a 600Ω load.
2. Digit sequence consists of all 16 DTMF tones.
3. Tone duration = 40 ms. Tone pause = 40 ms.
4. Nominal DTMF frequencies are used, measured at GS.
5. Both tones in the composite signal have an equal amplitude.
6. Bandwidth limited (0 to 3 kHz) Gaussian noise.
7. The precise dial tone frequencies are (350 and 440 Hz) 2%.
8. For an error rate of better than 1 in 10,000.
9. Referenced to lowest level frequency component in DTMF signal.
10. Minimum signal acceptance level is measured with specified maximum frequency deviation.
11. Input pins defined as IN+, IN-, and OE.
12. External voltage source used to bias VREF
.
13. This parameter also applies to a third tone injected onto the power supply.
14. Referenced to Single - Ended Input Configuration on page 3. Input DTMF tone level at -28 dBm.
Rev. 3
6
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M-8870
Timing Diagram
Explanation of Events
(A) Tone bursts detected, tone duration invalid, outputs not updated.
(B) Tone #n detected, tone duration valid, tone decoded and latched in outputs.
(C) End of tone #n detected, tone absent duration valid, outputs remain latched until next valid tone.
(D) Outputs switched to high impedance state.
(E) Tone #n + 1 detected, tone duration valid, tone decoded and latched in outputs (currently high impedance).
(F) Acceptable dropout of tone #n + 1, tone absent duration invalid, outputs remain latched.
(G) End of tone #n + 1 detected, tone absent duration valid, outputs remain latched until next valid tone.
Explanation of Symbols
VIN
DTMF composite input signal.
ESt
Early steering output. Indicates detection of valid tone frequencies.
Steering input/guard time output. Drives external RC timing circuit.
4-bit decoded tone output.
St/GT
Q1 - Q4
StD
Delayed steering output. Indicates that valid frequencies have been present/
absent for the required guardtime, thus constituting a valid signal.
OE
tREC
tREC
tID
Output enable (input). A low level shifts Q1 - Q4 to its high impedance state.
Maximum DTMF signal duration not detected as valid.
Minimum DTMF signal duration required for valid recognition.
Minimum time between valid DTMF signals.
tDO
tDP
tDA
Maximum allowable dropout during valid DTMF signal.
Time to detect the presence of valid DTMF signals.
Time to detect the absence of valid DTMF signals.
TGTP
TGTA
Guard time, tone present.
Guard time, tone absent.
Rev. 3
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7
M-8870
Figure 9 Mechanical Dimensions
Tolerances for 18 - pin Dip
Inches
Metric (mm)
Min
-
Max
.210
-
Min
Max
5.33
-
A
A1
b
-
.015
.014
.045
.008
.880
.300
.240
.38
.022
.070
.014
.920
.325
.280
.36
.56
b2
C
1.1
1.7
.20
.36
D
23.35
7.62
6.10
23.37
8.26
7.11
E
E1
e
.100 BSC
2.54 BSC
ec
L
0°
15°
0°
15°
.115
.150
2.92
3.81
Tolerances for 18 - pin Dip
Inches
Metric (mm)
Min
Min
Max
.1043
.0118
.020
Max
2.65
.30
A
A1
b
.0926
.0040
.013
2.35
.10
.33
.51
D
E
.4469
.2914
.4625
.2992
11.35
7.4
11.75
7.6
e
.050 BSC
1.27 BSC
H
L
.394
.016
.419
.050
10.00
.40
10.65
1.27
Dimensions
mm
(inches)
Rev. 3
8
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Specification: DS-M-8870-R3
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