MX8830B [IXYS]
Half Bridge Based MOSFET Driver, PDSO8, MS-012AA, SOIC-8;
| 型号： | MX8830B |
| 厂家： | 
IXYS CORPORATION |
| 描述： | Half Bridge Based MOSFET Driver, PDSO8, MS-012AA, SOIC-8 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总12页 (文件大小：634K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX8830B/MX8830R/MX8830X
Synchronous Buck MOSFET Driver
Features:
General Description
The MX8830 family are 1A Source / 1A Sink
Synchronous Buck MOSFET Drivers. These
Synchronous Buck MOSFET Drivers are specifically
designed to drive two N-channel power MOSFETs
in a synchronous buck converter. The High-Side
driver is powered via a bootstrapped power
connection. The driver is capable of 13ns High-Side
output, and 12ns Low-Side output transition times
driving a 3000pF load.
• Logic Level Gate Drive Compatible
• 1A Source, 1A Sink Peak Drive Current
• Programmable High-Side Driver Turn-on Delay
• Supports Floating Voltage for Top Driver Up to
24V
• MX8830B/MX8803R/MX8830X: Undervoltage
Lockout
• MX8830R/MX8830X: Output Shutdown, Low
Side Shutdown Inputs
The
MX8830B,
MX8830R,
and
MX8830X
incorporate an undervoltage lockout to prevent
unintentional gate drive output during low voltage
conditions. The MX8830R/X include External
Shutdown, and the MX8830X Low-Side Drive
Shutdown features. Simultaneous shutdown of both
outputs prevents rapid output capacitor discharge.
The high-side turn-on delay is adjustable with an
external capacitor added at the DLY pin.
• 10µA Shut Down Current
• 2mA Quiescent Current (Non- Switching)
• Bootstrapped High Side Driver
• Cross-Conduction Protection
Applications:
• Multiphase Desktop CPU Supplies
• Mobile CPU Core Voltage supplies
The MX8830B/MX8830R/MX8830X are designed to
operate over a temperature range of -40°C to
+85°C. The MX8830B is available in an 8-Lead
SOIC, and the MX8830R in a 10-lead DFN.
• High Current / Low Voltage DC/DC
Synchronous Buck Converters
Figure 1. MX8830B Functional Block Diagram Figure 2. MX8830R Functional Block Diagram
and General Application Circuit and General Application Circuit
MX8830
Drawing No. 0883009
1
8/9/07
www.claremicronix.com
MX8830B/MX8830R/MX8830X
Figure 3. MX8830X Functional Block Diagram and General Application Circuit
Ordering Information
Part No.
Description
Package Pack Quantity
Under Voltage Lockout
MX8830B
SOIC-8
SOIC-8
DFN-10
DFN-10
Die
98 (Tube)
2500 (Tape&Reel)
121 (Tube)
2000 (Tape&Reel)
Waffle Pack
Under Voltage Lockout
MX8830BTR
MX8830R10
MX8830R10TR
MX8830X
Under Voltage Lockout , Power Down, External Delay Cap
Under Voltage Lockout , Power Down, External Delay Cap
UVLO , Power Ready, Power Down, Low Side Shutdown, Ext Dly Cap
Absolute Maximum Ratings
Parameter
VDD
Rating
Absolute Maximum Ratings are stress ratings.
Stresses in excess of these ratings can cause
permanent damage to the device. Functional
operation of the device at these or any other
conditions beyond those indicated in the operational
sections of this data sheet is not implied. Exposure
of the device to the absolute maximum ratings for
an extended period may degrade the device and
affect its reliability.
-0.3V to +7V
-0.3V to +30V
-0.3V to +7V
-0.2V to +24V
-0.3V to +7V
-40°C to +85°C
-40°C to +125°C
150°C/W
BST
BST to SW
SW
PWM
Operating Ambient Temp Range
Operating Junction Temp Range
θJA
θJC
40°C/W
Storage Temp Range
-65°C to +150°C
Lead Temperature (Soldering, 10 sec) +300°C
ESD Warning
ESD (electrostatic discharge) sensitive device. Although the MX8830B/MX8830R/MX8830X feature proprietary ESD protection
circuitry, permanent damage may be sustained if subjected to high energy electrostatic discharges. Proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
MX8830
Drawing No. 0883009
2
8/9/07
www.claremicronix.com
MX8830B/MX8830R/MX8830X
Lead / Signal Description and Configurations
MX8830B MX8830R
MX8830X
Name Description
Upper Gate Driver Floating DC Power Terminal for
Bootstrap Capacitor Connection.
1
10
Bonding Pad
BST
Analog Ground
2
3
2
3
Bonding Pad AGND
Three State PWM Input. PWM input to the Gate Drivers.
Bonding Pad
PWM
Positive Supply Terminal for Logic and Lower Gate
Driver. A ceramic bypass capacitor of 1uF should be
connected from VDD to PGND.
4
5
Bonding Pad
VDD
Lower Gate Driver Output Terminal
5
6
7
6
7
8
Bonding Pad
LGD
Lower Gate Driver DC Power Return Terminal
Upper Gate Driver Floating DC Power Return Terminal
Bonding Pad PGND
Bonding Pad
Bonding Pad
SW
Upper Gate Driver Output Terminal
8
9
HGD
Terminal for External Delay Capacitor Connection.
Capacitor to Ground at this pin adds propagation delay
from Lower Gate Driver going Low to the Upper Gate
Driver going High.
N/A
4
Bonding Pad
Bonding Pad
DLY
tDLY (nS) = CDLY (pF) x (0.5nS/pF)
TTL-level Shut Down Input Signal with active pull-up.
__
SD
SD
SD
is low,
enables normal operation when high. When
N/A
1
the driver outputs are forced low and IDD is at its
minimum.
TTL-level Low Side Shut Down Input Signal with active
pull-up. LSD, when low forces the Lower Gate Driver
output low.
When LSD is high, the lower Gate Driver output is
enabled.
___
LSD
N/A
N/A
N/A
N/A
Bonding Pad
Bonding Pad
Power Good Output Terminal. Logic high at this terminal
indicates VDD is above the UVLO Threshold.
PRDY
SOIC and DFN Top View Lead Configurations
MX8830
Drawing No. 0883009
3
8/9/07
www.claremicronix.com
MX8830B/MX8830R/MX8830X
Electrical Characteristics
Power Supply Terminals
TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V
Parameter
Symbol
Conditions
Min Typ Max Unit
Analog Supply
Voltage Range
High Gate Driver
Supply Voltage Range
Low Gate Driver
Supply Voltage Range
Floating Supply
Voltage Range
Analog Supply
Current
VDD
VDD
4.5
4.5
4.5
0.0
5.5
5.5
5.5
24.0
4
V
V
VBST - VSW
VDD - VPGND
VSW - VPGDN
V
V
Normal Mode
PWM = VPGND
IDD
2
mA
mA
High Gate Driver
Supply Current
Normal Mode
PWM = VPGND
IBST
0.5
10
<1
1
Analog Supply
Current
Shut Down Mode, LSD = VDD,
SD = PWM = VPGND
IDD_Shutdown
IBST_Shutdown
µA
µA
High Gate Driver
Supply Current
Shut Down Mode
LSD = PWM = VPGND
10
Digital Input Terminals
Parameter
TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V
Symbol
Conditions
Min
Typ
Max
Unit
___ __
LSD = SD = VDD
Input Leakage Current
IIN
-1
1
µA
Input pull-down Current
2
10
100
µA
µA
__
Input pull-up Current
Input pull-up Current
-2
-10
-100
SD = VPGND
___
LSD = VPGND
-2
-10
-100
µA
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
VIH
VIL
2.0
V
V
0.8
PWM Input
Parameter
(See Timing Diagram)
Symbol
Conditions
Min
Typ
250
-250
3.7
Max
Unit
µA
µA
V
VPWM = 5V
VPWM = 0V
VDD = 5V
VDD = 5V
Input Current
IPWM
PWM Rising Threshold
PWM Falling Threshold
1.3
V
Typical Three-State
Shutdown Window
1.5
3.6
V
MX8830
Drawing No. 0883009
4
8/9/07
www.claremicronix.com
MX8830B/MX8830R/MX8830X
UVLO Circuit
TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V
Parameter
Symbol
UVOLRISE
UVOLFALL
Conditions
Min
4.2
3.9
Typ
4.4
4.25
10
Max
4.5
4.5
Unit
V
V
mA
mA
VDD Rising Threshold
VDD Falling Threshold
PRDY Source Current
PRDY Sink Current
PRDYSOURCE VDD -100mV
PRDYSINK
VSS + 200mV
5
Delay Circuit
Parameter
TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V
Symbol
Conditions
Min
Typ
Max
Unit
Upper Gate-Driver Turn
on Delay Time with
respect to external delay
capacitor
Capacitor CDLY(pF) from DLY
pin to PGND
tDLY
0.5
nS/pF
High Side Gate Driver Circuit
TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
High Side Gate-Driver
On-Resistance, Sourcing RHGD_SRC
Current
VBST – VSW = 4.6V
2.2
Ω
High Side Gate-Driver
On-Resistance, Sinking
Current
RHGD_SNK
VBST – VSW = 4.6V
1.2
20
15
Ω
nS
nS
A
C
LOAD = 3nF
TR_HGD measured from 10% to
90% of (VHGD - VSW
LOAD = 3nF
TF_HGD measured from 90% to
10% of (VHGD - VSW
LOAD = 3nF
TR_HGD measured from 10% to
90% of (VHGD - VSW
LOAD = 3nF
TF_HGD measured from 90% to
10% of (VHGD - VSW
CLOAD_HGD = CLOAD_LGD = 3nF
DLY = 0pF
High Side Gate-Driver(1)
Rise-Time
tR_HGD
13
10
)
C
High Side Gate-Driver(1)
Fall-Time
tF_HGD
)
C
High Side Gate-Driver(1)
Source Current
ISOURCE
ISINK
0.6
0.8
0.9
1.2
)
C
High Side Gate-Driver(1)
Sink Current
A
)
35
50
nS
nS
tPD_HGD1
tPD_HGD2
Propagation Delay(1)
C
MX8830
Drawing No. 0883009
5
8/9/07
www.claremicronix.com
MX8830B/MX8830R/MX8830X
Low Side Gate Driver Circuit
TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Low Side Gate-Driver
On-Resistance, Sourcing RLGD_SRC
Current
VDD – VPGND = 4.6V
2
Ω
Low Side Gate-Driver
On-Resistance, Sinking
Current
RLGD_SNK
VDD – VPGND = 4.6V
1
Ω
nS
nS
A
C
LOAD = 3nF
R_LGD measured from 10% to
90% of (VLGD – VPGND
LOAD = 3nF
TF_LGD measured from 90% to
10% of (VLGD - VSW
LOAD = 3nF
TR_LGD measured from 10% to
90% of (VLGD – VPGND
LOAD = 3nF
TF_LGD measured from 90% to
10% of (VLGD - VSW
LOAD_HGD = CLOAD_LGD = 3nF
CDLY = 0pF
Low Side Gate-Driver(1)
Rise-Time
tR_LGD
T
12
9
18
12
)
C
Low Side Gate-Driver(1)
Fall-Time
tF_LGD
)
C
Low Side Gate-Driver(1)
Source Current
ISOURCE
ISINK
0.67
1.0
1.0
1.3
)
C
Low Side Gate-Driver(1)
Sink Current
A
)
60
20
nS
nS
tPD_LGD1
tPD_LGD2
C
Propagation Delay(1)
Shut Down Circuit Characteristics
TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V
Parameter
Symbol
tPD_LGDSD1
tPD_LGDSD2
tPD_GDSD1
tPD_GDSD2
Tpd_tri1
Conditions
Min
Typ
25
10
400
800
500
500
Max
Unit
nS
nS
nS
nS
Propagation Delay(2)
Propagation Delay(2)
Propagation Delay(3)
Propagation Delay(3)
PWM Tri-State
Turn On Delay
Turn Off Delay
nS
nS
PWM Tri-State
*Notes:
Tpd_tri2
(1) See Timing Diagram in Figure 4
(2) See Timing Diagram in Figure 5
(3) See Timing Diagram in Figure 6
MX8830
Drawing No. 0883009
6
8/9/07
www.claremicronix.com
MX8830B/MX8830R/MX8830X
Figure 4. Non-Overlap Timing Diagram for MX8830B/8830B/8830X
PWM
tpd_lgd2
tf_lgd
10%
tpd_hgd2
tr_lgd
90%
LGD
tpd_lgd1
tr_hgd
90%
tf_hgd
tpd_hgd1
HGD-SW
10%
___
__
Figure 5. LSD Propagation Delay Timing
for MX8830R/X
Figure 6. SD Propagation Delay Timing
for MX8830R/X
LSD
10%
SD
10%
tpd_lgdsd2
tpd_gdsd2
tpd_lgdsd1
LGD
tpd_gdsd1
LGD/HGD
90%
90%
MX8830
Drawing No. 0883009
7
8/9/07
www.claremicronix.com
MX8830B/MX8830R/MX8830X
Package Outlines
SOIC – 8
DFN – 10
(REF.)
TOP VIEW
SIDE VIEW
BOTTOM VIEW
MX8830
Drawing No. 0883009
8
8/9/07
www.claremicronix.com
MX8830B/MX8830R/MX8830X
Theory of Operation
Detailed Circuit Description
(Refer to the Application Diagrams)
The MX8830 family are dual MOSFET drivers,
designed to drive two external N-channel power
MOSFETs. The low-side driver is designed to drive
a non-floating N-channel power MOSFET and its
output is out of phase with the PWM input. The
high-side driver is designed to drive a floating N-
channel power MOSFET and its output is in phase
with the PWM input. An external bootstrap circuit
The PMW input signal controls both the High Side
and Low Side power MOSFET drivers. The Power
MOSFETs are driven so that the SW node follows
the polarity of the PWM signal.
provides the floating power supply to the high-side Low-Side Gate Driver
driver. The Low-Side Gate Driver is designed to drive a
ground referenced N-Channel Power MOSFET. In
The bootstrap circuit consists of a Schottky diode a synchronous buck converter application, it drives
and a boost capacitor. When the PWM input the gate of the synchronous rectifier FET, (Q2).
transitions to a logic low, the low-side power When the driver is enabled, (MX8830R/X
MOSFET turns ON, the SW node is pulled to SD=LSD=VDD), the driver output is 180˚ out of
ground, and the bootstrap capacitor is charged to phase with the PWM input. The internal overlap
VDD through the Schottky diode. When the PWM protection circuit monitors the High-Side Gate
transitions to a logic high, the high side power Driver, and allows the Low-Side Gate Driver to turn
MOSFET begins to turn on and the SW node rises on only when the High-Side Gate Driver output
up to the input supply, VIN. In turn the boost falls below 1.0 Volt. The supply rails for the Low-
capacitor raises the BST node voltage to a level Side Gate Driver are VDD and PGND.
equal to the input supply plus the boost capacitor
voltage, providing sufficient voltage to the BST
node to turn on the High-Side Power MOSFET. An
High-Side Gate Driver
The High-Side Gate Driver is designed to drive a
internal
cross-conduction
prevention
circuit
floating N-Channel Power MOSFET referenced to
SW. In a synchronous buck converter application,
it drives the gate of the high side power MOSFET,
(Q1). When the driver is enabled (MX8830R/X
SD=VDD), the driver output is in phase with the
PWM input. The bootstrap supply rails for the High-
monitors both gate driver outputs and allows each
driver output to turn ON only when the other output
driver turns OFF and falls below 1V.
Three-State PWM Input
A unique feature of these drivers and other Side Gate Driver are BST and SW, and are
Micronix drivers is the addition of a shutdown generated by an external bootstrap circuit. The
window to the PWM input. If the PWM signal bootstrap circuit consists of a Schottky diode
enters and remains within the shutdown window for DBST, and a bootstrap capacitor CBST. During
a set holdoff time, the driver outputs are disabled start up, the SW pin is at ground and the bootstrap
and both MOSFET gates are pulled and held low. capacitor CBST charges up to VDD through the
The shutdown state is removed when the PWM Schottky diode DBST. When the PWM input
signal moves outside the shutdown window. transitions high the High-Side Gate Driver begins
Otherwise, the PWM rising and falling thresholds to turn Q1 ON by transferring charge from the
outlined in the Electrical Specifications determine bootstrap capacitor CBST to the gate of Q1. As Q1
when the lower and upper gates are enabled.
turns on the SW pin will rise up to VIN, forcing the
BST pin to VIN + VBOOSTCAP. This supplies the
This feature helps prevent a negative transient on required gate to source voltage to Q1. When PWM
the output voltage when the output is shut down, transitions low the High-Side Driver and in turn Q1
eliminating the Schottky diode that is used in some switch off. When SW falls below 1 Volt the Low-
systems for protecting the load from reversed Side Gate Driver turns on and recharges the
output voltage events.
bootstrap capacitor which completes the cycle.
MX8830
Drawing No. 0883009
9
8/9/07
www.claremicronix.com
MX883B/MX883R/MX883X
Overlap Protection Circuit
pin low forces the HGD and LGD outputs low, and
reduces the supply current by disabling the internal
reference.
The overlap protection circuit (OPC) monitors the
High Side and Low Side Gate Driver Outputs and
prevents both main power switches, Q1 and Q2,
from being ON at the same time. This inhibits
excessive shoot-through currents and minimizes
the associated losses.
Under Voltage Lockout
The Under Voltage Lockout (UVLO) circuit holds
both driver outputs low during VDD supply ramp-
up. The UVLO logic becomes active and in control
of the driver outputs at a supply voltage of no
greater than 1.5 V. When the supply voltage rises
above the UVLO upper threshold the circuit allows
the PWM input to control the drivers.
When the PWM input transitions low, Q1 begins to
turn OFF, and Q2 turns ON only when the High-
Side Gate Driver output falls below 1 volt. By
waiting for the voltage on the High Side Gate
Driver Output pin to reach 1 volt, the overlap
protection circuit ensures that Q1 is OFF before Q2
turns on.
Application Information
Similarly, when the PWM input transitions high, Q2
begins to turn OFF, and Q1 turns ON after the Supply Capacitor Selection
overlap protection circuit detects that the voltage at A 1 uF ceramic bypass capacitor is recommended
the Low-Side Gate Driver output has dropped for the VDD input to provide noise suppression.
below 1 volt. Once the driver output voltage falls The bypass capacitor should be located as close
below 1 volt, the overlap protection circuit initiates as possible to MX8830.
a delay timer that adds additional delay set by the
external capacitor connected to the DLY pin. This Bootstrap Circuit
programmable delay circuit allows adjustments to The bootstrap circuit requires a charge storage
optimize performance based on the switching capacitor CBST and a Schottky diode DBST, as
characteristics of the external power MOSFET.
shown in Figure 1. Selecting these components
should be done with consideration of the electrical
characteristics of the high-side FET chosen.
Additionally, after PWM input transitions low and if
SW node voltage does not fall below the non-
overlap protection circuit threshold within 100nS,
the low side driver turns ON automatically.
The bootstrap capacitor voltage rating must
exceed the maximum input voltage, (VIN) + the
maximum VDD voltage. The capacitance is
determined using the following equation:
QGATE
Low-Side Driver Shutdown
The MX8830R/X include a Low-Side Gate Driver
shutdown feature. A logic low signal at the LSD
input shuts down the Low Side Gate Driver, and in
turn the synchronous rectifier FET. This signal can
be used to achieve maximum battery life under
light load conditions and maximum efficiency under
heavy load conditions. Under heavy load
conditions, LSD should be high so that the
synchronous switch is controlled by the PWM
signal for maximum efficiency. Under light load
conditions the LSD can be low to disable the Low
Side Gate Driver so the switching current can be
minimized.
CBST
=
∆VBST
Where, QGATE is the total gate charge of Q1, and
∆VBST is the allowable Q1 voltage droop.
To maximize the available drive for Q1 in the
bootstrap circuit a Schottky diode is recommended.
The bootstrap diode voltage rating must exceed
the maximum input voltage, (VIN) + the maximum
VDD voltage. The average forward current can be
estimated by:
IF(AVG) = QGATE X FMAX
Shutdown
where FMAX is the maximum PWM input switching
frequency. Peak surge current is dependent on the
source impedance of the 5V supply and the ESR
of CBST, and should be checked in-circuit.
For optimal system power management, the
MX8830R/X drivers can be shut down to conserve
power. When the SD pin is high, the MX8830R/X
are enabled for normal operation. Pulling the SD
MX8830
Drawing No. 0883009
10
8/9/07
www.claremicronix.com
MX883B/MX883R/MX883X
Delay Capacitor Selection
A ceramic capacitor is recommended for the DLY
input, and should be located as close a possible to
the DLY pin.
Printed Circuit Board Layout Considerations
Use the following general guidelines when
designing printed circuit boards:
1. Trace out the high current paths and use short,
wide traces to make these connections.
2. Locate the VDD bypass capacitor as close as
possible to the VDD and PGND pins.
3. Connect the source of the Lower MOSFET,
(Q2) as close as possible the PGND.
MX8830
Drawing No. 0883009
11
8/9/07
www.claremicronix.com
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IXYS Corporation
United Kingdom
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Eastern Region
[Eastern North America, Mexico, South America]
IXYS Corporation
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Tel: 508-528-6883
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Central Region
[Central North America]
IXYS Corporation
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Check the IXYS Website for the local sales
office nearest you. (www.ixys.com)
Tel: 724-836-8530
Fax: 724-836-8540
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Western Region
[Western North America]
IXYS Corporation
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Tel: 858-792-1101
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European Headquarters
IXYS Semiconductor GMBH
Edisonstrasse 15
D- 68623 Lampertheim
Germany
Micronix cannot assume responsibility for use of any circuitry other than
circuitry entirely embodied in this Micronix product. No circuit patent licenses
nor indemnity are expressed or implied. Micronix reserves the right to change
the specification and circuitry, without notice at any time. The products
described in this document are not intended for use in medical implantation or
other direct life support applications where malfunction may result in direct
physical harm, injury or death to a person.
Tel : 49-6206-503203
Fax: 49-6206-503286
marcom@ixys.de
Specification: MX8830
©Copyright 2007, Micronix, Inc.
All rights reserved. Printed in USA.
MX8830
Drawing No. 0883009
12
8/9/07
www.claremicronix.com
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