PDM31098SA15SOTR [IXYS]
SRAM;
| 型号： | PDM31098SA15SOTR |
| 厂家： | 
IXYS CORPORATION |
| 描述： | SRAM 静态存储器 |
| 文件： | 总8页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
PDM31098
4 Megabit 3.3V Static RAM
1Mx 4-Bit
Features
Description
1
2
■ High-speed access times
Com’l: 8, 10 12, 15, and 20 ns
Ind’l.: 12, 15, 20 ns
■ Low power operation (typical)
- PDM31098SA
Active: 300 mW
Standby: 25 mW
■ Single +3.3V (±0.3V) power supply
■ TTL-compatible inputs and outputs
■ Packages
The PDM31098 is a high-performance CMOS static
RAMs organized as 1,048,576 x 4 bits. Writing is
accomplished when the write enable (WE) and chip
enable CE inputs are both LOW. Reading is
accomplished when WE remains HIGH and OE and
CE are both LOW.
The PDM31098 operates from a single +3.3V power
supply and all the inputs and outputs are fully TTL-
compatible.
3
The PDM31098 is available in a 32-pin 400-mil plas-
tic SOJ package.
Plastic SOJ (400 mil) - SO
4
5
6
Functional Block Diagram
8
A0
•
Decoder
Memory
Matrix
•
•
•
•
•
•
•
•
•
Addresses
•
A19
9
• • • • •
I/O0
Input
Data
Control
Column I/O
•
•
10
11
12
I/O7
•
•
•
CE
WE
OE
Rev. 1.3 - 5/27/98
1
PRELIMINARY
PDM31098
Pin Configuration
SOJ
A0
A1
1
2
3
4
5
6
7
8
32 A19
31 A18
Name
Description
A2
A17
A16
A15
30
29
28
A3
A19-A0
I/O3-I/O0
OE
Address Inputs
A4
CE
I/O0
Vcc
Vss
I/O1
WE
A5
27 OE
Data Inputs/Outputs
Output Enable Input
Write Enable Input
Chip Enable Inputs
No Connect
26
25
I/O3
Vss
9
24 Vcc
WE
10
11
12
13
14
I/O2
A14
A13
A12
A11
A10
NC
23
22
21
20
19
CE
NC
A6
A7
V
Power (+3.3V)
CC
SS
15
16
18
17
A8
V
Ground
A9
(1)
Truth Table
OE
WE
CE
I/O
MODE
X
X
L
X
X
H
L
H
X
L
L
L
Hi-Z
Hi-Z
Standby
Standby
D
Read
OUT
X
H
D
Write
IN
H
Hi-Z
Output Disable
NOTE: 1. H = V , L = V , X = DON’T CARE
IH
IL
(1)
Absolute Maximum Ratings
Symbol
Rating
Com’l.
Ind.
Unit
V
Terminal Voltage with Respect to V
Temperature Under Bias
Storage Temperature
–0.5 to +4.6
–55 to +125
–55 to +125
1.0
–0.5 to +4.6
–65 to +135
–65 to +150
1.0
V
°C
°C
W
TERM
BIAS
STG
SS
T
T
P
Power Dissipation
T
I
DC Output Current
50
50
mA
°C
OUT
(2)
T
Maximum Junction Temperature
125
145
j
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device.This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The cal-
culation should be of the form: T = T + P * θ where T is the ambient temperature, P
j
a
ja
a
is average operating power and θ the thermal resistance of the package. For this
ja
product, use the following θ value:
ja
o
SOJ: 59 C/W
o
TSOP : 90 C/W
2
Rev. 1.3 -5/27/98
PRELIMINARY
PDM31098
DC Electrical Characteristics (V = 3.3V, ± 0.3V)
CC
Symbol
Parameter
Test Conditions
Min.
–5
Max.
Unit
µA
1
2
I
Input Leakage Current
Output Leakage Current
V
= Max., V = V to V
CC
5
5
LI
CC
IN
SS
I
V
= Max.,
–5
µA
LO
CC
CE = V
IH
V
= V to V
OUT
SS CC
(1)
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.3
2.2
—
0.8
Vcc+0.3
0.4
V
V
V
V
IL
IH
V
I
I
= 8 mA, V = Min.
OL CC
OL
OH
3
V
= –4 mA, V = Min.
2.4
—
OH
CC
NOTE:1.V (min) = –3.0V for pulse width less than 20 ns
IL
4
Power Supply Characteristics
-8
-10
-12
-15
-20
5
Symbol Parameter
Operating Current
CE = V
Com’l Com’l Com’l Ind. Com’l Ind. Com’l Ind. Unit
I
190
175
165
175
155
165
145
155
mA
CC
IL
f = f
= 1/t
RC
= Max.
= 0 mA
MAX
6
V
CC
I
OUT
I
Standby Current
CE = V
50
10
45
10
40
10
45
10
35
10
40
15
30
10
35
15
mA
mA
SB
IH
f = f
= 1/t
RC
MAX
V
= Max.
CC
I
Full Standby Current
SB1
CE ≥ V – 0.2V
CC
8
f = 0
V
V
= Max.,
CC
≥ V – 0.2V or ≤ 0.2V
IN
CC
SHADED AREA = PRELIMINARY DATA
NOTES: All values are maximum guaranteed values.
9
10
11
12
(1)
Capacitance (T = +25°C, f = 1.0 MHz)
A
Symbol
Parameter
Max.
Unit
C
Input Capacitance
Output Capacitance
8
8
pF
pF
IN
C
OUT
NOTE:1. This parameter is determined by device characterization but is not production tested.
Rev. 1.3 - 5/27/98
3
PRELIMINARY
PDM31098
AC Test Conditions
Input pulse levels
V
to 3.0V
2.5 ns
1.5V
SS
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
1.5V
See Figures 1 and 2
+3.3V
+3.3V
317Ω
317Ω
DOUT
351Ω
DOUT
351Ω
30 pF
5 pF
Figure 2. Output Load Equivalent
(for TLZCE, tHZCE, tLZWE, tLZOE, tHZOE)
Figure 1. Output Load Equivalent
(4, 5)
Read Cycle No. 1
t
RC
ADDR
t
AA
t
OH
D
PREVIOUS DATA VALID
DATA VALID
OUT
4
Rev. 1.3 -5/27/98
PRELIMINARY
PDM31098
(2, 4, 6)
Read Cycle No. 2
t
RC
1
2
ADDR
t
AA
t
ACE
CE1
t
t
HZCE
LZCE
3
OE
t
t
LZOE
HZOE
D
OUT
DATA VALID
t
4
AOE
5
AC Electrical Characteristics
Description
-8*
-10*
–12
–15
–20
6
READ Cycle
Sym
Min Max Min Max Min Max Min Max Min Max Units
READ cycle time
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
—
—
3
—
8
10
—
—
3
—
10
10
—
—
5
12
—
—
3
—
12
12
—
—
6
15
—
—
3
—
15
15
—
—
7
20
—
—
3
—
20
20
—
—
7
RC
Address access time
t
AA
Chip enable access time
Output hold from address change
t
ACE
8
t
—
—
4
OH
(1,3)
Chip enable to output in low Z
t
t
3
3
3
3
3
LZCE
8
(1,2,3)
Chip disable to output in high Z
Output enable access time
—
—
0
—
—
0
—
—
0
—
—
0
—
—
0
HZCE
t
4
5
6
7
8
AOE
(1,3)
(1,3)
Output Enable to output in low Z
t
—
4
—
4
—
5
—
6
—
7
LZOE
HZOE
9
Output disable to output in high Z
t
—
—
—
—
—
SHADED AREA = PRELIMINARY DATA
* V = 3.3V + 5%
CC
10
11
12
Rev. 1.3 - 5/27/98
5
PRELIMINARY
PDM31098
Write Cycle No. 1 (Write Enable Controlled)
t
WC
ADDR
t
t
AH
AW
CE1
WE
t
AS
t
WP2
t
t
DH
DS
D
IN
DATA VALID
t
HZWE
t
LZWE
HIGH-Z
D
OUT
Write Cycle No. 2 (Write Enable Controlled)
t
WC
ADDR
t
t
AH
AW
t
CW
CE1
WE
t
AS
t
WP1
t
t
DH
DS
D
IN
DATA VALID
HIGH-Z
D
OUT
NOTE: Output Enable (OE) is inactive (high)
6
Rev. 1.3 -5/27/98
PRELIMINARY
PDM31098
Write Cycle No. 3 (Chip Enable Controlled)
t
WC
1
2
ADDR
t
t
AH
AW
t
AS
CE1
WE
t
WP1
3
t
t
DH
DS
D
DATA VALID
IN
4
HIGH-Z
D
OUT
NOTE: Output Enable (OE) is inactive (high)
5
AC Electrical Characteristics
6
Description
-8*
-10*
-12
-15
-20
WRITE Cycle
Sym
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
WRITE cycle time
t
t
8
7
7
—
—
—
10
8
—
—
—
12
10
10
—
—
—
15
11
11
—
—
—
20
13
13
—
—
—
ns
ns
ns
WC
Chip enable to end of write
Address valid to end of write
CW
t
8
AW
Address setup time
t
0
0
7
—
—
—
0
0
8
—
—
—
0
0
8
—
—
—
0
0
9
—
—
—
0
0
—
—
—
ns
ns
ns
AS
8
Address hold from end of write
Write pulse width
t
t
AH
10
WP
Data setup time
Data hold time
t
ns
ns
ns
ns
5
0
—
—
—
4
6
0
—
—
—
5
7
0
—
—
—
6
8
0
—
—
—
7
9
0
—
—
—
9
DS
DH
t
9
(1,3)
Write disable to output in low Z
Write enable to output in high Z
t
t
0
0
0
0
0
LZWE
(1,3)
—
—
—
—
—
HZWE
SHADED AREA = PRELIMINARY DATA
* V = 3.3V + 5%
10
CC
NOTES: (For two previous Electrical Characteristics tables)
1.The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured ±200 mV from steady state 11
voltage.
2.At any given temperature and voltage condition, t
3.This parameter is sampled.
4.WE is high for a READ cycle.
is less than t
.
HZCE
LZCE
5.The device is continuously selected. All the Chip Enables are held in their active state.
6.The address is valid prior to or coincident with the latest occuring Chip Enable.
12
Rev. 1.3 - 5/27/98
7
PRELIMINARY
PDM31098
Ordering Information
XXXXX
X
XX
Speed
X
X
X
Device Type Power
Package
Type
Process
Temp. Range
Preferred
Shipping
Container
Blank Tubes
TR
TY
Tape & Reel
Tray
Blank
I
A
Commercial (0° to +70°C)
Industrial (–40°C to +85°C)
Automotive (–40°C to +105°C)
SO
32-pin 400-mil Plastic SOJ
8/10 Commercial Only
12
15
20
SA
Standard Power
PDM31098 - (1Mx4) Static RAM
Faster Memories for a FasterWorld ™
8
Rev. 1.3 -5/27/98
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