PDM31256SA20SOITY [IXYS]
Standard SRAM, 32KX8, 20ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28;
| 型号： | PDM31256SA20SOITY |
| 厂家： | 
IXYS CORPORATION |
| 描述： | Standard SRAM, 32KX8, 20ns, CMOS, PDSO28, 0.300 INCH, PLASTIC, SOJ-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总7页 (文件大小：227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PDM31256
3.3V 256K Static RAM
32K x 8-Bit
1
2
Description
Features
The PDM31256 is a high-performance CMOS static
RAM organized as 32,768 x 8 bits. Writing to this
device is accomplished when the write enable (WE)
and the chip enable (CE) inputs are both LOW.
Reading is accomplished when WE remains HIGH
and CE and OE are both LOW.
■ High-speed access times
Com’l: 10, 12, 15 and 20ns
Ind’l: 12, 15 and 20ns
■ Low power operation (typical)
- PDM31256SA
3
Active: 200 mW
Standby: 15mW
The PDM31256 operates from a single +3.3V power
supply and all the inputs and outputs are fully TTL-
compatible.
■ Single +3.3V (±0.3V) power supply
■ TTL-compatible inputs and outputs
4
The PDM31256 is available in a 28-pin 300-mil
plastic SOJ and a 28-pin plastic TSOP (I).
■ Packages
5
Plastic SOJ (300 mil) - SO
Plastic TSOP (I) - T
6
Functional Block Diagram
A0
Decoder
Memory
Matrix
•
•
•
•
•
•
•
•
•
Addresses
8
•
•
A14
•
• • • •
I/O0
Input
Column I/O
9
Data
Control
•
•
I/O7
•
•
•
10
11
12
CE
Control
WE
OE
Rev. 3.3 - 4/29/98
1
PDM31256
Pin Configurations
SOJ
Pin Description
TSOP
Vcc
WE
A13
A8
1
A14
A12
A7
28
27
26
25
24
23
Name
Description
2
3
4
5
6
7
8
A10
CE
OE
A11
A9
21
20
19
18
17
16
15
14
13
12
11
10
9
22
23
24
25
26
27
28
1
A14-A0
I/O7-I/O0
OE
Address Inputs
Data Inputs/Outputs
Output Enable Input
Write Enable Input
Chip Enable Input
Power (+3.3V)
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
I/O2
I/O1
I/O0
A0
A6
A8
A13
WE
Vcc
A14
A12
A7
A9
A5
A11
OE
A4
WE
A3
22
21
20
19
18
17
16
15
2
3
A10
CE
CE
A2
A6
4
9
A1
V
CC
SS
A5
5
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
A0
A1
A2
A4
6
V
Ground
A3
8
7
I/O0
I/O1
I/O2
Vss
Truth Table
OE
WE
CE
I/O
MODE
X
L
X
H
L
H
L
L
L
Hi-Z
Standby
Read
D
OUT
X
H
D
Write
IN
H
Hi-Z
Output Disable
NOTE: 1. H = V , L = V , X = DON’T CARE
IH
IL
(1)
Absolute Maximum Ratings
Symbol
Rating
Com’l.
Ind.
Unit
V
Terminal Voltage with Respect to Vss
Temperature Under Bias
Storage Temperature
–0.5 to +4.6
–55 to +125
–55 to +125
1.0
–0.5 to +4.6
–65 to +135
–65 to +150
1.0
V
°C
°C
W
TERM
BIAS
STG
T
T
P
Power Dissipation
T
I
DC Output Current
50
50
mA
°C
OUT
(2)
T
Maximum Junction Temperature
125
145
j
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The
calculation should be of the form: T = T + P * θ where T is the ambient tempera-
j
a
ja
a
ture, P is average operating power and θ the thermal resistance of the package. For
ja
this product, use the following θ values:
ja
o
SOJ: 78 C/W
o
TSOP: 112 C/W
2
Rev. 3.3 - 4/29/98
PDM31256
Recommended DC Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
1
2
V
V
Supply Voltage
3.0
0
3.3
0
3.6
0
V
V
CC
SS
Supply Voltage
Commercial
Industrial
Ambient Temperature
Ambient Temperature
0
25
25
70
85
°C
°C
–40
DC Electrical Characteristics (V = 3.3V ± 0.3V)
3
CC
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
I
Input Leakage Current
V
= MAX., V
–5
5
µA
LI
CC
IN
= Vss to V
CC
4
I
Output Leakage Current
V
= MAX.,
CC
–5
5
µA
LO
CE = V , V
Vss to V
=
IH OUT
CC
(1)
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
–0.3
2.2
—
0.8
Vcc+0.3
0.4
V
V
V
IL
5
IH
OL
V
I
= 8 mA
OL
V
= Min.
CC
V
Output High Voltage
I
V
= –4 mA,
OH
2.4
—
V
OH
6
= Min.
CC
NOTE:1.V (min) = –3.0V for pulse width less than 20 ns.
IL
Power Supply Characteristics
-10
-12
-15
-17
-20
8
Symbol Parameter
Operating Current
CE = V
Com’l. Com’l Ind. Com’l Ind. Com’l Ind. Com’l Ind. Unit
I
140
130
130
120
120
120
120
110
110
mA
CC
IL
f = f
= 1/t
RC
= Max.
= 0 mA
MAX
9
V
CC
I
OUT
I
Standby Current
CE = V
45
10
40
10
35
15
35
10
35
15
35
10
35
15
30
10
30
15
mA
mA
SB
IH
10
11
12
f = f
= 1/t
RC
MAX
V
= Max.
CC
I
Full Standby Current
SB1
CE ≥ V – 0.2V
CC
f = 0
V
V
= Max.,
CC
≥ V – 0.2V or ≤ 0.2V
IN
CC
NOTES: All values are maximum guaranteed values.
Rev. 3.3 - 4/29/98
3
PDM31256
(1)
Capacitance (T = +25°C, f = 1.0 MHz)
A
Symbol
Parameter
Max.
Unit
C
C
Input Capacitance
Output Capacitance
8
8
pF
pF
IN
OUT
NOTE: 1. This parameter is determined by device characterization but is not production
tested.
AC Test Conditions
Input pulse levels
V
to 3.0V
2.5 ns
1.5V
SS
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
1.5V
See Figures 1 and 2
+3.3V
+3.3V
319Ω
319Ω
DATAOUT
353Ω
DATAOUT
353Ω
5 pF
30 pF
Figure 1. Output Load Equivalent
Figure 2. Output Load Equivalent
(for t , t , t , t , t
,
LZCE HZCE LZWE HZWE LZOE
t
)
HZOE
Typical Delta t
AA
vs Capacitive Loading
5
4
3
2
1
0
0
30
60
90
120
Additional Lumped Capacitive Loading (pF)
Figure 3.
4
Rev. 3.3 - 4/29/98
PDM31256
(1)
Read Cycle No. 1
t
RC
1
2
ADDR
t
AA
OH
PREVIOUS DATA VALID
t
D
DATA VALID
OUT
3
(2)
Read Cycle No. 2
t
RC
ADDR
4
t
AA
t
ACE
CE
OE
t
t
HZCE
LZCE
t
t
t
LZOE
HZOE
5
D
OUT
DATA VALID
AOE
6
AC Electrical Characteristics
Description
-10
-12
-15
-17
Max Min
20
-20
Max
READ Cycle
Sym Min. Max. Min. Max. Min. Max. Min
Units
8
READ cycle time
t
10
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
17
RC
Address access time
Chip enable access time
t
10
10
12
12
15
15
17
17
20
20
AA
t
ACE
9
Output hold from address change
t
3
5
3
5
3
5
3
5
3
5
OH
(3,4,5)
Chip enable to output in low Z
Chip disable to output in high Z
t
LZCE
HZCE
(3,4,5)
(4)
t
8
10
10
12
15
10
11
12
Chip enable to power up time
t
0
0
0
0
0
0
0
0
0
0
PU
(4)
Chip disable to power down time
Output enable access time
t
10
5
12
6
15
8
17
9
20
10
PD
t
AOE
(4,5)
Output enable to output in low Z
t
LZOE
HZOE
(4,5)
Output disable to output in high Z
t
8
8
8
8
8
Rev. 3.3 - 4/29/98
5
PDM31256
Write Cycle No. 1 (Write Enable Controlled)
t
WC
ADDR
t
AW
t
t
t
AH
CW
CE
t
t
AS
WP
WE
t
DH
DS
D
IN
DATA VALID
t
t
HZWE
LZWE
HIGH Z
D
OUT
Write Cycle No. 2 (Chip Enable Controlled)
t
WC
ADDR
t
AW
t
t
t
t
AS
CW
AH
CE
WP
UNDEFINED
DON'T CARE
WE
t
t
DS
DATA VALID
DH
D
IN
AC Electrical Characteristics
Description
-10
-12
-15
-17
-20
WRITE Cycle
Sym Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
WRITE cycle time
t
10
10
10
0
12
10
10
0
15
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
17
12
12
0
20
13
13
0
WC
CW
Chip enable to end of write
Address valid to end of write
Address setup time
t
t
AW
t
AS
Address hold from end of write
Write pulse width
t
t
0
0
0
0
0
AH
8
10
7
11
7
11
8
12
9
WP
Data setup time
t
7
DS
DH
Data hold time
t
0
0
0
0
0
(4,5)
(4,5)
Write disable to output in low Z
t
t
0
0
0
0
0
LZWE
Write enable to output in high Z
3
3
3
3
3
HZWE
6
Rev. 3.3 - 4/29/98
PDM31256
NOTES: (For two previous Electrical Characteristics tables)
1. The device is continuously selected. Chip Enable is held in its active state.
2. The address is valid prior to or coincident with the latest occuring Chip Enable.
1
2
3. At any given temperature and voltage condition, t
4. This parameter is sampled.
is less than t
.
HZCE
LZCE
5. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured ±200 mV from steady state voltage.
3
Ordering Information
XXXXX
X
XX
Speed
X
X
X
4
Device Type Power
Package
Type
Process
Temp. Range
Preferred
Shipping
Container
Blank Tubes
TR
TY
Tape & Reel
Tray
5
Blank
I
A
Commercial (0° to +70°C)
Industrial (–40°C to +85°C)
Automotive (–40°C to +105°C)
SO
T
28-pin 300-mil Plastic SOJ
28-pin Plastic TSOP (I)
6
10
12
15
17
20
Commercial Only
Standard Power
SA
PDM31256 - 256K (32Kx8) Sync. Static RAM
8
9
10
11
12
Faster Memories for a FasterWorld ™
Rev. 3.3 - 4/29/98
7
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