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PDM31532LA20TA [IXYS]

Standard SRAM, 64KX16, 20ns, CMOS, PDSO44, PLASTIC, TSOP2-44;
PDM31532LA20TA
型号： PDM31532LA20TA
厂家： IXYS CORPORATION    IXYS CORPORATION
描述：

Standard SRAM, 64KX16, 20ns, CMOS, PDSO44, PLASTIC, TSOP2-44

静态存储器 光电二极管
文件： 总9页 (文件大小：236K)
中文：  中文翻译
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PDM31532  
64K x 16 CMOS  
3.3V Static RAM  
1
2
Features  
Description  
■ High-speed access times  
- Com’l: 9, 10, 12, 15 and 20 ns  
- Ind: 12, 15 and 20 ns  
■ Low power operation (typical)  
- PDM31532LA  
The PDM31532 is a high-performance CMOS static  
RAM organized as 65,536 x 16 bits. The PDM31532  
features low power dissipation using chip enable  
(CE) and has an output enable input (OE) for fast  
memory access. Byte access is supported by upper  
and lower byte controls.  
3
Active: 200 mW  
Standby: 10 mW  
- PDM31532SA  
Active: 250 mW  
The PDM31532 operates from a single 3.3V power  
supply and all inputs and outputs are fully TTL-  
compatible.  
4
Standby: 20 mW  
The PDM31532 is available in a 44-pin 400 mil plas-  
tic SOJ and a plastic TSOP (II) package for high-  
density surface assembly and is suitable for use in  
high-speed applications requiring high-speed  
storage.  
■ High-density 64K x 16 architecture  
■ 3.3V (±0.3V) power supply  
■ Fully static operation  
■ TTL-compatible inputs and outputs  
■ Output buffer controls: OE  
■ Data byte controls: LB, UB  
■ Packages:  
5
6
Plastic SOJ (400 mil) - SO  
Plastic TSOP - T (II)  
Functional Block Diagram  
Vcc  
8
Vss  
Memory  
A8-A0  
Cell  
Array  
256 x 128 x 32  
32K x 32  
9
Data  
Input/  
Output  
Buffer  
I/O15-I/O0  
Sense Amp  
10  
11  
12  
Column  
Decoder  
WE  
OE  
UB  
LB  
Control  
Logic  
Column  
Address  
Buffer  
Clock  
Generator  
CE  
A15-A9  
Rev. 4.3 - 3/27/98  
1
PDM31532  
Pin Configuration  
SOJ  
TSOP (II)  
A4  
1
44  
43  
42  
41  
40  
39  
38  
37  
A5  
A4  
A3  
44  
A5  
1
A3  
2
A6  
43  
42  
41  
40  
39  
38  
37  
2
A6  
A2  
3
A7  
A2  
A7  
3
A1  
4
OE  
A1  
OE  
4
A0  
5
UB  
A0  
UB  
5
CE  
6
LB  
CE  
LB  
6
I/O0  
7
I/O15  
I/O14  
I/O13  
I/O12  
Vss  
Vcc  
I/O11  
I/O10  
I/O9  
I/O8  
NC  
I/O0  
I/O1  
I/O2  
I/O3  
Vcc  
Vss  
I/O4  
I/O15  
I/O14  
7
I/O1  
8
8
I/O2  
9
36  
35  
34  
33  
32  
31  
30  
29  
36 I/O13  
35 I/O12  
9
I/O3  
10  
10  
11  
12  
13  
Vcc  
11  
34  
33  
32  
31  
30  
29  
Vss  
Vcc  
I/O11  
I/O10  
I/O9  
I/O8  
NC  
Vss  
12  
I/O4  
13  
I/O5  
I/O6  
I/O7  
WE  
A15  
A14  
A13  
A12  
NC  
14  
I/O5 14  
15  
16  
17  
18  
I/O6  
15  
I/O7  
16  
28  
27  
26  
25  
24  
23  
WE  
17  
28  
27  
26  
25  
A8  
A15  
A14  
A13  
A12  
NC  
18  
A8  
A9  
19  
20  
21  
22  
A9  
19  
20  
21  
22  
A10  
A11  
NC  
A10  
24 A11  
NC  
23  
Pin Description  
Name  
Description  
A15-A0  
I/O15-I/O0  
CE  
Address Inputs  
Data Inputs  
Chip Enable Input  
Write Enable Input  
Output Enable Input  
Data Byte Control Inputs  
No Connect  
WE  
OE  
LB, UB  
NC  
V
Ground  
ss  
V
Power (+3.3V)  
CC  
(1)  
Capacitance  
(T = +25°C, f = 1.0 MHz)  
A
Symbol  
Parameter  
Conditions  
Max.  
Unit  
C
C
Input Capacitance  
Output Capacitance  
V
= V  
SS  
6
8
pF  
pF  
IN  
IN  
V
= V  
SS  
I/O  
I/O  
NOTE: 1. This parameter is determined by device characterization, but is not production tested.  
2
Rev. 4.3 - 3/27/98  
PDM31532  
Operating Mode  
Mode  
CE  
OE  
WE  
LB  
UB  
I/O7-I/O0  
I/O15-I/O8  
Power  
1
2
Read  
L
L
H
L
H
L
L
L
Output  
High Impedance  
Output  
Output  
Output  
I
I
I
I
I
I
I
I
CC  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
H
L
High Impedance  
Input  
Write  
L
X
L
L
Input  
H
L
L
High Impedance  
Input  
Input  
H
x
High Impedance  
High Impedance  
High Impedance  
High Impedance  
Output Disable  
Standby  
L
L
H
X
X
H
X
X
X
H
X
High Impedance  
High Impedance  
High Impedance  
3
H
X
H
I
SB  
NOTE: H = V , L = V , X = DON’T CARE  
IH  
IL  
4
(2)  
Absolute Maximum Ratings  
5
Symbol  
Rating  
Com’l.  
Ind.  
Unit  
V
Terminal Voltage with Respect to V  
Temperature Under Bias  
Storage Temperature  
–0.5 to +4.6  
–55 to +125  
–55 to +125  
1.5  
–0.5 to +4.6  
–65 to +135  
–65 to +150  
1.5  
V
°C  
°C  
W
TERM  
BIAS  
STG  
SS  
T
T
6
P
Power Dissipation  
T
I
DC Output Current  
50  
50  
mA  
°C  
OUT  
(3)  
T
Maximum Junction Temperature  
125  
145  
j
NOTE: 2. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may  
cause permanent damage to the device. This is a stress rating only and functional  
operation of the device at these or any other conditions above those indicated in the  
operational sections of this specification is not implied. Exposure to absolute maxi-  
mum rating conditions for extended periods may affect reliability.  
8
3. Appropriate thermal calculations should be performed in all cases and specifically for  
those where the chosen package has a large thermal resistance (e.g., TSOP). The  
9
calculation should be of the form: T = T + P * θ where T is the ambient tempera-  
j
a
ja  
a
ture, P is average operating power and θ the thermal resistance of the package. For  
ja  
this product, use the following θ values:  
ja  
o
SOJ: 59 C/W  
TSOP: 87 C/W  
o
10  
11  
12  
Recommended DC Operating Conditions  
Symbol  
Description  
Min.  
Typ.  
Max.  
Unit  
V
V
Supply Voltage  
3.0  
0
3.3  
0
3.6  
0
V
V
CC  
SS  
Supply Voltage  
Industrial  
Ambient Temperature  
Ambient Temperature  
–40  
0
25  
25  
85  
70  
°C  
°C  
Commercial  
Rev. 4.3 - 3/27/98  
3
PDM31532  
DC Electrical Characteristics (V = 3.3V ± 0.3V)  
CC  
Symbol  
Parameter  
Test Conditions  
Min.  
Max.  
Unit  
I
Input Leakage Current  
V
= Max., V = Vss to V  
Com’l/  
Ind.  
–5  
5
µA  
LI  
CC  
IN  
CC  
I
Output Leakage Current  
V
= Max.,  
Com’l/  
Ind.  
–5  
5
µA  
LO  
CC  
CE = V , V  
= Vss to V  
CC  
IH OUT  
(4)  
V
V
Input Low Voltage  
Input High Voltage  
–0.3  
2.2  
0.8  
V
V
IL  
Vcc +  
0.3  
IH  
V
V
Output Low Voltage  
Output High Voltage  
I
I
= 8 mA, V = Min.  
—
0.4  
—
V
V
OL  
OL  
CC  
= –4 mA, V = Min.  
2.4  
OH  
OH  
CC  
NOTE: 4. V (min) = –3.0V for pulse width less than 20 ns.  
IL  
Power Supply Characteristics  
-9  
-10  
-12  
-15  
-20  
Symbol Parameter  
Operating Current  
CE = V  
Com’l Com’l Com’l Ind. Com’l Ind. Com’l Ind. Unit  
I
SA  
LA  
175  
165  
150  
160  
130  
140  
120  
130  
mA  
CC  
IL  
f = f  
= 1/t  
RC  
150  
140  
130  
140  
120  
130  
110  
120  
mA  
MAX  
V
= Max.  
= 0 mA  
CC  
I
OUT  
I
Standby Current  
CE = V  
SA  
LA  
SA  
30  
15  
5
30  
15  
5
30  
15  
5
30  
15  
5
30  
15  
5
30  
15  
5
30  
15  
5
30  
15  
5
mA  
mA  
mA  
SB  
IH  
f = f  
= 1/t  
RC  
MAX  
V
= Max.  
CC  
I
Full Standby  
Current  
SB1  
CE ≥ V – 0.2V  
CC  
f = 0  
LA  
2
2
2
5
2
5
2
5
mA  
V
V
= Max.,  
CC  
≥ V – 0.2V  
IN  
CC  
or ≤ 0.2V  
NOTE:  
All values are maximum guaranteed values.  
4
Rev. 4.3 - 3/27/98  
PDM31532  
AC Test Conditions  
Input pulse levels  
V
to 3.0V  
SS  
1
2
Input rise and fall times  
Input timing reference levels  
Output reference levels  
Output load  
2.5 NS  
1.5V  
1.5V  
See Figures 1 and 2  
3
4
5
+3.3V  
+3.3V  
317Ω  
6
317Ω  
DOUT  
351Ω  
DOUT  
351Ω  
5 pF  
30 pF  
Figure 2. Output Load Equivalent  
(for t , t , t , t  
Figure 1. Output Load  
LZCE HZCE LZWE HZWE,  
8
t
, t  
, t  
, t  
)
LZOE HZOE LZBE HZBE  
9
10  
11  
12  
Rev. 4.3 - 3/27/98  
5
PDM31532  
Read Timing Diagram  
t
RC  
ADDRESSES  
t
AA  
t
t
OH  
ACE  
CE  
OE  
t
(5)  
AOE  
t
HZCE  
t
(5)  
t
BA  
HZOE  
(5)  
UB, LB  
(5)  
t
LZBE  
t
HZBE  
(5)  
t
LZOE  
(5)  
t
LZCE  
D
OUT  
Output Data Valid  
AC Electrical Characteristics  
(7)  
(7)  
Description  
READ Cycle  
-9  
–10  
–12  
–15  
–20  
Symbol Min  
Max Min  
Max Min  
Max Min  
Max Min  
Max Unit  
READ cycle time  
t
9
—
—
—
3
—
9
10  
—
—
—
3
—
10  
10  
6
12  
—
—
—
3
—
12  
12  
7
15  
—
—
—
3
—
15  
15  
8
20  
—
—
—
3
—
20  
20  
9
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address access time  
t
AA  
Chip enable access time  
Byte access time  
t
9
ACE  
t
6
BA  
Output hold from address change  
Byte disable to output in low-Z  
Byte enable to output in high-Z  
t
—
—
7
—
—
7
—
—
8
—
—
9
—
—
9
OH  
t
0
0
0
0
0
LZBE  
HZBE  
t
—
3
—
3
—
3
—
3
—
3
(1, 5)  
Chip enable to output in low-Z  
t
—
6
—
6
—
7
—
8
—
9
LZCE  
HZCE  
(1, 5)  
Chip disable to output high-Z  
t
—
—
0
—
—
0
—
—
0
—
—
0
—
—
0
Output enable access time  
t
6
6
7
8
9
AOE  
(1, 5)  
Output enable to output in low-Z  
t
—
6
—
6
—
7
—
8
—
9
LZOE  
HZOE  
(1, 5)  
Output disable to output in high-Z  
t
—
—
—
—
—
6
Rev. 4.3 - 3/27/98  
PDM31532  
(8)  
Write Cycle 1 Timing Diagram (WE Controlled)  
t
WC  
1
2
ADDRESSES  
t
AW  
t
t
t
AH  
AS  
WP  
WE  
CE  
t
CW  
3
t
BW  
UB, LB  
4
(5)  
(5)  
t
t
LZWE  
HZWE  
High Impedance  
(9)  
(10)  
D
OUT  
t
t
DH  
DS  
5
D
IN  
Data Stable  
6
(8)  
Write Cycle 2 Timing Diagram (CE Controlled)  
t
WC  
8
ADDRESSES  
t
AW  
t
AS  
t
t
AH  
WP  
9
WE  
CE  
t
CW  
10  
11  
12  
t
BW  
UB, LB  
(5)  
(5)  
t
t
HZWE  
LZBE  
(5)  
t
LZCE  
High Impedance  
D
OUT  
t
t
DH  
DS  
D
IN  
Data Stable  
Rev. 4.3 - 3/27/98  
7
PDM31532  
(8)  
Write Cycle 3 Timing Diagram (UB, LB Controlled)  
t
WC  
ADDRESSES  
t
AW  
t
AS  
t
t
AH  
WP  
WE  
CE  
t
CW  
t
BW  
UB, LB  
(5)  
(5)  
t
t
LZCE  
(5)  
HZWE  
t
LZBE  
High Impedance  
D
OUT  
t
t
DH  
DS  
D
IN  
Data Stable  
AC Electrical Characteristics  
Description  
(7)  
(7)  
-9  
-10  
-12  
-15  
-20  
WRITE Cycle  
Sym Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit  
WRITE cycle time  
t
t
9
8
—
—
—
—
—
—
—
—
—
—
7
10  
9
—
—
—
—
—
—
—
—
—
—
7
12  
10  
10  
10  
0
—
—
—
—
—
—
—
—
—
—
7
15  
11  
11  
12  
0
—
—
—
—
—
—
—
—
—
—
8
20  
12  
12  
13  
0
—
—
—
—
—
—
—
—
—
—
9
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
Chip enable to end of write  
Address valid to end of write  
Byte pulse width  
CW  
t
8
9
AW  
t
8
9
BW  
Address setup time  
Address hold from end of write  
Write pulse width  
t
0
0
AS  
AH  
WP  
t
0
0
0
0
0
t
t
7
7
8
9
10  
9
Data setup time  
t
6
6
7
8
DS  
DH  
Data hold time  
0
0
0
0
0
(1, 5, 8)  
Byte disable to output in low Z  
t
1
1
1
1
1
LZBE  
HZBE  
(1, 5, 8)  
Byte enable to output in high Z  
t
—
—
—
—
—
(1, 5, 8)  
Output disable to output in low Z  
t
0
—
7
0
—
7
0
—
7
0
—
8
0
—
9
ns  
ns  
LZOE  
(1, 5, 8)  
Output enable to output in high Z  
t
t
—
—
—
—
—
HZOE  
(1, 5, 8)  
Write disable to output in low Z  
1
—
7
1
—
7
1
—
7
1
—
8
1
—
9
ns  
ns  
LZWE  
HZWE  
(1, 5, 8)  
Write enable to output in high Z  
t
—
—
—
—
—
8
Rev. 4.3 - 3/27/98  
PDM31532  
Notes for AC Tables  
NOTES: 5. Measured with C = 5 pF as in Figure 2. Transition is measured ± 200 mV from steady state voltage  
L
6. At any given temperature and voltage condition, t  
is less than t  
and t  
is less than t  
.
HZCE  
LZCE  
HZWE  
LZWE  
1
2
7. Vcc = 3.3V +5%  
8. If OE is HIGH during a write cycle, the outputs are in a high-impedance state during this period.  
9. If the CE LOW transition occurs coincident with or after the WE LOW transition, outputs remain in a high  
impedance state  
10.If the CE HIGH transition occurs coincident with or after the WE HIGH transition, outputs remain in a high  
impedance state.  
3
4
5
6
Ordering Information  
XXXXX  
X
XX  
X
X
X
Speed  
Device Type Power  
Package  
Type  
Process  
Temp. Range  
Preferred  
Shipping  
Container  
Blank Tubes  
TR  
TY  
Tape & Reel  
Tray  
8
Blank  
I
A
Commercial (0° to +70°C)  
Industrial (–40°C to +85°C)  
Automotive (–40°C to +105°C)  
SO  
T
44-pin 400-mil Plastic SOJ  
44-pin Plastic TSOP (II)  
9
9
Commercial Only  
Commercial Only  
10  
12  
15  
20  
10  
11  
12  
SA  
LA  
Standard Power  
Low Power  
PDM31532 - (64Kx16) Static RAM  
Faster Memories for a FasterWorld ™  
Rev. 4.3 - 3/27/98  
9

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