PDM41256LA12TATY [IXYS]
Standard SRAM, 32KX8, 12ns, CMOS, PDSO28, PLASTIC, TSOP1-28;
| 型号： | PDM41256LA12TATY |
| 厂家： | 
IXYS CORPORATION |
| 描述： | Standard SRAM, 32KX8, 12ns, CMOS, PDSO28, PLASTIC, TSOP1-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总8页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PDM41256
256K Static RAM
32K x 8-Bit
1
2
Description
Features
The PDM41256 is a high-performance CMOS static
RAM organized as 32,768 x 8 bits. Writing to this
device is accomplished when the write enable (WE)
and the chip enable (CE) inputs are both LOW.
Reading is accomplished when WE remains HIGH
and CE and OE are both LOW.
■ High-speed access times
Com’l: 7, 8, 10, 12 and 15ns
Ind’l: 8, 10, 12 and 15ns
(use 15ns for slower designs)
■ Low power operation (typical)
- PDM41256SA
Active: 475 mW
Standby: 100 mW
- PDM41256LA
Active: 425mW
The PDM41256 operates from a single +5V power
supply and all the inputs and outputs are fully TTL-
compatible. The PDM41256 comes in two versions:
the standard power version PDM41256SA and the
low power version PDM41256LA. Both versions are
functionally the same and differ only in their power
consumption.
4
Standby: 25 mW
■ Single +5V (±10%) power supply
■ TTL-compatible inputs and outputs
■ Packages
5
The PDM41256 is available in a 28-pin plastic TSOP
(I) and a 28-pin 300-mil plastic SOJ.
Plastic SOJ (300 mil) - SO
Plastic TSOP (I) - T
6
Functional Block Diagram
7
A
•
0
Decoder
Memory
•
•
•
•
8
•
Addresses
Matrix
•
•
•
•
•
A 14
9
• • • • •
I/O0
Input
Data
Control
Column I/O
•
•
10
11
12
I/O7
•
•
•
CE
WE
OE
Rev. 4.4 - 4/29/98
1
PDM41256
SOJ
Pin Configurations
TSOP (I)
Pin Description
Vcc
WE
A13
A8
1
A14
A12
A7
28
27
26
25
24
23
Name
Description
2
3
4
5
6
7
8
A10
CE
OE
A11
A9
21
20
19
18
17
16
15
14
13
12
11
10
9
22
23
24
25
26
27
28
1
A14-A0
I/O7-I/O0
OE
Address Inputs
Data Inputs/Outputs
Output Enable Input
Write Enable Input
Chip Enable Input
Power (+5V)
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
I/O2
I/O1
I/O0
A0
A6
A8
A13
WE
Vcc
A14
A12
A7
A9
A5
A11
OE
A4
WE
A3
22
21
20
19
18
17
16
15
2
3
A10
CE
CE
A2
A6
4
9
A1
V
CC
SS
A5
5
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
A0
A1
A2
A4
6
V
Ground
A3
8
7
I/O0
I/O1
I/O2
Vss
Truth Table
OE
WE
CE
I/O
MODE
X
L
X
H
L
H
L
L
L
Hi-Z
Standby
Read
D
OUT
X
H
D
Write
IN
H
Hi-Z
Output Disable
NOTE: 1. H = V , L = V , X = DON’T CARE
IH
IL
(1)
Absolute Maximum Ratings
Symbol
Rating
Com’l.
Ind.
Unit
V
Terminal Voltage with Respect to Vss
Temperature Under Bias
Storage Temperature
–0.5 to +7.0
–55 to +125
–55 to +125
1.0
–0.5 to +7.0
–65 to +135
–65 to +150
1.0
V
°C
°C
W
TERM
BIAS
STG
T
T
P
Power Dissipation
T
I
DC Output Current
50
50
mA
°C
OUT
(2)
T
Maximum Junction Temperature
125
145
j
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability.
2. Appropriate thermal calculations should be performed in all cases and specifically for
those where the chosen package has a large thermal resistance (e.g., TSOP). The
calculation should be of the form: T = T + P * θ where T is the ambient tempera-
j
a
ja
a
ture, P is average operating power and θ the thermal resistance of the package. For
ja
this product, use the following θ values:
ja
o
SOJ: 78 C/W
o
TSOP: 112 C/W
2
Rev. 4.4 - 4/29/98
PDM41256
Recommended DC Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
V
Supply Voltage
4.5
0
5.0
0
5.5
0
V
V
CC
1
2
Supply Voltage
SS
Commercial
Industrial
Ambient Temperature
Ambient Temperature
0
25
25
70
85
°C
°C
–40
DC Electrical Characteristics (V = 5.0V ± 10%)
CC
PDM41256SA
PDM41256LA
Unit
Symbol
Parameter
Test Conditions
Min.
Max.
Min.
Max.
4
I
Input Leakage Current
V
= MAX., V = Vss to V
Com’l/
Ind.
–5
5
–1
1
µA
µA
LI
CC
IN
CC
I
Output Leakage Current
V
= MAX.,
Com’l/
Ind.
–5
5
–1
1
LO
CC
CE = V , V
= Vss to V
CC
IH OUT
(1)
(1)
5
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
–0.5
2.2
0.8
6.0
–0.5
2.2
0.8
6.0
V
V
V
IL
IH
OL
V
I
I
=8 mA, V = Min.
—
—
0.4
0.5
—
—
0.4
0.5
OL
OL
CC
= 10 mA, V = Min.
CC
6
V
Output High Voltage
I
= –4 mA, V = Min.
2.4
—
2.4
—
V
OH
OH
CC
NOTE: 1. V (min) = –3.0V for pulse width less than 20 ns.
IL
7
Power Supply Characteristics
-7
-8
-10
-12
-15
8
Symbol Parameter
Power Com’l. Com’l. Ind. Com’l. Ind. Com’l. Ind. Com’l. Ind. Units
I
Operating Current
CE = V
SA
LA
210
190
200
180
210
190
190
170
200
180
170
150
180
160
150
130
160
140
mA
mA
CC
IL
9
f = f
= 1/t
RC
MAX
V
= Max
= 0 mA
CC
I
OUT
I
I
Standby Current
CE = V
SA
LA
SA
LA
90
90
20
5
80
80
20
5
80
80
20
5
70
70
20
5
70
70
20
5
60
60
20
5
60
60
20
5
50
50
20
5
50
50
20
5
mA
mA
mA
mA
SB
10
11
12
IH
f = f
= 1/t
RC
MAX
V
= Max
CC
Full Standby Current
SB1
CE ≥ V – 0.2V
CC
f = 0
V
V
= Max
CC
≥ V – 0.2V or ≤ 0.2V
IN
CC
SHADED AREA = PRELIMINARY DATA
NOTE:All values are maximum guaranteed values.
Rev. 4.4 - 4/29/98
3
PDM41256
(1)
Capacitance (T = +25°C, f = 1.0 MHz)
A
Symbol
Parameter
Max.
Unit
C
C
Input Capacitance
Output Capacitance
8
8
pF
pF
IN
OUT
NOTE: 1. This parameter is determined by device characterization but is not production
tested.
AC Test Conditions
Input pulse levels
V
to 3.0V
3 ns
SS
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
1.5V
1.5V
See Figures 1 and 2
+5V
+5V
480Ω
480Ω
DOUT
255Ω
DOUT
255Ω
5 pF
30 pF
Figure 1. Output Load Equivalent
Figure 2. Output Load Equivalent
(for t , t , t , t , t
,
LZCE HZCE LZWE HZWE LZOE
t
)
HZOE
Typical Delta t
5
vs Capacitive Loading
AA
4
3
2
1
0
0
30
60
90
120
Additional Lumped Capacitive Loading (pF)
Figure 3.
4
Rev. 4.4 - 4/29/98
PDM41256
(1)
Read Cycle No. 1
t
RC
1
2
ADDR
t
AA
OH
PREVIOUS DATA VALID
t
D
DATA VALID
OUT
(2)
Read Cycle No. 2
t
RC
4
ADDR
t
AA
t
ACE
CE
OE
5
t
t
HZCE
LZCE
t
t
t
HZOE
LZOE
6
D
OUT
DATA VALID
AOE
7
AC Electrical Characteristics
Description
(6)
(6)
(6)
--7
--8
-10
-12
-15
8
READ Cycle
Sym Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
READ cycle time
t
7
8
10
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address access time
t
7
7
8
8
10
10
12
12
15
15
AA
9
Chip enable access time
Output hold from address change
t
ACE
t
3
5
3
5
3
5
3
5
3
5
OH
(3, 4, 5)
Chip enable to output in low Z
t
LZCE
HZCE
10
11
12
(3, 4, 5)
Chip disable to output in high Z
t
5
6
6
6
6
(4)
Chip enable to power up time
t
t
0
0
0
0
0
0
0
0
0
0
PU
PD
(4)
Chip disable to power down time
7
5
8
5
10
5
12
6
15
8
Output enable access time
t
AOE
LZOE
HZOE
(4, 5)
Output enable to output in low Z
t
(4, 5)
Output disable to output in high Z
t
5
6
6
6
6
SHADED AREA = PRELIMINARY DATA.
Notes referenced are after Data Retention Table.
Rev. 4.4 - 4/29/98
5
PDM41256
Write Cycle No. 1 (Write Enable Controlled)
t
WC
ADDR
t
AW
t
t
t
AH
CW
CE
t
t
AS
WP
WE
t
DH
DS
D
IN
DATA VALID
t
t
HZWE
LZWE
HIGH Z
D
OUT
Write Cycle No. 2 (Chip Enable Controlled)
t
WC
ADDR
t
AW
t
t
t
t
AS
CW
AH
CE
WP
UNDEFINED
DON'T CARE
WE
t
t
DS
DH
D
DATA VALID
IN
AC Electrical Characteristics
Description
(6)
(6)
(6)
-7
-8
-10
-12
-15
WRITE Cycle
Sym Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
WRITE cycle time
t
7
7
7
0
0
7
6
0
0
8
8
8
0
0
8
7
0
0
10
10
10
0
12
10
10
0
15
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
Chip enable to end of write
Address valid to end of write
Address setup time
t
CW
t
AW
t
AS
AH
WP
Address hold from end of write
Write pulse width
t
0
0
0
t
t
8
8
11
7
Data setup time
t
7
7
DS
Data hold time
0
0
0
DH
(4, 5)
(4, 5)
Write disable to output in low Z
t
0
0
0
LZWE
HZWE
Write enable to output in high Z
t
3
3
3
3
3
SHADED AREA = PRELIMINARY DATA
6
Rev. 4.4 - 4/29/98
PDM41256
Low V Data Retention Waveform
CC
Data Retention Mode
1
2
V
4.5V
4.5V
CC
V
DR
t
t
CDR
R
V
V
DR
IH
CE
V
IL
DON'T CARE
4
5
Data Retention Electrical Characteristics (LA Version Only)
Symbol Parameter
for Retention Data
Test Conditions
Min.
Typ.
Max.
Unit
6
V
V
2
—
95
—
V
DR
CC
I
Data Retention Current
CE ≥ V – 0.2V
V
V
= 2V
= 3V
—
—
500
750
µA
µA
CCDR
CC
CC
V
≥ V – 0.2V
IN
CC
or ≤ 0.2V
350
CC
7
t
Chip Deselect to Data Retention Time
Operation Recovery Time
0
—
—
—
—
ns
ns
CDR
(4)
t
t
RC
R
NOTES: (For three previous Electrical Characteristics tables)
1. The device is continuously selected. Chip Enable is held in its active state.
2. The address is valid prior to or coincident with the latest occuring Chip Enable.
8
3. At any given temperature and voltage condition, t
4. This parameter is sampled.
is less than t
.
HZCE
LZCE
5. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured ±200 mV from steady state voltage
6. Vcc = 5V ± 5%.
9
10
11
12
Rev. 4.4 - 4/29/98
7
PDM41256
Ordering Information
XXXXX
X
XX
X
X
X
Speed
Device Type Power
Package
Type
Process
Temp. Range
Preferred
Shipping
Container
Blank Tubes
TR
TY
Tape & Reel
Tray
Blank
Commercial (0° to +70°C)
Industrial (–40°C to +85°C)
I
A
Automotive (–40°C to +105°C)
SO
T
28-pin 300-mil Plastic SOJ
28-pin Plastic TSOP (I)
Commercial Only
7
8
10
12
15
(use 15ns for slower designs)
SA
LA
Standard Power
Low Power
PDM41256- 256K (32Kx8) Static RAM
Faster Memories for a Faster World ™
8
Rev. 4.4 - 4/29/98
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