PDM4M3120S15M [IXYS]
SRAM Module, 1MX32, 15ns, CMOS, SIMM-72;
| 型号： | PDM4M3120S15M |
| 厂家： | 
IXYS CORPORATION |
| 描述： | SRAM Module, 1MX32, 15ns, CMOS, SIMM-72 静态存储器 |
| 文件： | 总10页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
PDM4M3120
3.3V, 1M x 32 CMOS
Static RAM Module
1
The PDM4M3120 is packaged in a 72-pin FR-4 ZIP
(Zig-zag In-line vertical Package) or a 72-pin SIMM or
Angled SIMM (Single In-line Memory Module). The
Features
■ High-density 3.3V, 4 megabyte Static RAM
module
■ Low profile 72-pin ZIP (Zig-zag In-line vertical
Package) or 72-pin SIMM or Angled SIMM
(Single In-line Memory Module)
■ Fast access time: 12 ns (max.)
■ Surface mounted plastic components on an
epoxy laminate (FR-4) substrate.
■ Single 3.3V (±10%) power supply
■ Multiple V pins and decoupling capacitors for
maximum noise immunity
■ Inputs/ outputs directly TTL compatible
ZIP configuration allows 72 pins to be placed on a 2
package 3.950" long and 0.365" wide. At only 0.590"
high, this low-profile package is ideal for systems
with minimum board spacing. The SIMM configura-
tion allows use of edge mounted sockets to secure the 3
module.
All inputs and outputs of the PDM4M3120 are TTL
compatible and operate from a single 3.3V supply.
Full asynchronous circuitry requires no clock or
refresh for operation and provides equal access and
cycle times for ease of use.
SS
4
Four identification pins (PD0, PD1, PD2, PD3) are pro-
vided for applications in which different density
versions of the module are used. In this way, the tar-
5
Description
The PDM4M3120 is a 3.3V, 1M x 32 static RAM
module constructed on an epoxy laminate (FR-4)
substrate using eight 1M x 4 static RAMs in plastic
SOJ packages. Availability of four chip select lines
(one for each of four RAMs) provides byte access.
The PDM4M3120 is available with access times as
fast as 12 ns with minimal power consumption.
get system can read the respective levels of PD0, PD1, 6
PD2, PD3 to determine a 1M depth.
7
9
Functional Block Diagram
CS1
CS2
CS3
CS4
20
ADDRESS
WE
4
10
11
12
PD3-PD0
1M x 32
RAM
OE
8
8
8
8
I/O31-I/O0
Rev 1.1
1
PRELIMINARY
PDM4M3120
Pin Configuration(1)
Pin Assignment
Pin
Signal
1
3
NC
PD0 - Vss
I/O31-I/O0
A19-A0
CS4-CS1
WE
Data Inputs/Outputs
Addresses
2
NC
PD3
PD0
I/O0
I/O1
I/O2
I/O3
Vcc
A7
PD2
Vss
PD1 - NC
PD2 - Vss
PD3 - NC
4
5
Chip Selects
Write Enable
Output Enable
Depth Identification
Power
6
7
PD1
I/O8
I/O9
I/O10
I/O11
A0
8
9
OE
10
12
14
16
18
20
22
24
26
28
30
32
34
36
11
13
15
17
19
21
23
25
27
29
31
33
35
PD3-PD0
V
V
CC
SS
Ground
A1
A8
A2
A9
I/O12
I/O13
I/O14
I/O15
Vss
I/O4
I/O5
I/O6
I/O7
WE
A15
CS2
A14
CS1
ZIP, SIMM
TOP VIEW
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
CS4
A17
OE
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
CS3
A16
Vss
I/O24
I/O25
I/O26
I/O27
A3
I/O16
I/O17
I/O18
I/O19
A10
A4
A11
A5
A12
Vcc
A13
A6
I/O20
I/O21
I/O22
I/O23
Vss
I/O28
I/O29
I/O30
I/O31
A18
NC
A19
NC
NOTE: 1. Pins 3, 4, 6, and 7 (PD0, PD1, PD02, and PD3
respectively) are read by the user to determine the
density of the module. If PD0 reads V , PD1 reads
SS
NC, PD2 reads V , PD3 reads NC then the mod-
SS
ule has a 1M depth.
2
Rev 1.1
PRELIMINARY
PDM4M3120
Truth Table
CS
OE
WE
Mode
Output
Power
1
2
Deselect/
Power-down
H
X
X
High-Z
Standby
Read
L
L
L
L
X
H
H
L
DATA
Active
Active
Active
OUT
Write
DATA
IN
Deselect
H
High-Z
3
Absolute Maximum Ratings(1)
4
Symbol
Rating
Terminal Voltage with Respect to V
Com’l.
Ind.
Unit
V
–0.5 to +4.6
–10 to +85
–55 to +125
0 to +70
1.0
–0.5 to +4.6
–10 to +85
–65 to +150
–40 to +85
1.0
V
TERM
SS
T
Temperature Under Bias
Storage Temperature
Operating Temperature
Power Dissipation
°C
°C
°C
W
BIAS
5
T
STG
T
A
P
T
6
I
DC Output Current
50
50
mA
OUT
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device.This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
7
Recommended DC Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
9
V
V
Supply Voltage
3.0
0
3.3
0
3.6
0
V
CC
Supply Voltage
V
SS
Commercial
Industrial
Ambient Temperature
Ambient Temperature
0
25
25
70
85
°C
°C
10
11
12
–40
Rev 1.1
3
PRELIMINARY
PDM4M3120
DC Electrical Characteristics (V = 3.3V ± 10%, T = 0°C to 70°C)
CC
A
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
I
I
I
Input Leakage Current
(Address)
V
V
V
= Max.,V = V to V
CC
—
80
µA
LI
CC
IN
SS
Input Leakage Current
(Data)
= Max., V = V to V
CC
—
—
10
10
µA
µA
LI
CC
IN
SS
Output Leakage Current
= V to V , V = Max.,
SS CC CC
LO
OUT
CS = V
IH
V
V
V
V
Output Low Voltage
Output High Voltage
Input High Voltage
Input Low Voltage
I
I
= 8 mA, V = Min.
—
2.4
2.2
0.4
—
V
V
V
V
OL
OH
IH
OL
OL
CC
= –4 mA, V = Min.
CC
6.0
0.8
(1)
–0.5
IL
NOTE 1.
V = –1.5V for pulse widths less than 10 ns, once per cycle.
IL
Power Supply Characteristics
(1)
Symbol
Parameter
Max
Unit
I
I
I
Operating Current
900
200
85
mA
CC
SB
CS = V , V = Max., f = f , Outputs Open
IL
CC
MAX
Standby Current
CS ≥ V , V = Max., f = f , Outputs Open
MAX
mA
mA
IH
CC
Full Standby CurrentCS ≥ V – 0.2V,
SB1
CC
f = 0, V > V – 0.2V or < 0.2V, Outputs Open
IN
CC
NOTE 1. Preliminary specification only.
Capacitance(1) (T = +25°C, f = 1.0 MHz)
A
Symbol
Parameter
Data I/O Capacitance, V = 0V
Max.
Unit
C
15
60
75
20
pF
pF
pF
pF
I/O
IN
C
Input Capacitance, (Address) V = 0V
IN
IN(1)
C
Input Capacitance, (WE, OE) V = 0V
IN
IN(2)
C
Input Capacitance, (CS), V = 0V
IN
IN(3)
NOTE 1. This parameter is determined by device characteristics but is not production tested.
4
Rev 1.1
PRELIMINARY
PDM4M3120
AC Test Conditions
Input Pulse Levels
V
to 3.0V
SS
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
2.5 ns
1
2
1.5V
1.5V
See Figures 1 and 2
3
+3.3V
+3.3V
317Ω
317Ω
4
DATAOUT
351Ω
DATAOUT
351Ω
5 pF*
30 pF*
5
* Including scope and jig capacitances
* Including scope and jig capacitances
6
Figure 2. Output Load
(for tOHZ, tCHZ, tOLZ, and tCLZ
Figure 1. Output Load
)
7
9
10
11
12
Rev 1.1
5
PRELIMINARY
PDM4M3120
AC Electrical Characteristics (Vcc = 3.3V ± 10%, T = 0°C to +70°C)
A
PDM4M3120SXXZ, PDM4M3120SXXM
-20 ns -15 ns -12 ns
Min. Max. Min. Max. Min. Max.
Symbol
Parameter
Unit
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
20
—
15
—
12
—
ns
ns
RC
Address Access Time
—
20
—
15
—
12
AA
Chip Select Access Time
—
3
20
—
10
—
7
—
3
15
—
8
—
3
12
—
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ACS
(1)
Chip Select to Output inLow-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Chip Deselect to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power-Up Time
Chip Deselect to Power-Down Time
CLZ
OE
—
0
—
0
—
0
(1)
(1)
—
7
—
7
OLZ
—
—
3
—
—
3
—
—
3
CHZ
OHZ
OH
(1)
7
7
7
—
—
20
—
—
15
—
—
12
(1)
0
0
0
PU
(1)
—
—
—
PD
Write Cycle
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
20
12
12
0
—
—
—
–
15
10
10
0
—
—
—
—
—
—
7
12
10
10
0
—
—
—
—
—
—
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CW
AW
AS
Chip Select to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
15
3
—
—
7
13
3
12
3
WP
WR
WHZ
DW
DH
Write Recovery Time
(1)
Write Enable to Output in High-Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
—
12
0
—
10
0
—
10
0
—
—
—
—
—
—
—
—
—
(1)
OW
0
0
0
NOTE 1. This parameter is determined by device characteristics but is not production tested.
6
Rev 1.1
PRELIMINARY
PDM4M3120
Timing Waveforms of Read Cycle No.1(1)
t
RC
1
2
ADDRESS
t
AA
OE
t
t
OH
(5)
OE
(5)
t
OLZ
CS
3
t
t
OHZ
ACS
(5)
(5)
t
t
CHZ
CLZ
D
OUT
4
5
Timing Waveforms of Read Cycle No.2(1,2,4)
t
RC
6
ADDRESS
t
AA
t
t
OH
OH
7
D
OUT
Previous Data Valid
Data Valid
Timing Waveforms of Read Cycle No.3(1,3,4)
9
CS
t
ACS
10
11
12
(5)
(5)
t
t
CLZ
CLZ
D
OUT
NOTES
1
WE is HIGH for Read Cycle.
2. Device is continuously selected. CS = V .
3. Address valid prior to or coincident with CS transition LOW.
4. OE = V .
IL
IL
5. Transition is measured ±200 mV for steady state. This parameter is
determined by device characteristics but is not production tested.
Rev 1.1
7
PRELIMINARY
PDM4M3120
(1,2,3,7)
WE
Timing Waveforms of Write Cycle No.1 (
Controlled)
t
WC
ADDRESS
OE
t
AW
CS
(7)
t
t
t
WR
AS
WP
WE
(6)
t
WHZ
(6)
(6)
(6)
t
t
t
OHZ
OHZ
OW
D
OUT
(4)
(4)
t
t
DH
DW
D
IN
Data Valid
(1,2,3,5)
CS
Timing Waveforms of Write Cycle No.2 (
Controlled)
t
WC
ADDRESS
t
AW
CS
t
t
t
WR
AS
CW
WE
t
t
DH
DW
D
IN
Data Valid
NOTES
1
WE orCS must be HIGH during all address transitions.
2. A write occurs during the overlap (t ) of a LOWCS and a LOWWE.
WP
3.
t
is measured from the earlier ofCS orWE going HIGH to end the write cycle.
WR
4. During this period, I/O pins are in the output state, and input signals must be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs
remain in a high-impedance state.
6. Transition is measured ±200 mV for steady state with a 5 pF load (including scope and jig). This
parameter is determined by device characteristics but is not production tested.
7. If OE is LOW during aWE controlled write cycle, the write pulse width must be the larger of t or
WP
(t
+ t ) to allow the I/O drivers to turn off and data to be placed on the bus for the required t
.
WHZ
DW
DW
If OE is HIGH during aWE controlled write cycle, this requirement does not apply and the write
pulse width can be as short as the specified t
.
WP
8
Rev 1.1
PRELIMINARY
PDM4M3120
Package Dimensions
ZIP Version
1
2
SIDE VIEW
FRONT VIEW
3.950
0.365
0.590
3
0.125
0.020
0.250
0.100
0.050
0.100
4
PIN 1
BACK VIEW
5
6
PIN 1
7
SIMM Version
SIDE VIEW
0.350
FRONT VIEW
4.250
3.984
9
0.650
0.400
0.250
0.250
0.050
PIN 1
0.050
10
11
12
0.080
BACK VIEW
PIN 1
Rev 1.1
9
PRELIMINARY
PDM4M3120
Angled SIMM Version
SIDE VIEW
4.255
Max.
3.988
3.980
0.350
Max.
COMPONENTS BOTH SIDES
(NOT SHOWN)
0.680
Max.
0.403
0.397
.220 ref
.130 ref
0.251
0.249
0.255
0.245
0.085
0.075
PIN 1
0.050
Typical
0.630 R
0.610 R
0.255
0.245
3.752
3.748
Ordering Information
PDM4M XXXXX
S
XX
X
X
Device Power Speed Package Temp
Blank Commercial (0 to 70°C)
AM
M
72-pin Angled SIMM
72-pin SIMM
Z
72-pin ZIP
12
15
20
Commercial
S
Standard Power
3120
1M x 32
3.3V
10
Rev 1.1
相关型号：
©2020 ICPDF网 联系我们和版权申明