PDM4M4110S35Z [IXYS]
SRAM Module, 512KX32, 35ns, CMOS, ZIP-72;
| 型号： | PDM4M4110S35Z |
| 厂家： | 
IXYS CORPORATION |
| 描述： | SRAM Module, 512KX32, 35ns, CMOS, ZIP-72 静态存储器 内存集成电路 |
| 文件： | 总10页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
PDM4M4110
512K x 32 CMOS
Static RAM Module
1
The PDM4M4110 is packaged in a 72-pin FR-4 ZIP
(Zig-zag In-line vertical Package) or a 72-pin SIMM
(Single In-line Memory Module). The ZIP configura-
Features
■ High-density 2 megabyte Static RAM module
■ Low profile 72-pin ZIP (Zig-zag In-line vertical
Package) or 72-pin SIMM (Single In-line Memory
Module)
tion allows 72 pins to be placed on a package 3.95" 2
long and 0.250" wide. At only 0.600" high, this low-
profile package is ideal for systems with minimum
board spacing. The SIMM configuration allows use of
■ Fast access time: 15 ns (max.)
■ Surface mounted plastic components on an epoxy
laminate (FR-4) substrate Single 5V (±10%) power
supply
■ Multiple V pins and decoupling capacitors for
maximum noise immunity
■ Inputs/outputs directly TTL compatible
3
edge mounted sockets to secure the module.
All inputs and outputs of the PDM4M4110 are TTL
compatible and operate from a single 5V supply. Mul-
tiple ground pins and on board decoupling capacitors
SS
4
provide maximum immunity from noise.
Four identification pins (PD0, PD1, PD2, PD3) are pro-
vided for applications in which different density
versions of the module are used. In this way, the tar-
get system can read the respective levels of PD0, PD1,
PD2, PD3 to determine a 512K depth.
Description
5
The PDM4M4110 is a 512K x 32 static RAM module
constructed on an epoxy laminate (FR-4) substrate
using four (4) 512K x 8 static RAMs in plastic SOJ
packages. Availability of four chip select lines pro-
vides byte access. The PDM4M4110 is available with
access times as fast as 15 ns with minimal power
consumption.
6
7
Functional Block Diagram
9
CS1
CS2
CS3
CS4
19
A18-A0
WE
4
10
PD3-PD0
512K x 32
RAM
OE
11
8
8
8
8
I/O31-I/O0
12
Rev 2.3
PRELIMINARY
PDM4M4110
(1)
Pin Configuration
Pin Assignment
Pin
Signal
1
3
5
7
9
NC
PD0 - NC
2
NC
PD3
PD0
I/O0
I/O1
I/O2
I/O3
Vcc
A7
PD2
Vss
PD1 - NC
I/O31-I/O0
A18-A0
CS4-CS1
WE
Data Inputs/Outputs
Addresses
4
PD2 - OPEN
PD3 - NC
6
Chip Selects
Write Enable
Output Enable
Depth Identification
Power
PD1
I/O8
I/O9
I/O10
I/O11
A0
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
OE
11
13
15
17
19
21
23
25
27
29
31
33
35
PD3-PD0
V
CC
V
Ground
SS
NC
No Connect
A1
A8
A2
A9
I/O12
I/O13
I/O14
I/O15
Vss
I/O4
I/O5
I/O6
I/O7
WE
A15
CS2
A14
CS1
ZIP, SIMM
TOP VIEW
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
CS4
A17
OE
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
CS3
A16
Vss
I/O24
I/O25
I/O26
I/O27
A3
I/O16
I/O17
I/O18
I/O19
A10
A4
A11
A5
A12
Vcc
A13
A6
I/O20
I/O21
I/O22
I/O23
Vss
I/O28
I/O29
I/O30
I/O31
A18
NC
NC
NC
NOTE: 1. Pins 3, 4, 6, and 7 (PD0, PD1, PD02, and PD3
respectively) are read by the user to determine the
density of the module. If PD0 reads NC, PD1 reads
NC, PD2 reads OPEN, PD3 reads NC then the
module has a 512K depth.
Rev 2.3
PRELIMINARY
PDM4M4110
Truth Table
CS
OE
WE
Mode
Output
Power
1
2
Deselect/
Power-down
H
X
X
High-Z
Standby
Read
L
L
L
L
X
H
H
L
DATA
Active
Active
Active
OUT
Write
DATA
IN
Deselect
H
High-Z
3
(1)
Absolute Maximum Ratings
4
Symbol
Rating
Com’l.
Ind.
Unit
V
Terminal Voltage with Respect to V
Temperature Under Bias
Storage Temperature
–0.5 to +7.0
–10 to +85
–55 to +125
0 to +70
1.0
–0.5 to +7.0
–10 to +85
–65 to +150
0 to +70
1.0
V
°C
°C
°C
W
TERM
BIAS
STG
A
SS
T
T
T
5
Operating Temperature
Power Dissipation
P
T
6
I
DC Output Current
50
50
mA
OUT
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device.This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
7
Recommended DC Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
9
V
V
Supply Voltage
4.5
0
5.0
0
5.5
0
V
V
CC
Supply Voltage
SS
Commercial
Ambient Temperature
0
25
70
°C
10
11
12
Rev 2.3
PRELIMINARY
PDM4M4110
DC Electrical Characteristics (V = 5.0V ± 10%, T = 0°C to +70°C)
CC
A
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
I
I
I
Input Leakage Current
(Address and Control)
V
V
V
= Max.,V = V to V
CC
—
40
µA
LI
CC
IN
SS
Input Leakage Current
(Data)
= Max., V = V to V
CC
—
—
10
10
µA
µA
LI
CC
IN
SS
Output Leakage Current
= V to V , V = Max.,
SS CC CC
LO
OUT
CS = V
IH
V
V
V
V
Output Low Voltage
Output High Voltage
Input High Voltage
Input Low Voltage
I
I
= 8 mA, V = Min.
—
0.4
—
V
V
V
V
OL
OH
IH
OL
OL
CC
= –4 mA, V = Min.
2.4
2.2
CC
6.0
0.8
(1)
–0.5
IL
NOTE 1. V = –2.0V for pulse widths less than 10 ns, once per cycle.
IL
Power Supply Characteristics
(1)
Symbol
Parameter
Max
Unit
I
I
I
Operating Current
680
160
60
mA
CC
CS = V , V = Max., f = f , Outputs Open
IL
CC
MAX
Standby Current
CS ≥ V , V = Max., f = f , Outputs Open
MAX
mA
mA
SB
IH
CC
Full Standby Current CS ≥ V – 0.2V,
SB1
CC
f = 0, V > V – 0.2V or < 0.2V
IN
CC
NOTE 1. Preliminary specification only.
Capacitance(1) (T = +25°C, f = 1.0 MHz)
A
Symbol
Parameter
Input Capacitance, (Data) V = 0V
Max.
Unit
C
C
C
12
40
12
pF
pF
pF
IN(D)
IN(A)
OUT
IN
Input Capacitance, (Address and Control) V = 0V
IN
Input Capacitance, V
= 0V
OUT
NOTE 1. This parameter is determined by device characteristics but is not production tested.
Rev 2.3
PRELIMINARY
PDM4M4110
AC Test Conditions
Input Pulse Levels
V
to 3.0V
SS
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
5 ns
1.5V
1.5V
1
2
See Figures 1 and 2
3
+5V
+5V
480Ω
480Ω
4
DATAOUT
255Ω
DATAOUT
255Ω
5 pF*
30 pF*
5
* Including scope and jig capacitances
* Including scope and jig capacitances
6
Figure 2. Output Load
(for tOHZ, tCHZ, tOLZ, and tCLZ)
Figure 1. Output Load
7
9
10
11
12
Rev 2.3
PRELIMINARY
PDM4M4110
AC Electrical Characteristics (Vcc = 5V ± 10%, T = 0°C to +70°C)
A
PDM4M4110SXXZ, PDM4M4110SXXM
-15 ns -20 ns -25 ns -35 ns
Min. Max. Min. Max. Min. Max. Min. Max.
Symbol
Parameter
Unit
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
15
—
—
5
—
15
15
—
6
20
—
—
3
—
20
20
—
10
—
12
8
25
—
—
3
—
25
25
—
12
—
14
10
—
—
25
35
—
—
3
—
35
35
—
15
—
16
12
—
—
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address Access Time
AA
Chip Select Access Time
ACS
(1)
Chip Select to Output inLow-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Chip Deselect to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power-Up Time
Chip Deselect to Power-Down Time
CLZ
—
0
—
0
—
0
—
0
OE
(1)
(1)
—
10
6
OLZ
—
—
3
—
—
3
—
—
3
—
—
3
CHZ
OHZ
OH
(1)
—
—
15
—
—
20
(1)
0
0
0
0
PU
PD
(1)
—
—
—
—
Write Cycle
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
15
13
13
3
—
—
—
—
—
—
8
20
18
18
3
—
—
—
–
25
20
20
3
—
—
—
—
—
—
13
—
—
—
35
25
25
3
—
—
—
—
—
—
15
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CW
AW
Chip Select to End of Write
Address Valid to End of Write
Address Setup Time
(2)
AS
Write Pulse Width
13
0
15
0
—
—
8
17
0
22
0
WP
WR
(2)
(1)
Write Recovery Time
Write Enable to Output in High-Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
—
10
0
—
12
0
—
15
0
—
20
0
WHZ
—
—
—
—
—
—
DW
(2)
DH
(1)
2
2
2
2
OW
NOTE 1. This parameter is determined by device characteristics but is not production tested.
2. t = 0 ns for CS controlled write cycles. t , t = 3 ns for CS controlled write cycles
AS
DH WR
Rev 2.3
PRELIMINARY
PDM4M4110
(1)
Timing Waveforms of Read Cycle No.1
t
RC
1
2
ADDRESS
t
AA
OE
CS
t
t
OH
(5)
OE
(5)
t
OLZ
3
t
t
OHZ
ACS
(5)
(5)
t
t
CHZ
CLZ
D
OUT
4
5
(1,2,4)
Timing Waveforms of Read Cycle No.2
t
RC
6
ADDRESS
t
AA
t
t
OH
OH
7
D
OUT
Previous Data Valid
Data Valid
(1,3,4)
Timing Waveforms of Read Cycle No.3
9
CS
t
ACS
10
11
12
(5)
(5)
t
t
CLZ
CLZ
D
OUT
NOTES 1 WE is HIGH for Read Cycle.
2. Device is continuously selected. CS = V .
IL
3. Address valid prior to or coincident with CS transition LOW.
4. OE = V .
5. Transition is measured ±200 mV for steady state. This parameter is
IL
determined by device characteristics but is not production tested.
Rev 2.3
PRELIMINARY
PDM4M4110
(1)
Timing Waveforms of Write Cycle No.1
t
WC
ADDRESS
OE
t
WR
t
AW
CS
(2)
t
t
AS
WP
WE
(4,9)
(6)
t
t
OHZ
WHZ
D
OUT
t
t
DH
DW
D
IN
(1,6)
Timing Waveforms of Write Cycle No.2
t
WC
ADDRESS
(3)
WR
t
t
AW
t
CW
CS
(5)
(2)
t
WP
WE
t
OH
(4,9)
t
(9)
t
t
AS
WHZ
OW
(7)
D
OUT
t
t
DH
DW
(8)
D
IN
NOTES 1 WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (t ) of a LOW CS .
WP
3. t
is measured from the earlier of CS or WE going HIGH to end the write cycle.
WR
4. During this period, I/O pins are in the output state, and input signals to the opposite phase to the outputs must not
be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-
impedance state.
6. OE is continuously LOW (OE = V )
IL
7. D
is the same phase of write data of this write cycle.
OUT
8. If CS is LOW during this period, I/O pins are in the output state. Then the data input signals of the opposite phase
to the outputs must not be applied to them.
9. Transition is measured ±200 mV for steady state with a 5 pF load (including scope and jig).This parameter is deter-
mined by device characteristics but is not production tested.
Rev 2.3
PRELIMINARY
PDM4M4110
Package Dimensions
ZIP Version
1
2
SIDE VIEW
0.250
FRONT VIEW
3.950
0.600
3
0.125
0.020
0.250
0.100
0.050
0.100
PIN 1
4
BACK VIEW
5
6
PIN 1
7
SIMM Version
SIDE VIEW
0.250
FRONT VIEW
4.250
3.984
0.650
0.250
9
0.400
0.250
0.050
PIN 1
0.050
10
11
12
0.080
BACK VIEW
PIN 1
Rev 2.3
PRELIMINARY
PDM4M4110
Ordering Information
PDM4M XXXXX
S
XX
X
X
Device Power Speed Package Temp
Blank Commercial (0 to 70°C)
Z
72-pin ZIP
M
72-pin SIMM
15
20
25
35
Commercial
S
Standard Power
512K x 32
4110
Rev 2.3
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