Z84C0006FEC [IXYS]
Microprocessor, 8-Bit, 6.17MHz, CMOS, PQFP44, QFP-44;
| 型号： | Z84C0006FEC |
| 厂家： | 
IXYS CORPORATION |
| 描述： | Microprocessor, 8-Bit, 6.17MHz, CMOS, PQFP44, QFP-44 外围集成电路 |
| 文件： | 总31页 (文件大小：345K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Z84C90
KIO Serial/Parallel Counter
Timer
Product Specification
PS011802-0902
ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432
Telephone: 408.558.8500 • Fax: 408.558.8300 • http://www.ZiLOG.com
This publication is subject to replacement by a later edition. To determine whether a later edition exists, or
to request copies of publications, contact:
ZiLOG Worldwide Headquarters
532 Race Street
San Jose, CA 95126-3432
Telephone: 408.558.8500
Fax: 408.558.8300
www.ZiLOG.com
Windows is a registered trademark of Microsoft Corporation.
Document Disclaimer
©2002 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or
technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT
ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES,
OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR
INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES,
OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty
and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes no
warranty of merchantability or fitness for any purpose Except with the express written approval of ZiLOG, use of
information, devices, or technology as critical components of life support systems is not authorized. No licenses are
conveyed, implicitly or otherwise, by this document under any intellectual property rights.
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
iii
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Precautions & Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
iv
List of Figures
Figure 1. KIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. Z84C90 84-Pin PLCC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. 100-Pin LQFP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. PIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. PIA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. CTC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Crystal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. SIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. I/O Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Serial I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Counter/Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Port I/O Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. Interrupt Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15. Op Code Fetch Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
v
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Z84C90 KIO Serial/Parallel/Counter/TimerPackages . . . . . . . . . . . . . . . . . . 1
KIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DC Characteristics of the Z84C90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC Characteristics of the Z84C90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Daisy Chain Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
1
Z84C90
KIO Serial/Parallel Counter/Timer
Product Specification
Features
Table 1. Z84C90 KIO Serial/Parallel/Counter/Timer Packages
Part Number
Package
Frequency (MHz)
Z84C9008ASC
Z84C9010ASC
Z84C9008VEC
Z84C9008VSC
Z84C9010VSC
Z84C9012VSC
100-pin LQFP
100-pin LQFP
84-pin PLCC
84-pin PLCC
84-pin PLCC
84-pin PLCC
8
10
8
8
10
12
General Description
ZiLOG’s Z84C90 Serial/Parallel/Counter/Timer KIO is a multi-channel, multipurpose I/O
device designed to provide the end-user with a cost-effective and powerful solution to
meet peripheral needs. The Z84C90 combines the features of one Z84C30 CTC, one
Z84C20 PIO, a Z84C4x SIO, a 8-bit, bit-programmable I/O port, and a crystal-oscillator
into a single package (84-pin PLCC or 100-pin LQFP). Using fifteen internal registers for
data and programming information, the KIO can easily be configured to any given system
environment. Although the optimum performance is obtained with a Z84C00 CPU, the
KIO can just as easily be used with any other CPU.
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
2
PA0-PA7
ARDY
ASTB
PIO
PB0-PB7
BRDY
BSTB
OSC
XTAL1
Oscillator
XTAL0
PIA/
MUX
CLKOUT
PC0-PCV
RXDA
RXCA
TXDA
TXCA
CTSA
DCDA
D0-D7
A0-A3
CS
Bus
Interface
and
MI
SIO
RD
RXDB
IORQ
RESET
CLK
RXCB
TXDB
Control
TXCB
CTSB
DCDB
ZC/TO0
CLK/TRG0
ZC/TO1
CLK/TRG1
INT
IE1
IE0
Interrupt
Control
CTC
ZC/TO2
CLK/TRG2
ZC/TO3
CLK/TRG3
Figure 1. KIO Block Diagram
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
3
Absolute Maximum Ratings
Voltage on VCC with respect to VSS
–0.3V to +7.0V
Voltages on all inputs with respect to
VSS
–0.3V to VCC +0.3V
Operating Ambient Temperature
See Ordering
Information
Storage Temperature
–65 C to +150 C
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This rating is a stress rating only. Operation of the device at any
condition above those indicated in the operational sections of these specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
4
Pin Types
PC1 (SYNCB)
PC2 (DTRB)
PC3 (RTSB)
TxDA
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CLK/TRG
CLK/TRG
CLK/TRG
D7
D6
D5
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
2
1
0
TxCA
RxCA
RxDA
PA0
PA1
PA2
VCC
PA3
GND
PA4
PA5
PA6
D4
GND
V
CC
D3
D2
D1
D0
84-Pin PLCC
V
CC
XTAL1
XTAL0
GND
PA7
PC4 (RTSA)
PC5 (DTRA)
PC6 (SYNCA)
PC7 (WT/RDYA)
CLOCK
CLKOUT
OSC
INT
Figure 2. Z84C90 84-Pin PLCC Configuration
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
5
75
70
65
60
55
51
NC
NC
NC
NC
GND
GND
PB7
PB6
PB5
PB4
PB3
76
80
50
45
40
35
PC0 (WT/RDYB)
GND
CSTA
DCDA
DCDB
CTSB
TxDB
TxCB
RxCB
RxDB
A0
A1
A2
A3
CS
M1
RD
VCC
PB2
PB1
PB0
85
90
BRDY
BSTB
ARDY
ASTB
ZC/TO3
ZC/TO2
ZC/TO1
ZC/TO0
IE1
100-Pin LQFP
95
IORQ
RESET
CLK/TRG3
30
26
IE0
VCC
NC
NC
NC
NC
100
1
5
10
15
20
25
Figure 3. 100-Pin LQFP Configuration
Pin Descriptions
A0–A3. Address bus (inputs). Used to select the port/register for each bus cycle.
ARDY, BRDY. Port Ready (outputs, Active High). These signals indicate that the port is
ready for a data transfer. In Mode 0, the signal indicates that the port has data available to
the peripheral device. In Mode 1, the signal indicates that the port is ready to accept data
from the peripheral device. In Mode 2, ARDY indicates that Port A has data available for
the peripheral device, but that the data is not be placed onto PA0–PA7 until the ASTB sig-
nal is Active. BRDY indicates that Port A is able to accept data from a peripheral device.
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
6
Port B does not support Mode 2 operation and can only be used in
Note:
Mode 3 when Port A is programmed for Mode 2. BRDY is not
associated with Port B when it is operating in Mode 3.
ASTB, BSTB. Port Strobe (inputs, Active Low). These signals indicate that the peripheral
device has performed a transfer. In Mode 0, the signal indicates that the peripheral device
has accepted the data present on the port pins. In Mode 1, the signal causes the data on the
port pins to be latched onto Port A. In Mode 2, ASTB Low causes the data in the output
data latch of Port A to be placed onto the Port A pins. BSTB Low causes the data present
on the Port A pins to be latched into the Port A input data latch. The end of the current
transaction is noted by the rising edge of these signals.
Note:
Port B does not support Mode 2 operation, and can only be used in
Mode 3 when Port A is programmed for Mode 2. BSTB is not
associated with Port B when it is operating in Mode 3.
CLK/TRG0–CLK/TRG3. External Clock/Timer Trigger (inputs, user-selectable Active
High or Low). These four pins correspond to the four counter/timer channels of the KIO.
In Counter mode, each active edge causes the downcounter to decrement. In Timer mode,
an active edge starts the timer.
CLKOUT. Clock Out (output). This output is a divide-by-two of the oscillator (XTAL)
input.
CLOCK. System Clock (input). This clock must be the same as (or a derivative of) the
CPU clock. If the CLKOUT is to be used as the system clock, then these two pins must be
connected together.
CS. Chip Select (input, Active Low). Used to activate the internal register decoding mech-
anism and allow the KIO to perform a data transfer to/from the CPU.
CTSA, CTSB. Clear to Send (inputs, Active Low). These signals are modem control sig-
nals for the serial channels. When programmed for Auto Enable, a Low on these pins
enables their respective transmitters. If not programmed as Auto Enable, these pins may
be used as general-purpose input signals.
D –D . Data Bus (bidirectional, Active High, 3-stated). Used for data exchanges between
0
7
the CPU and the KIO for programming and data transfer. The KIO also monitors the data
bus for RETI instructions to maintain its Interrupt Under Service (IUS) status.
DCDA, DCDB. Data Carrier Detect (inputs, Active Low). These signals are modem con-
trol signals for the serial channels. When programmed for Auto Enable, a Low on these
pins enables their respective receivers. If not programmed as Auto Enable, these pins may
be used as general-purpose input signals.
DTRA, DTRB. Data Terminal Ready (outputs, Active Low). These signals are modem
control signals for the serial channels. They follow the state programmed into their respec-
tive serial channels, and are multiplexed with Port C, bits 5 and 2, respectively.
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
7
IEI. Interrupt Enable In (input, Active High). This signal is used with Interrupt Enable
Out (IEO) to form a priority daisy chain when there is more than one interrupt-driven
device. A High on this line indicates that no higher-priority device is requesting an inter-
rupt.
IEO. Interrupt Enable Out (output, Active High). This signal is used with Interrupt Enable
In (IEI) to form a priority daisy chain when there is more than one interrupt-driven device.
A High on this line indicates that this device is requesting an interrupt, and that no higher-
priority device, is not requesting an interrupt. A Low blocks any lower-priority devices
from requesting an interrupt.
IORQ. Input/Output Request (input, Active Low). IORQ is used with RD, A –A , and CS
0
3
to transfer data between the KIO and the CPU. When IORQ, RD, and CS are Active Low,
the device selected by A –A transfers data to the CPU. When IORQ and CS are Active
0
3
Low, but RD is Active High, the device selected by A –A is written into by the CPU.
0
3
When IORQ and M1 are both Active Low, the KIO may respond with an interrupt vector
from its highest-priority interrupting device.
M1. Machine Cycle 1 (input, Active Low). When M1 and RD are Low, the Z80 CPU
fetches an instruction from memory; the KIO decodes this cycle to determine if the RETI
instruction sequence is being executed. When M1 and IORQ are both active, the KIO
decodes the cycle to be an interrupt acknowledge, and may respond with a vector from its
highest-priority interrupting device.
OSC. Oscillator (output). This output is a reference clock for the oscillator.
PA0–PA7. Port A Bus (bidirectional, tristated). One of the 8-bit ports of the PIO. PA is
0
the least-significant bit of the bus.
PB0–PB7. Port B Bus (bidirectional, tristated). One of the 8-bit ports of the PIO. PB is
0
the least-significant bit of the bus. This port can also supply 1.5mA at 1.5V to drive Dar-
lington transistors.
PC0–PC7. Port C Bus (bidirectional, tristated). PC is the least-significant bit of the bus.
0
These pins are multiplexed between the 8-bit PIA and additional modem control signals
for the serial channels.
RD. Read (input, Active Low). When RD is active, a memory or I/O read operation is in
progress. RD is used with A –A , CS and IORQ to transfer data between the KIO and
0
3
CPU.
RESET. Reset (input, Active Low). A Low on this pin forces the KIO into a Reset condi-
tion. This signal must be active for a minimum of three Clock cycles. The KIO resets so
that the PIO ports operate in Mode 1
•
•
•
With handshakes inactive and interrupts disabled
PIA port in Input mode and active
CTC channel counting terminated and interrupts disabled
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
8
•
•
SIO channels disabled
Marking with interrupts disabled.
All control registers must be rewritten after a hardware reset.
RTSA, RTSB. Request to Send (outputs, Active Low). These signals are modem control
signals for their serial channels. They follow the inverse state programmed into their
respective serial channels, and are multiplexed with Port C, bits 4 and 3, respectively.
RxCA, RxCB. Receive Clock (inputs, Active Low). These clocks are used to assemble
the data in the receiver shift register for their serial channels. Data is sampled on the rising
edge of the clock.
RxDA, RxDB. Receive Data (inputs, Active High). These pins are the input data pins to
the receive shift register for their serial channels.
SYNCA, SYNCB. Synchronization (bidirectional, Active Low). In the Asynchronous
mode of operation, these pins act much like the CTS and DCD pins. Transitions affect the
Sync/Hunt status bit for their respective serial channels, but serve no other purpose. These
pins are multiplexed with Port C, bits 6 and 1, respectively.
TxCA, TxCB. Transmit Clock (inputs, Active Low). These clocks are used to transmit
data from the transmit shift register for their serial channels. Data is transmitted on the
falling edge of the clock.
TxDA, TxDB. Transmit Data (outputs, Active High). These pins are the output data pins
from the transmitter for their serial channels.
WT/RDYA, WT/RDYB. Wait/Ready (outputs, open-drain when programmed as Wait;
tristated when programmed as Ready). These pins may be programmed as Ready lines for
a DMA controller or Wait lines for interfacing to a CPU. As a Ready line, these pins indi-
cate (when Active Low) that the transmitter or the receiver requests a transfer between the
serial channel and the DMA. As a Wait line, these pins dictate (when Low) that the CPU
must wait until the transmitter or receiver can complete the requested transaction. These
pins are multiplexed with Port C, bit 7 and 0, respectively.
XTALI. Crystal/Clock Connection. (input).
XTALO. Crystal Connection. (output).
ZC/TO0–ZC/TO3. Zero count/Time-out (outputs, Active High). These four pins are out-
puts from the four counter/timer channels of the KIO. Each pin pulses High when its cor-
responding downcounter reaches 0.
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
9
Table 2. KIO Registers
Address
A3 A2 A1 A0
Register 0: PIO Port A Data
Register 1: PIO Port A Command
Register 2: PIO Port B Data
Register 3: PIO Port B Command
Register 4: CTC Channel 0
Register 5: CTC Channel 1
Register 6:
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Register 7:
Register 8: SIO Port A Data
Register 9: SIO Port A Command/Status
Register 10: SIO Channel B Data
Register 11: SIO Channel B Command/Status
Register 12: PIA Port C Data
Register 13: PIA Port C Command
Register 14: KIO Command
Register 15: Reserved
Note: Additionally, IORQ and CS must be Low. Registers are written to or read from by the CPU,
applying a 1 or a 0 respectively on the RD pin.
Standard Test Conditions
The DC Characteristics and Capacitance sections below apply to the following standard
test conditions, unless otherwise noted. All voltages are referenced to GND (0V). Posi-
tive current flows into the referenced pin.
Available operating temperature ranges are:
•
•
S = 0° C to +70° C
E = –40° C to +100° C
Voltage Supply Range: +5.0V ± 10%
All AC parameters assume a load capacitance of 100 pF. Add 10 ns delay for each 50 pF
increase in load up to a maximum of 200 pF for the data bus and 100 pF for the address
and control lines. AC timing measurements are referenced to 1.5 volts (except for
CLOCK, which is referenced to the 10% and 90% points.
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
10
The Ordering Information section lists temperature ranges and product numbers. Package
drawings are in the Package Information section. Refer to the Literature List for additional
documentation.
+5V
2.1K
From Output
Under Test
100 pF
250
µA
Figure 4. Test Load Diagram
Internal
Control
Logic
8
Data or
Control
Port A
I/O
Handshake
Data
CPU
Bus I/O
Peripheral
Interface
Internal Bus
Control
8
Data or
Control
Port B
I/O
Handshake
Interrupt
Control
3
Interrupt Control Lines
Figure 5. PIO Block Diagram
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
11
Port C
PC0`PC7
Data Bus
Dir.
Ctrl.
Figure 6. PIA Block Diagram
Internal
Control
Logic
Data
8
INT
CPU
Bus
I/O
Interrupt
Logic
Internal Bus
IE1
IE0
Control
6
4
4
ZC/TO
Counter/
Timer
Logic
CLK/TRG
Reset
Figure 7. CTC Block Diagram
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
12
ZTALI
Crystal
Inputs
C1
C2
XTALO
Figure 8. Crystal Connection
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
13
Serial
Data
Channel
Channel A
Control
and
Status
Registers
Channel A
Clocks
Sync
Wait/Ready
Channel A
Modem or
Control
Other
Internal
Control
Logic
and
Control
Status
I
n
t
e
r
n
a
l
Data
8
7
Channel B
Modem or
CPU
Bus
I/O
Control
and
Status
Other
Control
Control
B
u
s
Serial
Data
Interrupt
Control
Lines
Interrupt
Control
Logic
Channel
Clocks
Channel B
Sync
Wait/Ready
Channel B
Control
and
Status
Registers
Figure 9. SIO Block Diagram
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
14
DC Characteristics
V
= 5.0V +/– 10% unless otherwise specified.
cc
Table 3. DC Characteristics of the Z84C90
Symbol Item Min
Clock Input Low Voltage –0.3
Max
Unit Condition
V
V
V
V
V
V
V
+0.45
V
ILC
IHC
IL
Clock Input High Voltage
Input Low Voltage
V
–0.6 V +0.3
cc
CC
–0.3
2.2
+0.8
V
V
Input High Voltage
V
cc
IH
Output Low Voltage
Output High Voltage 1
Output High Voltage 2
Input Leakage Current
3-State Leakage Current
+0.4
V
I
I
I
= 2.0mA
= 1.6mA
= 250mA
OL
OL
OH
OH
2.4
V
OH1
OH2
V
–0.8
V
CC
I
I
I
±10.0
±10.0
–40
mA
mA
mA
V = 0.4~V
in
LI
cc
cc
cc
V = 0.4~V
OL
in
SYNC Pin Leakage
Current
+10
V = 0.4~V
in
L(SY)
I
Darlington Drive Current –1.5
(Port B and ZC/T00~3)
mA
V
R
= 1.5V
OH
OHD
CC
= 390 Ohms
EXT
I
Power Supply Current*
8 MHz
10MHz
15
15
15
mA
mA
V
V
V
= 5 V
CC
= V –.2V
= .2V
IH
IL
cc
12.5MHz
*Measurement made with output floating over specified temperature and voltage ranges.
Table 4. Capacitance
Symbol
Parameter
Minimum Maximum Unit
CCLOCK
CIN
COUT
Clock Capacitance
Input Capacitance
Output Capacitance
10
10
15
cF
cF
cF
TA = 25°C, f = 1MHz
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
15
AC Characteristics
Table 5. AC Characteristics of the Z84C90
8MHz
10MHz1
12MHz
Max Min Max U/M
No. Symbol
Parameter
Min
Max
Min
Bus Interface Timing
1
2
3
4
5
6
TcC
Clock Cycle Time
125
55
DC
DC
DC
10
100
42
DC
DC
DC
10
80 DC ns
32 DC ns
32 DC ns
10 ns
TwCh
TwCl
TfC
Clock Pulse Width (High)
Clock Pulse Width (Low)
Clock Fall Time
55
42
TrC
Clock Rise Time
10
10
10 ns
TsA(Rlf)
Address, CS Setup to RD, IORQ
Fall
50
40
30
ns
7
8
9
TsRl(Cr)
Th
RD, IORQ to Clock Rise Setup
Hold Time for Specified Setup
CLOCK Rise to Data Out Delay
50
15
50
15
40
15
ns
ns
TdCr(DO)
100
75
80
60
65 ns
55 ns
10 TdRlr(DOz)
RD, IORQ Rise to Data Out Float
Delay
11 ThRDr(D)
12 TsD(Cr)
M1,RD,IORQ Rise to Data Float
Data in to Clock Rise Setup
15
30
15
25
15
22
ns
ns
13 TdIOI(DO)
IORQ Fall to Data Out Delay
(INTACK Cycle)2
95
95
95 ns
14 ThIOr(D)
15 THIOr(A)
16 TsM1f(Cr)
17 TsM1r(Cf)
IORQ Rise to Data Float (INTACK)
IORQ Rise to Address Hold
M1 Fall to Clock Rise Setup
15
15
15
15
15
15
40
15
ns
ns
ns
ns
40
40
M1 Rise to Clock Fall Setup
(M1 Cycle)
-15
-15
18 TdM1f(IEOf)
M1 Fall to IEO Fall Delay (Interrupt
Immediately preceding M1 Fall)3
ns
•
•
•
19 TsIEI(IOf)
IEI to IORQ Fall Setup3
IEI Fall to IEO Fall Delay3
ns
•
160
•
150
•
20 TdIEIf(IEOf)
21 TdIEIf(IEOr)
125 ns
IEI Rise to IEO Rise Delay
(after ED Decode)3
160
150
125 ns
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
16
Table 5. AC Characteristics of the Z84C90 (Continued)
8MHz
10MHz1
12MHz
Max Min Max U/M
No. Symbol
Parameter
Min
Max
Min
22 TsIEI(Cf)
IEI to Clock Fall Setup (for 4D
Decode)
50
40
30
ns
23 TsIOr(Cf)
IORQ Rise to Clock Fall Setup
(to activate RDY on next clock)
100
100
ns
PIO Timing
24 TdCf(RDYr)
25 TdCf(RDYf)
26 TwSTB
Clock Fall to RDY Rise Delay
Clock Fall to RDY Fall Delay
STB Pulse Width
100
100
100
100
ns
ns
ns
ns
100
100
80
27 TsSTBr(Cf)
STB Rise to Clock Fall Setup
(to activate RDY on next clock
cycle)
100
28 TdIOf(PD)
29 TsPD(STBr)
30 TdSTBI(PD)
IORQ Fall to Port Data Valid
(Mode 0)
140
120
ns
ns
ns
ns
ns
Port A,B Data to STB Rise Setup
Time (Mode 1)
140
75
STB Fall to Port A,B Data Valid
Delay (Mode 2)
150
140
250
290
120
120
200
220
31 TdSTBr(PDz) STB Rise to Port Data Float Delay
(Mode 2)
32 TdPD(INTf)
Port Data Match to INT Fall Delay
(Mode 3)
33 TdSTBr(INTf) STB Rise to INT Fall Delay
ns
–
34 TsPD(RIf)
PIA Port Data to RD, IORQ Fall
Setup
TBD
TBD
35 TdCr(PD)
CTC Timing
Clock Rise to Port Data Valid Delay
80
80
ns
36 TdCr(INTf)
37 TsCTRr(Cr)c
Clock Rise to INT Rise Delay
TcC+100
TcC+80
ns
ns
CLK/TRG Rise to Clock Rise Setup
(for immediate count, Counter
mode)
90
90
38 TsCTRr(Cr)t
PS011802-0902
CLK/TRG Rise to Clock Rise Setup
(for enabling prescaler on following
Clock Rise, Timer mode)
90
90
ns
Z84C90
KIO Serial/Parallel Counter Timer
17
Table 5. AC Characteristics of the Z84C90 (Continued)
8MHz
Min Max
(36)+(38)
10MHz1
Min Max Min Max U/M
(36)+(38)
12MHz
No. Symbol
Parameter
39 TdCTRr(INTf) CLK/TRG Rise to INT Fall Delay
TsCTRr(Cr) satisfied
(1)+(36)+(38) (1)+(36)+(38)
TsCTRr(Cr) not satisfied
40 TcCTR
CLK/TRG Cycle Time4
CLK/TRG Width High
(2TcC) DC (2TcC) DC
ns
ns
ns
ns
ns
ns
ns
41 TwCTRh
42 TwCTRI
43 TrCTR
90
90
DC
DC
30
30
90
90
DC
DC
30
CLK/TRG Width Low
CLK/TRG Rise Time
44 TfCTR
CLK/TRG Fall Time
30
45 TdCr(ZCr)
46 TdCf(ZCf)
SIO Timing
Clock Rise to ZC/TO Rise Delay
Clock Fall to ZC/TO Fall Delay
80
80
80
80
47 TdIOf(W/Rf)
IORQ Fall to WT/RDY Fall Delay
(Wait Mode)
130
85
110
85
ns
ns
ns
48 TdCr(W/Rf)
49 TdCf(W/Rz)
Clock Rise to WT/RDY Delay
(Ready Mode)
Clock Fall to WT/RDY Float Delay
(Wait Mode)
90
80
50 TwPh
51 TwPI
Pulse Width High
Pulse Width Low
TxC Cycle Time
TxC Width High
TxC Width Low
TxC Rise Time
TxC Fall Time
150
150
250
85
120
120
200
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
52 TcTxC
53 TwTxCh
54 TwTxCl
55 TrTxC
56 TfTxC
DC
DC
DC
60
DC
DC
DC
60
85
80
60
60
57 TdTxCf(TxD) TxC Fall to TxD Delay (x1 mode)
160
9
120
9
58 TdTxCf(W/Rf) TxC Fall to WT/RDY Fall Delay
(Ready Mode)5
5
5
59 TdTxCf(INTf) TxC Fall to INT Fall Delay5
5
9
5
9
ns
ns
ns
ns
60 TcRxC
61 TwRxCh
62 TwRxCl
RxC Cycle Time
RxC Width High
RxC Width Low
250
85
DC
DC
DC
200
80
DC
DC
DC
85
80
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
18
Table 5. AC Characteristics of the Z84C90 (Continued)
8MHz
Min Max
10MHz1
12MHz
Max Min Max U/M
No. Symbol
63 TrRxC
64 TfRxC
Parameter
Min
RxC Rise Time
RxC Fall Time
60
60
60
60
ns
ns
ns
ns
ns
65 TsRxD(RxCr) RxD to RxC Rise Setup
0
0
66 ThRxCr(RxD) RxC Rise to RxD Hold Time
80
60
10
67 TdRxCr(W/Rf) RxC Rise to W/RDY Fall Delay
10 13
13
(Ready Mode)5
68 TdRxCf(INTf) RxC to INT Fall Delay5
10 13
10
4
13
7
ns
ns
69 TdRxCr
RxC Rise to SYNC Fall Delay
(Output Mode)
4
7
(SYNCf)
70 TsSYNCf
SYNC Fall to RxC Rise Setup
(External Sync Mode)
-100
-100
ns
(RxCr)
71 TdCf(IEOr)
72 TdCf(IEOf)
Clock Fall to IEO Rise Delay
Clock Fall to IEO Fall Delay
90
75
90
ns
ns
ns
110
73 ThDI(M1r,Rdr) Data Hold Time to M1 Rise or RD
0
0
Rise
74 TsM1/RD(C)
Setup time for M1 and RD to clock
Rising (with Data Valid)
20
20
Notes:
1. Maximum SIO data rate is f(CLOCK) divided by 5.
2. For a Z80 CPU above 8 MHz, one Wait state is required to meet this parameter.
3. These daisy chain parameters include contributions from the PIO, SIO, and CTC cells, and vary slightly
depending on how these are ordered by the KIO command register. See Table 5.
4. Counter mode only; when using a cycle time less than 3 TcC, parameter #37 must be met.
5. units are TcC.
Table 6.Daisy Chain Parameters
8 MHz
Min
10 MHz
Max Min
12 MHz
Max Min Max U/M
No. Symbol
Parameter
(PIO at #1)
(CTC at #1)
(SIO at #1)
181 TdM1(IEO)
160
180
230
150
150
200
125 ns
125 ns
200 ns
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
19
Table 6.Daisy Chain Parameters (Continued)
8 MHz
Min
10 MHz
Max Min
12 MHz
No. Symbol
Parameter
(PIO at #3)
(CTC at #3)
(SIO at #3)
Max Min Max U/M
192 TsIEI (IO)
170
140
160
160
115
130
130
ns
ns
170
180
ns
203 TdIEI(IEOf)
214 TdIEI(IEOr)
160
160
150
150
125 ns
125 ns
Notes: to calculate Z80 KIO daisy-chain timing, use the Z80 PIO, CTC, and SIO with I/O buffers on the chain. The
following are calculation formulas:
1. Parameter 18: M1 falling to IEO delay TdM1(IEO) = TdM1(IO)#1 + TdIEI(IEO)#2 + TdIEI(IEO)#3 + Output Buffer
Delay).
2. Parameter 19: IEI to IORQ falling setup time TsIEI(IO) = TdIEI(IEO)#1 + TdIEI(IEO)#2 + TdIEI(IEO)#3 + Input
Buffer Delay).
3. Parameter 20: IEI falling delay = TdIEI(IEOf) - TdIEI(IEOf)PIO + TdIEI(IEOf)CTC + TdIEI(IEOf)SIO + (Input buffer
Delay) + (Output Buffer Delay).
4. Parameter 21: IEI rising to IEO rising delay (after ED decode) - TdIEI(IEOr) = TdIEI(IEOr)PIO + TdIEI(IEOr)CTC
+ TdIEI(IEOr)SIO + ((Input buffer Delay) + (Output Buffer Delay).
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
20
1
Clock
2
3
5
4
A0–A3
CS
6
7
8
15
IORQ
RD
10
10
6
7
8
Read Cycle
Write Cycle
9
D0–D7
RD
12
11
D0–D7
47
48
49
WT/RDY
Wait Mode
48
WT/RDY
Ready Mode
Figure 10. I/O Read/Write Timing (M1 = 1)
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
21
CTS DCD
SYNC
50
51
52
54
TxC
TxD
53
55
56
57
58
WT/RDY
INT
59
60
RxC
62
61
63
66
64
65
RxD
WT/RDY
INT
67
68
70
SYNC
Figure 11. Serial I/O Timing
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
22
Clock
40
41
42
CLK/TRG
Counter
43
37
44
CLK/TRG
Timer
38
46
45
ZC/TO
INT
36
39
Figure 12. Counter/Timer Timing
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
23
Clock
IORQ
RD
34
Port C
Input
35
Port C
Output
24
25
23
RDY
STB
27
26
28
Mode 0
Mode 1
Mode 2
Mode 3
29
8
30
31
33
32
INT
Figure 13. Port I/O Read/Write Timing
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
24
T4
T3
T1
T2
Two
Two
Clock
INT
36
17
11
14
16
M1
7
IORQ
13
D0–D7
19
IE1
IE0
18
Figure 14. Interrupt Acknowledge Cycle
Clock
17
16
M1
RD
73
73
12
D0–D7
IE1
22
71
20
IE0
72
21
Figure 15. Op Code Fetch Cycle
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
25
Precautions & Limitations
The following describe the limitations of Revision A of the Z84C90 KIO.
Problem:
Daisy-chain. If the KIO has an Interrupt Pending during and Interrupt Acknowledge
cycle, KIO misses the status of the IE1 pin. This produces vector contention if there is a
higher interrupting device. It works fine if only one device is in the system.
Work Around:
There is no problem if the application has only one peripheral in the daisy chain. For two
or more peripherals in the system, a “hardware workaround circuit” is needed. Please con-
tact your local Zilog representatives to get more detailed information.
Problem:
Reset. KIO requires the M1 signal to exit from Reset state. If the M1 signal is not
received, the KIO can not be programmed. This is not a problem for users of the Z80
CPU.
Workaround:
If the CPU is other than a Z80, an M1 signal is needed to exit RESET status. Otherwise,
the KIO can not be programmed.
Problem:
Port C. When Port C is used as Parallel I/O (not as SIO’s modem signals) and there is a
status change on PC1 or PC6, the status of SYNCA or SYNCB (SIO cell) also changes.
Work Around:
Before using Port C as a parallel port, set the SIO modem signal mode back to Port C. This
procedure avoids the problem.
Problem:
Interrupt Acknowledge cycle. The KIO modifies the contents of the KIO control register
(specifically, the KIO modifies the daisy-chain configuration) if the CE pin is active dur-
ing the Interrupt Acknowledge cycle (with other conditions satisfied).
PS011802-0902
Z84C90
KIO Serial/Parallel Counter Timer
26
Work Around:
This problem could happen under the following narrowly defined conditions:
•
•
•
•
CE signal is active throughout the Interrupt Acknowledge cycle.
The address on the bus, A3–A0, is “110b”.
During this time, bit D3 is 1.
At the end of the Interrupt Acknowledge cycle, M1 goes inactive prior to the IORQ
signal.
•
At the time period of CE active, IORQ active, and M1 returns to the inactive state; all
during the rising edge of the clock.
This problem is not the case with the Z80 CPU. However, other CPUs could be affected.
One of the possible workarounds is to add the condition M1 not active to generate a CE
signal.
PS011802-0902
相关型号：
©2020 ICPDF网 联系我们和版权申明