Z8674312FEC [IXYS]
Microcontroller, 8-Bit, UVPROM, Z8 CPU, 12MHz, CMOS, PQFP44,;
| 型号： | Z8674312FEC |
| 厂家： | 
IXYS CORPORATION |
| 描述： | Microcontroller, 8-Bit, UVPROM, Z8 CPU, 12MHz, CMOS, PQFP44, 可编程只读存储器 时钟 微控制器 外围集成电路 |
| 文件： | 总58页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY PRODUCT SPECIFICATION
1
Z86E33/733/E34
Z86E43/743/E44
1
CMOS Z8 OTP MICROCONTROLLERS
FEATURES
■ Auto Power-On Reset (POR)
ROM
(KB)
RAM*
(Bytes)
I/O
Lines
Speed
(MHz)
Device
■ Programmable OTP Options:
RC Oscillator
Z86E33
Z86733
Z86E34
Z86E43
Z86743
Z86E44
4
8
237
237
237
236
236
236
24
24
24
32
32
32
12
12
12
12
12
12
EPROM Protect
Auto Latch Disable
Permanently Enabled WDT
Crystal Oscillator Feedback Resistor Disable
RAM Protect
16
4
8
16
■ Low-Power Consumption: 60 mW
Note: *General-Purpose
■ Fast Instruction Pointer: 0.75 µs
■ Standard Temperature (V = 3.5V to 5.5V)
CC
■ Two Standby Modes: STOP and HALT
■ Digital Inputs CMOS Levels, Schmitt-Triggered
■ Software Programmable Low EMI Mode
■ Extended Temperature (V = 4.5V to 5.5V)
CC
■ Available Packages:
28-Pin DIP/SOIC/PLCC OTP (E33/733/E34)
40-Pin DIP OTP (E43/743/E44)
44-Pin PLCC/QFP OTP (E43/743/E44)
■ Two Programmable 8-Bit Counter/Timers Each
with a 6-Bit Programmable Prescaler
■ Software Enabled Watch-Dog Timer (WDT)
■ Six Vectored, Priority Interrupts from Six
■ Push-Pull/Open-Drain Programmable on
Different Sources
Port 0, Port 1, and Port 2
■ Two Comparators
■ 24/32 Input/Output Lines
■ Clock-Free WDT Reset
■ On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC, RC, or External Clock Drive
GENERAL DESCRIPTION
The Z86E33/733/E34/E43/743/E44 8-Bit One-Time Pro-
grammable (OTP) Microcontrollers are members of Zilog's
single-chip Z8 MCU family featuring enhanced wake-up
tional control registers that allow easy access to register
mapped peripheral and I/O circuits.
®
For applications demanding powerful I/O capabilities, the
Z86E33/733/E34 have 24 pins, and the Z86E43/743/E44
have 32 pins of dedicated input and output. These lines are
grouped into four ports, eight lines per port, and are config-
urable under software control to provide timing, status sig-
circuitry, programmable Watch-Dog Timers, Low Noise
EMI options, and easy hardware/software system expan-
sion capability.
Four basic address spaces support a wide range of mem-
ory configurations. The designer has access to three addi-
DS97Z8X1500
P R E L I M I N A R Y
1
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
GENERAL DESCRIPTION (Continued)
nals, and parallel I/O with or without handshake, and ad-
dress/data bus for interfacing external memory.
Power connections follow conventional descriptions be-
low:
Notes: All signals with a preceding front slash, "/", are
active Low. For example, B//W (WORD is active Low);
/B/W (BYTE is active Low, only).
Connection
Power
Circuit
Device
V
V
DD
CC
Ground
GND
V
SS
(E43/743/E44 Only)
VCC
XTAL /AS /DS R//W /RESET
Output Input
GND
Machine Timing
&
Port 3
Instruction Control
RESET
WDT, POR
Counter/
Timers (2)
ALU
FLAGS
Interrupt
OTP
Control
Register
Pointer
Two Analog
Comparators
Program
Counter
Register File
Port 2
Port 0
Port 1
8
4
4
I/O
Address or I/O
(Nibble Programmable)
Address/Data or I/O
(Byte Programmable)
(E43/743/E44 Only)
(Bit Programmable)
Figure 1. Functional Block Diagram
P R E L I M I N A R Y
2
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
D7 - 0
1
AD 11- 0
Z8 MCU
AD 11- 0
Address
MUX
D7 - 0
Data
MUX
EPROM
AD 13- 0
Address
Counter
D7 - 0
Z8
Port 2
TEST ROM
OTP
Options
PGM +Test
Mode Logic
VPP
P33
CLR CLK
(P00) (P01)
/OE
P31
EPM
P32
/PGM
P02
/CE
XT1
Figure 2. EPROM Programming Block Diagram
DS97Z8X1500
P R E L I M I N A R Y
3
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
PIN IDENTIFICATION
Table 1. 40-Pin DIP Pin Identification
Standard Mode
1
R//w
P25
40
/DS
Pin #
Symbol
Function
Direction
P24
P23
P22
P21
P20
P03
P13
P12
GND
P02
P11
P10
P01
P00
P30
P36
P37
P35
/RESET
P26
P27
P04
P05
P06
P14
P15
P07
1
R//W
Read/Write
Output
2-4
5-7
8-9
10
11
P25-P27
P04-P06
P14-P15
P07
Port 2, Pins 5,6,7
Port 0, Pins 4,5,6
Port 1, Pins 4,5
Port 0, Pin 7
In/Output
In/Output
In/Output
In/Output
V
Power Supply
CC
12-13
14
P16-P17
XTAL2
XTAL1
P31-P33
P34
Port 1, Pins 6,7
Crystal Oscillator
Crystal Oscillator
Port 3, Pins 1,2,3
Port 3, Pin 4
Address Strobe
Reset
In/Output
Output
Input
DIP 40 - Pin
VCC
P16
P17
XTAL2
XTAL1
P31
15
16-18
19
Input
Output
Output
Input
20
/AS
P32
P33
P34
/AS
21
/RESET
P35
22
Port 3, Pin 5
Port 3, Pin 7
Port 3, Pin 6
Port 3, Pin 0
Port 0, Pins 0,1
Port 1, Pins 0,1
Port 0, Pin 2
Ground
Output
Output
Output
Input
23
P37
20
21
24
P36
25
P30
Figure 3. 40-Pin DIP Pin Configuration
Standard Mode
26-27
28-29
30
P00-P01
P10-P11
P02
In/Output
In/Output
In/Output
31
GND
32-33
34
P12-P13
P03
Port 1, Pins 2,3
Port 0, Pin 3
In/Output
In/Output
35-39
40
P20-P24
/DS
Port 2, Pins 0,1,2,3,4 In/Output
Data Strobe
Output
4
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
1
6
1
40
39
7
P21
P22
P23
P24
/DS
NC
R//W
P25
P26
P27
P04
P30
P36
P37
P35
/RESET
R//RL
/AS
P34
P33
P32
P31
44-Pin PLCC
17
29
28
18
Figure 4. 44-Pin PLCC Pin Configuration
Standard Mode
Table 2. 44-Pin PLCC Pin Identification
Table 2. 44-Pin PLCC Pin Identification
Pin #
Symbol
Function
Direction
Pin #
Symbol
Function
Direction
1-2
3-4
5
GND
Ground
28
XTAL1
Crystal Oscillator
Port 3, Pins 1,2,3
Port 3, Pin 4
Input
P12-P13
P03
Port 1, Pins 2,3
Port 0, Pin 3
In/Output
In/Output
29-31 P31-P33
Input
32
33
34
35
36
37
38
39
P34
Output
Output
6-10
11
P20-P24
/DS
Port 2, Pins 0,1,2,3,4 In/Output
/AS
Address Strobe
Data Strobe
Output
R//RL
/RESET
P35
ROM/ROMless select Input
12
NC
No Connection
Read/Write
Reset
Input
13
R//W
Output
Port 3, Pin 5
Port 3, Pin 7
Port 3, Pin 6
Port 3, Pin 0
Port 0, Pins 0,1
Port 1, Pins 0,1
Port 0, Pin 2
Output
Output
Output
Input
14-16 P25-P27
17-19 P04-P06
20-21 P14-P15
Port 2, Pins 5,6,7
Port 0, Pins 4,5,6
Port 1, Pins 4,5
Port 0, Pin 7
In/Output
In/Output
In/Output
In/Output
P37
P36
P30
22
P07
40-41 P00-P01
42-43 P10-P11
In/Output
In/Output
In/Output
23-24 VCC
Power Supply
Port 1, Pins 6,7
Crystal Oscillator
25-26 P16-P17
In/Output
Output
44
P02
27
XTAL2
DS97Z8X1500
P R E L I M I N A R Y
5
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
PIN IDENTIFICATION (Continued)
33
23
22
P21
P22
P23
P24
/DS
NC
R//W
P25
P26
P27
P04
34
P30
P36
P37
P35
/RESET
R//RL
/AS
P34
P33
44-Pin QFP
P32
P31
12
11
44
1
Figure 5. 44-Pin QFP Pin Configuration
Standard Mode
Table 3. 44-Pin QFP Pin Identification
Table 3. 44-Pin QFP Pin Identification
Pin # Symbol
Function
Direction
Pin # Symbol
22 P30
Function
Direction
1-2
3-4
5
P05-P06 Port 0, Pins 5,6
P14-P15 Port 1, Pins 4,5
In/Output
In/Output
In/Output
Port 3, Pin 0
Input
23-24 P00-P01 Port 0, Pin 0,1
25-26 P10-P11 Port 1, Pins 0,1
In/Output
In/Output
In/Output
P07
Port 0, Pin 7
6-7
8-9
10
11
VCC
Power Supply
27
P02
Port 0, Pin 2
Ground
P16-P17 Port 1, Pins 6,7
In/Output
Output
Input
28-29 GND
XTAL2
XTAL1
Crystal Oscillator
Crystal Oscillator
30-31 P12-P13 Port 1, Pins 2,3
In/Output
In/Output
In/Output
Output
32
P03
Port 0, Pin 3
12-14 P31-P33 Port 3, Pins 1,2,3
Input
33-37 P20-24
Port 2, Pins 0,1,2,3,4
Data Strobe
15
16
17
18
19
20
21
P34
Port 3, Pin 4
Address Strobe
ROM/ROMless select
Reset
Output
Output
Input
38
39
40
/DS
NC
/AS
No Connection
Read/Write
R//RL
/RESET
P35
R//W
Output
Input
41-43 P25-P27 Port 2, Pins 5,6,7
44 P04 Port 0, Pin 4
In/Output
In/Output
Port 3, Pin 5
Port 3, Pin 7
Port 3, Pin 6
Output
Output
Output
P37
P36
6
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
Table 4. 40-Pin DIP Package Pin Identification
EPROM Mode
1
NC
D5
40
NC
D4
Pin # Symbol Function
Direction
1
D6
D7
D3
D2
D1
D0
1
NC
No Connection
Data 5,6,7
2-4
5-10
11
D5-D7
NC
In/Output
NC
NC
NC
NC
NC
NC
VCC
NC
NC
NC
/CE
/OE
EPM
VPP
NC
NC
No Connection
Power Supply
V
CC
NC
NC
NC
GND
/PGM
NC
NC
CLK
CLR
NC
NC
NC
NC
NC
12-14 NC
No Connection
Chip Select
15
16
17
18
/CE
Input
Input
Input
Input
40-Pin DIP
/OE
EPM
VPP
Output Enable
EPROM Prog. Mode
Prog. Voltage
No Connection
Clear
19-25 NC
26
27
CLR
CLK
Input
Input
Clock
28-29 NC
No Connection
Prog. Mode
30
31
/PGM
GND
Input
Ground
20
21
32-34 NC
No Connection
Data 0,1,2,3,4
No Connection
35-39 D0-D4
In/Output
Figure 6. 40-Pin DIP Pin Configuration
EPROM Mode
40
NC
DS97Z8X1500
P R E L I M I N A R Y
7
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
PIN IDENTIFICATION (Continued)
6
1
40
39
7
D1
D2
D3
D4
NC
NC
NC
D5
D6
D7
NC
NC
NC
NC
NC
NC
NC
NC
NC
VPP
EPM
/OE
44 -Pin PLCC
17
29
28
18
Figure 7. 44-Pin PLCC Pin Configuration
EPROM Programming Mode
Table 5. 44-Pin PLCC Pin Configuration
EPROM Programming Mode
Table 5. 44-Pin PLCC Pin Configuration
EPROM Programming Mode
Pin #
Symbol Function Direction
Pin #
Symbol Function
Direction
1-2
GND
NC
Ground
29
30
/OE
Output Enable
Input
Input
3-5
No Connection
Data 0,1,2,3,4
No Connection
Data 5,6,7
EPM
EPROM Prog.
Mode
6-10
11-13
14-16
17-22
23-24
25-27
28
D0-D4
NC
In/Output
In/Output
31
V
Prog. Voltage
Input
PP
D5-D7
NC
32-39
40
NC
No Connection
Clear
No Connection
Power Supply
No Connection
Chip Select
CLR
CLK
NC
Input
Input
VCC
NC
41
Clock
42-43
44
No Connection
Prog. Mode
/CE
Input
/PGM
Input
8
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
1
33
23
22
D1
D2
D3
D4
NC
NC
NC
D5
D6
D7
NC
34
NC
NC
NC
NC
NC
NC
NC
NC
VPP
EPM
/OE
44 -Pin QFP
12
11
44
1
Figure 8. 44-Pin QFP Pin Configuration
EPROM Programming Mode
Table 6. 44-Pin QFP Pin Identification
EPROM Programming Mode
Table 6. 44-Pin QFP Pin Identification
EPROM Programming Mode
Pin #
Symbol Function
Direction
Pin #
Symbol Function Direction
1-5
6-7
NC
V
No Connection
24
CLK
NC
Clock
Input
Power Supply
25-26
27
No Connection
Prog. Mode
Ground
CC
8-10
11
NC
No Connection
Chip Select
/PGM
GND
NC
Input
/CE
/OE
EPM
Input
Input
Input
28-29
30-32
33-37
38-40
41-43
44
12
Output Enable
No Connection
Data 0,1,2,3,4
No Connection
Data 5,6,7
13
EPROM Prog.
Mode
D0-D4
NC
In/Output
In/Output
14
V
Prog. Voltage
Input
Input
D5-D7
NC
PP
15-22
23
NC
No Connection
Clear
No Connection
CLR
DS97Z8X1500
P R E L I M I N A R Y
9
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
PIN IDENTIFICATION (Continued)
1
P25
P26
P27
P04
P05
28
P24
P23
P22
P21
P20
P03
VSS
P02
P01
P00
P30
P36
P37
P35
4
26
25
1
5
XP0X5
P06
P07
VCC
XT2
XT1
P31
PX2X1X
P20
P03
VSS
P02
P01
P00
P06
P07
28-Pin
DIP/SOIC
28-Pin PLCC
VCC
XTAL2
XTAL1
P31
11
19
18
12
P32
P33
P34
14
15
Figure 9. Standard Mode
28-Pin DIP/SOIC Pin Configuration
Figure 10. Standard Mode
28-Pin PLCC Pin Configuration
Table 7. 28-Pin DIP/SOIC/PLCC
Pin Identification
Standard Mode
Pin # Symbol
Function
Direction
In/Output
1-3
4-7
8
P25-P27
P04-P07
Port 2, Pins 5,6,
Port 0, Pins 4,5,6,7 In/Output
Power Supply
V
CC
9
XTAL2
XTAL1
Crystal Oscillator Output
Crystal Oscillator Input
Port 3, Pins 1,2,3 Input
10
11-13 P31-P33
14-15 P34-P35
Port 3, Pins 4,5
Port 3, Pin 7
Port 3, Pin 6
Port 3, Pin 0
Output
Output
Output
Input
16
17
18
P37
P36
P30
19-21 P00-P02
Port 0, Pins 0,1,2 In/Output
Ground
22
23
V
SS
P03
Port 0, Pin 3
In/Output
In/Output
24-28 P20-P24
Port 2, Pins
0,1,2,3,4
10
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
Table 8. 28-Pin EPROM
Pin Identification
EPROM Mode
1
D5
D6
D7
28
D4
D3
D2
1
Pin #
Symbol Function
Direction
1-3
4-7
8
D5-D7
NC
Data 5,6,7
In/Output
NC
D1
NC
D0
No Connection
Power Supply
NC
NC
VCC
NC
/CE
/OE
EPM
VPP
NC
NC
VSS
/PGM
CLK
CLR
NC
NC
NC
NC
V
CC
28-Pin
DIP/SOIC
9
NC
No connection
Chip Select
10
11
12
/CE
/OE
EPM
Input
Input
Input
Output Enable
EPROM Prog.
Mode
13
V
Prog. Voltage
Input
PP
14
15
14-18 NC
No Connection
Clear
19
20
21
22
CLR
CLK
Clock
Figure 11. EPROM Programming Mode
28-Pin DIP/SOIC Pin Configuration
/PGM
Prog. Mode
Ground
Input
V
SS
23
NC
No Connection
Data 0,1,2,3,4
24-28 D0-D4
In/Output
4
26
25
1
5
XNXCX
NC
NC
VCC
NC
/CE
/OE
DXX1X
D0
NC
VSS
/PGM
CLK
CLR
28-Pin PLCC
11
19
18
12
Figure 12. EPROM Programming Mode
28-Pin PLCC Pin Configuration
DS97Z8X1500
P R E L I M I N A R Y
11
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
ABSOLUTE MAXIMUM RATINGS
Parameter
Min
Max
Units
Ambient Temperature under Bias
Storage Temperature
–40
–65
–0.6
+105
+150
+7
C
C
V
Voltage on any Pin with Respect to V [Note 1]
SS
Voltage on V Pin with Respect to V
–0.3
–0.6
+7
V
V
DD
SS
Voltage on XTAL1, P32, P33 and /RESET Pins with Respect to
[Note 2]
V
+1
DD
V
SS
Total Power Dissipation
1.21
220
W
Maximum Allowable Current out of V
mA
SS
Maximum Allowable Current into V
180
mA
DD
Maximum Allowable Current into an Input Pin [Note 3]
Maximum Allowable Current into an Open-Drain Pin [Note 4]
Maximum Allowable Output Current Sunk by Any I/O Pin
Maximum Allowable Output Current Sourced by Any I/O Pin
Maximum Allowable Output Current Sunk by /RESET Pin
–600
–600
+600
+600
25
µA
µA
mA
mA
mA
25
3
Notes:
1. This applies to all pins except XTAL pins and where otherwise noted.
2. There is no input protection diode from pin to VDD
.
3. This excludes XTAL pins.
4. Device pin is not at an output Low state.
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; functional operation of the
device at any condition above those indicated in the oper-
ational sections of these specifications is not implied. Ex-
posure to absolute maximum rating conditions for an ex-
tended period may affect device reliability.
Total power dissipation should not exceed 1.2 W for the
package. Power dissipation is calculated as follows:
Total Power Dissipation = V x [ I – (sum of I ) ]
DD
DD
OH
+ sum of [ (V – V ) x I
]
DD
OH
OH
+ sum of (V x I )
0L
0L
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin
(Test Load).
From Output
Under Test
150 pF
Figure 13. Test Load Diagram
12
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
CAPACITANCE
T = 25°C, V = GND = 0V, f = 1.0 MHz; unmeasured pins returned to GND.
A
CC
1
Parameter
Min
Max
Input capacitance
Output capacitance
I/O capacitance
0
0
0
12 pF
12 pF
12 pF
DC ELECTRICAL CHARACTERISTICS
T = 0 °C to +70 °C
A
V
Typical
@ 25°C Units
CC
Sym
Parameter
Note [3]
Min
Max
Conditions
Driven by
External Clock
Generator
Notes
V
V
Clock Input High Voltage
3.5V
5.5V
0.7 V
0.7 V
V
V
+0.3
1.8
2.5
V
V
CH
CC
CC
CC
+0.3
CC
Clock Input Low Voltage
3.5V
5.5V
GND-0.3
GND-0.3
0.2 V
0.2 V
0.9
1.5
V
V
Driven by
External Clock
Generator
CL
CC
CC
V
V
V
V
V
V
V
V
V
V
Input High Voltage
Input Low Voltage
3.5V
5.5V
0.7 V
0.7 V
V
V
+0.3
+0.3
2.5
2.5
V
V
IH
CC
CC
CC
CC
3.5V
5.5V
GND-0.3
GND-0.3
0.2 V
0.2 V
1.5
1.5
V
V
IL
CC
CC
Output High Voltage
Low EMI Mode
3.5V
5.5V
V
V
–0.4
-0.4
3.3
4.8
V
V
I
= – 0.5 mA
OH
OH1
OL
CC
OH
CC
Output High Voltage
3.5V
5.5V
V
V
–0.4
–0.4
3.3
4.8
V
V
I
I
= -2.0 mA
= -2.0 mA
CC
OH
CC
OH
Output Low Voltage
Low EMI Mode
3.5V
5.5V
0.4
0.4
0.2
0.2
V
V
I
I
= +1.0 mA
= +1.0 mA
OL
OL
Output Low Voltage
3.5V
5.5V
0.4
0.4
0.1
0.1
V
V
I
I
= + 4.0 mA
= + 4.0 mA
8
8
OL1
OL2
RH
RL
OL
OL
Output Low Voltage
3.5V
5.5V
1.2
1.2
0.5
0.5
V
V
I
I
= + 10 mA
= + 10 mA
8
8
OL
OL
Reset Input High
Voltage
3.5V
5.5V
.8 V
.8 V
V
1.7
2.1
V
V
13
13
CC
CC
CC
CC
V
Reset Input Low Voltage
3.5V
5.5V
GND –0.3
GND –0.3
0.2 V
0.2 V
1.3
1.7
V
V
13
13
CC
CC
Reset Output Low
Voltage
3.5V
5.5V
0.6
0.6
0.3
0.2
V
V
I
I
= +1.0 mA
= +1.0 mA
13
13
OLR
OL
OL
V
V
Comparator Input
Offset Voltage
3.5V
5.5V
25
25
10
10
mV
mV
OFFSET
Input Common Mode
Voltage Range
3.5V
5.5V
0
0
V
V
-1.0V
V
V
10
10
ICR
CC
CC
-1.0V
I
I
Input Leakage
3.5V
5.5V
–1
–1
2
2
0.032
0.032
µA
µA
V
V
= 0V, V
= 0V, V
IL
IN
IN
CC
CC
Output Leakage
3.5V
5.5V
–1
-1
2
2
0.032
0.032
µA
µA
V
V
= 0V, V
= 0V, V
OL
IN
IN
CC
CC
DS97Z8X1500
P R E L I M I N A R Y
13
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
DC ELECTRICAL CHARACTERISTICS (Continued)
T = 0 °C to +70 °C
A
V
Typical
CC
Sym
Parameter
Note [3]
Min
Max
@ 25°C Units
Conditions
Notes
I
I
I
Reset Input Current
3.5V
5.5V
–20
–20
–130
–180
–65
–112
µA
µA
IR
Supply Current
3.5V
5.5V
15
20
5
15
mA @ 12 MHz
mA @ 12 MHz
4,5
4,5
CC
Standby Current
Halt Mode
3.5V
5.5V
4
6
2
4
mA
mA
V
= 0V, V
CC
4,5
4,5
CC1
CC2
IN
@ 12 MHz
3.5V
5.5V
3
5
1.5
3
mA Clock Divide by
mA 16 @ 12 MHz
4,5
4,5
I
Standby Current
Stop Mode
3.5V
5.5V
3.5V
5.5V
10
10
15
30
2
3
7
µA
µA
µA
µA
V
V
V
V
= 0V, V
= 0V, V
= 0V, V
= 0V, V
6,11
6,11
6,11,14
6,11,14
IN
IN
IN
IN
CC
CC
CC
CC
10
I
I
Auto Latch
Low Current
3.5V
5.5V
0.7
1.4
8
15
2.4
4.7
µA 0V <V <V
9
9
ALL
IN
CC
CC
µA
0V <V <V
IN
Auto Latch
High Current
3.5V
5.5V
–0.6
–1
–5
–8
–1.8
–3.8
µA 0V<V <V
9
9
ALH
IN
CC
CC
µA
0V<V <V
IN
T
Power On Reset
3.5V
5.5V
3.0
2.0
24
13
7
4
ms
ms
POR
V
Auto Reset Voltage
2.3
3.0
2.8
V
1,7
LV
Notes:
1. Device does function down to the Auto Reset voltage.
2. GND=0V
3. The VCC voltage specification of 5.5V guarantees 5.0V ± 0.5V and
the VCC voltage specification of 3.5V guarantees only 3.5V.
4. All outputs unloaded, I/O pins floating, inputs at rail.
5. CL1= CL2 = 22 pF
6. Same as note [4] except inputs at VCC.
7. Max. temperature is 70°C.
8. STD Mode (not Low EMI Mode)
9. Auto Latch (mask option) selected
10. For analog comparator inputs when analog comparators are
enabled.
11. Clock must be forced Low, when XTAL1 is clock driven and XTAL2
is floating.
12. Typicals are at VCC = 5.0V and VCC = 3.5V
13. Z86E43/743/E44 only.
14. WDT running
14
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
T =–40 °C to +105 °C
A
V
Typical
@ 25°C Units
CC
Sym
Parameter
Note [3]
Min
Max
Conditions
Notes
1
V
V
V
V
V
Clock Input High
Voltage
4.5V
5.5V
0.7 V
0.7 V
V
V
+0.3
2.5
2.5
V
V
Driven by External
Clock Generator
CH
CL
IH
CC
CC
CC
+0.3
CC
Clock Input Low
Voltage
4.5V
5.5V
GND-0.3
GND-0.3
0.2 V
0.2 V
1.5
1.5
V
V
Driven by External
Clock Generator
CC
CC
Input High Voltage
4.5V
5.5V
0.7 V
0.7 V
V
V
+0.3
+0.3
2.5
2.5
V
V
CC
CC
CC
CC
Input Low Voltage
4.5V
5.5V
GND-0.3
GND-0.3
0.2 V
0.2 V
1.5
1.5
V
V
IL
CC
CC
Output High
Voltage Low EMI
Mode
4.5V
5.5V
V
V
–0.4
–0.4
4.8
4.8
V
V
I
I
= – 0.5 mA
= – 0.5 mA
8
8
OH
CC
OH
CC
OH
V
V
V
V
V
V
Output High Voltage
4.5V
5.5V
V
V
–0.4
–0.4
4.8
4.8
V
V
I
I
= -2.0 mA
= -2.0 mA
8
8
OH1
CC
OH
CC
OH
Output Low Voltage
Low EMI Mode
4.5V
5.5V
0.4
0.4
0.2
0.2
V
V
I
I
= +1.0 mA
= +1.0 mA
OL
OL
OL
Output Low Voltage
4.5V
5.5V
0.4
0.4
0.1
0.1
V
V
I
I
= + 4.0 mA
= +4.0 mA
8
8
OL1
OL2
RH
OL
OL
Output Low Voltage
4.5V
5.5V
1.2
1.2
0.5
0.5
V
V
I
I
= + 12 mA
= + 12 mA
8
8
OL
OL
Reset Input High
Voltage
4.5V
5.5V
.8 V
.8 V
V
1.7
2.1
V
V
13
13
CC
CC
CC
CC
V
Reset Output Low
Voltage
4.5V
5.5V
0.6
0.6
0.3
0.2
V
V
I
I
= +1.0 mA
= +1.0 mA
13
13
OLR
OL
OL
V
V
Comparator Input
Offset Voltage
4.5V
5.5V
25
25
10
10
mV
mV
OFFSET
Input Common
Mode Voltage
Range
4.5V
5.5V
0
0
V
V
-1.5V
V
V
10
10
ICR
CC
CC
-1.5V
I
I
Input Leakage
4.5V
5.5V
–1
–1
2
2
<1
<1
µA
µA
V
V
= 0V, V
= 0V, V
IL
IN
IN
CC
CC
Output Leakage
4.5V
5.5V
–1
–1
2
2
<1
<1
µA
µA
V
V
= 0V, V
= 0V, V
OL
IN
IN
CC
CC
I
I
I
Reset Input Current
Supply Current
4.5V
5.5V
–18
–18
–180
–180
–112
–112
µA
µA
13
13
IR
4.5V
5.5V
20
20
15
15
mA @ 12 MHz
mA @ 12 MHz
4,5
4,5
CC
CC1
Standby Current
Halt Mode
4.5V
6
2
mA
V
= 0V, V
4,5
IN
CC
CC
@ 12 MHz
= 0V, V
5.5V
6
4
mA
4,5
V
IN
@ 12 MHz
I
Standby Current
(Stop Mode)
4.5V
5.5V
4.5V
5.5V
10
10
40
40
2
3
10
10
µA
µA
µA
µA
V
V
V
V
= 0V, V
= 0V, V
= 0V, V
= 0V, V
6,11
6,11
6,11,14
6,11,14
CC2
IN
IN
IN
IN
CC
CC
CC
CC
DS97Z8X1500
P R E L I M I N A R Y
15
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
DC ELECTRICAL CHARACTERISTICS (Continued)
T =–40 °C to +105 °C
A
V
Typical
CC
Sym
Parameter
Note [3]
Min
Max
@ 25°C Units
Conditions
Notes
I
I
Auto Latch Low
Current
4.5V
5.5V
1.4
1.4
20
20
4.7
4.7
µA
µA
0V < V < V
9
9
ALL
IN
CC
CC
0V < V < V
IN
Auto Latch High
Current
4.5V
5.5V
–1.0
–1.0
–10
–10
–3.8
–3.8
µA
µA
0V < V < V
9
9
ALH
IN
CC
CC
0V < V < V
IN
T
Power On Reset
4.5V
5.5V
2.0
2.0
14
14
4
4
ms
ms
POR
V
Auto Reset Voltage
2.0
3.3
2.8
V
1
LV
1. Device does function down to the Auto Reset voltage.
2. GND=0V
3. The VCC voltage specification of 5.5V guarantees 5.0V ± 0.5V.
4. All outputs unloaded, I/O pins floating, inputs at rail.
5. CL1= CL2 = 22 pF
6. Same as note [4] except inputs at VCC
.
7. Maximum temperature is 70°C
8. STD Mode (not Low EMI Mode)
9. Auto Latch (mask option) selected
10. For analog comparator inputs when analog comparators are
enabled.
11. Clock must be forced Low, when XTAL1 is clock driven and XTAL2
is floating.
12. Typicals are at VCC = 5.0V
13. Z86E43/743/E44 only.
14. WDT is not running.
16
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
R//W, /DM
1
13
19
12
Port 0
Port 1
/AS
16
18
3
A7 - A0
D7 - D0 IN
1
2
9
1
1
8
4
6
5
/DS
(Read)
17
10
Port1
A7 - A0
D7 - D0 OUT
14
15
7
/DS
(Write)
Figure 14. External I/O or Memory Read/Write Timing
(Z86E43/743/E44 Only)
DS97Z8X1500
P R E L I M I N A R Y
17
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
DC ELECTRICAL CHARACTERISTICS (Continued)
T = 0°C to 70°C
A
12 MHz
Note [3]
V
No
Symbol
TdA(AS)
Parameter
Min
Max
Units
Notes
CC
1
Address Valid to /AS Rise
Delay
3.5V
5.5V
35
35
ns
ns
2
2
2
3
4
5
6
7
8
9
TdAS(A)
TdAS(DR)
TwAS
/AS Rise to Address Float
Delay
3.5V
5.5V
45
45
ns
ns
2
2
/AS Rise to Read Data
Req’d Valid
3.5V
5.5V
250
250
ns
ns
1,2
1,2
/AS Low Width
3.5V
5.5V
55
55
ns
ns
2
2
TdAS(DS)
TwDSR
Address Float to /DS Fall
/DS (Read) Low Width
/DS (Write) Low Width
3.5V
5.5V
0
0
ns
ns
3.5V
5.5V
200
200
ns
ns
1,2
1,2
TwDSW
3.5V
5.5V
110
110
ns
ns
1,2
1,2
TdDSR(DR)
ThDR(DS)
/DS Fall to Read Data Req’d
Valid
3.5V
5.5V
150
150
ns
ns
1,2
1,2
Read Data to /DS Rise Hold
Time
3.5V
5.5V
0
0
ns
ns
2
2
10 TdDS(A)
/DS Rise to Address Active
Delay
3.5V
5.5V
45
55
ns
ns
2
2
11 TdDS(AS)
12 TdR/W(AS)
13 TdDS(R/W)
14 TdDW(DSW)
15 TdDS(DW)
16 TdA(DR)
/DS Rise to /AS Fall Delay
3.5V
5.5V
30
45
ns
ns
2
2
R//W Valid to /AS Rise
Delay
3.5V
5.5V
45
45
ns
ns
2
2
/DS Rise to R//W Not Valid
3.5V
5.5V
45
45
ns
ns
2
2
Write Data Valid to /DS Fall
(Write) Delay
3.5V
5.5V
55
55
ns
ns
2
2
/DS Rise to Write Data Not
Valid Delay
3.5V
5.5V
45
55
ns
ns
2
2
Address Valid to Read Data
Req’d Valid
3.5V
5.5V
310
310
ns
ns
1,2
1,2
17 TdAS(DS)
18 TdDM(AS)
19 ThDS(AS)
/AS Rise to /DS Fall Delay
3.5V
5.5V
65
65
ns
ns
2
2
/DM Valid to /AS Rise Delay
3.5V
5.5V
35
35
ns
ns
2
2
/DS Valid to Address Valid
Hold Time
3.5V
5.5V
35
35
ns
ns
2
2
Notes:
1. When using extended memory timing, add 2 TpC.
2. Timing numbers given are for minimum TpC.
3. The VCC voltage specification of 5.5V guarantees 5.0V ±0.5V and
the VCC voltage specification of 3.5V guarantees only 3.5V
Standard Test Load
All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
For Standard Mode (not Low-EMI Mode for outputs) with SMR D1 = 0, D0 = 0.
18
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
T = -40°C to 105°C
A
12 MHz
Note [3]
1
V
No
Symbol
TdA(AS)
Parameter
Min
Max
Units
Notes
CC
1
Address Valid to /AS Rise
Delay
4.5V
5.5V
35
35
ns
ns
2
2
2
3
4
5
6
7
8
9
TdAS(A)
TdAS(DR)
TwAS
/AS Rise to Address Float
Delay
4.5V
5.5V
45
45
ns
ns
2
2
/AS Rise to Read Data
Req’d Valid
4.5V
5.5V
250
250
ns
ns
1,2
1,2
/AS Low Width
4.5V
5.5V
55
55
ns
ns
2
2
TdAS(DS)
TwDSR
Address Float to /DS Fall
/DS (Read) Low Width
/DS (Write) Low Width
4.5V
5.5V
0
0
ns
ns
4.5V
5.5V
200
200
ns
ns
1,2
1,2
TwDSW
4.5V
5.5V
110
110
ns
ns
1,2
1,2
TdDSR(DR)
ThDR(DS)
/DS Fall to Read Data Req’d
Valid
4.5V
5.5V
150
150
ns
ns
1,2
1,2
Read Data to /DS Rise Hold
Time
4.5V
5.5V
0
0
ns
ns
2
2
10 TdDS(A)
/DS Rise to Address Active
Delay
4.5V
5.5V
45
55
ns
ns
2
2
11 TdDS(AS)
12 TdR/W(AS)
13 TdDS(R/W)
14 TdDW(DSW)
15 TdDS(DW)
16 TdA(DR)
/DS Rise to /AS Fall Delay
4.5V
5.5V
45
45
ns
ns
2
2
R//W Valid to /AS Rise
Delay
4.5V
5.5V
45
45
ns
ns
2
2
/DS Rise to R//W Not Valid
4.5V
5.5V
45
45
ns
ns
2
2
Write Data Valid to /DS Fall
(Write) Delay
4.5V
5.5V
55
55
ns
ns
2
2
/DS Rise to Write Data Not
Valid Delay
4.5V
5.5V
55
55
ns
ns
2
2
Address Valid to Read Data
Req’d Valid
4.5V
5.5V
310
310
ns
ns
1,2
1,2
17 TdAS(DS)
18 TdDM(AS)
19 ThDS(AS)
/AS Rise to /DS Fall Delay
4.5V
5.5V
65
65
ns
ns
2
2
/DM Valid to /AS Rise Delay
4.5V
5.5V
35
35
ns
ns
2
2
/DS Valid to Address Valid
Hold Time
4.5V
5.5V
35
35
ns
ns
2
2
Notes:
1. When using extended memory timing, add 2 TpC.
2. Timing numbers given are for minimum TpC.
3. The VCC voltage specification of 5.5V guarantees 5.0V ± 0.5V and
the VCC voltage specification of 3.5V guarantees only 3.5V
Standard Test Load
All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
For Standard Mode (not Low-EMI Mode for outputs) with SMR, D1 = 0, D0 = 0.
DS97Z8X1500
P R E L I M I N A R Y
19
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
DC ELECTRICAL CHARACTERISTICS (Continued)
3
1
Clock
2
2
3
7
7
TIN
4
5
6
IRQN
8
9
Clock
Setup
11
Stop
Mode
Recovery
Source
10
Figure 15. Additional Timing Diagram
20
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
Additional Timing Table (Divide-By-One Mode)
T = 0 °C to +70 °C
A
1
4 MHz
6 MHz
V
CC
No
Symbol
TpC
Parameter
Note [6]
Min
Max
Min
Max
Units
Notes
1
Input Clock Period
3.5V
5.5V
250
250
DC
DC
166
166
DC
DC
ns
ns
1,7,8
1,7,8
2
3
4
5
6
7
TrC,TfC
TwC
Clock Input Rise &
Fall Times
3.5V
5.5V
25
25
25
25
ns
ns
1,7,8
1,7,8
Input Clock Width
3.5V
5.5V
100
100
100
100
ns
ns
1,7,8
1,7,8
TwTinL
TwTinH
TpTin
Timer Input Low
Width
3.5V
5.5V
100
70
100
70
ns
ns
1,7,8
1,7,8
Timer Input High
Width
3.5V
5.5V
5TpC
5TpC
5TpC
5TpC
1,7,8
1,7,8
Timer Input Period
3.5V
5.5V
8TpC
8TpC
8TpC
8TpC
1,7,8
1,7,8
TrTin, TfTin Timer Input Rise
& Fall Timer
3.5V
5.5V
100
100
100
100
ns
ns
1,7,8
1,7,8
8A TwIL
8B TwIL
Int. Request Low
Time
3.5V
5.5V
100
70
100
70
ns
ns
1,2,7,8
1,2,7,8
Int. Request Low
Time
3.5V
5.5V
5TpC
5TpC
5TpC
5TpC
1,3,7,8
1,3,7,8
9
TwIH
Int. Request Input
High Time
3.5V
5.5V
5TpC
5TpC
5TpC
5TpC
1,2,7,8
1,2,7,8
10
Twsm
STOP Mode
Recovery Width
Spec
3.5V
5.5V
12
12
12
12
ns
ns
4,8
4,8
11
Tost
Oscillator Startup
Time
3.5V
5.5V
5TpC
5TpC
5TpC
5TpC
4,8,9
4,8,9
Notes:
1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
2. Interrupt request via Port 3 (P31-P33).
3. Interrupt request via Port 3 (P30).
4. SMR-D5 = 1, POR STOP Mode Delay is on.
5. Reg. WDTMR.
6. The VCC voltage specification of 5.5V guarantees 5.0V ±0.5V and
the VCC voltage specification of 3.5V guarantees 3.5V only.
7. SMR D1 = 0.
8. Maximum frequency for internal system clock is 4 MHz when
using Low EMI OSC PCON Bit D7 = 0.
9. For RC and LC oscillator, and for oscillator driven by clock driver.
DS97Z8X1500
P R E L I M I N A R Y
21
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
Additional Timing Table (Divide-By-One Mode)
T
= -40 °C to +105 °C
A
4 MHz
6 MHz
V
CC
No
Symbol
TpC
Parameter
Note [6]
Min
Max
Min
Max
Units
Notes
1
Input Clock Period
4.5V
5.5V
250
250
DC
DC
166
166
DC
DC
ns
ns
1,7,8
1,7,8
2
3
4
5
6
7
TrC,TfC
TwC
Clock Input Rise &
Fall Times
4.5V
5.5V
25
25
25
25
ns
ns
1,7,8
1,7,8
Input Clock Width
4.5V
5.5V
100
100
100
100
ns
ns
1,7,8
1,7,8
TwTinL
TwTinH
TpTin
Timer Input Low
Width
4.5V
5.5V
100
70
100
70
ns
ns
1,7,8
1,7,8
Timer Input High
Width
4.5V
5.5V
5TpC
5TpC
5TpC
5TpC
1,7,8
1,7,8
Timer Input Period
4.5V
5.5V
8TpC
8TpC
8TpC
8TpC
1,7,8
1,7,8
TrTin, TfTin Timer Input Rise
& Fall Timer
4.5V
5.5V
100
100
100
100
ns
ns
1,7,8
1,7,8
8A TwIL
8B TwIL
Int. Request Low
Time
4.5V
5.5V
100
70
100
70
ns
ns
1,2,7,8
1,2,7,8
Int. Request Low
Time
4.5V
5.5V
5TpC
5TpC
5TpC
5TpC
1,3,7,8
1,3,7,8
9
TwIH
Int. Request Input
High Time
4.5V
5.5V
5TpC
5TpC
5TpC
5TpC
1,2,7,8
1,2,7,8
10
Twsm
STOP Mode
Recovery Width
Spec
4.5V
5.5V
12
12
12
12
ns
ns
4,8
4,8
11
Tost
Oscillator Startup
Time
4.5V
5.5V
5TpC
5TpC
5TpC
5TpC
4,8,9
4,8,9
Notes:
1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
2. Interrupt request via Port 3 (P31-P33).
3. Interrupt request via Port 3 (P30).
4. SMR-D5 = 1, POR STOP Mode Delay is on.
5. Reg. WDTMR.
6. The VCC voltage specification of 5.5V guarantees 5.0V ±0.5V and
the VCC voltage specification of 3.5V guarantees 3.5V only.
7. SMR D1 = 0.
8. Maximum frequency for internal system clock is 4 MHz when
using Low EMI OSC PCON Bit D7 = 0.
9. For RC and LC oscillator, and for oscillator driven by clock driver.
22
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
Handshake Timing Diagrams
1
Data In Valid
Data In
Next Data In Valid
1
2
3
/DAV
Delayed DAV
(Input)
4
5
6
RDY
Delayed RDY
(Output)
Figure 16. Input Handshake Timing
Data Out
Data Out Valid
Next Data Out Valid
7
/DAV
Delayed DAV
(Output)
8
9
11
10
RDY
Delayed RDY
(Input)
Figure 17. Output Handshake Timing
DS97Z8X1500
P R E L I M I N A R Y
23
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
Additional Timing Table (Divide by Two Mode)
T = 0 °C to +70 °C
A
4 MHz
12 MHz
V
CC
No
Symbol
TpC
Parameter
Note [6]
Min
Max
Min
Max
Units Conditions Notes
1
Input Clock Period
3.5V
5.5V
62.5
62.5
DC
DC
250
250
DC
DC
ns
ns
1,7,8
1,7,8
2
TrC,TfC
TwC
Clock Input Rise &
Fall Times
3.5V
5.5V
15
15
25
25
ns
ns
1,7,8
1,7,8
3
Input Clock Width
3.5V
5.5V
31
31
31
31
ns
ns
1,7,8
1,7,8
4
TwTinL
TwTinH
TpTin
Timer Input Low
Width
3.5V
5.5V
70
70
70
70
ns
ns
1,7,8
1,7,8
5
Timer Input High
Width
3.5V
5.5V
5TpC
5TpC
5TpC
5TpC
1,7,8
1,7,8
6
Timer Input Period
3.5V
5.5V
8TpC
8TpC
8TpC
8TpC
1,7,8
1,7,8
7
TrTin, TfTin Timer Input Rise
& Fall Timer
3.5V
5.5V
100
100
100
100
ns
ns
1,7,8
1,7,8
8A
8B
9
TwIL
TwIL
TwIH
Twsm
Int. Request Low
Time
3.5V
5.5V
70
70
70
70
ns
ns
1,2,7,8
1,2,7,8
Int. Request Low
Time
3.5V
5.5V
5TpC
5TpC
5TpC
5TpC
1,3,7,8
1,3,7,8
Int. Request Input
High Time
3.5V
5.5V
5TpC
5TpC
5TpC
5TpC
1,2,7,8
1,2,7,8
10
STOP Mode
Recovery Width
Spec
3.5V
5.5V
12
12
12
12
ns
ns
4,8
4,8
11
12
Tost
Oscillator Startup
Time
3.5V
5.5V
5TpC
5TpC
5TpC
5TpC
4,8
4,8
Twdt
Watch-Dog Timer
Delay Time Before
Timeout
3.5V
5.5V
10
5
10
5
ms
ms
D0 = 0
D1 = 0
5,11
5,11
3.5V
5.5V
20
10
20
10
ms
ms
D0 = 1
D1 = 0
5,11
5,11
3.5V
5.5V
40
20
40
20
ms
ms
D0 = 0
D1 = 1
5,11
5,11
3.5V
5.5V
160
80
160
80
ms
ms
D0 = 1
D1 = 1
5,11
5,11
Notes:
1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
2. Interrupt request via Port 3 (P31-P33)
3. Interrupt request via Port 3 (P30)
4. SMR-D5 = 1, POR STOP Mode Delay is on
5. Reg. WDTMR
6. The VCC voltage specification of 5.5V guarantees 5.0V ±0.5V and
the VCC voltage specification of 3.5V guarantees 3.5V only.
7. SMR D1 = 0
8. Maximum frequency for internal system clock is 2 MHz when using
Low EMI OSC PCON Bit D7 = 0.
9. For RC and LC oscillator, and for oscillator driven by clock driver.
10. Standard Mode (not Low EMI output ports)
11. Using internal RC
24
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
Additional Timing Table (Divide by Two Mode)
T = -40 °C to +105 °C
A
1
4 MHz
12 MHz
V
CC
No
Symbol
TpC
Parameter
Note [6]
Min
Max
Min
Max
Units Conditions Notes
1
Input Clock Period
4.5V
5.5V
62.5
62.5
DC
DC
250
250
DC
DC
ns
ns
1,7,8
1,7,8
2
TrC,TfC
TwC
Clock Input Rise &
Fall Times
4.5V
5.5V
15
15
25
25
ns
ns
1,7,8
1,7,8
3
Input Clock Width
4.5V
5.5V
31
31
31
31
ns
ns
1,7,8
1,7,8
4
TwTinL
TwTinH
TpTin
Timer Input Low
Width
4.5V
5.5V
70
70
70
70
ns
ns
1,7,8
1,7,8
5
Timer Input High
Width
4.5V
5.5V
5TpC
5TpC
5TpC
5TpC
1,7,8
1,7,8
6
Timer Input Period
4.5V
5.5V
8TpC
8TpC
8TpC
8TpC
1,7,8
1,7,8
7
TrTin, TfTin Timer Input Rise
& Fall Timer
4.5V
5.5V
100
100
100
100
ns
ns
1,7,8
1,7,8
8A
8B
9
TwIL
TwIL
TwIH
Twsm
Int. Request Low
Time
4.5V
5.5V
70
70
70
70
ns
ns
1,2,7,8
1,2,7,8
Int. Request Low
Time
4.5V
5.5V
5TpC
5TpC
5TpC
5TpC
1,3,7,8
1,3,7,8
Int. Request Input
High Time
4.5V
5.5V
5TpC
5TpC
5TpC
5TpC
1,2,7,8
1,2,7,8
10
STOP Mode
Recovery Width
Spec
4.5V
5.5V
12
12
12
12
ns
ns
4,8
4,8
11
12
Tost
Oscillator Startup
Time
4.5V
5.5V
5TpC
5TpC
5TpC
5TpC
4,8
4,8
Twdt
Watch-Dog Timer
Delay Time Before
Timeout
4.5V
5.5V
5
5
5
5
ms
ms
D0 = 0
D1 = 0
5,11
5,11
4.5V
5.5V
10
10
10
10
ms
ms
D0 = 1
D1 = 0
5,11
5,11
4.5V
5.5V
20
20
20
20
ms
ms
D0 = 0
D1 = 1
5,11
5,11
4.5V
5.5V
80
80
80
80
ms
ms
D0 = 1
D1 = 1
5,11
5,11
Notes:
1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
2. Interrupt request via Port 3 (P31-P33)
3. Interrupt request via Port 3 (P30)
4. SMR-D5 = 1, POR STOP Mode Delay is on
5. Reg. WDTMR
6. The VCC voltage specification of 5.5V guarantees 5.0V ±0.5V and
the VCC voltage specification of 3.5V guarantees 3.5V only.
7. SMR D1 = 0
8. Maximum frequency for internal system clock is 2 MHz when using
Low EMI OSC PCON Bit D7 = 0.
9. For RC and LC oscillator, and for oscillator driven by clock driver.
10. Standard Mode (not Low EMI output ports)
11. Using internal RC
DS97Z8X1500
P R E L I M I N A R Y
25
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
PIN FUNCTIONS
XTAL2 Crystal 2 (time-based output). This pin connects a
parallel-resonant crystal, ceramic resonator, LC, or RC
network to the on-chip oscillator output.
EPROM Programming Mode
D7-D0 Data Bus. The data can be read from or written to
external memory through the data bus.
R//W Read/Write (output, write Low). The R//W signal is
Low when the CCP is writing to the external program or
data memory (Z86E43/743/E44 only).
V
Power Supply. This pin must supply 5V during the
CC
EPROM read mode and 6V during other modes.
/CE Chip Enable (active Low). This pin is active during
EPROM Read Mode, Program Mode, and Program Verify
Mode.
/RESET Reset (input, active Low). Reset will initialize the
MCU. Reset is accomplished either through Power-On,
Watch-Dog Timer reset, STOP-Mode Recovery, or exter-
nal reset. During Power-On Reset and Watch-Dog Timer
Reset, the internally generated reset drives the reset pin
low for the POR time. Any devices driving the reset line
must be open-drain in order to avoid damage from a pos-
sible conflict during reset conditions. Pull-up is provided in-
ternally. After the POR time, /RESET is a Schmitt-trig-
gered input. (/Reset is available on Z86E43/743/E44 only.)
/OE Output Enable (active Low). This pin drives the direc-
tion of the Data Bus. When this pin is Low, the Data Bus is
output, when High, the Data Bus is input.
EPM EPROM Program Mode. This pin controls the differ-
ent EPROM Program Mode by applying different voltages.
V
age.
Program Voltage. This pin supplies the program volt-
PP
To avoid asynchronous and noisy reset problems, the
Z86E43/743/E44 is equipped with a reset filter of four exter-
nal clocks (4TpC). If the external reset signal is less than
4TpC in duration, no reset occurs. On the fifth clock after
the reset is detected, an internal RST signal is latched and
held for an internal register count of 18 external clocks, or
for the duration of the external reset, whichever is longer.
During the reset cycle, /DS is held active Low while /AS cy-
cles at a rate of TpC/2. Program execution begins at loca-
tion 000CH, 5-10 TpC cycles after /RESET is released. For
Power-On Reset, the reset output time is 5 ms. The
Z86E43/743/E44 does not reset WDTMR, SMR, P2M, and
P3M registers on a STOP-Mode Recovery operation.
/PGM Program Mode (active Low). When this pin is Low,
the data is programmed to the EPROM through the Data
Bus.
CLR Clear (active High). This pin resets the internal ad-
dress counter at the High Level.
CLK Address Clock. This pin is a clock input. The internal
address counter increases by one for each clock cycle.
Application Precaution
The production test-mode environment may be enabled
accidentally during normal operation if excessive noise
/ROMless (input, active Low). This pin, when connected to
GND, disables the internal ROM and forces the device to
function as a Z86C90/C89 ROMless Z8. (Note that, when
surges above V occur on pins P31 and /RESET.
CC
In addition, processor operation of Z8 OTP devices may be
left unconnected or pulled High to V , the device func-
CC
affected by excessive noise surges on the V , EPM, /OE
tions normally as a Z8 ROM version).
PP
pins while the microcontroller is in Standard Mode.
Note: When using in ROM Mode in High EMI (noisy) envi-
Recommendations for dampening voltage surges in both
test and OTP mode include the following:
ronment, the ROMless pins should be connected directly
to V
.
CC
■ Using a clamping diode to V
/DS (output, active Low). Data Strobe is activated once for
each external memory transfer. For a READ operation,
data must be available prior to the trailing edge of /DS. For
WRITE operations, the falling edge of /DS indicates that
output data is valid.
CC
■ Adding a capacitor to the affected pin
■ Enable EPROM/Test Mode Disable OTP option bit.
Standard Mode
/AS (output, active Low). Address Strobe is pulsed once at
the beginning of each machine cycle for external memory
transfer. Address output is from Port 0/Port 1 for all exter-
nal programs. Memory address transfers are valid at the
trailing edge of /AS. Under program control, /AS is placed
in the high-impedance state along with Ports 0 and 1, Data
Strobe, and Read/Write.
XTAL Crystal 1 (time-based input). This pin connects a
parallel-resonant crystal, ceramic resonator, LC, RC net-
work, or external single-phase clock to the on-chip oscilla-
tor input.
26
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
Port 0 (P07-P00). Port 0 is an 8-bit, bidirectional, CMOS-
compatible I/O port. These eight I/O lines can be config-
ured under software control as a nibble I/O port, or as an
address port for interfacing external memory. The input
buffers are Schmitt-triggered and nibble programmed. Ei-
ther nibble output that can be globally programmed as
push-pull or open-drain. Low EMI output buffers can be
globally programmed by the software. Port 0 can be placed
under handshake control. In Handshake Mode, Port 3
lines P32 and P35 are used as handshake control lines.
The handshake direction is determined by the configura-
tion (input or output) assigned to Port 0's upper nibble. The
lower nibble must have the same direction as the upper
nibble.
For external memory references, Port 0 provides address
bits A11-A8 (lower nibble) or A15-A8 (lower and upper nib-
ble) depending on the required address space. If the ad-
dress range requires 12 bits or less, the upper nibble of
Port 0 can be programmed independently as I/O while the
lower nibble is used for addressing. If one or both nibbles
are needed for I/O operation, they must be configured by
writing to the Port 0 mode register. In ROMless mode, after
a hardware reset, Port 0 is configured as address lines
A15-A8, and extended timing is set to accommodate slow
memory access. The initialization routine can include re-
configuration to eliminate this extended timing mode. In
ROM mode, Port 0 is defined as input after reset.
1
Port 0 can be set in the High-Impedance Mode if selected
as an address output state, along with Port 1 and the con-
trol signals /AS, /DS, and R//W (Figure 18).
4
Port 0 (I/O)
MCU
4
Handshake Controls
/DAV0 and RDY0
(P32 and P35)
Open-Drain
OEN
PAD
Out
1.5
2.3V Hysteresis
In
Auto Latch
R
500 kΩ
Figure 18. Port 0 Configuration
P R E L I M I N A R Y
DS97Z8X1500
27
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
PIN FUNCTIONS (Continued)
Port 1 (P17-P10). Port 1 is an 8-bit, bidirectional, CMOS-
compatible port with multiplexed Address (A7-A0) and
Data (D7-D0) ports. These eight I/O lines can be pro-
grammed as inputs or outputs or can be configured under
software control as an Address/Data port for interfacing
external memory. The input buffers are Schmitt-triggered
and the output buffers can be globally programmed as ei-
ther push-pull or open-drain. Low EMI output buffers can
be globally programmed by the software. Port 1 can be
placed under handshake control. In this configuration, Port
3, lines P33 and P34 are used as the handshake controls
RDY1 and /DAV1 (Ready and Data Available). To inter-
face external memory, Port 1 must be programmed for the
multiplexed Address/Data mode. If more than 256 external
locations are required, Port 0 outputs the additional lines
(Figure 19).
Port 1 can be placed in the high-impedance state along
with Port 0, /AS, /DS, and R//W, allowing the
Z86E43/743/E44 to share common resources in multipro-
cessor and DMA applications. In ROM mode, Port 1 is de-
fined as input after reset.
Port 2 (I/O)
MCU
Handshake Controls
/DAV1 and RDY1
(P33 and P34)
Open-Drain
OEN
PAD
Out
1.5
2.3V Hysteresis
In
Auto Latch
R
500 kΩ
Figure 19. Port 1 Configuration (Z86E43/743/E44 Only)
28
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
Port 2 (P27-P20). Port 2 is an 8-bit, bidirectional, CMOS-
compatible I/O port. These eight I/O lines can be config-
ured under software control as an input or output, indepen-
dently. All input buffers are Schmitt-triggered. Bits pro-
grammed as outputs can be globally programmed as
either push-pull or open-drain. Low EMI output buffers can
be globally programmed by the software. When used as an
I/O port, Port 2 can be placed under handshake control. Af-
ter reset, Port 2 is defined as an input.
In Handshake Mode, Port 3 lines P31 and P36 are used as
handshake control lines. The handshake direction is deter-
mined by the configuration (input or output) assigned to bit
7 of Port 2 (Figure 20).
1
Port 2 (I/O)
MCU
Handshake Controls
/DAV2 and RDY2
(P31 and P36)
Open-Drain
OEN
PAD
Out
1.5
2.3V Hysteresis
In
Auto Latch
R ≈ 500 KΩ
Figure 20. Port 2 Configuration
DS97Z8X1500
P R E L I M I N A R Y
29
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
PIN FUNCTIONS (Continued)
Port 3 (P37-P30). Port 3 is an 8-bit, CMOS-compatible
port with four fixed inputs (P33-P30) and four fixed outputs
(P37-P34). These eight lines can be configured by soft-
ware for interrupt and handshake control functions. Port 3,
Pin 0 is Schmitt- triggered. P31, P32, and P33 are stan-
dard CMOS inputs with single trip point (no Auto Latches)
and P34, P35, P36, and P37 are push-pull output lines.
Low EMI output buffers can be globally programmed by
the software. Two on-board comparators can process an-
alog signals on P31 and P32 with reference to the voltage
on P33. The analog function is enabled by setting the D1
of Port 3 Mode Register (P3M). The comparator output can
be outputted from P34 and P37, respectively, by setting
PCON register Bit D0 to 1 state. For the interrupt function,
P30 and P33 are falling edge triggered interrupt inputs.
P31 and P32 can be programmed as falling, rising or both
edges triggered interrupt inputs (Figure 21). Access to
Note: When enabling or disabling analog mode, the fol-
lowing is recommended:
1. Allow two NOP delays before reading this comparator
output.
2. Disable global interrupts, switch to analog mode, clear
interrupts, and then re-enable interrupts.
3. IRQ register bits 3 to 0 must be cleared after enabling
analog mode.
Note: P33-P30 differs from the Z86C33/C43/233/243 in
that there is no clamping diode to V due to the EPROM
CC
high-voltage circuits. Exceeding the V
maximum
IH
specification during standard operating mode may cause
the device to enter EPROM mode.
Counter/Timer 1 is made through P31 (T ) and P36
IN
(T
). Handshake lines for Port 0, Port 1, and Port 2 are
OUT
also available on Port 3 (Table 9).
30
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
1
MCU
Port 3
(I/O or Control)
Auto Latch
R ≈ 500 KΩ
P30
P30 Data
Latch IRQ3
R247 = P3M
1 = Analog
0 = Digital
D1
DIG.
AN.
P31 (AN1)
IRQ2, Tin, P31 Data Latch
+
-
P32 (AN2)
P33 (REF)
IRQ0, P32 Data Latch
IRQ1, P33 Data Latch
+
-
From Stop Mode
Recovery Source
Figure 21. Port 3 Configuration
DS97Z8X1500
P R E L I M I N A R Y
31
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
PIN FUNCTIONS (Continued)
Table 9. Port 3 Pin Assignments
Pin
I/O
CTC1
Analog
Interrupt
P0 HS
P1 HS
P2 HS
Ext
P30
P31
IN
IN
IRQ3
IRQ2
T
AN1
D/R
IN
P32
P33
P34
P35
P36
IN
AN2
REF
IRQ0
IRQ1
D/R
R/D
IN
D/R
R/D
OUT
OUT
OUT
AN1-Out
/DM
T
R/D
OUT
P37
OUT
An2-Out
Comparator Inputs. Port 3, P31, and P32, each have a
comparator front end. The comparator reference voltage
P33 is common to both comparators. In analog mode, P31
and P32 are the positive input of the comparators and P33
is the reference voltage of the comparators.
■ The pre-drivers slew rate reduced to 10 ns typical.
■ Low EMI output drivers have resistance of 200 Ohms
(typical).
■ Low EMI Oscillator.
Auto Latch. The Auto Latch puts valid CMOS levels on all
CMOS inputs (except P33-P31) that are not externally
driven. Whether this level is 0 or 1, cannot be determined.
A valid CMOS level, rather than a floating node, reduces
excessive supply current flow in the input buffer. Auto
Latches are available on Port 0, Port 1, Port 2, and P30.
There are no Auto Latches on P31, P32, and P33.
■ Internal SCLK/TCLK= XTAL operation limited to a
maximum of 4 MHz - 250 ns cycle time, when Low EMI
Oscillator is selected.
■ Note for emulation only:
Do not set the emulator to emulate Port 1 in low EMI
mode. Port 1 must always be configured in Standard
Mode.
Low EMI Emission. The Z86E43/743/E44 can be pro-
grammed to operate in a low EMI Emission Mode in the
PCON register. The oscillator and all I/O ports can be pro-
grammed as low EMI emission mode independently. Use
of this feature results in:
32
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION
The MCU incorporates the following special functions to
enhance the standard Z8 architecture to provide the user
with increased design flexibility.
Note: The device V
specification before the TPOR expires.
must rise up to the operating V
CC CC
1
Program Memory. The MCU can address up to 4/8/16 KB
of Internal Program Memory (Figure 22). The first 12 bytes
of program memory are reserved for the interrupt vectors.
These locations contain six 16-bit vectors that correspond
to the six available interrupts. For EPROM mode, byte 12
(000CH) to address 4095 (0FFFH)/8191 (1FFFH)/16384
(3FFFH), consists of programmable EPROM. After reset,
the program counter points at the address 000CH, which
is the starting address of the user program.
RESET. The device is reset in one of three ways:
1. Power-On Reset
2. Watch-Dog Timer
3. Stop-Mode Recovery Source
Note: Having the Auto Power-on Reset circuitry built-in,
the MCU does not need to be connected to an external
power-on reset circuit. The reset time is Tpor. The MCU
does not re-initialize WDTMR, SMR, P2M, and P3M
registers to their reset values on a Stop-Mode Recovery
operation.
In ROMless mode, the Z86E43/743/E44 can address up to
64 KB of External Program Memory. The ROM/ROMless
option is only available on the 44-pin devices.
ROM Mode
65535
ROMless Mode
External
ROM and RAM
4096/8192/16384
External
ROM and RAM
4095/8191/16383
On-Chip EPROM
Location of
First Byte of
Instruction
Executed
After RESET
12
11
10
9
IRQ5
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQ0
IRQ0
IRQ5
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQ0
IRQ0
8
7
Interrupt
Vector
(Lower Byte)
6
5
4
Interrupt
Vector
(Upper Byte)
3
2
1
0
(Z86E43/743/E44 Only)
Figure 22. Program Memory Map
P R E L I M I N A R Y
DS97Z8X1500
33
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
EPROM Protect. When in ROM Protect Mode, and exe-
cuting out of External Program Memory, instructions LDC,
LDCI, LDE, and LDEI cannot read Internal Program Mem-
ory.
mode, the Z86E43/743/E44 can address up to 64 KB of data
memory. External data memory may be included with, or
separated from, the external program memory space.
/DM, an optional I/O function that can be programmed to
appear on pin P34, is used to distinguish between data
and program memory space (Figure 23). The state of the
/DM signal is controlled by the type of instruction being ex-
ecuted. An LDC opcode references PROGRAM (/DM inac-
tive) memory, and an LDE instruction references data
(/DM active Low) memory.
When in EPROM Protect Mode and executing out of Inter-
nal Program Memory, instructions LDC, LDCI, LDE, and
LDEI can read Internal Program Memory.
Data Memory (/DM). In ROM Mode, the Z86E43/743/E44
can address up to 60/56/48 KB of external data memory
beginning at location 4096/8192/16384. In ROMless
EPROM
ROMless Mode
65535
External
Data
External
Data
Memory
Memory
4096/8192/16384
4095/8191/16383
Not Addressable
0
(Z86E43/743/E44 Only)
Figure 23. Data Memory Map
34
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
Register File. The register file consists of three I/O port
registers, 236/125 general-purpose registers, 15 control
and status registers, and three system configuration regis-
ters in the expanded register group. The instructions can
access registers directly or indirectly through an 8-bit ad-
dress field. This allows a short 4-bit register address using
the Register Pointer (Figure 24). In the 4-bit mode, the reg-
ister file is divided into 16 working register groups, each
occupying 16 continuous locations. The Register Pointer
addresses the starting location of the active working-regis-
ter group.
1
Note: Register Group E0-EF can only be accessed
through working register and indirect addressing modes.
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register Bank
Working Register Pointer
Default After Reset = 00H
Figure 24. Register Pointer Register
Expanded Register File(ERF). The register file has been
expanded to allow for additional system control registers,
mapping of additional peripheral devices and input/output
ports into the register address area. The Z8 register ad-
dress space R0 through R15 is implemented as 16 groups
of 16 registers per group (Figure 26). These register banks
are known as the Expanded Register File (ERF).
The low nibble (D3-D0) of the Register Pointer (RP) select
the active ERF Bank, and the high nibble (D7-D4) of regis-
ter RP select the working register group. Three system
configuration registers reside in the Expanded Register
File at bank FH: PCON, SMR, and WDTMR. The rest of
the Expanded Register is not physically implemented and
is reserved for future expansion.
DS97Z8X1500
P R E L I M I N A R Y
35
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
r7 r6 r5 r4
r3 r2 r1 r0
R253
(Register Pointer)
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.
FF
F0
EF
80
7F
70
6F
60
5F
50
4F
The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register.
40
3F
Specified Working
Register Group
30
2F
20
1F
Register Group 1
R15 to R0
10
0F
R15 to R4*
R3 to R0*
Register Group 0
I/O Ports
00
* Expanded Register Bank (0) is selected
in this figure by handling bits D3 to D0 as
"0" in Register R253 (RP).
Figure 25. Register Pointer
36
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
Z8® STANDARD CONTROL REGISTERS
RESET CONDITION
1
D7 D6 D5 D4 D3 D2 D1 D0
REGISTER
% FF
SPL
SPH
0
0
0
0
0
0
0
0
0
0
U
U
0
U
1
0
1
0
U
0
U
0
REGISTER POINTER
7
6
5
4
3
2
1
0
% FE
% FD
% FC
% FB
% FA
% F9
% F8
% F7
% F6
% F5
% F4
% F3
% F2
% F1
% F0
0
0
0
0
0
0
0
RP
0
0
0
0
0
0
0
Working Register
Group Pointer
Expanded Register
Group Pointer
FLAGS
IMR
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
IRQ
0
IPR
U
0
U
1
U
0
U
0
U
1
U
1
U
0
†
*
*
P01M
P3M
0
0
0
0
0
0
0
P2M
1
1
1
1
1
1
1
PRE0
T0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
0
Z8 Reg. File
%FF
%FO
PRE1
T1
U
0
TMR
Reserved
EXPANDED REG. BANK (F)
REGISTER
RESET CONDITION
% (F) 0F
% (F) 0E
% (F) 0D
WDTMR
U
U
U
0
1
1
0
0
1
0
*
*
Reserved
%7F
U
U
U
U
U
U
SMR2
Reserved
SMR
% (F) 0C
% (F) 0B
**
0
0
1
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCON
% (F) 0A
% (F) 09
% (F) 08
% (F) 07
% (F) 06
% (F) 05
% (F) 04
Reserved
%0F
%00
% (F) 03
% (F) 02
% (F) 01
% (F) 00
1
1
1
1
1
1
1
0
EXPANDED REG. BANK (0)
REGISTER
RESET CONDITION
Notes:
1
% (0) 03
% (0) 02
% (0) 01
P3
P2
P1
P0
1
1
1
U
U
U
U
U = Unknown
*
*
†
For ROMless reset condition: "10110110"
Will not be reset with a STOP Mode Recovery
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
*
** Will not be reset with a STOP Mode Recovery, except Bit D0.
% (0) 00
Figure 26. Expanded Register File Architecture
DS97Z8X1500
P R E L I M I N A R Y
37
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
General-Purpose Registers (GPR). These registers are
undefined after the device is powered up. The registers
keep their last value after any reset, as long as the reset
Counter/Timers. There are two 8-bit programmable
counter/timers (T0 and T1), each driven by its own 6-bit
programmable prescaler. The T1 prescaler is driven by in-
ternal or external clock sources; however, the T0 prescaler
is driven by the internal clock only (Figure 27).
occurs in the V voltage-specified operating range. The
CC
register R254 is general-purpose on Z86E33/733/E34.
R254 and R255 are set to 00H after any reset or STOP-
Mode Recovery.
The 6-bit prescalers can divide the input frequency of the
clock source by any integer number from 1 to 64. Each
prescaler drives its counter, which decrements the value
(1 to 256), that has been loaded into the counter. When the
counter reaches the end of count, a timer interrupt request,
IRQ4 (T0) or IRQ5 (T1), is generated.
RAM Protect. The upper portion of the RAM's address
spaces 80H to EFH (excluding the control registers) can
be protected from reading and writing. This option can be
selected during the EPROM Programming Mode. After this
option is selected, the user can activate this feature from
the internal EPROM. D6 of the IMR control register (R251)
is used to turn off/on the RAM protect by loading a 0 or 1,
respectively. A "1" in D6 indicates RAM Protect enabled.
The counters can be programmed to start, stop, restart to
continue, or restart from the initial value. The counters can
also be programmed to stop upon reaching one (single
pass mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode).
Stack. The Z86E43/743/E44 external data memory or the
internal register file can be used for the stack. The 16-bit
Stack Pointer (R254-R255) is used for the external stack,
which can reside anywhere in the data memory for ROM-
less mode, but only from 4096/8192/16384 to 65535 in
ROM mode. An 8-bit Stack Pointer (R255) is used for the
internal stack on the Z8 that resides within the 236 gener-
al-purpose registers (R4-R239). SPH (R254) can be used
as a general-purpose register when using internal stack
only. R254 and R255 are set to 00H after any reset or
Stop- Mode Recovery.
The counters, but not the prescalers, can be read at any
time without disturbing their value or count mode. The
clock source for T1 is user-definable and can be either the
internal microprocessor clock divided by four, or an exter-
nal signal input through Port 3. The Timer Mode register
configures the external timer input (P31) as an external
clock, a trigger input that can be retriggerable or non-retrig-
gerable, or as a gate input for the internal clock. Port 3 line
P36 serves as a timer output (T
) through which T0, T1,
OUT
or the internal clock can be output. The counter/timers can
be cascaded by connecting the T0 output to the input of
T1.
38
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
OSC
1
Internal Data Bus
Write
D1 (SMR)
Write
Read
÷ 2
PRE0
Initial Value
Register
T0
T0
Initial Value
Register
Current Value
Register
D0 (SMR)
6-Bit
Down
8-bit
Down
÷ 16
÷4
Counter
Counter
IRQ4
Internal
Clock
TOUT
P36
÷2
External Clock
Clock
Logic
6-Bit
Down
8-Bit
Down
IRQ5
÷4
Counter
Counter
Internal Clock
Gated Clock
Triggered Clock
PRE1
Initial Value
Register
T1
T1
Initial Value
Register
Current Value
Register
TIN P31
Write
Write
Internal Data Bus
Read
Figure 27. Counter/Timer Block Diagram
DS97Z8X1500
P R E L I M I N A R Y
39
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Interrupts. The MCU has six different interrupts from six
different sources. The interrupts are maskable and priori-
tized (Figure 28). The six sources are divided as follows:
four sources are claimed by Port 3 lines P33-P30) and two
in counter/timers. The Interrupt Mask Register globally or
individually enables or disables the six interrupt requests
(Table 10).
IRQ0 IRQ2
IRQ1, 3, 4, 5
Interrupt
Edge
IRQ (D6, D7)
Select
IRQ
IMR
IPR
6
Global
Interrupt
Enable
Interrupt
Request
Priority
Logic
Vector Select
Figure 28. Interrupt Block Diagram
Table 10. Interrupt Types, Sources, and Vectors
Name
Source
Vector Location
Comments
IRQ0
IRQ1
IRQ2
/DAV0, IRQ0
IRQ1
0, 1
2, 3
4, 5
External (P32), Rising/Falling Edge Triggered
External (P33), Falling Edge Triggered
/DAV2, IRQ2, T
External (P31), Rising/Falling Edge Triggered
IN
IRQ3
IRQ4
IRQ5
IRQ3
T0
6, 7
8, 9
External (P30), Falling Edge Triggered
Internal
Internal
TI
10, 11
40
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
Table 11. IRQ Register Configuration
IRQ Interrupt Edge
P31 P32
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority Register (IPR). An interrupt
machine cycle is activated when an interrupt request is
granted. Thus, disabling all subsequent interrupts, saves
the Program Counter and Status Flags, and then branches
to the program memory vector location reserved for that in-
terrupt. All interrupts are vectored through locations in the
program memory. This memory location and the next byte
contain the 16-bit starting address of the interrupt service
routine for that particular interrupt request.
D7
D6
1
0
0
1
1
0
1
0
1
F
F
F
R
R
F
R/F
R/F
Notes:
F = Falling Edge
R = Rising Edge
To accommodate polled interrupt systems, interrupt inputs
are masked and the interrupt request register is polled to
determine which of the interrupt requests need service.
Clock. The on-chip oscillator has a high-gain, parallel-res-
onant amplifier for connection to a crystal, RC, ceramic
resonator, or any suitable external clock source (XTAL1 =
Input, XTAL2 = Output). The crystal should be AT cut, 10
KHz to 16 MHz max, with a series resistance (RS) less
than or equal to 100 Ohms.
An interrupt resulting from AN1 is mapped into IRQ2, and
an interrupt from AN2 is mapped into IRQ0. Interrupts
IRQ2 and IRQ0 may be rising, falling or both edge trig-
gered, and are programmable by the user. The software
may poll to identify the state of the pin.
The crystal should be connected across XTAL1 and
XTAL2 using the vendor's recommended capacitor values
from each pin directly to device pin Ground. The RC oscil-
lator option can be selected in the programming mode.
The RC oscillator configuration must be an external resis-
tor connected from XTAL1 to XTAL2, with a frequency-set-
ting capacitor from XTAL1 to Ground (Figure 29).
Programming bits for the Interrupt Edge Select are located
in bits D7 and D6 of the IRQ Register (R250). The
configuration is shown in Table 11.
XTAL1
XTAL2
XTAL1
XTAL1
XTAL2
XTAL1
XTAL2
C1
C2
C1
C2
C1
L
R
XTAL2
Ceramic Resonator or
Crystal
LC
RC
External Clock
C1, C2 = 22 pF
@ 5V Vcc (TYP)
C1, C2 = 33 pF TYP*
F = 8 MHz
L= 130 µH *
F = 3 MHz *
C1 = 100 pF
R = 2K
F = 6 MHz
* Typical value including pin parasitics
Figure 29. Oscillator Configuration
DS97Z8X1500
P R E L I M I N A R Y
41
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Power-On Reset (POR). A timer circuit clocked by a ded-
icated on-board RC oscillator is used for the Power-On Re-
In order to enter STOP or HALT Mode, it is necessary to
first flush the instruction pipeline to avoid suspending exe-
cution in mid-instruction. To do this, the user must execute
a NOP (Opcode=FFH) immediately before the appropriate
sleep instruction, that is:
set (POR) timer function. The POR timer allows V and
CC
the oscillator circuit to stabilize before instruction execu-
tion begins.
The POR timer circuit is a one-shot timer triggered by one
of three conditions:
FF
6F
NOP
STOP
or
; clear the pipeline
; enter STOP Mode
1. Power fail to Power OK status
2. Stop-Mode Recovery (if D5 of SMR=0)
3. WDT time-out
FF
7F
NOP
HALT
; clear the pipeline
; enter HALT Mode
STOP. This instruction turns off the internal clock and ex-
ternal crystal oscillation and reduces the standby current
to 10 microamperes or less. STOP Mode is terminated by
one of the following resets: either by WDT time-out, POR,
a Stop-Mode Recovery Source, which is defined by the
SMR register or external reset. This causes the processor
to restart the application program at address 000CH.
The POR time is a nominal 5 ms. Bit 5 of the STOP mode
Register (SMR) determines whether the POR timer is by-
passed after STOP-Mode Recovery (typical for an external
clock and RC/LC oscillators with fast start up times).
HALT. Turns off the internal CPU clock, but not the XTAL
oscillation. The counter/timers and external interrupt IRQ0,
IRQ1, and IRQ2 remain active. The device is recovered by
interrupts, either externally or internally generated. An in-
terrupt request must be executed (enabled) to exit HALT
Mode. After the interrupt service routine, the program con-
tinues from the instruction after the HALT.
Port Configuration Register (PCON). The PCON regis-
ter configures the ports individually; comparator output on
Port 3, open-drain on Port 0 and Port 1, low EMI on Ports
0, 1, 2 and 3, and low EMI oscillator. The PCON register is
located in the expanded register file at Bank F, location 00
(Figure 30).
PCON (FH) 00H
D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
0 Port 1 Open Drain
1 Port 1 Push-pullActive*
0 Port 0 Open Drain
1 Port 0 Push-pull Active*
0
1
Port 0 Low EMI
Port 0 Standard*
0 Port 1 Low EMI
1 Port 1 Standard*
0
1
Port 2 Low EMI
Port 2 Standard*
0
1
Port 3 Low EMI
Port 3 Standard*
Low EMI Oscillator
0
1
Low EMI
Standard*
* Default SettingAfter Reset
Figure 30. Port Configuration Register (PCON)
(Write Only)
42
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
Comparator Output Port 3 (D0). Bit 0 controls the com-
parator output in Port 3. A "1" in this location brings the
comparator outputs to P34 and P37, and a "0" releases the
Port to its standard I/O configuration. The default value is
0.
Low EMI Port 3 (D6). Port 3 can be configured as a Low
EMI Port by resetting this bit (D6=0) or configured as a
Standard Port by setting this bit (D6=1). The default value
is 1.
1
Low EMI OSC (D7). This bit of the PCON Register con-
trols the low EMI noise oscillator. A "1" in this location con-
figures the oscillator with standard drive. While a "0" con-
figures the oscillator with low noise drive, however, it does
not affect the relationship of SCLK and XTAL. The low EMI
mode will reduce the drive of the oscillator (OSC). The de-
fault value is 1. Note: 4 MHz is the maximum external
clock frequency when running in the low EMI oscillator
mode.
Port 1 Open-Drain (D1). Port 1 can be configured as an
open-drain by resetting this bit (D1=0) or configured as
push-pull active by setting this bit (D1=1). The default val-
ue is 1.
Port 0 Open-Drain (D2). Port 0 can be configured as an
open-drain by resetting this bit (D2=0) or configured as
push-pull active by setting this bit (D2=1). The default val-
ue is 1.
Stop-Mode Recovery Register (SMR). This register
selects the clock divide value and determines the mode of
Stop-Mode Recovery (Figure 31). All bits are Write Only
except bit 7 which is a Read Only. Bit 7 is a flag bit that is
hardware set on the condition of STOP Recovery and
reset by a power-on cycle. Bit 6 controls whether a low or
high level is required from the recovery source. Bit 5
controls the reset delay after recovery. Bits 2, 3, and 4 of
the SMR register specify the Stop-Mode Recovery Source.
The SMR is located in Bank F of the Expanded Register
File at address 0BH.
Low EMI Port 0 (D3). Port 0 can be configured as a Low
EMI Port by resetting this bit (D3=0) or configured as a
Standard Port by setting this bit (D3=1). The default value
is 1.
Low EMI Port 1 (D4). Port 1 can be configured as a Low
EMI Port by resetting this bit (D4=0) or configured as a
Standard Port by setting this bit (D4=1). The default value
is 1. Note: The emulator does not support Port 1 low EMI
mode and must be set D4 = 1.
Low EMI Port 2 (D5). Port 2 can be configured as a Low
EMI Port by resetting this bit (D5=0) or configured as a
Standard Port by setting this bit (D5=1). The default value
is 1.
DS97Z8X1500
P R E L I M I N A R Y
43
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
SMR (F) 0B
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide by 16
0 OFF **
1 ON
External Clock Divide by 2
0 SCLK/TCLK =XTAL/2*
1 SCLK/TCLK =XTAL
Stop Mode Recovery Source
000 POR and/or External Reset
001 P30
*
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0:3
111 P2 NOR 0:7
Stop Delay
0 OFF
*
1 ON
Stop Recovery Level
0 Low *
1 High
Stop Flag
0 POR
*
1 Stop Recovery
* Default setting after RESET.
** Default setting after RESET and STOP-Mode Recovery.
Figure 31. STOP-Mode Recovery Register
(Write-Only Except Bit D7,Which is Read-Only)
44
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
SCLK/TCLK Divide-by-16 Select (D0). This bit of the
SMR controls a divide-by-16 prescaler of SCLK/TCLK.
The purpose of this control is to selectively reduce device
power consumption during normal processor execution
(SCLK control) and/or HALT mode (where TCLK sources
counter/timers and interrupt logic).
PCON further helps lower EMI (i.e., D7 (PCON) = 0, D1
(SMR) = 1). The default setting is zero.
STOP-Mode Recovery Source (D2, D3, and D4). These
three bits of the SMR register specify the wake up source
of the STOP-Mode Recovery (Figure 32). Table 12 shows
the SMR source selected with the setting of D2 to D4. P33-
P31 cannot be used to wake up from STOP mode when
programmed as analog inputs. When the STOP-Mode Re-
covery sources are selected in this register then SMR2
register bits D0, D1 must be set to zero.
1
External Clock Divide-by-Two (D1). This bit can elimi-
nate the oscillator divide-by-two circuitry. When this bit is
0, the System Clock (SCLK) and Timer Clock (TCLK) are
equal to the external clock frequency divided by two. The
SCLK/TCLK is equal to the external clock frequency when
this bit is set (D1=1). Using this bit together with D7 of
Note: If the Port2 pin is configured as an output, this output
level will be read by the SMR circuitry..
SMR2 D1 D0
0
0
SMR2 D1 D0
SMR2 D1 D0
VDD
0
1
1
0
P20
P23
P20
P27
SMR D4 D3 D2
0
0
0
SMR D4 D3 D2 SMR D4 D3 D2 SMR D4 D3 D2
SMR D4 D3 D2
SMR D4 D3 D2
VDD
0
0
0
0
1
1
1
0
1
1
0
0
1
0
1
1
1
0
1
1
1
P20
P20
P30
P31
P32
P33
P27
P23
P27
To POR
RESET
Stop-Mode Recovery Edge
Select (SMR)
To P33 Data
Latch and IRQ1
MUX
P33 From Pads
Digital/Analog Mode
Select (P3M)
Figure 32. Stop-Mode Recovery Source
DS97Z8X1500
P R E L I M I N A R Y
45
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Table 12. Stop-Mode Recovery Source
Watch-Dog Timer Mode Register (WDTMR). The WDT
is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. The WDT is disabled after Pow-
er-On Reset and initially enabled by executing the WDT in-
struction and refreshed on subsequent executions of the
WDT instruction. The WDT is driven either by an on-board
RC oscillator or an external oscillator from XTAL1 pin. The
POR clock source is selected with bit 4 of the WDT regis-
ter.
D4
D3
D2
SMR Source selection
0
0
0
0
0
1
0
1
0
POR recovery only
P30 transition
P31 transition (Not in analog
mode)
0
1
1
0
1
0
P32 transition (Not in analog
mode)
P33 transition (Not in analog
mode)
Note: Execution of the WDT instruction affects the Z (Ze-
ro), S (Sign), and V (Overflow) flags.
1
1
1
0
1
1
1
0
1
P27 transition
WDT Time-Out Period (D0 and D1). Bits 0 and 1 control
a tap circuit that determines the time-out periods that can
be obtained (Table 13). The default value of D0 and D1
are 1 and 0, respectively.
Logical NOR of Port 2 bits 0-3
Logical NOR of Port 2 bits 0-7
Stop-Mode Recovery Delay Select (D5). The 5 ms RE-
SET delay after Stop-Mode Recovery is disabled by pro-
gramming this bit to a zero. A "1" in this bit will cause a 5
ms RESET delay after Stop-Mode Recovery. The default
condition of this bit is 1. If the fast wake up mode is select-
ed, the Stop-Mode Recovery source needs to be kept ac-
tive for at least 5TpC.
Table 13. Time-out Period of WDT
Time-out of Time-out of
the Internal the System
D1
D0
RC OSC
Clock
0
0
1
1
0
1
0
1
5 ms
10 ms*
20 ms
80 ms
128 SCLK
256 SCLK*
512 SCLK
2048 SCLK
Stop-Mode Recovery Level Select (D6). A "1" in this bit
defines that a high level on any one of the recovery sourc-
es wakes the MCU from STOP Mode. A 0 defines low level
recovery. The default value is 0.
Notes:
*The default setting is 10 ms.
Cold or Warm Start (D7). This bit is set by the device
upon entering STOP Mode. A "0" in this bit indicates that
the device has been reset by POR (cold). A "1" in this bit
indicates the device was awakened by a SMR source
(warm).
WDT During HALT Mode (D2). This bit determines
whether or not the WDT is active during HALT Mode. A "1"
indicates that the WDT is active during HALT. A "0" dis-
ables the WDT in HALT Mode. The default value is "1".
WDT During STOP Mode (D3). This bit determines
whether or not the WDT is active during STOP mode. A "1"
indicates active during STOP. A "0" disables the WDT dur-
ing STOP Mode. This is applicable only when the WDT
clock source is the internal RC oscillator.
Stop-Mode Recovery Register 2 (SMR2). This register
contains additional Stop-Mode Recovery sources. When
the Stop-Mode Recovery sources are selected in this reg-
ister then SMR Register Bits D2, D3, and D4 must be 0.
SMR:10
D1 D0
Operation
Clock Source For WDT (D4). This bit determines which
oscillator source is used to clock the internal POR and
WDT counter chain. If the bit is a 1, the internal RC oscil-
lator is bypassed and the POR and WDT clock source is
driven from the external pin, XTAL1, and the WDT is
stopped in STOP Mode. The default configuration of this
bit is 0, which selects the RC oscillator.
Description of Action
0
0
1
0
1
0
POR and/or external reset recovery
Logical AND of P20 through P23
Logical AND of P20 through P27
46
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
Permanent WDT. When this feature is enabled, the WDT
is enabled after reset and will operate in Run and Halt
Mode. The control bits in the WDTMR do not affect the
WDT operation. If the clock source of the WDT is the inter-
nal RC oscillator, then the WDT will run in STOP mode. If
the clock source of the WDT is the XTAL1 pin, then the
WDT will not run in STOP mode.
cycles from the execution of the first instruction after
Power-On Reset, Watch-Dog reset or a STOP-Mode
Recovery (Figures 33 and 34). After this point, the register
cannot be modified by any means, intentional or
otherwise. The WDTMR cannot be read and is located in
Bank F of the Expanded Register File at address location
0FH.
1
Note: WDT time-out in STOP Mode will not reset
SMR,SMR2,PCON, WDTMR, P2M, P3M, Ports 2 & 3 Data
Registers, but will activate the Tpor delay.
Clock Free WDT Reset. The WDT will enable the Z8 to
reset the I/O pins whenever the WDT times out, even with-
out a clock source running on the XTAL1 and XTAL2 pins.
WDTMR Bit D4 must be 0 for the clock Free WDT to work.
The I/O pins will default to their default settings
WDTMR Register Accessibility. The WDTMR register is
accessible only during the first 60 internal system clock
WDTMR (F) 0F
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC System Clock
00
01
10
11
5 ms
10 ms
20 ms
80 ms
128 SCLK
256 SCLK
512 SCLK
2048 SCLK
*
WDT During HALT
0
1
OFF
ON
*
WDT During STOP
0
1
OFF
ON
*
XTAL1/INT RC Select for WDT
0
1
On-Board RC
XTAL
*
Reserved (Must be 0)
*
Default setting after RESET
Figure 33. Watch-Dog Timer Mode Register
Write Only
DS97Z8X1500
P R E L I M I N A R Y
47
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
/Reset
4 Clock
Filter
/Clear
CLK
18 Clock RESET
Generator
RESET
Internal
/RESET
WDT Select
(WDTMR)
WDT TAP SELECT
CLK Source
Select
(WDTMR)
5ms POR
CK
5ms
25ms 100ms
15ms
XTAL
M
U
X
WDT/POR Counter Chain
/CLR
Internal
RC OSC.
2V Operating
Voltage Det.
+
-
VDD
VLV
/WDT
From Stop
Mode
Recovery
Source
Stop Delay
Select (SMR)
Figure 34. Resets and WDT
48
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
Auto Reset Voltage. An on-board Voltage Comparator
operation of the device. Reset is globally driven if V is
CC
checks that V is at the required level to ensure correct
below V (Figure 35).
CC
LV
1
3.7
VCC
(Volts)
3.5
3.3
3.1
2.9
2.7
2.5
2.3
-60
-40
-20
0
20
40
60
80
100
120
140
Temperature
(°C)
Figure 35. Typical V Voltage vs Temperature
LV
DS97Z8X1500
P R E L I M I N A R Y
49
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
Z8 CONTROL REGISTER DIAGRAMS
PCON (FH) 00H
WDTMR (F) 0F
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC System Clock
Comparator Output Port 3
0 P34, P37 Standard*
1 P34, P37 Comparator Output
00
01
10
11
5 ms
10 ms
20 ms
80 ms
128 SCLK
256 SCLK
512 SCLK
2048 SCLK
*
0
1
Port 1 Open-Drain
Port 1 Push-PullActive*†
WDT During HALT
0
1
OFF
0
1
Port 0 Open-Drain
Port 0 Push-pullActive*
ON
*
WDT During STOP
0
1
0
1
Port 0 Low EMI
Port 0 Standard*
OFF
ON
*
XTAL1/INT RC Select for WDT
0
1
Port 1 Low EMI
Port 1 Standard*†
0
On-Board RC
*
1
XTAL
0
1
Port 2 Low EMI
Port 2 Standard*
Reserved (Must be 0)
0
1
Port 3 Low EMI
Port 3 Standard*
*
Default setting after RESET
Low EMI Oscillator
0
1
Low EMI
Standard*
* Default SettingAfter Reset
† Must Be 1 for Z86E33/733/E34
Figure 38. Watch-Dog Timer Mode Register
Write Only
Figure 36. Port Configuration Register
Write Only
SMR2 (0F) DH
D7 D6 D5 D4 D3 D2 D1 D0
SMR (FH) 0B
D7 D6 D5 D4 D3 D2 D1 D0
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,P24,
P25,P26,P27
SCLK/TCLK Divide-by-16
0
1
OFF **
ON
Reserved (Must be 0)
Note: Not used in conjunction with SMR Source
External Clock Divide by 2
0
1
SCLK/TCLK =XTAL/2*
SCLK/TCLK =XTAL
Stop Mode Recovery Source†
000 POR Only and/or External Reset*
001 P30
010 P31
011 P32
100 P33
Figure 39. STOP-Mode Recovery Register 2
Write Only
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
R240
D7 D6 D5 D4 D3 D2 D1 D0
Stop Delay
0
1
OFF
ON*
Reserved (Must be 0)
Stop Recovery Level
0
Low*
1
High
Stop Flag
0
1
POR*
Stop Recovery
Figure 40. Reserved
* Default setting after RESET.
** Default setting after RESET and STOP-Mode Recovery.
† Not used in conjunction with SMR2 Source
Figure 37. STOP-Mode Recovery Register
Write Only Except Bit D7,Which is Read Only
50
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
R241 TMR
R243 PRE1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
Count Mode
0
1
No Function*
Load T0
0
1
T1 Single Pass*
T1 Modulo N
0
1
Disable T0 Count*
Enable T0 Count
Clock Source
1
0
T1 Internal
T1 External Timing Input
(TIN Mode)
0
1
No Function*
Load T1
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
0
1
Disable T1 Count*
Enable T1 Count
*Default After Reset
TIN Modes
00 External Clock Input*
01 Gate Input
10 Trigger Input
(Non-retriggerable)
11 Trigger Input
(Retriggerable)
Figure 43. Prescaler 1 Register
F3H:Write Only
TOUT Modes
00 Not Used*
01 T0 Out
R244 T0
D7 D6 D5 D4 D3 D2 D1 D0
10 T1 Out
11 Internal Clock Out
Default After Reset = 00H
T0 Initial Value
(When Written)
(Range: 1-256 Decimal
01-00 HEX)
T0 Current Value
(When Read)
Figure 41. Timer Mode Register
F1H: Read/Write
Figure 44. Counter/Timer 0 Register
F4H; Read/Write
R242 T1
D7 D6 D5 D4 D3 D2 D1 D0
T1 Initial Value
(When Written)
(Range: 1-256 Decimal
01-00 HEX)
R245 PRE0
D7 D6 D5 D4 D3 D2 D1 D0
T1 Current Value
(When Read)
Count Mode
0
1
T1 Single Pass
T1 Modulo N
Figure 42. Counter/Timer 1 Register
F2H: Read/Write
Reserved (Must be 0)
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
Figure 45. Prescaler 0 Register
F5H:Write Only
DS97Z8X1500
P R E L I M I N A R Y
51
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
Z8 CONTROL REGISTER DIAGRAMS (Continued)
R246 P2M
R248 P01M
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
P03 - P00 Mode
00 Output
01 Input
P20 - P27 I/O Definition
*
0
1
Defines Bit as Output
Defines Bit as Input*
1X A11 -A8
* Default After Reset
Stack Selection
0
1
External
Internal*
P17 - P10 Mode
00 Byte Output†
01 Byte Input*
10 AD7 -AD0
Figure 46. Port 2 Mode Register
F6H:Write Only
11 High-Impedance AD7 - AD0,
/AS, /DS, /R//W, A11 - A8,
A15 -A12, If Selected
R247 P3M
External Memory Timing
0
1
Normal*
Extended
D7 D6 D5 D4 D3 D2 D1 D0
P07 - P04 Mode
00 Output
01 Input*
0
1
Port 2 Open-Drain
Port 2 Push-pull Active
1X A15 - A12
0
1
P31, P32 Digital Mode
P31, P32 Analog Mode
Reset Condition = 0100 1101B
For ROMless Condition = 1011 0110B
† Z86E33/733/E34 Must be 00
* Default After Reset
0
1
P32 = Input
P35 = Output
P32 = /DAV0/RDY0
P35 = RDY0//DAV0
Figure 48. Port 0 and 1 Mode Register
F8H:Write Only
00
P33 = Input
P34 = Output
01
10
11
P33 = Input
P34 = /DM
P33 = /DAV1/RDY1
P34 = RDY1//DAV1
†
R249 IPR
D7 D6 D5 D4 D3 D2 D1 D0
0
1
P31 = Input (TIN)
P36 = Output (TOUT)
P31 = /DAV2/RDY2
P36 = RDY2//DAV2
0
P30 = Input
P37 = Output
Interrupt Group Priority
000 Reserved
001 C > A> B
010 A > B > C
011 A > C > B
100 B > C >A
101 C > B >A
110 B > A > C
111 Reserved
Reserved (Must be 0)
Default After Reset = 00H
† Z86E33/733/E34 Must Be 00
Figure 47. Port 3 Mode Register
F7H:Write Only
IRQ1, IRQ4 Priority (Group C)
0
IRQ1 > IRQ4
1
IRQ4 > IRQ1
IRQ0, IRQ2 Priority (Group B)
0
1
IRQ2 > IRQ0
IRQ0 > IRQ2
IRQ3, IRQ5 Priority (Group A)
0
1
IRQ5 > IRQ3
IRQ3 > IRQ5
Reserved (Must be 0)
Figure 49. Interrupt Priority Register
F9H:Write Only
52
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
R250 IRQ
D7 D6 D5 D4 D3 D2 D1 D0
1
Expanded Register Bank
Working Register Pointer
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = P30 Input
IRQ4 = T0
Default After Reset = 00H
IRQ5 = T1
Inter Edge
P31 ↓ P32 ↓ = 00
P31 ↓ P32 ↑ = 01
P31 ↑ P32 ↓ = 10
P31 ↑↓ P32 ↑↓ = 11
Figure 53. Register Pointer
FDH: Read/Write
Default After Reset = 00H
R254 SPH
D7 D6 D5 D4 D3 D2 D1 D0
Figure 50. Interrupt Request Register
FAH: Read/Write
(Z86E43/743/E44)
Stack Pointer Upper
Byte (SP8 - SP15)
R251 IMR
(Z86E33/733/E34)
0 = 0 State
1 = 1 State
D7 D6 D5 D4 D3 D2 D1 D0
Default after Reset = 00H
1
Enables IRQ5-IRQ0
(D0 = IRQ0)
Figure 54. Stack Pointer High
FEH: Read/Write
1 Enables RAM Protect †
Enables Interrupts
1
† This option must be selected when ROM code is
submitted for ROM Masking, otherwise this control bit
is disabled permanently.
R255 SPL
D7 D6 D5 D4 D3 D2 D1 D0
Figure 51. Interrupt Mask Register
FBH: Read/Write
Stack Pointer Lower
Byte (SP0 - SP7)
Default after Reset = 00H
R252 FLAGS
D7 D6 D5 D4 D3 D2 D1 D0
Figure 55. Stack Pointer Low
FFH: Read/Write
User Flag F1
User Flag F2
Half Carry Flag
DecimalAdjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
Figure 52. Flag Register
FCH: Read/Write
DS97Z8X1500
P R E L I M I N A R Y
53
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
PACKAGE INFORMATION
Figure 56. 40-Pin DIP Package Diagram
Figure 57. 44-Pin PLCC Package Diagram
54
P R E L I M I N A R Y
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
1
Figure 58. 44-Pin QFP Package Diagram
Figure 59. 28-Pin DIP Package Diagram
DS97Z8X1500
P R E L I M I N A R Y
55
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
PACKAGE INFORMATION (Continued)
Figure 60. 28-Pin SOIC Package Diagram
Figure 61. 28-Pin PLCC Package Diagram
P R E L I M I N A R Y
56
DS97Z8X1500
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
ORDERING INFORMATION
Z86E43/743/E44 (12 MHz)
1
40-Pin DIP
44-Pin PLCC
44-Pin QFP
Z86E4312PSC
Z86E4312PEC
Z8674312PSC
Z8674312PEC
Z86E4412PSC
Z86E4412PEC
Z86E4312VSC
Z86E4312VEC
Z8674312VSC
Z8674312VEC
Z86E4412VSC
Z86E4412VEC
Z86E4312FSC
Z86E4312FEC
Z8674312FSC
Z8674312FEC
Z86E4412FSC
Z86E4412FEC
Z86E33/733/E34 (12 MHz)
28-Pin DIP
28-Pin SOIC
28-Pin PLCC
Z86E3312PSC
Z86E3312PEC
Z8673312PSC
Z8673312PEC
Z86E3412PSC
Z86E3412PEC
Z86E3312SSC
Z86E3312SEC
Z8673312SSC
Z8673312SEC
Z86E3412SSC
Z86E3412SEC
Z86E3312VSC
Z86E3312VEC
Z8673312VSC
Z8673312VEC
Z86E3412VSC
Z86E3412VEC
For fast results, contact your local Zilog sales office for assistance in ordering the part desired.
Package
Speed
P = Plastic DIP
12 = 12 MHz
V = Plastic Chip Carrier
Environmental
F = Plastic Quad Flat Pack
S = SOIC (Small Outline Integrated Circuit)
C = Plastic Standard
Temperature
S = 0 °C to +70 °C
E = -40 °C to +105 °C
Example:
Z 86E43 12 P S C
is a Z8E43, 12 MHz, DIP, 0° to +70°C, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
DS97Z8X1500
P R E L I M I N A R Y
57
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Zilog
© 1997 by Zilog, Inc. All rights reserved. No part of this
document may be copied or reproduced in any form or by
any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change
without notice. Devices sold by Zilog, Inc. are covered by
warranty and patent indemnification provisions appearing
in Zilog, Inc. Terms and Conditions of Sale only.
Zilog, Inc. shall not be responsible for any errors that may
appear in this document. Zilog, Inc. makes no commitment
to update or keep current the information contained in this
document.
Zilog’s products are not authorized for use as critical
components in life support devices or systems unless a
specific written agreement pertaining to such intended use
is executed between the customer and Zilog prior to use.
Life support devices or systems are those which are
intended for surgical implantation into the body, or which
sustains life whose failure to perform, when properly used
in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in
significant injury to the user.
ZILOG, INC. MAKES NO WARRANTY, EXPRESS,
STATUTORY, IMPLIED OR BY DESCRIPTION,
REGARDING THE INFORMATION SET FORTH HEREIN
OR REGARDING THE FREEDOM OF THE DESCRIBED
DEVICES
FROM
INTELLECTUAL
PROPERTY
INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY
OF MERCHANTABILITY OR FITNESS FOR ANY
PURPOSE.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
FAX 408 370-8056
Internet: http://www.zilog.com
58
P R E L I M I N A R Y
DS97Z8X1500
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