Z86E0812PSG [IXYS]
Microcontroller, 8-Bit, OTPROM, 12MHz, CMOS, PDIP18, PLASTIC, DIP-18;
| 型号： | Z86E0812PSG |
| 厂家： | 
IXYS CORPORATION |
| 描述： | Microcontroller, 8-Bit, OTPROM, 12MHz, CMOS, PDIP18, PLASTIC, DIP-18 可编程只读存储器 电动程控只读存储器 时钟 微控制器 光电二极管 外围集成电路 装置 |
| 文件： | 总44页 (文件大小：211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY PRODUCT SPECIFICATION
1
Z86E04/E08
1
CMOS Z8 OTP MICROCONTROLLERS
PRODUCT DEVICES
Part
Oscillator
Type
Operating
VCC
Operating
ROM
(KB)
Number
Temperature
Package
Z86E0412PEC
Crystal
Crystal
RC
4.5V–5.5V
4.5V–5.5V
4.5V–5.5V
4.5V–5.5V
4.5V–5.5V
4.5V–5.5V
4.5V–5.5V
4.5V–5.5V
4.5V–5.5V
4.5V–5.5V
4.5V–5.5V
4.5V–5.5V
4.5V–5.5V
4.5V–5.5V
4.5V–5.5V
4.5V–5.5V
–40°C/105°C
0°C/70°C
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
18-Pin DIP
18-Pin DIP
18-Pin DIP
18-Pin DIP
18-Pin SOIC
18-Pin SOIC
18-Pin SOIC
18-Pin SOIC
18-Pin DIP
18-Pin DIP
18-Pin DIP
18-Pin DIP
18-Pin SOIC
18-Pin SOIC
18-Pin SOIC
18-Pin SOIC
Z86E0412PSC1866
Z86E0412PSC1903
Z86E0412PEC1903
Z86E0412SEC
0°C/70°C
RC
–40°C/105°C
–40°C/105°C
0°C/70°C
Crystal
Crystal
RC
Z86E0412SSC1866
Z86E0412SSC1903
Z86E0412SEC1903
Z86E0812PEC
0°C/70°C
RC
–40°C/105°C
–40°C/105°C
0°C/70°C
Crystal
Crystal
RC
Z86E0812PSC1866
Z86E0812PSC1903
Z86E0812PEC1903
Z86E0812SEC
0°C/70°C
RC
–40°C/105°C
–40°C/105°C
0°C/70°C
Crystal
Crystal
RC
Z86E0812SSC1866
Z86E0812SSC1903
Z86E0812SEC1903
0°C/70°C
RC
–40°C/105°C
Several key product features of the extensive family of Zilog Z86E04/E08 CMOS OTP microcontrollers are presented in
the above table. This table enables the user to identify which of the E04/E08 product variants most closely match the us-
er’s application requirements.
DS97Z8X1104
P R E L I M I N A R Y
1
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
FEATURES
■ 14 Input/Output Lines
■ Two Programmable 8-Bit Counter/Timers, Each with
6-Bit Programmable Prescaler
■ Six Vectored, Prioritized Interrupts
(3 falling edge, 1 rising edge, 2 timers)
■ WDT/ Power-On Reset (POR)
■ Two Analog Comparators
■ On-Chip Oscillator that Accepts XTAL, Ceramic
Resonance, LC, RC, or External Clock
■ Program Options:
■ Clock-Free WDT Reset
–
–
–
–
–
Low Noise
ROM Protect
■ Low-Power Consumption (50 mw typical)
■ Fast Instruction Pointer (1µs @ 12 MHz)
■ RAM Bytes (125)
Auto Latch
Watch-Dog Timer (WDT)
EPROM/Test Mode Disable
GENERAL DESCRIPTION
Zilog's Z86E04/E08 Microcontrollers (MCU) are One-Time
Programmable (OTP) members of Zilog’s single-chip Z8®
MCU family that allow easy software development, debug,
prototyping, and small production runs not economically
desirable with masked ROM versions.
Note: All Signals with an overline, “ ”, are active Low, for
example: B/W (WORD is active Low); B/W (BYTE is active
Low, only).
Power connections follow conventional descriptions be-
low:
For applications demanding powerful I/O capabilities, the
Z86E04/E08's dedicated input and output lines are
grouped into three ports, and are configurable under soft-
ware control to provide timing, status signals, or parallel
I/O.
Connection
Power
Circuit
VCC
Device
VDD
VSS
Ground
GND
Two on-chip counter/timers, with a large number of user
selectable modes, offload the system of administering
real-time tasks such as counting/timing and I/O data com-
munications.
2
P R E L I M I N A R Y
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
Input
XTAL
Vcc
GND
1
Machine
Timing & Inst.
Control
Port 3
Counter/
Timers (2)
ALU
OTP
FLAG
Interrupt
Control
Register
Pointer
Two Analog
Comparators
Program
Counter
General-Purpose
Register File
Port 2
Port 0
I/O
I/O
(Bit Programmable)
Figure 1. Functional Block Diagram
DS97Z8X1104
P R E L I M I N A R Y
3
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
GENERAL DESCRIPTION (Continued)
D7–0
AD 10–0
Z8 MCU
AD 10–0
Address
MUX
D7–0
Data
MUX
EPROM
AD 10–0
Address
Counter
D7–0
Z8
Port 2
3 bits
ROM PROT
Low Noise
Clear Clock
P00 P01
PGM
Mode Logic
VPP
P33
EPM
P32
PGM
P30
OE
P31
CE
XT1
Figure 2. EPROM Programming Mode Block Diagram
4
P R E L I M I N A R Y
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
PIN DESCRIPTION
1
1
D4
D5
D6
D7
VCC
18
D3
D2
D1
D0
GND
PGM
CLOCK
CLEAR
VPP
1
P24
P25
P26
P27
VCC
18
P23
P22
P21
P20
GND
P02
P01
P00
P33
NC
CE
OE
XTAL2
XTAL1
P31
9
10
9
10
EPM
P32
Figure 3. 18-Pin EPROM Mode Configuration
Figure 4. 18-Pin DIP/SOIC Mode Configuration
Table 1. 18-Pin DIP Pin Identification
EPROM Programming Mode
Table 2. 18-Pin DIP/SOIC Pin Identification
Standard Mode
Pin #
Symbol
Function
Direction
Pin #
Symbol
Function
Direction
1–4
5
D4–D7
VCC
Data 4, 5, 6, 7
Power Supply
In/Output
1–4
5
P24–P27
VCC
Port 2, Pins 4,5,6,7
Power Supply
In/Output
6
NC
No Connection
Chip Enable
6
XTAL2
XTAL1
P31
Crystal Osc. Clock
Crystal Osc. Clock
Port 3, Pin 1, AN1
Port 3, Pin 2, AN2
Port 3, Pin 3, REF
Port 0, Pins 0,1,2
Ground
Output
Input
7
CE
Input
Input
Input
Input
7
8
OE
Output Enable
EPROM Prog Mode
Prog Voltage
8
Input
9
EPM
VPP
9
P32
Input
10
11
12
13
14
15–18
10
P33
Input
Clear
Clock
PGM
GND
D0–D3
Clear Clock
Address
Input
Input
Input
11–13 P00–P02
14 GND
15–18 P20–P23
In/Output
Prog Mode
Ground
Port 2, Pins 0,1,2,3
In/Output
Data 0,1, 2, 3
In/Output
DS97Z8X1104
P R E L I M I N A R Y
5
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; functional operation of the
device at any condition above those indicated in the oper-
ational sections of these specifications is not implied. Ex-
posure to absolute maximum rating conditions for an ex-
tended period may affect device reliability. Total power
dissipation should not exceed 462 mW for the package.
Power dissipation is calculated as follows:
Total Power Dissipation = VDD x [IDD–(sum of IOH)]
+ sum of [(VDD–VOH) x IOH
+ sum of (V0L x I0L)
]
Parameter
Min
Max
Units
Note
Ambient Temperature under Bias
Storage Temperature
–40
–65
–0.7
+105
+150
+12
C
C
V
Voltage on any Pin with Respect to VSS
Voltage on VDD Pin with Respect to VSS
Voltage on Pins 7, 8, 9, 10 with Respect to VSS
Total Power Dissipation
1
2
–0.3
–0.6
+7
VDD+1
1.65
300
V
V
W
Maximum Allowable Current out of VSS
Maximum Allowable Current into VDD
mA
220
+600
+600
25
mA
µA
Maximum Allowable Current into an Input Pin
Maximum Allowable Current into an Open-Drain Pin
Maximum Allowable Output Current Sinked by Any I/O Pin
Maximum Allowable Output Current Sourced by Any I/O Pin
Total Maximum Output Current Sinked by a Port
Total Maximum Output Current Sourced by a Port
Notes:
–600
–600
3
4
µA
mA
mA
mA
mA
25
60
45
1. This applies to all pins except where otherwise noted. Maximum current into pin must be ± 600 µA.
2. There is no input protection diode from pin to VDD(not applicable to EPROM Mode).
3. This excludes Pin 6 and Pin 7.
4. Device pin is not at an output Low state.
6
P R E L I M I N A R Y
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin (Fig-
ure 5).
From Output
Under Test
1
150 pF
Figure 5. Test Load Diagram
CAPACITANCE
TA = 25°C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
Parameter
Min
Max
Input capacitance
Output capacitance
I/O capacitance
0
0
0
10 pF
20 pF
25 pF
DS97Z8X1104
P R E L I M I N A R Y
7
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
DC ELECTRICAL CHARACTERISTICS
Standard Temperature
TA = 0°C to +70°C
Typical
VCC [4]
Sym
Parameter
Min
Max
12
@ 25°C Units Conditions
Notes
VINMAX Max Input Voltage
4.5V
5.5V
4.5V
V
V
V
IIn<250 µA
IIn<250 µA
1
1
12
VCH
Clock Input High
Voltage
0.8 VCC VCC+0.3
2.8
2.8
1.7
1.7
Driven by External
Clock Generator
5.5V
4.5V
5.5V
0.8 VCC VCC+0.3
V
V
V
Driven by External
Clock Generator
VCL
Clock Input Low
Voltage
VSS–0.3
VSS–0.3
0.2 VCC
0.2 VCC
Driven by External
Clock Generator
Driven by External
Clock Generator
VIH
VIL
Input High Voltage
Input Low Voltage
Output High Voltage
4.5V
5.5V
0.7 VCC VCC+0.3
0.7 VCC VCC+0.3
2.8
2.8
V
V
4.5V
5.5V
VSS–0.3
VSS–0.3
0.2 VCC
0.2 VCC
1.5
1.5
V
V
VOH
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
VCC–0.4
VCC–0.4
VCC–0.4
VCC–0.4
4.8
4.8
4.8
4.8
0.1
0.1
0.1
0.1
0.8
0.8
10.0
10.0
2.8
V
V
IOH = –2.0 mA
5
5
IOH = –2.0 mA
V
Low Noise @ IOH = –0.5 mA
Low Noise @ IOH = –0.5 mA
IOL = +4.0 mA
V
VOL1
Output Low Voltage
Output Low Voltage
0.8
0.4
V
5
5
V
IOL = +4.0 mA
0.4
V
Low Noise @ IOL = 1.0 mA
Low Noise @ IOL = 1.0 mA
IOL = +12 mA,
0.4
V
VOL2
0.8
V
5
5
0.8
V
IOL = +12 mA,
VOFFSET Comparator Input
Offset Voltage
25.0
25.0
3.0
mV
mV
V
VLV
VCC Low Voltage
Auto Reset
2.2
@ 6 MHz Max.
Int. CLK Freq.
IIL
Input Leakage
(Input Bias Current of
Comparator)
4.5V
5.5V
–1.0
–1.0
1.0
1.0
µA VIN = 0V, VCC
µA VIN = 0V, VCC
IOL
Output Leakage
4.5V
5.5V
–1.0
–1.0
0
1.0
1.0
µA VIN = 0V, VCC
µA VIN = 0V, VCC
V
VICR
Comparator Input
Common Mode
Voltage Range
VCC –1.0
8
P R E L I M I N A R Y
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
TA = 0°C to +70°C
Typical
@ 25°C Units Conditions
VCC [4]
Sym Parameter
Min
Max
Notes
ICC
Supply Current
4.5V
11.0
6.8
mA All Output and I/O Pins
5,7
1
Floating @ 2 MHz
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
11.0
15.0
15.0
20.0
20.0
4.0
6.8
mA All Output and I/O Pins
Floating @ 2 MHz
5,7
5,7
5,7
5,7
5,7
5,7
8.2
mA All Output and I/O Pins
Floating @ 8 MHz
8.2
mA All Output and I/O Pins
Floating @ 8 MHz
12.0
12.0
2.5
mA All Output and I/O Pins
Floating @ 12 MHz
mA All Output and I/O Pins
Floating @ 12 MHz
ICC1
Standby Current
mA HALT Mode VIN = 0V,
VCC @ 2 MHz
5.5V
4.5V
5.5V
4.5V
5.5V
4.0
5.0
5.0
7.0
7.0
2.5
3.0
3.0
4.0
4.0
mA HALT Mode VIN = 0V,
VCC @ 2 MHz
5,7
5,7
5,7
5,7
5,7
mA HALT Mode VIN = 0V,
VCC @ 8 MHz
mA HALT Mode VIN = 0V,
VCC @ 8 MHz
mA HALT Mode VIN = 0V,
VCC @ 12 MHz
mA HALT Mode VIN = 0V,
VCC @ 12 MHz
ICC
Supply Current
(Low Noise Mode)
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
11.0
11.0
13.0
13.0
15.0
15.0
6.8
6.8
7.5
7.5
8.2
8.2
mA All Output and I/O Pins
Floating @ 1 MHz
7
7
7
7
7
7
mA All Output and I/O Pins
Floating @ 1 MHz
mA All Output and I/O Pins
Floating @ 2 MHz
mA All Output and I/O Pins
Floating @ 2 MHz
mA All Output and I/O Pins
Floating @ 4 MHz
mA All Output and I/O Pins
Floating @ 4 MHz
DS97Z8X1104
P R E L I M I N A R Y
9
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
DC ELECTRICAL CHARACTERISTICS (Continued)
TA = 0°C to +70°C
Typical
VCC [4]
Sym Parameter
Min
Max
@ 25°C
Units Conditions
Notes
ICC1 Standby Current
(Low Noise Mode)
4.5V
4.0
2.5
2.5
2.8
2.8
3.0
3.0
1.0
1.0
mA HALT Mode VIN = 0V,
VCC @ 1 MHz
7
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.0
4.5
mA HALT Mode VIN = 0V,
VCC @ 1 MHz
7
7
mA HALT Mode VIN = 0V,
VCC @ 2 MHz
4.5
mA HALT Mode VIN = 0V,
VCC @ 2 MHz
7
5.0
mA HALT Mode VIN = 0V,
VCC @ 4 MHz
7
5.0
mA HALT Mode VIN = 0V,
VCC @ 4 MHz
7
ICC2 Standby Current
10.0
10.0
µA
STOP Mode VIN = 0V, VCC
WDT is not Running
STOP Mode VIN = 0V,VCC
WDT is not Running
0V < VIN < VCC
7,8
7,8
µA
IALL Auto Latch Low
Current
4.5V
5.5V
4.5V
5.5V
32.0
32.0
16
16
µA
µA
µA
µA
0V < VIN < VCC
0V < VIN < VCC
0V < VIN < VCC
IALH Auto Latch High
Current
–16.0
–16.0
–8.0
–8.0
Notes:
1. Port 2 and Port 0 only
2. VSS = 0V = GND
3. The device operates down to VLV of the specified frequency for VLV . The minimum operational VCC is determined on the value of
the voltage VLV at the ambient temperature. The VLV increases as the temperature decreases.
4. VCC = 4.5 to 5.5V, typical values measured at VCC = 5.0V.
The VCC voltage specification of 5.5 V guarantees 5.0 V ± 0.5V with typical values measured at VCC = 5.0V.
5. Standard Mode (not Low EMI Mode)
6. Z86E08 only
7. All outputs unloaded and all inputs are at VCC or VSS level.
8. If analog comparator is selected, then the comparator inputs must be at VCC level.
10
P R E L I M I N A R Y
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
DC ELECTRICAL CHARACTERISTICS
Extended Temperature
1
TA = –40°C to
+105°C
Min Max
Typical
VCC [4]
Sym
Parameter
@ 25°C
Units
Conditions
IIN < 250 µA
Notes
VINMAX Max Input Voltage
4.5V
5.5V
4.5V
12.0
12.0
V
V
V
1
1
IIN < 250 µA
VCH
Clock Input High
Voltage
0.8 VCC VCC+0.3
0.8 VCC VCC+0.3
VSS–0.3 0.2 VCC
VSS–0.3 0.2 VCC
2.8
2.8
1.7
1.7
Driven by External
Clock Generator
5.5V
4.5V
5.5V
V
V
V
Driven by External
Clock Generator
VCL
Clock Input Low
Voltage
Driven by External
Clock Generator
Driven by External
Clock Generator
VIH
VIL
Input High Voltage
Input Low Voltage
4.5V
5.5V
4.5V
5.5V
0.7 VCC VCC+0.3
2.8
2.8
1.5
1.5
4.8
4.8
V
V
0.7 VCC VCC+0.3
VSS–0.3 0.2 VCC
V
VSS–0.3 0.2 VCC
V
VOH
Output High Voltage 4.5V
VCC–0.4
VCC–0.4
VCC–0.4
VCC–0.4
0.4
V
IOH = –2.0 mA
5
5
5.5V
4.5V
5.5V
V
IOH = –2.0 mA
V
Low Noise @ IOH = –0.5 mA
Low Noise @ IOH = –0.5 mA
IOL = +4.0 mA
V
VOL1
Output Low Voltage
Output Low Voltage
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
0.1
0.1
V
5
5
0.4
V
IOL = +4.0 mA
0.4
0.1
V
Low Noise @ IOL = 1.0 mA
Low Noise @ IOL = 1.0 mA
IOL = +12 mA,
0.4
0.1
V
VOL2
1.0
0.3
V
5
5
1.0
0.3
V
IOL = +12 mA,
VOFFSET Comparator Input
Offset Voltage
25.0
10.0
10.0
2.8
mV
mV
V
25.0
VLV
VCC Low Voltage
Auto Reset
1.8
3.8
@ 6 MHz Max. Int.
CLK Freq.
3
IIL
Input Leakage
(Input Bias Current
of Comparator)
4.5V
5.5V
–1.0
–1.0
1.0
1.0
µA
µA
VIN = 0V, VCC
VIN = 0V, VCC
IOL
Output Leakage
4.5V
5.5V
–1.0
–1.0
1.0
1.0
µA
µA
V
VIN = 0V, VCC
VIN = 0V, VCC
VICR
Comparator Input
Common Mode
Voltage Range
0
VCC –1.5
DS97Z8X1104
P R E L I M I N A R Y
11
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
DC ELECTRICAL CHARACTERISTICS (Continued)
TA = –40°C to
+105°C
Min Max
Typical
VCC [4]
Sym
Parameter
@ 25°C
Units
Conditions
Notes
ICC
Supply Current
4.5V
11.0
11.0
15.0
15.0
20.0
20.0
5.0
6.8
mA
All Output and I/O Pins
Floating @ 2 MHz
5,7
5,7
5,7
5,7
5,7
5,7
5,7
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
6.8
8.2
mA
mA
mA
mA
mA
mA
All Output and I/O Pins
Floating @ 2 MHz
All Output and I/O Pins
Floating @ 8 MHz
8.2
All Output and I/O Pins
Floating @ 8 MHz
12.0
12.0
2.5
All Output and I/O Pins
Floating @ 12 MHz
All Output and I/O Pins
Floating @ 12 MHz
ICC1
Standby Current
HALT Mode VIN = 0V,
VCC @ 2 MHz
5.5V
4.5V
5.5V
4.5V
5.5V
5.0
5.0
5.0
7.0
7.0
2.5
3.0
3.0
4.0
4.0
mA
mA
mA
mA
mA
HALT Mode VIN = 0V,
VCC @ 2 MHz
5,7
5,7
5,7
5,7
5,7
HALT Mode VIN = 0V,
VCC @ 8 MHz
HALT Mode VIN = 0V,
VCC @ 8 MHz
HALT Mode VIN = 0V,
VCC @ 12 MHz
HALT Mode VIN = 0V,
VCC @ 12 MHz
ICC
Supply Current
(Low Noise Mode)
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
11.0
11.0
13.0
13.0
15.0
15.0
6.8
6.8
7.5
7.5
8.2
8.2
mA
mA
mA
mA
mA
mA
All Output and I/O Pins
Floating @ 1 MHz
7
7
7
7
7
7
All Output and I/O Pins
Floating @ 1 MHz
All Output and I/O Pins
Floating @ 2 MHz
All Output and I/O Pins
Floating @ 2 MHz
All Output and I/O Pins
Floating @ 4 MHz
All Output and I/O Pins
Floating @ 4 MHz
12
P R E L I M I N A R Y
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
TA = –40°C to +105°C
Typical
@ 25°C Units Conditions
VCC [4]
Sym
Parameter
Min
Max
Notes
ICC1
Standby Current
(Low Noise Mode)
4.5V
4.0
2.5
2.5
2.8
2.8
3.0
3.0
1.0
1.0
mA HALT Mode VIN = 0V,
7
1
VCC @ 1 MHz
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.0
4.5
4.5
5.0
5.0
20
mA HALT Mode VIN = 0V,
VCC @ 1 MHz
7
7
mA HALT Mode VIN = 0V,
VCC @ 2 MHz
mA HALT Mode VIN = 0V,
VCC @ 2 MHz
7
mA HALT Mode VIN = 0V,
VCC @ 4 MHz
7
mA HALT Mode VIN = 0V,
VCC @ 4 MHz
7
ICC2
Standby Current
µA STOP Mode VIN = 0V, VCC
WDT is not Running
7,8
7,8
20
µA STOP Mode VIN = 0V, VCC
WDT is not Running
IALL
Auto Latch Low
Current
4.5V
5.5V
4.5V
5.5V
40
40
16
16
µA 0V < VIN < VCC
µA 0V < VIN < VCC
µA 0V < VIN < VCC
µA 0V < VIN < VCC
IALH
Auto Latch High
Current
–20.0
–20.0
–8.0
–8.0
Notes:
1. Port 2 and Port 0 only
2. VSS = 0V = GND
3. The device operates down to VLV of the specified frequency for VLV . The minimum operational VCC is determined on the value of
the voltage VLV at the ambient temperature. The VLV increases as the temperature decreases.
4. VCC = 4.5V to 5.5V, typical values measured at VCC = 5.0V
5. Standard Mode (not Low EMI Mode)
6. Z86E08 only
7. All outputs unloaded and all inputs are at VCC or VSS level.
8. If analog comparator is selected, then the comparator inputs must be at VCC level.
DS97Z8X1104
P R E L I M I N A R Y
13
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
AC ELECTRICAL CHARACTERISTICS
3
1
Clock
2
2
3
7
7
TIN
4
5
6
IRQ N
8
9
Figure 6. AC Electrical Timing Diagram
14
P R E L I M I N A R Y
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
AC ELECTRICAL CHARACTERISTICS
Timing Table (Standard Mode for SCLK/TCLK = XTAL/2)
Standard Temperature
1
TA= 0 °C to +70 °C
8 MHz 12 MHz
15
VCC
No
Symbol
TpC
Parameter
Input Clock Period
Min
Max
Min
Max
Units
Notes
1
2
3
4
5
6
7
8
9
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
125
125
DC
DC
25
83
83
DC
DC
15
ns
ns
ns
ns
ns
ns
ns
ns
1
1
TrC,TfC
TwC
Clock Input Rise
and Fall Times
1
25
15
1
Input Clock Width
62
62
41
41
1
1
TwTinL
TwTinH
TpTin
Timer Input Low Width
Timer Input High Width
Timer Input Period
100
70
100
70
1
1
5TpC
5TpC
5TpC
5TpC
1
1
8TpC 8TpC
1
8TpC 8TpC
1
TrTin,
TtTin
Timer Input Rise
and Fall Time
100
100
100
ns
ns
ns
ns
1
100
1
TwIL
TwIH
Twdt
Tpor
Int. Request Input
Low Time
70
70
70
1,2
1,2
1,2
1,2
1
70
5TpC 5TpC
5TpC 5TpC
12
Int. Request Input
High Time
10
Watch-Dog Timer
Delay Time for Timeout
12
12
20
20
ms
ms
ms
ms
12
1
11
Power-On Reset Time
80
80
20
20
80
80
1
1
Notes:
1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
2. Interrupt request through Port 3 (P33–P31).
DS97Z8X1104
P R E L I M I N A R Y
15
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
AC ELECTRICAL CHARACTERISTICS
Timing Table (Standard Mode for SCLK/TCLK = XTAL/2)
Extended Temperature
TA= –40 °C to +105 °C
8 MHz 12 MHz
VCC
No
Symbol
TpC
Parameter
Min
Max
Min
Max
Units
Notes
1
2
3
4
5
6
7
8
9
Input Clock Period
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
125
125
DC
DC
25
25
62
62
83
83
DC
DC
15
15
41
41
ns
ns
ns
ns
ns
ns
ns
ns
1
1
TrC,TfC
TwC
Clock Input Rise
and Fall Times
1
1
Input Clock Width
1
1
TwTinL
TwTinH
TpTin
Timer Input Low Width
Timer Input High Width
Timer Input Period
70
70
1
70
70
1
5TpC
5TpC
8TpC
8TpC
5TpC
5TpC
8TpC
8TpC
1
1
1
1
TrTin,
TtTin
Timer Input Rise
and Fall Time
100
100
100
100
ns
ns
ns
ns
1
1
TwIL
TwIH
Twdt
Tpor
Int. Request Input
Low Time
70
70
70
70
1,2
1,2
1,2
1,2
1
Int. Request Input
High Time
5TpC
5TpC
10
5TpC
5TpC
10
10
Watch-Dog Timer
Delay Time for Timeout
ms
ms
ms
ms
10
10
1
11
Power-On Reset Time
12
100
100
12
100
100
1
12
12
1
Notes:
1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
2. Interrupt request made through Port 3 (P33–P31).
16
P R E L I M I N A R Y
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
AC ELECTRICAL CHARACTERISTICS
Low Noise Mode, Standard Temperature
1
TA= 0 °C to +70 °C
1 MHz 4 MHz
VCC
No
Symbol
Parameter
Min
Max
Min
Max
Units
Notes
1
TPC
Input Clock Period
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
1000
1000
DC
DC
25
250
250
DC
DC
25
ns
ns
ns
ns
ns
ns
ns
ns
1
1
2
TrC
TfC
Clock Input Rise
and Fall Times
1
25
25
1
3
TwC
Input Clock Width
500
500
125
125
1
1
4.
TwTinL
TwTinH
TpTin
Timer Input Low Width
Timer Input High Width
Timer Input Period
70
70
1
70
70
1
5
2.5TpC
2.5TpC
4TpC
4TpC
2.5TpC
2.5TpC
4TpC
4TpC
1
1
6
1
1
7
TrTin,
TtTin
Timer Input Rise
and Fall Time
100
100
100
100
ns
ns
ns
ns
1
1
8
TwIL
Low Time
Int. Request Input
70
70
70
70
1,2
1,2
1,2
1,2
1
9
TwIH
High Time
Int. Request Input
2.5TpC
2.5TpC
12
2.5TpC
2.5TpC
12
10
Twdt
Watch-Dog Timer
Delay Time for Timeout
ms
ms
12
12
1
Notes:
1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
2. Interrupt request through Port 3 (P33–P31).
DS97Z8X1104
P R E L I M I N A R Y
17
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
AC ELECTRICAL CHARACTERISTICS (Continued)
Low Noise Mode, Extended Temperature
TA= –40 °C to +105 °C
1 MHz 4 MHz
VCC
No
Symbol
Parameter
Min
Max
Min
Max
Units
Notes
1
TPC
Input Clock Period
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
1000
1000
DC
DC
25
250
250
DC
DC
25
ns
ns
ns
ns
ns
ns
ns
ns
1
1
2
TrC
TfC
Clock Input Rise
and Fall Times
1
25
25
1
3
TwC
Input Clock Width
500
500
125
125
1
1
4.
TwTinL
TwTinH
TpTin
Timer Input Low Width
Timer Input High Width
Timer Input Period
70
70
1
70
70
1
5
2.5TpC
2.5TpC
2.5TpC
2.5TpC
4TpC
4TpC
1
1
6
4TpC
4TpC
100
1
1
7
TrTin,
TtTin
Timer Input Rise
and Fall Time
100
100
ns
ns
ns
ns
1
100
1
8
TwIL
TwIH
Twdt
Int. Request Input
Low Time
70
70
70
70
1,2
1,2
1,2
1,2
1
9
Int. Request Input
High Time
2.5TpC
2.5TpC
10
2.5TpC
2.5TpC
10
10
Watch-Dog Timer
Delay Time for Timeout
ms
ms
10
10
1
Notes:
1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.
2. Interrupt request through Port 3 (P33–P31).
18
P R E L I M I N A R Y
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
LOW NOISE VERSION
Low EMI Emission
■ Output drivers have resistances of 500 Ohms (typical).
■ Oscillator divide-by-two circuitry eliminated.
1
The Z86E04/E08 can be programmed to operate in a Low
EMI Emission Mode by means of a mask ROM bit option.
Use of this feature results in:
The Low EMI Mode is mask-programmable to be selected
by the customer at the time the ROM code is submitted.
■ All pre-driver slew rates reduced to 10 ns typical.
■ Internal SCLK/TCLK operation limited to a maximum of
4 MHz–250 ns cycle time.
PIN FUNCTIONS
Clock Address Clock. This pin is a clock input. The internal
address counter increases by one with one clock cycle.
OTP Programming Mode
D7–D0 Data Bus. Data can be read from, or written to, the
EPROM through this data bus.
PGM Program Mode (active Low). A Low level at this pin
programs the data to the EPROM through the Data Bus.
VCC Power Supply. It is typically 5V during EPROM Read
Mode and 6.4V during the other modes (Program, Pro-
gram Verify, and so on).
Application Precaution
The production test-mode environment may be enabled
accidentally during normal operation if excessive noise
surges above VCC occur on the XTAL1 pin.
CE Chip Enable (active Low). This pin is active during
EPROM Read Mode, Program Mode, and Program Verify
Mode.
In addition, processor operation of Z8 OTP devices may be
affected by excessive noise surges on the VPP, CE, EPM,
OE pins while the microcontroller is in Standard Mode.
OE Output Enable (active Low). This pin drives the Data
Bus direction. When this pin is Low, the Data Bus is output.
When High, the Data Bus is input.
Recommendations for dampening voltage surges in both
test and OTP Mode include the following:
EPM EPROM Program Mode. This pin controls the differ-
ent EPROM Program Modes by applying different
voltages.
■ Using a clamping diode to VCC.
■ Adding a capacitor to the affected pin.
VPP Program Voltage. This pin supplies the program volt-
age.
Clear Clear (active High). This pin resets the internal ad-
dress counter at the High Level.
Note: Programming the EPROM/Test Mode Disable
option will prevent accidental entry into EPROM Mode or
Test Mode.
DS97Z8X1104
P R E L I M I N A R Y
19
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
PIN FUNCTIONS (Continued)
XTAL1, XTAL2 Crystal In, Crystal Out (time-based input
and output, respectively). These pins connect a parallel-
resonant crystal, LC, or an external single-phase clock
(8 MHz or 12 MHz max) to the on-chip clock oscillator and
buffer.
Auto Latch. The Auto Latch puts valid CMOS levels on all
CMOS inputs (except P33, P32, P31) that are not external-
ly driven. A valid CMOS level, rather than a floating node,
reduces excessive supply current flow in the input buffer.
On Power-up and Reset, the Auto Latch will set the ports
to an undetermined state of 0 or 1. Default condition is
Auto Latches enabled.
Port 0, P02–P00. Port 0 is a 3-bit bidirectional, Schmitt-
triggered CMOS-compatible I/O port. These three I/O lines
can be globally configured under software control to be in-
puts or outputs (Figure 7).
Port 0 (I/O)
Z8
OE
PAD
Out
VCC@ 5.0V
2.3 Hysteresis
1.5
In
Auto Latch Option
R
500 kΩ
Figure 7. Port 0 Configuration
P R E L I M I N A R Y
20
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
Port 2, P27–P20. Port 2 is an 8-bit, bit programmable, bi-
directional, Schmitt-triggered CMOS-compatible I/O port.
These eight I/O lines can be configured under software
control to be inputs or outputs, independently. Bits pro-
grammed as outputs can be globally programmed as ei-
ther push-pull or open-drain (Figure 8).
1
Z8
Port 2 (I/O)
Open-Drain
/OE
PAD
Out
1.5
2.3 Hysteresis
VCC @ 5.0V
In
Auto Latch Option
R
500 kΩ
Figure 8. Port 2 Configuration
DS97Z8X1104
P R E L I M I N A R Y
21
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
PIN FUNCTIONS (Continued)
Port 3, P33–P31. Port 3 is a 3-bit, CMOS-compatible port
with three fixed input (P33–P31) lines. These three input
lines can be configured under software control as digital
Schmitt-trigger inputs or analog inputs.
These three input lines are also used as the interrupt
sources IRQ0–IRQ3, and as the timer input signal TIN (Fig-
ure 9).
Z8
Port 3
0 = Digital
R247 = P3M 1 = Analog
D1
TIN
DIG.
AN.
P31 Data Latch
IRQ2
PAD
+
-
P31 (AN1)
IRQ3
P32 Data Latch
IRQ0
PAD
PAD
+
-
P32 (AN2)
P33 (REF)
P33 Data Latch
IRQ1
V
cc
IRQ 0,1,2 = Falling Edge Detection
IRQ3 = Rising Edge Detection
Figure 9. Port 3 Configuration
22
P R E L I M I N A R Y
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
Comparator Inputs. Two analog comparators are added
to input of Port 3, P31, and P32, for interface flexibility. The
comparators reference voltage P33 (REF) is common to
both comparators.
Mode. The common voltage range is 0–4 V when the VCC
is 5.0V; the power supply and common mode rejection ra-
tios are 90 dB and 60 dB, respectively.
1
Interrupts are generated on either edge of Comparator 2's
output, or on the falling edge of Comparator 1's output.
The comparator output is used for interrupt generation,
Port 3 data inputs, or TIN through P31. Alternatively, the
comparators can be disabled, freeing the reference input
(P33) for use as IRQ1 and/or P33 input.
Typical applications for the on-board comparators; Zero
crossing detection, A/D conversion, voltage scaling, and
threshold detection. In Analog Mode, P33 input functions
serve as a reference voltage to the comparators.
The dual comparator (common inverting terminal) features
a single power supply which discontinues power in STOP
FUNCTIONAL DESCRIPTION
The following special functions have been incorporated
into the Z8 devices to enhance the standard Z8 core archi-
tecture to provide the user with increased design flexibility.
RESET. This function is accomplished by means of a Pow-
er-On Reset or a Watch-Dog Timer Reset. Upon power-
up, the Power-On Reset circuit waits for TPOR ms, plus 18
clock cycles, then starts program execution at address
000C (Hex) (Figure 10). The Z8 control registers' reset val-
ue is shown in Table 3.
INT OSC
XTAL OSC
POR
(Cold Start)
Chip Reset
Delay Line
TPOR msec
18 CLK
Reset Filiter
P27
(Stop Mode)
Figure 10. Internal Reset Configuration
Power-On Reset (POR). A timer circuit clocked by a ded-
icated on-board RC oscillator is used for a POR timer func-
tion. The POR time allows VCC and the oscillator circuit to
stabilize before instruction execution begins. The POR
timer circuit is a one-shot timer triggered by one of the four
following conditions:
Watch-Dog Timer Reset. The WDT is a retriggerable
one-shot timer that resets the Z8 if it reaches its terminal
count. The WDT is initially enabled by executing the WDT
instruction and is retriggered on subsequent execution of
the WDT instruction. The timer circuit is driven by an on-
board RC oscillator.
■ Power-bad to power-good status
■ Stop-Mode Recovery
■ WDT time-out
■ WDH time-out
DS97Z8X1104
P R E L I M I N A R Y
23
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Table 3. Control Registers
Reset Condition
Addr.
Reg.
D7
D6
D5
D4
D3
D2
D1
D0 Comments
FF
FD
FC
FB
FA
SPL
RP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FLAGS
IMR
U
0
U
U
U
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
IRQ
U
0
IRQ3 is used for positive edge
detection
F9
IPR
U
U
U
1
U
U
U
1
U
U
U
1
U
0
U
U
U
1
U
U
U
1
U
0
U
1
0
1
0
U
0
U
0
F8*
F7*
F6*
F5
P01M
P3M
P2M
PRE0
T0
U
1
0
1
Inputs after reset
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
0
F4
F3
PRE1
T1
F2
U
0
F1
TMR
Note: *Registers are not reset after a STOP-Mode Recovery using P27 pin. A subsequent reset will cause these control registers to
be reconfigured as shown in Table 4 and the user must avoid bus contention on the port pins or it may affect device reliability.
24
P R E L I M I N A R Y
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
Program Memory. The Z86E04/E08 addresses up to
1K/2KB of Internal Program Memory (Figure 11). The first
12 bytes of program memory are reserved for the interrupt
vectors. These locations contain six 16-bit vectors that cor-
respond to the six available interrupts. Bytes 0–1024/2048
are on-chip one-time programmable ROM.
Register File. The Register File consists of three I/O port
registers, 124 general-purpose registers, and 14 control
and status registers R0–R3, R4–R127 and R241–R255,
respectively (Figure 12). General-purpose registers occu-
py the 04H to 7FH address space. I/O ports are mapped
as per the existing CMOS Z8.
1
Identifiers
1023/2047
Location
Identifiers
SPL
3FFH/7FFH
255 (FFH)
Stack Pointer (Bits 7-0)
Location of
First Byte of
Instruction
Executed
After RESET
On-Chip
ROM
254 (FE)
253 (FD)
252 (FC)
General-Purpose Register
GPR
RP
Register Pointer
12
11
0CH
0BH
FLAGS
Program Control Flags
Interrupt Mask Register
Interrupt Request Register
Interrupt Priority Register
IRQ5
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQ0
IRQ0
IMR
IRQ
251 (FB)
250 (FA)
10
9
0AH
09H
IPR
249 (F9)
248 (F8)
8
7
6
08H
07H
06H
P01M
P3M
P2M
PRE0
T0
Ports 0-1 Mode
Port 3 Mode
Interrupt
Vector
(Lower Byte)
247 (F7)
246 (F6)
245 (F5)
Port 2 Mode
T0 Prescaler
5
4
05H
04H
Interrupt
Vector
(Upper Byte)
244 (F4)
243 (F3)
242 (F2)
241 (F1H)
Timer/Counter 0
T1 Prescaler
3
03H
PRE1
T1
2
1
0
02H
01H
00H
Timer/Counter 1
TMR
Timer Mode
Not Implemented
Figure 11. Program Memory Map
128
127 (7FH)
General-Purpose
Registers
4
3
P3
P2
P1
P0
Port 3
Port 2
2
1
Reserved
Port 0
0 (00H)
Figure 12. Register File
DS97Z8X1104
P R E L I M I N A R Y
25
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
The Z8 instructions can access registers directly or indi-
rectly through an 8-bit address field. This allows short 4-bit
register addressing using the Register Pointer.
Stack Pointer. The Z8 has an 8-bit Stack Pointer (R255)
used for the internal stack that resides within the 124 gen-
eral-purpose registers.
In the 4-bit mode, the register file is divided into eight work-
ing register groups, each occupying 16 continuous loca-
tions. The Register Pointer (Figure 13) addresses the
starting location of the active working-register group.
General-Purpose Registers (GPR). These registers are
undefined after the device is powered up. The registers
keep their last value after any reset, as long as the reset
occurs in the VCC voltage-specified operating range. Note:
Register R254 has been designated as a general-purpose
register and is set to 00 Hex after any reset or Stop-Mode
Recovery.
Counter/Timer. There are two 8-bit programmable
counter/timers (T0 and T1), each driven by its own 6-bit
programmable prescaler. The T1 prescaler is driven by in-
ternal or external clock sources; however, the T0 can be
driven by the internal clock source only (Figure 14).
r7 r6 r5 r4
r3 r2 r1 r0
R253
(Register Pointer)
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.
The 6-bit prescalers divide the input frequency of the clock
source by any integer number from 1 to 64. Each prescaler
drives its counter, which decrements the value (1 to 256)
that has been loaded into the counter. When both counter
and prescaler reach the end of count, a timer interrupt re-
quest IRQ4 (T0) or IRQ5 (T1) is generated.
FF
F0
R15 to R0
7F
70
6F
60
5F
The counter can be programmed to start, stop, restart to
continue, or restart from the initial value. The counters are
also programmed to stop upon reaching zero (Single-Pass
Mode) or to automatically reload the initial value and con-
tinue counting (Modulo-N Continuous Mode).
50
4F
The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register.
40
3F
Specified Working
Register Group
30
2F
The counters, but not the prescalers, are read at any time
without disturbing their value or count mode. The clock
source for T1 is user-definable and is either the internal mi-
croprocessor clock divided by four, or an external signal in-
put through Port 3. The Timer Mode register configures the
external timer input (P31) as an external clock, a trigger in-
put that is retriggerable or non-retriggerable, or used as a
gate input for the internal clock.
20
1F
Register Group 1
R15 to R0
10
0F
R15 to R4*
R3 to R0
Register Group 0
I/O Ports
00
*Expanded Register Group (0) is selected in this figure
by handling bits D3 to D0 as "0" in Register R253(RP).
Figure 13. Register Pointer
26
P R E L I M I N A R Y
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
Internal Data Bus
1
Write
Write
Read
OSC
PRE0
Initial Value
Register
T0
T0
Initial Value
Register
Current Value
Register
*
÷ 2
6-Bit
Down
8-bit
Down
÷ 4
Counter
Counter
IRQ4
Internal Clock
External Clock
Clock
Logic
6-Bit
Down
Counter
8-Bit
Down
Counter
IRQ5
÷ 4
Internal Clock
Gated Clock
Triggered Clock
PRE1
Initial Value
Register
T1
T1
Initial Value
Register
Current Value
Register
TIN P31
Write
Write
Read
Internal Data Bus
* Note: By passed, if Low EMI Mode is selected.
Figure 14. Counter/Timers Block Diagram
DS97Z8X1104
P R E L I M I N A R Y
27
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Interrupts. The Z8 has six interrupts from six different
sources. These interrupts are maskable and prioritized
(Figure 15). The sources are divided as follows: the falling
edge of P31 (AN1), P32 (AN2), P33 (REF), the rising edge
of P32 (AN2), and two counter/timers. The Interrupt Mask
Register globally or individually enables or disables the six
interrupt requests (Table 4).
To accommodate polled interrupt systems, interrupt inputs
are masked and the interrupt request register is polled to
determine which of the interrupt requests needs service.
Note: User must select any Z86E08 mode in Zilog's C12
ICEBOX™ emulator. The rising edge interrupt is not sup-
ported on the CCP emulator (a hardware/software
workaround must be employed).
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register. All Z8 interrupts are
vectored through locations in program memory. When an
Interrupt machine cycle is activated, an Interrupt Request
is granted. This disables all subsequent interrupts, saves
the Program Counter and Status Flags, and then branches
to the program memory vector location reserved for that in-
terrupt. This memory location and the next byte contain the
16-bit starting address of the interrupt service routine for
that particular interrupt request.
Table 4. Interrupt Types, Sources, and Vectors
Vector
Name Source
Location Comments
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
Notes:
AN2(P32)
REF(P33)
AN1(P31)
AN2(P32)
T0
0,1
2,3
4,5
6,7
8,9
External (F)Edge
External (F)Edge
External (F)Edge
External (R)Edge
Internal
T1
10,11 Internal
F = Falling edge triggered
R = Rising edge triggered
IRQ0 - IRQ5
IRQ
IMR
IPR
Global
Interrupt
Enable
6
Interrupt
Request
PRIORITY
LOGIC
Vector Select
Figure 15. Interrupt Block Diagram
28
P R E L I M I N A R Y
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
Clock. The Z8 on-chip oscillator has a high-gain, parallel-
resonant amplifier for connection to a crystal, LC, RC, ce-
ramic resonator, or any suitable external clock source
(XTAL1 = INPUT, XTAL2 = OUTPUT). The crystal should
be AT cut, up to 12 MHz max., with a series resistance
(RS) of less than or equal to 100 Ohms.
The crystal should be connected across XTAL1 and
XTAL2 using the vendors crystal recommended capacitors
from each pin directly to device ground pin 14 (Figure 16).
Note that the crystal capacitor loads should be connected
to VSS, Pin 14 to reduce Ground noise injection.
1
XTAL1
XTAL2
XTAL1
XTAL2
XTAL1
XTAL2
XTAL1
XTAL2
C1
C1
C1
*
*
R
*
L
C2
C2
*
*
External Clock
RC
Ceramic Resonator or
Crystal
LC
@ 5V Vcc (TYP)
C1, C2 = 47 pF TYP *
F = 8 MHz
C1 = 100 pF
R = 2K
F = 6 MHz
* Typical value including pin parasitics
Figure 16. Oscillator Configuration
DS97Z8X1104
P R E L I M I N A R Y
29
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Table 5. Typical Frequency vs. RC Values
VCC = 5.0V @ 25°C
Load Capacitor
56 pFd
33 pFd
B(Hz)
100 pFd
0.00 1µFd
A(Hz) B(Hz)
Resistor (R)
A(Hz)
33K
A(Hz)
B(Hz)
20K
32K
78K
164K
300K
740K
1.3M
2M
A(Hz)
B(Hz)
11K
1.0M
560K
220K
100K
56K
20K
10K
5K
31K
52K
130K
270K
480K
1M
20K
34K
12K
20K
1.4K
2.5K
6K
1.4K
2.4K
6K
56K
19K
144K
315K
552K
1.4M
2.6M
4.4M
8M
84K
48K
45K
182K
330K
884K
1.6M
2.8M
6M
100K
185K
500K
980K
1.7K
3.8K
6.3K
95K
12K
12K
170K
450K
820K
1.3M
2.7M
4.2M
23K
22K
65K
61K
2M
130K
245K
600K
1.0M
123K
225K
536K
950K
3M
2K
5M
4M
1K
12M
7M
8.8M
6M
Notes:
A = STD Mode Frequency.
B = Low EMI Mode Frequency.
Table 6. Typical Frequency vs. RC Values
VCC = 3.3V @ 25°C
Load Capacitor
Resistor (R)
33 pFd
A(Hz)
56 pFd
B(Hz)
100 pFd
0.00 1µFd
B(Hz)
18K
A(Hz)
12K
A(Hz)
7.4K
12K
B(Hz)
7.7K
12K
A(Hz)
B(Hz)
1K
1.0M
560K
220K
100K
56K
20K
10K
5K
18K
30K
12K
20K
1K
1.6K
4K
30K
20K
1.6K
4K
70K
70K
47K
47K
30K
30K
150K
268K
690M
1.2M
2M
148K
250K
600K
1M
97K
96K
60K
60K
8K
8K
176K
463K
860K
1.5M
3.3M
5M
170K
416K
730K
1.2M
2.4M
3.6M
100K
286K
540K
950K
2.2M
3.6K
100K
266K
480K
820K
1.6M
2.6M
15K
40K
80K
151K
360K
660K
15K
40K
76K
138K
316K
565K
1.7M
3M
2K
4.6M
7M
1K
4.6M
Notes:
A = STD Mode Frequency.
B = Low EMI Mode Frequency.
30
P R E L I M I N A R Y
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
HALT Mode. This instruction turns off the internal CPU
clock but not the crystal oscillation. The counter/timers and
external interrupts IRQ0, IRQ1, IRQ2 and IRQ3 remain ac-
tive. The device is recovered by interrupts, either external-
ly or internally generated. An interrupt request must be ex-
ecuted (enabled) to exit HALT Mode. After the interrupt
service routine, the program continues from the instruction
after the HALT.
Watch-Dog Timer (WDT). The Watch-Dog Timer is en-
abled by instruction WDT. When the WDT is enabled, it
cannot be stopped by the instruction. With the WDT in-
struction, the WDT is refreshed when it is enabled within
every 1 Twdt period; otherwise, the controller resets itself,
The WDT instruction affects the flags accordingly; Z=1,
S=0, V=0.
1
WDT = 5F (Hex)
Note: On the C12 ICEBOX, the IRQ3 does not wake the
device out of HALT Mode.
Opcode WDT (5FH). The first time Opcode 5FH is execut-
ed, the WDT is enabled and subsequent execution clears
STOP Mode. This instruction turns off the internal clock
and external crystal oscillation and reduces the standby
current to 10 µA. The STOP Mode is released by a RESET
through a Stop-Mode Recovery (pin P27). A Low input
condition on P27 releases the STOP Mode. Program exe-
cution begins at location 000C(Hex). However, when P27
is used to release the STOP Mode, the I/O port Mode reg-
isters are not reconfigured to their default power-on condi-
tions. This prevents any I/O, configured as output when the
STOP instruction was executed, from glitching to an un-
known state. To use the P27 release approach with STOP
Mode, use the following instruction:
the WDT counter. This must be done at least every TWDT
otherwise, the WDT times out and generates a reset. The
generated reset is the same as a power-on reset of TPOR
;
,
plus 18 XTAL clock cycles. The software enabled WDT
does not run in STOP Mode.
Opcode WDH (4FH). When this instruction is executed it
enables the WDT during HALT. If not, the WDT stops
when entering HALT. This instruction does not clear the
counters, it just makes it possible to have the WDT running
during HALT Mode. A WDH instruction executed without
executing WDT (5FH) has no effect.
Permanent WDT. Selecting the hardware enabled Perma-
nent WDT option, will automatically enable the WDT upon
exiting reset. The permanent WDT will always run in HALT
Mode and STOP Mode, and it cannot be disabled.
LD
P2M, #1XXX XXXXB
NOP
STOP
X = Dependent on user's application.
Auto Reset Voltage (VLV). The Z8 has an auto-reset built-
in. The auto-reset circuit resets the Z8 when it detects the
VCC below VLV.
Note: A low level detected on P27 pin will take the device
out of STOP Mode even if configured as an output.
In order to enter STOP or HALT Mode, it is necessary to
first flush the instruction pipeline to avoid suspending exe-
cution in mid-instruction. To do this, the user executes a
NOP (opcode=FFH) immediately before the appropriate
SLEEP instruction, such as:
Figure 17 shows the Auto Reset Voltage versus tempera-
ture. If the VCC drops below the VCC operating voltage
range, the Z8 will function down to the VLV unless the inter-
nal clock frequency is higher than the specified maximum
VLV frequency.
FF
6F
NOP
; clear the pipeline
; enter STOP Mode
STOP
or
FF
7F
NOP
; clear the pipeline
; enter HALT Mode
HALT
DS97Z8X1104
P R E L I M I N A R Y
31
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Vcc
(Volts)
2.9
2.8
2.7
2.6
2.5
2.4
2.3
Temp
40°C 60°C
80°C
100°C
–40°C –20°C
0°C
20°C
Figure 17. Typical Auto Reset Voltage
(VLV) vs.Temperature
32
P R E L I M I N A R Y
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
ROM Protect. ROM Protect fully protects the Z8 ROM
code from being read externally. When ROM Protect is se-
lected, the instructions LDC and LDCI are supported
(Z86E04/E08 and Z86C04/C08 do not support the instruc-
tions of LDE and LDEI). When the device is programmed
for ROM Protect, the Low Noise feature will not automati-
cally be enabled.
Low EMI Emission
The Z8 can be programmed to operate in a low EMI Emis-
sion (Low Noise) Mode by means of an EPROM program-
mable bit option. Use of this feature results in:
1
■ Less than 1 mA consumed during HALT Mode.
■ All drivers slew rates reduced to 10 ns (typical).
Please note that when using the device in a noisy environ-
ment, it is suggested that the voltages on the EPM and CE
pins be clamped to VCC through a diode to VCC to prevent
accidentally entering the OTP Mode. The VPP requires
both a diode and a 100 pF capacitor.
■ Internal SCLK/TCLK = XTAL operation limited to a
maximum of 4 MHz–250 ns cycle time.
■ Output drivers have resistances of 500 ohms (typical).
■ Oscillator divide-by-two circuitry eliminated.
Auto Latch Disable. Auto Latch Disable option bit when
programmed will globally disable all Auto Latches.
In addition to VDD and GND (VSS), the Z8 changes all its pin
functions in the EPROM Mode. XTAL2 has no function,
XTAL1 functions as CE, P31 functions as OE, P32 func-
tions as EPM, P33 functions as VPP, and P02 functions as
PGM.
WDT Enable. The WDT Enable option bit, when pro-
grammed, will have the hardware enabled Permanent
WDT enabled after exiting reset and can not be stopped in
Halt or Stop Mode.
EPROM/Test Mode Disable. The EPROM/Test Mode
Disable option bit, when programmed, will disable the
EPROM Mode and the Factory Test Mode. Reading, veri-
fying, and programming the Z8 will be disabled. To fully
verify that this mode is disabled, the device must be power
cycled.
User Modes. Table 7 shows the programming voltage of
each mode.
Table 7. OTP Programming Table
VPP
VCC*
Programming Modes
EPROM READ
EPM
VH
CE
VIL
VIL
VIL
VH
VH
VH
VH
VH
OE
VIL
VIH
VIL
VIH
VIH
VIL
VIH
VIL
PGM
VIH
VIL
ADDR
ADDR
ADDR
ADDR
NU
DATA
Out
In
NU
VH
VH
VH
VH
VH
VH
VH
5.0V
6.4V
6.4V
6.4V
6.4V
6.4V
6.4V
6.4V
PROGRAM
VIH
VIH
VH
PROGRAM VERIFY
EPROM PROTECT
LOW NOISE SELECT
AUTO LATCH DISABLE
WDT ENABLE
VIH
VIL
Out
NU
NU
NU
NU
NU
VIH
VIH
VIL
VIL
NU
VIL
NU
VIL
NU
EPROM/TEST MODE
VIL
VIL
NU
Notes:
1. VH =12.75V ± 0.25 VDC
.
2. VIH = As per specific Z8 DC specification.
3. VIL= As per specific Z8 DC specification.
4. X = Not used, but must be set to VH or VIH level.
5. NU = Not used, but must be set to either VIH or VIL level.
6. IPP during programming = 40 mA maximum.
7. ICC during programming, verify, or read = 40 mA maximum.
8. * VCC has a tolerance of ±0.25V.
DS97Z8X1104
P R E L I M I N A R Y
33
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Internal Address Counter. The address of Z8 is generat-
ed internally with a counter clocked through pin P01
(Clock). Each clock signal increases the address by one
and the “high” level of pin P00 (Clear) will reset the ad-
dress to zero. Figure 18 shows the setup time of the serial
address input.
Programming Waveform. Figures 19, 20, 21 and 22
show the programming waveforms of each mode. Table 8
shows the timing of programming waveforms.
Programming Algorithm. Figure 23 shows the flow chart
of the Z8 programming algorithm.
Table 8. Timing of Programming Waveforms
Name Min
Parameters
Max
Units
1
2
3
Address Setup Time
Data Setup Time
VPP Setup
2
2
2
2
µs
µs
µs
µs
4
5
VCC Setup Time
Chip Enable Setup Time
Program Pulse Width
Data Hold Time
2
0.95
2
µs
ms
µs
µs
ns
ns
ms
µs
µs
µs
ms
ns
ns
6
7
8
OE Setup Time
2
9
Data Access Time
188
10
11
12
13
14
15
16
17
Data Output Float Time
Overprogram Pulse Width
EPM Setup Time
100
2.85
2
PGM Setup Time
2
Address to OE Setup Time
Option Program Pulse Width
OE Width
2
78
250
125
Address Valid to OE Low
34
P R E L I M I N A R Y
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
T2
1
P01 = Clock
T4
T1
T3
P00 = Clear
Vpp/EPM
T6
T5
Internal
Address
0 Min
Valid
Vih
Vil
Data
Invalid
Invalid
Valid
9
Legend:
30 ns Min
100 ns Min
200 ns Min
100 ns Min
15 ns Max
40 µs Min
T1 Reset Clock Width
T2 Input Clock High
T3 Input Clock Period
T4 Input Clock Low
T5 Clock to Address Counter Out Delay
T6 Epm/Vpp Set up Time
Figure 18. Z86E04/E08 Address Counter Waveform
DS97Z8X1104
P R E L I M I N A R Y
35
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
VIH
Address
Data
Address Stable
17
Address Stable
Valid
VIL
VIH
VIL
Invalid
Valid
9
Invalid
VIH
VIL
V
PP
VH
VIL
EPM
12
5.0V
VIH
VIL
V
CC
CE
OE
5
VIH
VIL
16
16
VIH
VIL
PGM
13
Figure 19. Z86E04/E08 Programming Waveform
(EPROM Read)
36
P R E L I M I N A R Y
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
VIH
VIL
VIH
VIL
Address
Stable
Address
1
1
Data
Stable
Data Out
Valid
Data
2
9
10
VH
VPP
EPM
VCC
VIH
3
VH
VIL
6V
5.0V
4
7
VIH
CE
OE
VIL
5
VIH
VIL
13
16
VIH
PGM
VIL
6
8
11
Program
Cycle
Verify
Cycle
Figure 20. Z86E04/E08 Programming Waveform
(Program and Verify)
DS97Z8X1104
P R E L I M I N A R Y
37
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
V
IH
Address
V
IL
V
IH
Data
V
IL
VH
VPP
V
IH
3
6V
VCC
5.0V
4
VH
CE
V
IH
5
V
IH
OE
V
IL
VH
V
IH
V
IH
EPM
V
IL
12
13
12
13
V
IH
PGM
V
IL
15
15
Low Noise Program
EPROM Protect
Figure 21. Z86E04/E08 Programming Options Waveform
(EPROM Protect and Low Noise Program)
38
P R E L I M I N A R Y
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
V
IH
Address
1
V
IL
V
IH
Data
VIL
VH
VPP
VIH
3
6V
V
CC
5.0V
4
V
H
CE
OE
V
IH
V
IH
5
V
IL
12
13
12
13
VIH
EPM
PGM
V
IL
12
13
12
13
V
IH
VIL
15
Auto Latch
15
15
WDT
EPROM/Test
Mode Disabl e
Figure 22. Z86E04/E08 Programming Options Waveform
(Auto Latch Disable, Permanent WDT Enable and
EPROM/Test Mode Disable)
DS97Z8X1104
P R E L I M I N A R Y
39
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Start
Addr =
First Location
VCC = 6.4V
VPP= 13.0V
N = 0
Program
1 ms Pulse
Increment N
Yes
N = 25 ?
No
Fail
Verify
One Byte
Fail
Verify
Byte
Pass
Pass
Prog. One Pulse
3xN ms Duration
Increment
Address
No
Last Addr ?
Yes
VCC = VPP = 5.0V
Fail
Verify All
Bytes
Pass
Device
Failed
Device
Passed
Figure 23. Z86E04/E08 Programming Algorithm
40
P R E L I M I N A R Y
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
Z8 CONTROL REGISTERS
R241 TMR
R244 T0
D7 D6 D5 D4 D3 D2 D1 D0
1
D7 D6 D5 D4 D3 D2 D1 D0
T
Initial Value
0
0
1
No Function
Load T0
(When Written)
(Range: 1-256 Decimal
01-00 HEX)
0
1
Disable T0 Count
Enable T0 Count
T
Current Value
0
(When READ)
0
1
No Function
Load T1
0
1
Disable T1 Count
Enable T1 Count
Figure 27. Counter/Timer 0 Register
(F4H: Read/Write)
TIN Modes
00 External Clock Input
01 Gate Input
10 Trigger Input
(Non-retriggerable)
11 Trigger Input
(Retriggerable)
R245 PRE0
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
Count Mode
0
1
T0 Single Pass
T0 Modulo N
Figure 24. Timer Mode Register (F1H: Read/Write)
Reserved (Must be 0)
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
R242 T1
D7 D6 D5 D4 D3 D2 D1 D0
T
Initial Value
1
Figure 28. Prescaler 0 Register (F5H:Write Only)
(When Written)
(Range 1-256 Decimal
01-00 HEX)
T
Current Value
1
(When READ)
R246 P2M
D7 D6 D5 D4 D3 D2 D1 D0
Figure 25. Counter Timer 1 Register (F2H: Read/Write)
P2 - P2 I/O Definition
7
0
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT
R243 PRE1
D7 D6 D5 D4 D3 D2 D1 D0
Figure 29. Port 2 Mode Register (F6H:Write Only)
Count Mode
0 = T Single Pass
1
1 = T Modulo N
1
Clock Source
R247 P3M
1 = T Internal
1
0 = T External Timing Input
1
D7 D6 D5 D4 D3 D2 D1 D0
(T ) Mode
IN
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
0
1
Port 2 Open-Drain
Port 2 Push-pull
Port 3 Inputs
0 Digital Mode
1 Analog Mode
Figure 26. Prescaler 1 Register (F3H:Write Only)
Reserved (Must be 0)
Figure 30. Port 3 Mode Register (F7H:Write Only)
DS97Z8X1104
P R E L I M I N A R Y
41
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
Z8 CONTROL REGISTERS (Continued)
R251 IMR
R248 P01M
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1 Enables IRQ0-IRQ5
P0 -P0 Mode
00 = Output
01 = Input
2
0
(D = IRQ0)
0
Reserved (Must be 0.)
1 Enables Interrupts
Reserved (Must be 1.)
Reserved (Must be 0.)
Figure 34. Interrupt Mask Register
(FBH: Read/Write)
Figure 31. Port 0 and 1 Mode Register
(F8H:Write Only)
R252 Flags
D7 D6 D5 D4 D3 D2 D1 D0
R249 IPR
D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1
User Flag F2
Half Carry Flag
Interrupt Group Priority
Reserved = 000
C > A > B = 001
A > B > C = 010
A > C > B = 011
B > C > A= 100
C > B > A= 101
B >A > C = 110
Reserved = 111
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
IRQ1, IRQ4 Priority (Group C)
0 = IRQ1 > IRQ4
1 = IRQ4 > IRQ1
Figure 35. Flag Register
(FCH: Read/Write)
IRQ0, IRQ2 Priority (Group B)
0 = IRQ2 > IRQ0
1 = IRQ0 > IRQ2
IRQ3, IRQ5 Priority (Group A)
0 = IRQ5 > IRQ3
1 = IRQ3 > IRQ5
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0.)
Figure 32. Interrupt Priority Register
(F9H:Write Only)
Expanded Register File
Working Register Pointer
Default After Reset = 00H
R250 IRQ
D7 D6 D5 D4 D3 D2 D1 D0
Figure 36. Register Pointer
(FDH: Read/Write)
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = P32 Input
IRQ4 = T0
R255 SPL
D7 D6 D5 D4 D3 D2 D1 D0
IRQ5 = T1
Reserved (Must be 0)
Stack Pointer Lower
Byte (SP - SP
)
0
7
Figure 33. Interrupt Request Register
(FAH: Read/Write)
Figure 37. Stack Pointer
(FFH: Read/Write)
42
P R E L I M I N A R Y
DS97Z8X1104
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
PACKAGE INFORMATION
1
18-Pin DIP Package Diagram
18-Pin SOIC Package Diagram
P R E L I M I N A R Y
DS97Z8X1104
43
Z86E04/E08
CMOS Z8 OTP Microcontrollers
Zilog
ORDERING INFORMATION
Z86E04
Z86E08
Standard Temperature
Standard Temperature
18-Pin DIP
18-Pin SOIC
18-Pin DIP
18-Pin SOIC
Z86E0412PSC
Z86E0412PEC
Z86E0412SSC
Z86E0412SEC
Z86E0812PSC
Z86E0812PEC
Z86E0812SSC
Z86E0812SEC
For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired.
Codes
Preferred Package
Speeds
P = Plastic DIP
12 =12 MHz
Longer Lead Time
Environmental
S = SOIC
C = Plastic Standard
Preferred Temperature
S = 0°C to +70°C
E = –40°C to +105°C
Example:
Z 86E04 12 P S C
is a Z86E04, 12 MHz, DIP, 0°C to +70°C, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
© 1998 by Zilog, Inc. All rights reserved. No part of this
document may be copied or reproduced in any form or by
any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change
without notice. Devices sold by Zilog, Inc. are covered by
warranty and patent indemnification provisions appearing
in Zilog, Inc. Terms and Conditions of Sale only.
Zilog, Inc. shall not be responsible for any errors that may
appear in this document. Zilog, Inc. makes no commitment
to update or keep current the information contained in this
document.
Zilog’s products are not authorized for use as critical
components in life support devices or systems unless a
specific written agreement pertaining to such intended use
is executed between the customer and Zilog prior to use.
Life support devices or systems are those which are
intended for surgical implantation into the body, or which
sustains life whose failure to perform, when properly used
in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in
significant injury to the user.
ZILOG, INC. MAKES NO WARRANTY, EXPRESS,
STATUTORY, IMPLIED OR BY DESCRIPTION,
REGARDING THE INFORMATION SET FORTH HEREIN
OR REGARDING THE FREEDOM OF THE DESCRIBED
DEVICES
FROM
INTELLECTUAL
PROPERTY
INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY
OF MERCHANTABILITY OR FITNESS FOR ANY
PURPOSE.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
FAX 408 370-8056
Internet: http://www.zilog.com
44
P R E L I M I N A R Y
DS97Z8X1104
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