Z8917520ASC [IXYS]
Microcontroller, 8-Bit, MROM, Z8 CPU, 20.4MHz, CMOS, PQFP100,;型号: | Z8917520ASC |
厂家: | IXYS CORPORATION |
描述: | Microcontroller, 8-Bit, MROM, Z8 CPU, 20.4MHz, CMOS, PQFP100, 微控制器 |
文件: | 总70页 (文件大小:2478K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY PRODUCT SPECIFICATION
1
Z89175
1
Z89176 (ROMLESS)
2
VOICE PROCESSING CONTROLLERS
FEATURES
■ Clock Speeds of 20.48 or 29.49 MHz
■ 16-Bit Digital Signal Processor (DSP)
■ 8K Word DSP Program ROM
ROM
(KB)
RAM*
(Bytes) Lines
I/O
Voltage
Range
Device
Z89175
Z89176
24
-
256
256
47
31
4.5V to 5.5V
4.5V to 5.5V
Note: *General-Purpose
■ 512 Words On-Chip DSP RAM
■ Watch-Dog Timer and Power-On Reset
■ Improved Low Power Stop Mode
■ 8-Bit A/D Converter with up to 16 kHz Sample Rate
■ 10-Bit PWM D/A Converter
■ On-Chip Oscillator which Accepts a Crystal
■ Six Vectored, Prioritized Z8 Interrupts
■ Three Vectored, Prioritized DSP Interrupts
or External Clock Drive
■ Improved Global Power-Down Mode
■ Low Power Consumption - 200 mW (typical)
■ Two Comparators
■ Two DSP Timers to Support Different A/D and D/A
Sampling Rates
®
■ IBM PC-Based Development Tools
■ RAM and ROM Protect
■ Developer’s Toolbox for T.A.M. Applications
■ On-Board Oscillator for 32.768 kHz Real-Time Clock
GENERAL DESCRIPTION
The Z89175/176 is a fully integrated, dual processor con-
troller designed for voice processing applications. The I/O
control processor is a Z8 with 24 KB of program memory,
The Z89176 is the ROMless version of the Z89175. How-
ever, the on-chip DSP is not ROMless.
®
Notes: All Signals with a preceding front slash, "/", are ac-
tive Low, e.g., B//W (WORD is active Low); /B/W (BYTE is
active Low, only).
two 8-bit counter/timers, and up to 47 I/O pins. The DSP is
a 16-bit processor with a 24-bit ALU and accumulator,
512x16 bits of RAM, single cycle instructions, and 8K
words of program ROM. The chip also contains a half-flash
8-bit A/D converter with up to a 16 kHz sample rate and a
10-bit PWM D/A converter. The sampling rates for the con-
verters are programmable. The precision of the 8-bit A/D
can be extended by resampling the data at a lower rate in
software. The Z8 and DSP processors are coupled by
mailbox registers and an interrupt system. DSP or Z8 pro-
grams can be directed by events in each other’s domain.
Power connections follow conventional descriptions be-
low:
Connection
Power
Circuit
Device
V
V
DD
CC
Ground
GND
V
SS
DS97TAD0100
P R E L I M I N A R Y
1
Z89175/Z89176
Voice Processing Controllers
Zilog
GENERAL DESCRIPTION (Continued)
Z8 Core Processor
DSP Coprocessor
The on-chip Z8 is Zilog’s 8-bit microcontroller core with an
Expanded Register File to allow access to register-
mapped peripheral and I/O circuits. The Z8 offers a flexible
I/O scheme, an efficient register and address space struc-
ture and a number of ancillary features which makes it ide-
ally suited for high-volume processing, peripheral control-
lers and consumer applications.
The DSP coprocessor is a second generation, 16-bit two’s
complement CMOS Digital Signal Processor (DSP). Most
instructions, including multiply and accumulate, are ac-
complished in a single clock cycle. The processor contains
two on-chip data RAM blocks of 256 words, a 8K word pro-
gram ROM, 24-bit ALU, 16x16 multiplier, 24-bit Accumula-
tor, shifter, six-level stack, three vectored interrupts and
two inputs for conditional program jumps. Each RAM block
contains a set of four pointers which can be incremented
or decremented automatically to affect hardware looping
without software overhead. The data RAMs can be simul-
taneously addressed and loaded to the multiplier for a true
single-cycle scalar multiply.
For applications demanding powerful I/O capabilities, the
Z89175 provides 47 pins dedicated to input and output.
These I/O lines are grouped into six ports. Each port is
configurable under software control to provide timing, sta-
tus signals and parallel I/O with or without handshake.
Four basic memory resources for the Z8 are available to
support a wide range of configurations: Program Memory,
Register File, Data Memory, and Expanded Register File.
The Z8 core processor is supported by an efficient register
file that allows any of 256 on-board data and control regis-
ters to be either the source and/or the destination of almost
any instruction. This unique architecture eliminates tradi-
tional microprocessor Accumulator bottlenecks and per-
mits rapid content switching.
Four external DSP registers are mapped into the expand-
ed register file of the Z8. Communication between the Z8
and the DSP occurs through those common registers
which form the mailbox registers.
The analog output is generated by a 10-bit resolution
Pulse Width Modulator. The PWM output is a digital signal
with CMOS output levels. The output signal has a resolu-
tion of 1 in 1024 with a sampling rate of 16 kHz (XTAL =
20.48 MHz). The sampling rate can be changed under
software control and can be set at 10 and 16 kHz. The dy-
namic range of the PWM is from 0 to 4V.
The Register File is composed of 236 bytes of general-pur-
pose registers, four I/O port registers, and 15 control and
status registers. The Expanded Register File consists of
mailbox registers, WDT mode register, DSP Control regis-
ter, Stop-Mode Recovery register, Port Configuration reg-
ister, and the control and data registers for Port 4 and Port
5. Some of these registers are shared with the DSP.
An 8-bit resolution half-flash A/D converter is provided.
The conversion is conducted with a sampling frequency of
16 kHz. (XTAL = 20.48 MHz) in order to provide oversam-
pling. The input signal is 4V peak to peak.
To unburden the software from supporting real-time prob-
lems such as counting/timing and data communication, the
Z8 offers two on-chip counter/timers with a large number
of user-selectable modes.
Two additional timers (Timer2 and Timer3) have been
added to support different sampling rates for the A/D and
D/A converters. These timers are free-running counters
that divide the crystal frequency to the appropriate sam-
pling of frequency. Two DSP I/O pins: DSP0, DSP1 are
provided for application.
Watch-Dog Timer and Stop-Mode Recovery features are
software driven by setting specific bits in control registers.
STOP and HALT instructions support reduced power op-
eration. The low-power Stop Mode allows parameter infor-
mation to be stored in the register file if power fails. An ex-
ternal capacitor or battery will retain device memory and
power the 32 kHz timer.
2
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
PIN DESCRIPTION
2
P00
P01
P02
Timer 0
Capture Reg.
Register File
256 x 8 Bit
Timer 1
P31
P32 Input
P33
Address
or I/O
(Nibble
P03
Port 0
Port 1
Port 2
Port 3
P34
P04
P05
P06
P07
Register Bus
Programmable)
Output
P35
P36
P37
Internal Address Bus
Internal Data Bus
24 Kbytes
Program
ROM
Z8 Core
(Z89175)
P40
P41
P42
P43
P44
P45
P46
P47
P10
P11
P12
P13
P14
P15
P16
P17
Expanded
Register Bus
I/O
(Bit
Expanded Register
Address/Data
or I/O
(Byte
Programmable)
File
(Z8)
Port 4
Programmable)
Extended Bus of the DSP
Peripheral
Register
(DSP)
P20
P21
P22
P23
P24
P25
P26
P27
P50
P51
P52
P53
P54
P55
P56
P57
256 Word
RAM 0
256 Word
RAM 1
mailbox
I/O
(Bit
I/O
(Bit
Port 5
Programmable)
Programmable)
Internal Address Bus
8K Words
Program
ROM
DSP Core
Internal Data Bus
INT 1
INT 2
DSP0
DSP1
RMLS
/AS
/DS
DSP Port
Ext.
Memory
Control
Extended Bus of the DSP
Timer 2
Timer 3
R/W
PWM
(10-Bit)
PWM
AN IN
XTAL1
XTAL2
OSC
AN VDD
AN GND
VREF+
VREF-
VDD
GND
/RESET
ADC
(8-Bit)
Power
32 kHz
OSC
OSC1
OSC2
Figure 1. Z89175/176 Functional Block Diagram
DS97TAD0100
P R E L I M I N A R Y
3
Z89175/Z89176
Voice Processing Controllers
Zilog
PIN DESCRIPTION (Continued)
80
81
75
70
65
60
55
51
50
NC
NC
P06
P05
NC
P04
VCC
P51
P50
P47
P46
P45
P44
P43
P42
P41
P40
P27
P26
P25
P24
P23
P22
P03
P02
P01
P00
GND
P17
P16
P15
P14
P13
P12
P11
P10
85
90
95
45
40
100-Pin QFP
35
31
GND
AGND
VREF-
ANIN
100
1
5
10
15
20
25
30
Figure 2. Z89175 100-Pin QFP Pin Configuration
4
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
Table 1. Z89175 100-Pin QFP Pin Identification
Pin
I/O Port
Symbol
Number
Direction
Function
2
GND
3, 53, 88, 97
16, 47, 77
Digital Ground
Digital V = +5V
V
CC
CC
VREF+
ANV
1
2
Input/Output
Analog Voltage Ref+
Analog V
DD
DD
PWM
RMLS
DSP1-0
/AS
4
5
Output
Input
PWM Output
Control Input
6, 7
8
Output
Output
Output
Output
DSP User Output 1, 0
Address Strobe
Data Strobe
/DS
9
R//W
10
Read/Write
NC
11
No Connection
P57-P54
XTAL2
XTAL1
P53-P52
P37-P34
P33-P31
/RESET
P20-P27
P40-P47
P50-P51
NC
12-15
17
Input/Output
Output
Port 5 Bit 7-4
Crystal Output (20.48 or 29.49 MHz)
Crystal Input (20.48 or 29.49 MHz)
Port 5 Bit 3-2
18
Input
19, 20
21-24
25-27
28
Input/Output
Output
Port 3 Bit 7-4
Input
Port 3 Bit 3-1
Input/Output
Input/Output
Input/Output
Input/Output
Reset
29-36
37-44
45, 46
48-52
54
Port 2, Bit 0-7
Port 4, Bit 0-7
Port 5, Bit 0-1
No Connection
OSC1
OSC2
NC
Input
Crystal Input (32.768 kHz)
Crystal Output (32.768 kHz)
No Connection
55
Output
56-76
78, 79
80-87
89-96
98
NC
No Connection
P07-P00
P17-P10
ANGND
VREF-
ANIN
Input/Output
Input/Output
Port 0, Bit 7-0
Port 1, Bit 7-0
Analog GND
99
Input
Input
Analog Voltage Ref-
Analog Input
100
DS97TAD0100
P R E L I M I N A R Y
5
Z89175/Z89176
Voice Processing Controllers
Zilog
PIN DESCRIPTION (Continued)
75
70
65
60
55
51
50
76
NC
NC
NC
NC
P07
NC
P06
NC
P05
P04
P03
P02
P01
P00
GND
P17
P16
P15
P14
P13
P12
P11
P10
NC
80
45
40
35
VCC
P51
P50
P47
P46
P45
P44
P43
P44
P45
P46
P47
P50
P51
VCC
NC
85
90
95
100-Pin VQFP
GND
AGND
VREF-
ANIN
VREF+
ANVDD
30
26
NC
NC
NC
NC
100
1
5
10
15
20
25
Figure 3. Z89175 100-Pin VQFP Pin Configuration
6
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
Table 2. Z89175 100-Pin VQFP Pin Identification
Pin
I/O Port
Symbol
Number
Direction
Symbol
2
GND
1, 51, 86, 95
Digital Ground
V
14, 45, 75
Digital VCC = +5V
CC
VREF+
ANV
99
Input/Output
Analog Voltage Ref+
Analog VDD
100
DD
PWM
RMLS
DSP1-0
/AS
2
Output
Input
PWM Output
3
Control Input
4, 5
Output
Output
Output
Output
DSP User Output 1, 0
Address Strobe
Data Strobe
6
/DS
7
R//W
8
Read/Write
NC
9
No Connection
Port 5 Bit 7-4
P57-P54
XTAL2
10-13
15
Input/Output
Output
Crystal Output (20.48 or
29.49 MHz)
XTAL1
16
Input
Crystal Input (20.48 or 29.49
MHz)
P53-P52
P37-P34
P33-P31
/RESET
P20-P27
P40-P47
P50-P51
NC
17, 18
19-22
23-25
26
Input/Output
Output
Port 5 Bit 3-2
Port 3 Bit 7-4
Input
Port 3 Bit 3-1
Input/Output
Input/Output
Input/Output
Input/Output
Reset
27-34
35-42
43, 44
46-50
52
Port 2, Bit 0-7
Port 4, Bit 0-7
Port 5, Bit 0-1
No Connection
Crystal Input (32.768 kHz)
Crystal Output (32.768 kHz)
No Connection
No Connection
Port 0, Bit 7-0
OSC1
Input
OSC2
53
Output
NC
54-74
76, 77
78-85
87-94
96
NC
P07-P00
P17-P10
ANGND
VREF-
ANIN
Input/Output
Input/Output
Port 1, Bit 7-0
Analog GND
97
Input
Input
Analog Voltage Ref-
Analog Input
98
DS97TAD0100
P R E L I M I N A R Y
7
Z89175/Z89176
Voice Processing Controllers
Zilog
PIN DESCRIPTION (Continued)
80
81
75
70
65
60
55
51
50
NC
NC
P06
P05
NC
P04
VCC
P51
P50
P47
P46
P45
P44
P43
P42
P41
P40
P27
P26
P25
P24
P23
P22
P03
P02
P01
P00
GND
P17
P16
P15
P14
P13
P12
P11
P10
85
90
95
45
40
100-Pin QFP
35
31
GND
AGND
VREF-
ANIN
100
1
5
10
15
20
25
30
Figure 4. Z89176 100-Pin QFP Pin Configuration
8
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
Table 3. Z89176 100-Pin QFP Pin Identification
I/O Port
Symbol
Pin Number
Direction
Function
2
GND
3, 53, 88, 97
5, 16, 47, 77
Digital Ground
Digital V = +5V
V
CC
CC
VREF+
ANV
1
2
Input/Output
Analog Voltage Ref+
Analog V
DD
DD
PWM
4
Output
Output
Output
Output
Output
PWM Output
DSP1-0
/AS
6, 7
8
DSP User Output 1, 0
Address Strobe
Data Strobe
/DS
9
R//W
10
Read/Write
NC
11
No Connection
P57-P54
XTAL2
XTAL1
P53-P52
P37-P34
P33-P31
/RESET
P20-P27
P40-P47
P50-P51
NC
12-15
17
Input/Output
Output
Port 5 Bit 7-4
Crystal Output (20.48 or 29.49 MHz)
Crystal Input (20.48 or 29.49 MHz)
Port 5 Bit 3-2
18
Input
19, 20
21-24
25-27
28
Input/Output
Output
Port 3 Bit 7-4
Input
Port 3 Bit 3-1
Input/Output
Input/Output
Input/Output
Input/Output
Reset
29-36
37-44
45, 46
48-52
54
Port 2, Bit 0-7
Port 4, Bit 0-7
Port 5, Bit 0-1
No Connection
OSC1
OSC2
NC
Input
Crystal Input (32.768 kHz)
Crystal Output (32.768 kHz)
No Connection
55
Output
56-76
78-79
80-87
89-96
98
NC
No Connection
P07-P00
P17-P10
ANGND
VREF-
ANIN
Input/Output
Input/Output
Port 0, Bit 7-0
Port 1, Bit 7-0
Analog GND
99
Input
Input
Analog Voltage Ref-
Analog Input
100
DS97TAD0100
P R E L I M I N A R Y
9
Z89175/Z89176
Voice Processing Controllers
Zilog
PIN DESCRIPTION (Continued)
75
70
65
60
55
51
50
76
NC
NC
NC
NC
P07
NC
P06
NC
P05
P04
P03
P02
P01
P00
GND
P17
P16
P15
P14
P13
P12
P11
P10
NC
80
45
40
35
VCC
P51
P50
P47
P46
P45
P44
P43
P42
P41
P40
P27
P26
P25
P24
P23
P22
P21
P20
/RESET
85
90
95
100-Pin VQFP
GND
AGND
VREF-
ANIN
VREF+
ANVDD
30
26
100
1
5
10
15
20
25
Figure 5. Z89176 100-Pin VQFP Pin Configuration
10
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
Table 4. Z89176 100-Pin VQFP Pin Identification
I/O Port
Symbol
Pin Number
1, 51, 86, 95
Direction
Function
2
GND
Digital Ground
V
3, 14, 45, 75
Digital V = +5V
CC
CC
VREF+
ANV
99
Input/Output
Analog Voltage Ref+
Analog VDD
100
DD
PWM
DSP1-0
/AS
2
Output
Output
Output
Output
Output
PWM Output
4, 5
6
DSP User Output 1, 0
Address Strobe
Data Strobe
/DS
7
R//W
NC
8
Read/Write
9
No Connection
P57-P54
XTAL2
XTAL1
P53-P52
P37-P34
P33-P31
/RESET
P20-P27
P40-P47
P50-P51
NC
10-13
15
Input/Output
Output
Port 5 Bit 7-4
Crystal Output (20.48 or 29.49 MHz)
Crystal Input (20.48 or 29.49 MHz)
Port 5 Bit 3-2
16
Input
17, 18
19-22
23-25
26
Input/Output
Output
Port 3 Bit 7-4
Input
Port 3 Bit 3-1
Input/Output
Input/Output
Input/Output
Input/Output
Reset
27-34
35-42
43, 44
46-50
52
Port 2, Bit 0-7
Port 4, Bit 0-7
Port 5, Bit 0-1
No Connection
OSC1
Input
Crystal Input (32.768 kHz)
Crystal Output (32.768 kHz)
No Connection
OSC2
53
Output
NC
54-74
76, 77
78-85
87-94
96
NC
No Connection
P07-P00
P17-P10
ANGND
VREF-
ANIN
Input/Output
Input/Output
Port 0, Bit 7-0
Port 1, Bit 7-0
Analog GND
97
Input
Input
Analog Voltage Ref-
Analog Input
98
DS97TAD0100
P R E L I M I N A R Y
11
Z89175/Z89176
Voice Processing Controllers
Zilog
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maxi-
mum Ratings can cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for an extended period can af-
fect device reliability.
Sym
Description
Min
Max
Units
V
Supply
Voltage (*)
–0.3
+7.0
V
CC
T
Storage Temp
–65°
+150°
C
C
STG
T
Oper.
Ambient
Temp.
†
A
Notes:
*Voltage on all pins with respect to GND.
†See Ordering Information.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (Figure 6).
+5V
2.1 kΩ
From Output
Under Test
150 pF
9.1 kΩ
Figure 6. Test Load Diagram
CAPACITANCE
T = 25°C, V
= GND = 0V, f = 1.0 MHz, unmeasured
CC
A
pins returned to GND.
Parameter
Min
Max
Input capacitance
Output capacitance
I/O capacitance
0
0
0
12 pF
12 pF
12 pF
12
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
DC ELECTRICAL CHARACTERISTICS
T = 0°C to +70°C
V
A
Typical
@ 25°C
CC
2
Sym
Parameter
Supply Current
Note 1
5.0V
5.0V
5.0V
5.0V
5.0V
Min
Max
65
20
20
7
Units
mA
Conditions
I
I
I
40
6
CC
Halt Mode Current
Stop Mode Current
Max Input Voltage
mA
CC1
CC2
6
µA
See Note 2
V
V
MAX
CH
Clock Input High
Voltage
0.9 V
V
+0.3
2.5
1.5
V
V
Driven by External
Clock Generator
CC
CC
V
Clock Input Low
Voltage
5.0V
GND –0.3
0.1 V
Driven by External
Clock Generator
CL
CC
V
V
V
V
V
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output Low Voltage
5.0V
5.0V
5.0V
5.0V
5.0V
0.7 V
V +0.3
CC
2.5
1.5
4.8
0.1
0.3
V
V
V
V
V
IH
CC
GND –0.3
–0.4
0.2 V
CC
IL
V
I
I
I
= –2.0 mA
OH
OL1
OL2
CC
OH
OL
OL
0.4
1.2
= +4.0 mA
= +12 mA, 3 Pin
Max
V
V
V
Reset Input High
Voltage
5.0V
5.0V
5.0V
.8 V
V
CC
2.1
V
RH
CC
Reset Input Low
Voltage
GND –0.3
0.2 V
1.7
10
Rl
CC
Comparator Input
Offset
25
mV
OFFSET
Voltage
I
I
I
Input Leakage
5.0V
5.0V
5.0V
–10
–10
10
10
10
10
µA
µA
µA
IL
Output Leakage
OL
IR
Reset Input Current
–55
–30
Notes:
1. 5.0V ±0.5V
2. When a 32 kHz crystal is used, additional value must be added to the Stop Mode current ICC2.
The sum will be 200 µA/max, 150 µA/typical.
DS97TAD0100
P R E L I M I N A R Y
13
Z89175/Z89176
Voice Processing Controllers
Zilog
DC ELECTRICAL CHARACTERISTICS
Z89175 A/D Converter
T = 0° C to +70°C
A
V
Sym
Parameter
Min
Max
Units
Conditions
DD
I
Input Leakage
Analog Input
5.5V
1.00
µA
ANV
=
5.50
V
IL
DD
V
=
=
=
=
0.00
5.50
0.00
5.50
V
V
V
V
IN
V
REFH
V
REFL
I
Input Leakage
Analog Input
5.5V
2.00
µA
ANV
DD
IH
V
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
5.50
5.50
0.00
5.50
0.00
5.50
5.50
5.50
5.50
0.00
5.50
0.00
0.00
5.50
5.50
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IN
V
REFH
V
REFL
I
Input Current
Input Current
Input Current
Input Current
5.5V
5.5V
5.5V
5.5V
1.00
2
mA
µA
V
IN
VREFH
V
REFL
ANV
DD
I
V
IN
VREFL
V
REFL
ANV
DD
I
–2.00
2
mA
µA
V
IN
VEFL
V
REFH
ANV
DD
I
V
VREFL
IN
V
REFH
ANV
DD
14
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
DC ELECTRICAL CHARACTERISTICS
21 Other Non-Regular I/O
2
T = 0° C to +70°C
A
V
Sym
Parameter
Min
Max
6.00
6.00
1.00
Units
Conditions
= 5.50 V
DD
I
Input Current ROMless Pin
Input Current ROMless Pin
5.5V
5.5V
5.5V
µA
µA
V
V
V
IRH
IN
IN
IN
I
= 0.00 V
= 5.50 V
IR1
I
Input Current ROMless Pin
During Reset Active
mA
IR
I
Input Current
XTAL2 pin in STOP mode
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
1.00
1.00
30
µA
µA
µA
µA
V
V
V
V
V
= 0.00 V
= 5.50 V
= 0.00 V
= 5.50 V
= 4.00 mA
=1.00 mA
= 4.00 mA
=1.00 mA
= 5.50 V
= 0.00 V
IHX2
IN
IN
I
Input Current
XTAL2 Pin in STOP mode
ILX2
I
Input current
XTAL1 Pin
IHX1
IN
I
Input Current
XTAL1 Pin
30
ILX1
IN
V
Output Low
Voltage XTAL2 Reset Inactive
1.20
0.60
I
I
I
I
OLXR
OL
OL
OH
OH
V
Output Low
Voltage XTAL2 Reset Inactive
V
OLX
OHXR
VOHX
V
Output High
Voltage XTAL2 Reset Inactive
4.00
4.00
V
I
Output High
Voltage XTAL2 Reset Inactive
V
I
Input Current
P31, P32, P33
1.00
1.00
µA
µA
V
IH
IN
IN
I
Input Current
V
IL
P31, P32, P33
DS97TAD0100
P R E L I M I N A R Y
15
Z89175/Z89176
Voice Processing Controllers
Zilog
AC CHARACTERISTICS
External I/O or Memory Read and Write Timing Diagram
R//W
13
12
Port 0, /DM
16
19
1
3
Port 1
/AS
A7 - A0
D7 - D0 IN
2
9
18
8
11
4
5
6
/DS
(Read)
17
10
Port1
A7 - A0
D7 - D0 OUT
14
15
7
/DS
(Write)
Figure 7. External I/O or Memory Read/Write Timing
16
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
AC CHARACTERISTICS
External I/O or Memory Read and Write Timing Table
2
V
T = 0°C to +70°C
A
CC
No Symbol
Parameter
Note 4
Min
Max
Units
Notes
1
2
TdA(AS)
Address Valid to /AS Rise Delay
/AS Rise to Address Float Delay
/AS Rise to Read Data Req’d Valid
/AS Low Width
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
25
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2,3
2,3
TdAS(A)
3
TdAS(DR)
TwAS
150
1,2,3
2,3
4
35
0
5
TdAZ(DS)
TwDSR
Address Float to /DS Fall
6
/DS (Read) Low Width
125
75
1,2,3
1,2,3
1,2,3
2,3
7
TwDSW
/DS (Write) Low Width
8
TdDSR(DR)
ThDR(DS)
TdDS(A)
TdDS(AS)
TdR/W(AS)
TdDS(R/W)
/DS Fall to Read Data Req’d Valid
Read Data to /DS Rise Hold Time
/DS Rise to Address Active Delay
/DS Rise to /AS Fall Delay
R//W Valid to /AS Rise Delay
/DS Rise to R//W Not Valid
90
9
0
10
11
12
13
14
40
35
25
35
40
2,3
2,3
2,3
2,3
TdDW(DSW) Write Data Valid to /DS Fall (Write)
Delay
2,3
15
16
TdDS(DW)
/DS Rise to Write Data Not Valid
Delay
5.0V
5.0V
25
ns
ns
2,3
TdA(DR)
Address Valid to Read Data Req’d
Valid
180
1,2,3
17
18
TdAS(DS)
TdDI(DS)
TdDM(AS)
/AS Rise to /DS Fall Delay
Data Input Setup to /DS Rise
/DM Valid to /AS Fall Delay
5.0V
5.0V
5.0V
48
50
20
ns
ns
ns
2,3
1,2,3
2,3
19
Notes:
1. When using extended memory timing add 2 TpC.
2. Timing numbers given are for minimum TpC.
3. See clock cycle dependent characteristics table.
4. 5.0 V ±0.5 V.
Standard Test Load
All timing references use 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
DS97TAD0100
P R E L I M I N A R Y
17
Z89175/Z89176
Voice Processing Controllers
Zilog
AC ELECTRICAL CHARACTERISTICS
Additional Timing Diagram
3
1
Clock
2
2
3
7
7
TIN
4
5
6
IRQN
9
8
Clock
Setup
11
Stop
Mode
Recovery
Source
10
Figure 8. Additional Timing
18
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
AC ELECTRICAL CHARACTERISTICS
Additional Timing Table
2
V
T = 0°C to +70°C
A
CC
No
Sym
TpC
Parameter
Input Clock Period
Note 5
Min
Max
Units
Notes
1
2
3
4
5
6
7
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
48.83
ns
ns
ns
ns
1, 6
1
TrC,TfC
TwC
Clock Input Rise & Fall Times
Input Clock Width
6
17
70
1,7
TwTinL
TwTinH
TpTin
Timer Input Low Width
Timer Input High Width
Timer Input Period
3TpC
8TpC
1
1
TrTin, TfTin Timer Input Rise & Fall Timer
100
ns
ns
1
8a TwIL
8b TwIL
Int. Request Low Time
Int. Request Low Time
Int. Request Input High Time
70
3TpC
3TpC
12
1,2
1
9
TwIH
1
10 Twsm
Stop-Mode Recovery Width
Spec
ns
1
11 Tost
12 Twdt
Oscillator Start-up Time
Watch-Dog Timer
5.0V
5.0V
5.0V
5.0V
5.0V
5TpC
5
3
ms
ms
ms
ms
D1 = 0, D0 = 0 [4]
D1 = 0, D0 = 1 [4]
D1 = 1, D0 = 0 [4]
D1 = 1, D0 = 1 [4]
15
25
100
Notes:
1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
2. Interrupt request via Port 3 (P31-P33).
3. SMR-D5 = 0
4. Reg. WDT
5. 5.0 V ±0.5 V
6. For 29.49 MHz, it will be 30.53 ns.
7. For 29.49 MHz, it will be 9 ns.
DS97TAD0100
P R E L I M I N A R Y
19
Z89175/Z89176
Voice Processing Controllers
Zilog
AC ELECTRICAL CHARACTERISTICS
Handshake Timing Diagrams
Data In
Data In Valid
Next Data In Valid
2
1
3
/DAV
(Input)
Delayed DAV
4
5
6
RDY
(Output)
Delayed RDY
Figure 9. Input Handshake Timing
Data Out
Data Out Valid
Next Data Out Valid
7
/DAV
Delayed DAV
(Output)
8
9
11
10
RDY
Delayed RDY
(Input)
Figure 10. Output Handshake Timing
20
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
AC ELECTRICAL CHARACTERISTICS
Handshake Timing Table
2
V
T = 0°C to +70°C
A
Data
CC
No
Symbol
TsDI(DAV)
Parameter
Note
Min
Max
Units Direction
1
2
3
4
5
6
7
8
9
Data In Setup Time
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
5.0V
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IN
IN
ThDI(RDY)
RDY to Data Hold Time
Data Available Width
TwDAV
40
IN
TdDAVI(RDY)
TdDAVId(RDY)
TdDO(DAV)
TcLDAV0(RDY)
TcLDAV0(RDY)
TdRDY0(DAV)
DAV Fall to RDY Fall Delay
DAV Rise to RDY Rise Delay
RDY Rise to DAV Fall Delay
Data Out to DAV Fall Delay
DAV Fall to RDY Fall Delay
RDY Fall to DAV Rise Delay
RDY Width
70
40
IN
IN
0
TpC
0
IN
OUT
OUT
OUT
OUT
OUT
70
40
10 TwRDY
40
11 TdRDY0d(DAV)
RDY Rise to DAV Fall Delay
Note:
5.0V ±0.5V
DS97TAD0100
P R E L I M I N A R Y
21
Z89175/Z89176
Voice Processing Controllers
Zilog
PIN FUNCTIONS
/RESET (input, active Low). This pin initializes the MCU.
Reset is accomplished either through Power-On Reset
(POR), Watch-Dog Timer (WDT) reset, Stop-Mode Recov-
ery, or external reset. During POR and WDT Reset, the in-
ternally generated reset signal is driving the reset pin Low
for the POR time. Any devices driving the reset line must
be open-drain to avoid damage from a possible conflict
during reset conditions. A /RESET will reset both the Z8
and the DSP.
XTAL2 Crystal 2 (time-based output). This pin connects a
parallel-resonant, crystal, ceramic resonant, or LC network
to the on-chip oscillator output.
DSP0 (output). DSP0 is a general-purpose output pin con-
nected to bit 6 of the Analog Control Register (DSP EXT4).
This bit has no special significance and can be used to out-
put data by writing to bit 6 of the ACR.
DSP1 (output). DSP1 is a general-purpose output pin con-
nected to bit 7 of the Analog Control Register (DSP EXT4).
This bit has no special significance and can be used to out-
put data by writing to bit 7 of the ACR.
For the Z8: After the POR time, /RESET is a Schmitt-trig-
gered input. To avoid asynchronous and noisy reset prob-
lems, the Z8 is equipped with a reset filter of four external
clocks (4TpC). If the external reset signal is less than 4TpC
in duration, no reset occurs. On the fifth clock after the
/RESET is detected, an internal RST signal is latched and
held for an internal register count of 18 external clocks, or
for the duration of the external reset, whichever is longer.
Program execution begins at location 000CH (hexadeci-
mal), 5-10 TpC cycles after /RESET is released. The Z8
does not reset WDT, SMR, P2M, and P3M registers on a
Stop-Mode Recovery operation.
PWM Pulse Width Modulator (Output). The PWM is a 10-
bit resolution D/A converter. This output is a digital signal
with CMOS output levels.
AN (input). Analog input for the A/D converter.
IN
ANV . Analog power supply for the A/D converter.
DD
VREF+ (input). Reference voltage (High) for the A/D con-
verter.
For the DSP: After POR, the DSP is in RUN mode. The Z8
controls the DSP commands to HALT, RUN or RESET.
When the DSP is in HALT mode, it cannot be woke up with
WDT or SMR.
V
. Digital power supply for the Z89175.
DD
GND. Digital ground for the Z89175.
RMLS ROMless (input, active High). This pin, when con-
nected to VDD, disables the internal Z8 ROM. (Note that,
when pulled Low to GND, the device functions normally as
the ROM version.) The DSP cannot be configured as
ROMless. This pin is only available on the Z89175.
OSC1 Oscillator 1 (time-based input). This pin connects a
parallel-resonant crystal, ceramic resonator, LC, RC net-
work to the on-chip oscillator input.
OSC2 Oscillator 2 (time-based output). This pin connects
a parallel-resonant crystal, ceramic resonator, LC, RC net-
work to the on-chip oscillator output.
R//W Read/Write (output, write Low). The R//W signal de-
fines the signal flow when the Z8 is reading or writing to an
external program or data memory. The Z8 is reading when
this pin is High and writing when this pin is Low.
NC No Connect. For the 100-pin QFP package, pins 63
through 76, and pins 78 and 79 should be tied to Ground.
Other NC pins must float.
/AS Address Strobe (output, active Low). Address Strobe
is pulsed once at the beginning of each machine cycle. Ad-
dress output is through Port 0/Port 1 for all external pro-
grams. Memory address transfers are valid at the trailing
edge of /AS. Under program control, /AS is placed in the
high-impedance state along with Ports 0 and 1, Data
Strobe, and Read/Write.
Port 0 (P07-P00). Port 0 is an 8-bit, bidirectional, CMOS
compatible port. These eight I/O lines are configured un-
der software control as a nibble I/O port, or as an address
port for interfacing external memory. The input buffers are
Schmitt-triggered and the output drivers are push-pull.
Port 0 is placed under handshake control. In this configu-
ration, Port 3, lines P32 and P35 are used as the hand-
shake control /DAV0 and RDY0. Handshake signal direc-
tion is dictated by the I/O direction to Port 0 of the upper
nibble P07-P04. The lower nibble must have the same di-
rection as the upper nibble.
/DS Data Strobe (output, active Low). Data Strobe is acti-
vated once for each external memory transfer. For read
operations, data must be available prior to the trailing edge
of /DS. For write operations, the falling edge of /DS indi-
cates that output data is valid.
The Auto Latch on Port 0 puts valid CMOS levels on all
CMOS inputs which are not externally driven. Whether this
level is 0 or 1 cannot be determined. A valid CMOS level,
rather than a floating node, reduces excessive supply cur-
rent flow in the input buffer.
XTAL1 Crystal 1 (time-based input). This pin connects a
parallel-resonant crystal, ceramic resonator, LC, RC net-
work, or an external single-phase clock to the on-chip os-
cillator input.
22
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
For external memory references, Port 0 provides address
bits A11-A8 (lower nibble) or A15-A8 (lower and upper nib-
ble) depending on the required address space. If the ad-
dress range requires 12 bits or less, the upper nibble of
Port 0 can be programmed independently as I/O while the
lower nibble is used for addressing. If one or both nibbles
are needed for I/O operation, they are configured by writ-
ing to the Port 0 mode register.
In ROMless mode, after a hardware reset, Port 0 is config-
ured as address lines A15-A8, and extended timing is set
to accommodate slow memory access. The initialization
routine can include reconfiguration to eliminate this ex-
tended timing mode. (In ROM mode, Port 0 is defined as
input after reset.)
2
Port 0 is set in the high-impedance mode if selected as an
address output state along with Port 1 and the control sig-
nals /AS, /DS, and R//W (Figure 11).
4
Port 0
(I/O or A15 - A8)
Z89175/176
4
MCU
Handshake Controls
/DAV0 and RDY0
(P32 and P35)
OEN
Pad
Out
1.5
2.3V Hysteresis
In
Auto Latch
R = 500 KΩ
Figure 11. Port 0 Configuration
P R E L I M I N A R Y
DS97TAD0100
23
Z89175/Z89176
Voice Processing Controllers
Zilog
PIN FUNCTIONS (Continued)
Port 1 (P17-P10). Port 1 is an 8-bit, bidirectional, CMOS
compatible port (Figure 12). It has multiplexed Address
(A7-A0) and Data (D7-D0) ports. These eight I/O lines are
programmed as inputs or outputs, or can be configured un-
der software control as an Address/Data port for interfac-
ing external memory. The input buffers are Schmitt-trig-
gered and the output drivers are push-pull.
able). Memory locations greater than 24575 (Z89175) (in
ROM mode) are referenced through Port 1. To interface
external memory, Port 1 must be programmed for the mul-
tiplexed Address/Data mode. If more than 256 external lo-
cations are required, Port 0 outputs the additional lines.
Port 1 can be placed in the high-impedance state along
with Port 0, /AS, /DS, and R//W, allowing the Z89175/176
to share common resources in multiprocessor and DMA
applications.
Port 1 can be placed under handshake control. In this con-
figuration, Port 3, lines P33 and P34 are used as the hand-
shake controls RDY1 and /DAV1 (Ready and Data Avail-
Port 1
(I/O or AD7 - AD0)
8
Z89175/176
MCU
Handshake Controls
/DAV2 and RDY2
(P31 and P36)
OEN
Pad
Out
1.5
2.3V Hysteresis
In
Auto Latch
R = 500 kΩ
Figure 12. Port 1 Configuration
P R E L I M I N A R Y
24
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
Port 2 (P27-P20). Port 2 is an 8-bit, bidirectional, CMOS
compatible I/O port. These eight I/O lines are configured
under software control independently as inputs or outputs.
Port 2 is always available for I/O operation. The input buff-
ers are Schmitt-triggered. Bits programmed as outputs can
be globally programmed as either push-pull or open-drain.
signal assignment for Port 3 lines P31 and P36 is dictated
by the direction (input or output) assigned to bit 7, Port 2
(Figure 13).
2
The Auto Latch on Port 2 puts valid CMOS levels on all
CMOS inputs which are not externally driven. Whether this
level is 0 or 1, cannot be determined. A valid CMOS level,
rather than a floating node, reduces excessive supply cur-
rent flow in the input buffer.
Port 2 can be placed under handshake control. In this con-
figuration, Port 3 lines P31 and P36 are used as the hand-
shake controls lines /DAV2 and RDY2. The handshake
Port 2
(I/O)
Z89175/176
MCU
Handshake Controls
/DAV2 and RDY2
(P31 and P36)
Open-Drain
OEN
Pad
Out
1.5
2.3V Hysteresis
In
Auto Latch
R = 500 KΩ
Figure 13. Port 2 Configuration
P R E L I M I N A R Y
DS97TAD0100
25
Z89175/Z89176
Voice Processing Controllers
Zilog
PIN FUNCTIONS (Continued)
Port 3 (P37-P31). Port 3 is a 7-bit, CMOS compatible port
with three fixed inputs (P33-P31) and four fixed outputs
(P37-P34). It is configured under software control for in-
put/output, counter/timers, interrupt, and port handshakes.
Pins P31, P32, and P33 are standard CMOS inputs; out-
puts are push-pull.
Handshake lines for ports 0, 1, and 2 are available on P31
through P36.
Port 3 also provides the following control functions: hand-
shake for Ports 0, 1, and 2 (/DAV and RDY); three external
interrupt request signals (IRQ3-IRQ1); timer input and out-
put signals (T and T
) (Figure 14).
IN
OUT
Two on-board comparators can process analog signals on
P31 and P32 with reference to the voltage on P33. The an-
alog function is enabled by programming bit 1 of the Port 3
Mode Register. Port 3, pin 3 is a falling edge interrupt in-
put. P31 and P32 are programmable as rising, falling or
both edge-triggered interrupts (IRQ register bits 6 and 7).
P33 is the comparator reference voltage input. Access to
Comparator Inputs. Port 3, pins P31 and P32 all have a
comparator front end. The comparator reference voltage,
pin P33, is common to both comparators. In analog mode,
P31 and P32 are the positive inputs to the comparators
and P33 is the reference voltage supplied to both compar-
ators. In digital mode, pin P33 can be used as a P33 reg-
ister input or IRQ1 source.
counter/timer1 is made through P31 (T ) and P36 (T
).
IN
OUT
Table 5. Port 3 Pin Assignments
Pin
I/O
CTC1
AN IN
Int.
P0 HS
P1 HS
P2 HS
EXT
P31
P32
P33
P34
P35
P36
P37
IN
TIN
AN1
AN2
REF
IRQ2
IRQ0
IRQ1
D/R
IN
D/R
IN
D/R
R/D
OUT
OUT
OUT
OUT
DM
R/D
TOUT
R/D
Notes:
HS = Handshake Signals
D = DAV
R = RDY
26
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
2
1
2
Port 3
(I/O or Control)
3
Z89175/176
MCU
4
5
6
7
R247 = P3M
1 = Analog
0 = Digital
D1
DIG.
AN.
IRQ2, T , P31 Data
IN
Latch
P31 (AN1)
+
-
IRQ0, P32 Data Latch
IRQ1, P33 Data Latch
P32 (AN2)
P33 (REF)
+
-
From Stop Mode
Recovery Source
Figure 14. Port 3 Configuration
DS97TAD0100
P R E L I M I N A R Y
27
Z89175/Z89176
Voice Processing Controllers
Zilog
PIN FUNCTIONS (Continued)
Port 4 (P47-P40). Port 4 is an 8-bit, bidirectional, CMOS
compatible I/O port (Figure 15). These eight I/O lines are
configured under software control independently as inputs
or outputs. Port 4 is always available for I/O operation. The
input buffers are Schmitt-triggered. Bits programmed as
outputs can be globally programmed as either push-pull or
open-drain.
Port 4 is a bit programmable general-purpose I/O port. The
control registers for Port 4 are mapped into the expanded
register file (Bank F) of the Z8.
Auto Latch. The Auto Latch on Port 4 puts valid CMOS
levels on all CMOS inputs which are not externally driven.
Whether this level is 0 or 1 cannot be determined. A valid
CMOS level, rather than a floating node, reduces exces-
sive supply current flow in the input buffer.
Z89175/176
MCU
Port 4
(I/O)
Open-Drain
OEN
Pad
Out
1.5
2.3V Hysteresis
In
Auto Latch
R = 500 KΩ
Figure 15. Port 4 Configuration
28
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
Port 5 (P53-P50). Port 5 is a 4-bit, bidirectional, CMOS
compatible I/O port (Figure 16). These four I/O lines are
configured under software control independently as inputs
or outputs. Port 5 is always available for I/O operation. The
input buffers are Schmitt-triggered. Bits programmed as
outputs can be globally programmed as either push-pull or
open-drain.
Port 5 is a bit programmable general-purpose I/O port. The
control registers for Port 5 are mapped into the expanded
register file (Bank F) of the Z8.
2
Auto Latch. The Auto Latch on Port 5 puts valid CMOS
levels on all CMOS inputs which are not externally driven.
Whether this level is 0 or 1 cannot be determined. A valid
CMOS level, rather than a floating node, reduces exces-
sive supply current flow in the input buffer.
Port 5
(I/O)
Z89175/176
MCU
Open-Drain
OEN
Pad
Out
1.5
2.3V Hysteresis
In
Auto Latch
R = 500 KΩ
Figure 16. Port 5 Configuration
DS97TAD0100
P R E L I M I N A R Y
29
Z89175/Z89176
Voice Processing Controllers
Zilog
®
Z8 FUNCTIONAL DESCRIPTION
The Z8 core of the Z89175/176 incorporates special func-
tions to enhance the Z8’s application in a variety of voice-
processing applications.
65535
24575
External
ROM and RAM
Reset. The device is reset in one of the following condi-
tions:
On-Chip
ROM
In ROM Mode
Location of
■ Power-On Reset
First Byte of
Instruction
Executed
■ Watch-Dog Timer
■ Stop-Mode Recovery Source
■ External Reset
After RESET
12
11
10
9
IRQ5
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQ0
IRQ0
Program Memory. The Z8 addresses up to 24 KB of inter-
nal program memory and 40 KB external memory (Figure
17). The first 12 bytes of program memory are reserved for
the interrupt vectors. These locations contain six 16-bit
vectors which correspond to the five user interrupts and
one DSP interrupt. Byte 12 to byte 24575 consist of on-
chip mask-programmed ROM. At addresses 24576 and
greater the Z8 executes external program memory. In
ROMless mode, the Z8 will execute external program
memory beginning at byte 12 and continuing through byte
65535.
8
7
Interrupt
Vector
(Lower Byte)
6
5
4
Interrupt
Vector
(Upper Byte)
3
2
1
0
Figure 17. Program Memory
30
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
ROM Protect. The 24 KB of internal program memory for
the Z8 is mask programmable. A ROM protect feature pre-
vents “dumping” of the ROM contents of Program Memory
by inhibiting execution of LDC, LDCI, LDE, and LDEI in-
structions. The ROM Protect option is mask-programma-
ble, to be selected by the customer at the time the ROM
code is submitted.
memory, and an LDE instruction references data (/DM ac-
tive Low) memory.
2
65535
Data Memory (/DM). In ROM mode, the Z8 can address
up to 40 KB of external data memory beginning at location
24576 (Figure 18). In ROMless mode, the Z8 can address
the full 64 KB of external data memory beginning at loca-
tion 12. External data memory can be included with, or
separated from, the external program memory space.
/DM, an optional I/O function that can be programmed to
appear on Port 34, is used to distinguish between data and
program memory space (Table 5). The state of the /DM
signal is controlled by the type of instruction being execut-
ed. An LDC opcode references PROGRAM (/DM inactive)
External
Data
Memory
24575
Not Addressable
(In ROM Mode)
0
Figure 18. Data Memory Map
DS97TAD0100
P R E L I M I N A R Y
31
Z89175/Z89176
Voice Processing Controllers
Zilog
®
Z8 FUNCTIONAL DESCRIPTION (Continued)
®
Register File. The standard Z8 register file consists of
Expanded Register File. The register file on the Z8 has
been expanded to allow for additional system control reg-
isters and for mapping of additional peripheral devices
along with I/O ports into the register address area. The Z8
register address space has been implemented as 16
banks of 16 register groups per bank (Figure 20). These
register banks are known as the ERF (Expanded Register
File). Bits 7-4 of register RP (Register Pointer) select the
working register group. Bits 3-0 of register RP select the
Expanded Register bank (Figure 21).
four I/O port registers, 236 general-purpose registers, and
15 control and status registers (R0-R3, R4-R239, and
R241-R255, respectively). The instructions access regis-
ters directly or indirectly through an 8-bit address field.
This allows a short, 4-bit register address using the Regis-
ter Pointer (Figure 19). In the 4-bit mode, the register file
is divided into 16 working register groups, each occupying
16 continuous locations. The Register Pointer addresses
the starting location of the active working register group
(Figure 20).
The SMR register, WDT Register, control and data regis-
ters for Port 4 and Port 5, and the DSP control register are
located in Bank F of the Expanded Register File. Bank B
of the Expanded Register File consists of the Mailbox In-
terface through which the Z8 and the DSP communicate.
The rest of the Expanded Register is not physically imple-
mented and is open for future expansion.
Note: Register Group E (Registers EF-E0) is only access-
ed through a working register and indirect addressing
modes.
RAM Protect. The upper portion of the Z8’s RAM address
spaces 80H to EFH (excluding the control registers) is pro-
tected from reading and writing. The RAM Protect bit op-
tion is mask-programmable and is selected by the custom-
er when the ROM code is submitted. After the mask option
is selected, the user activates the RAM Protect from the in-
ternal ROM code by loading a bit D6 in the IMR register to
either a 0 (OFF) or a 1 (ON). A 1 in D6 indicates RAM Pro-
tect enabled.
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register File Bank
Working Register Group
Stack. The Z8’s external data memory or the internal reg-
ister file is used for the stack. The 16-bit Stack Pointer
(R255-R254) is used for the external stack which can re-
side only from 24576 to 65535 in ROM mode or 0 to 65535
in ROMless mode. An 8-bit Stack Pointer (R255) is used
for the internal stack residing within the 236 general-pur-
pose registers (R239-R4). SPH can be used as a general-
purpose register when using internal stack only.
Figure 19. Register Pointer Register
32
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
2
R255
R253
R240
r7 r6 r5 r4
r3 r2 r1 r0
Group 15 (F) Control Registers
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group
R239
Group 14 (E)
Group 13 (D)
R223
R79
R63
R47
The upper nibble
of the register
file address
provided by the
instruction points
to the specified
working-register
group
Group 4 (4)
Group 3 (3)
Group 2 (2)
Specified Working
Register Group
R31
R15
Group 1 (1)
Group 0 (0)
R3
R0
I/O Ports
Figure 20. Register Pointer
DS97TAD0100
P R E L I M I N A R Y
33
Z89175/Z89176
Voice Processing Controllers
Zilog
®
Z8 FUNCTIONAL DESCRIPTION (Continued)
Z8 STANDARD CONTROL REGISTERS
RESET CONDITION
REGISTER BANK (0)
REGISTER GROUP 15(F)
D7 D6 D5 D4 D3 D2 D1 D0
FFH
FEH
FDH
FCH
FBH
FAH
F9H
F8H
F7H
F6H
F5H
% F4
F3H
F2H
F1H
F0H
SPL
REGISTER POINTER
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
SPH
RP
7
6
5
4
3
2
1
0
FLAGS
IMR
Working Register
Group Pointer
Expanded Register
Bank Pointer
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
IRQ
0
IPR
U
0
U
1
U
0
U
0
U
1
U
1
U
0
U
1
P01M
P3M
P2M
PRE0
T0
†
*
*
0
0
0
0
0
0
0
0
Z8 Reg. File
1
1
1
1
1
1
1
1
FFH
FOH
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
0
0
U
0
PRE1
T1
U
0
U
0
TMR
Reserved
Z8 EXPANDED REGISTER BANK (F)
REGISTER GROUP 0 (0) RESET CONDITION
F
7FH
E
D
(F) 0FH
(F) 0EH
(F) 0DH
WDTMR
HSEC
U
U
U
0
1
1
0
1
*
*
C
B
A
9
Reserved
DSP CON
8
(F) 0CH
(F) 0BH
(F) 0AH
(F) 09H
(F) 08H
U
0
U
0
U
1
1
0
U
0
U
0
U
0
U
0
7
6
SMR
5
Reserved
4
3
2
Reserved
Reserved
Reserved
P45CON
P5M
1
0
0FH
00H
(F) 07H
U
U
U
0
U
U
U
0
(F) 06H
(F) 05H
(F) 04H
1
1
1
1
1
1
1
1
U
U
U
U
U
U
U
U
P5
P4M
(F) 03H
(F) 02H
(F) 01H
(F) 00H
1
1
1
1
1
1
1
1
P4
U
U
U
U
U
U
U
U
Reserved
PCON
1
1
1
1
1
1
1
0
Notes:
Z8 EXPANDED REGISTER BANK (B)
U = Unknown
† = For ROMless mode, RESET Condition 10110110
Z8-DSP Mailbox Interface
(R0...R15)
Will not be Reset with a Stop-Mode Recovery
*
Z8 STANDARD REGISTER BANK (0)
REGISTER GROUP 0 RESET CONDITION
1
1
1
1
U
U
U
U
U
U
U
(0) 03H
(0) 02H
(0) 01H
P3
P2
P1
P0
*
U
U
U
U
U
*
*
*
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
(0) 00H
Figure 21. Expanded Register File Architecture
P R E L I M I N A R Y
34
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
Interrupts. The Z8 has six different interrupts from six dif-
ferent sources. The interrupts are maskable and prioritized
(Figure 22). The six sources are divided as follows; three
sources are claimed by Port 3 lines P33-P31, two by
counter/timers, and one by the DSP (Table 6). The Inter-
rupt Mask Register globally or individually enables or dis-
ables the six interrupt requests.
2
IRQ0 IRQ2
IRQ1, 3, 4, 5
Interrupt
Edge
IRQ Register
(D6, D7)
Select
IRQ
IMR
IPR
6
Global
Interrupt
Enable
Interrupt
Request
Priority
Logic
Vector Select
Figure 22. Interrupt Block Diagram
DS97TAD0100
P R E L I M I N A R Y
35
Z89175/Z89176
Voice Processing Controllers
Zilog
®
Z8 FUNCTIONAL DESCRIPTION (Continued)
Table 6. Interrupt Types, Sources, and Vectors
Programming bits for the Interrupt Edge Select are located
in the IRQ Register (R250), bits D7 and D6 . The configu-
ration is shown in Table 7.
Vector
Name
Source
Location
Comments
Table 7. IRQ Register
IRQ0 /DAV0, P32,
AN2
0, 1
External (P32),
Programmable Rise
or Fall Edge
IRQ
Interrupt Edge
D7
0
D6
0
P31
P32
F
Triggered
F
F
IRQ1 /DAV1, P33
2, 3
4, 5
External (P33), Fall
Edge Triggered
0
1
R
IRQ2 /DAV2, P31,
TIN, AN2
External (P31),
Programmable Rise
or Fall Edge
1
0
R
F
1
1
R/F
R/F
Notes:
Triggered
F = Falling Edge
R = Rising Edge
IRQ3
IRQ3
6, 7
8, 9
Internal (DSP
activated), Fall Edge
Triggered
Clock. The Z89175/176 on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to a crystal, LC,
ceramic resonator, or any suitable external clock source
(XTAL1 = Input, XTAL2 = Output). The crystal should be
AT cut, 20.48 MHz maximum, with a series resistance
(RS) less than or equal to 100 Ohms. The system clock
(SCLK) is one half the crystal frequency.
IRQ4
IRQ5
T0
TI
Internal
10, 11 Internal
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder controlled by
the Interrupt Priority Register. An interrupt machine cycle
is activated when an interrupt request is granted. This dis-
ables all subsequent interrupts, pushes the Program
Counter and Status Flags to the stack, and then branches
to the program memory vector location reserved for that in-
terrupt.
The crystal is connected across XTAL1 and XTAL2 using
capacitors from each pin to Ground (Figure 23).
All Z8 interrupts are vectored through locations in the pro-
gram memory. This memory location and the next byte
contain the 16-bit address of the interrupt service routine
for that particular interrupt request. To accommodate
polled interrupt systems, interrupt inputs are masked and
the Interrupt Request Register can be polled to determine
which of the interrupt requests needs service.
An interrupt resulting from AN1 is mapped into IRQ2, and
an interrupt from AN2 is mapped into IRQ0. Interrupts
IRQ2 and IRQ0 can be rising, falling or both edge trig-
gered, and are programmable by the user. The software
can poll to identify the state of the pin.
36
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
XTAL1
XTAL2
XTAL1
XTAL2
XTAL1
XTAL2
2
C1
C2
C1
C2
L
External Clock
Ceramic Resonator or
Crystal
LC
Figure 23. Oscillator Configuration
Counter/Timers. There are two 8-bit programmable
counter/timers (T1,T0), each driven by its own 6-bit pro-
grammable prescaler. The T1 prescaler is driven by inter-
nal or external clock sources. However, the T0 prescaler is
driven by the internal clock only (Figure 24).
The counters can be programmed to start, stop, restart to
continue, or restart from the initial value. The counters can
also be programmed to stop upon reaching zero (single
pass mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode).
The 6-bit prescalers can divide the input frequency of the
clock source by any integer number from 1 to 64. Each
prescaler drives its counter, which decrements the value
(0 to 256) that has been loaded into the counter. When the
counter reaches the end of the count, a timer interrupt re-
quest, IRQ4 (T0) or IRQ5 (T1), is generated.
The counters, but not the prescalers, are read at any time
without disturbing their value or count mode. The clock
source for T1 is user-definable and is either the internal mi-
croprocessor clock divided by four, or an external signal in-
put via Port 31. The Timer Mode register configures the ex-
ternal timer input (P31) as an external clock, a trigger input
that can be retriggerable or non-retriggerable, or
as a gate input for the internal clock. The counter/timers
can be cascaded by connecting the T0 output to the input
of T1.
DS97TAD0100
P R E L I M I N A R Y
37
Z89175/Z89176
Voice Processing Controllers
Zilog
®
Z8 FUNCTIONAL DESCRIPTION (Continued)
DSP Clock
÷ 2
÷ 2
÷ 2
OSC
D7, D6
(F) OC
(DSP CON)
Internal Data Bus
T0, T2, T3
Write
Write
Read
PRE0
Initial Value
Register
T0
T0
D0,D1
(SMR)
Initial Value
Register
Current Value
Register
÷ 16
6-Bit
Down
8-bit
Down
÷4
Counter
Counter
Internal
Clock
IRQ4
T
÷2
OUT
External Clock
P36
Clock
Logic
6-Bit
Down
8-Bit
Down
IRQ5
÷4
Counter
Counter
Internal Clock
Gated Clock
PRE1
Initial Value
Register
T1
T1
Initial Value
Register
Current Value
Register
Triggered Clock
TIN P31
Write
Internal Data Bus
Write
Read
Figure 24. Counter/Timer Block Diagram
38
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
Port Configuration Register (PCON). The PCON regis-
ter configures the comparator output on Port 3. The PCON
register (Figure 25) is located in the Expanded Register
File at Bank F, location 00H.
Power-On Reset (POR). A timer circuit clocked by a ded-
icated on-board RC oscillator is used for the Power-On Re-
set (POR) timer function. The POR time allows VCC and
the oscillator circuit to stabilize before instruction execu-
tion begins.
2
Comparator Output Port 3 (D0). Bit 0 controls the com-
parator use in Port 3. A 1 in this location brings the com-
parator outputs to P34 and P35, and a 0 releases the Port
to its standard I/O configuration.
The POR timer circuit is a one-shot timer triggered by one
of three conditions:
1. Power fail to Power OK status;
2. Stop-Mode Recovery (if D5 of SMR=1);
3. WDT time-out.
PCON (F) %00
D7 D6 D5 D4 D3 D2 D1 D0
The POR time is a nominal 5 ms. Bit 5 of the STOP mode
register determines whether the POR timer is bypassed af-
ter Stop-Mode Recovery (typical for external clock, RC/LC
oscillators).
R Always "1"
W 0 P34,P37 Standard output
1 P34,P37 Comparator output
R
Always "1"
W No effect
Note: Reset condition is 11111110
HALT. HALT turns off the internal CPU clock, but not the
XTAL oscillation. The counter/timers and external inter-
rupts IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The de-
vices are recovered by interrupts, either externally or inter-
nally generated.
Figure 25. Port Configuration Register (PCON)
Port 4 and 5 Configuration Register (P45CON). The
P45CON register configures Port 4 and Port 5, individual-
ly, to open-drain or push-pull active. This register is located
in the Expanded Register File at Bank F, location 06H (Fig-
ure 26).
STOP. This instruction turns off the internal clock and ex-
ternal crystal oscillation. It reduces the standby current to
20 µA or less. The STOP mode is terminated by a reset
only, either by WDT time-out, POR, SMR, or external re-
set. This causes the processor to restart the application
program at address 000CH. In order to enter STOP (or
HALT) mode, it is necessary to first flush the instruction
pipeline to avoid suspending execution in mid-instruction.
To do this, the user must execute a NOP (opcode=FFH)
immediately before the appropriate Sleep instruction, i.e.,
Port 4 Open-Drain (D0). Port 4 can be configured as an
open-drain by resetting this bit (D0 = 0) or configured as
push-pull active by setting this bit (D0 = 1). The default val-
ue is 1.
Port 5 Open-Drain (D4). Port 5 can be configured as an
open-drain by resetting this bit (D4 = 0) or configured as
push-pull active by setting this bit (D4 = 1). The default val-
ue is 1.
FF
6F
NOP
; clear the pipeline
; enter Stop mode
or
STOP
FF
7F
NOP
; clear the pipeline
; enter Halt mode
HALT
DS97TAD0100
P R E L I M I N A R Y
39
Z89175/Z89176
Voice Processing Controllers
Zilog
®
Z8 FUNCTIONAL DESCRIPTION (Continued)
Stop-Mode Recovery Register (SMR). This register se-
lects the clock divide value and determines the mode of
Stop-Mode Recovery (Figure 26). All bits are Write-Only
except bit 7, which is Read-Only. Bit 7 is a flag bit that is
hardware set on the condition of STOP recovery and reset
by a power-on cycle. Bit 6 controls whether a low level or
a high level is required from the recovery source. Bit 5 con-
trols the reset delay after recovery. Bits 2, 3, and 4, or the
SMR register, specify the source of the Stop-Mode Recov-
ery signal. Bits 0 and 1 determine the time-out period of the
WDT. The SMR is located in Bank F of the Expanded Reg-
ister group at address 0BH.
SMR (FH) 0BH
D7 D6 D5 D4 D3 D2 D1 D0
W 0 SCLK/TCLK not divided by 16†
1 SCLK/TCLK divided by 16
R Always "1"
Reserved
W 000 POR only*
001 No effect
010 P31
011 P32
100 P33
101 Half second timeout from
33 kHz ext. osc.
110 P2 NOR 0-3
111 P2 NOR 0-7
R
Always "1"
W Stop Delay
0 OFF
1 ON*
R Always "1"
W 0 Low Stop Recovery Level*
1 High Stop Recovery Level
R Always "1"
W No effect
R 0 POR*
* Default SettingAfter Reset
† Reset After Stop-Mode Recovery
1 Stop-Mode Recovery
Figure 26. Stop-Mode Recovery Register (SMR)
40
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
SCLK/TCLK divide-by-16 Select (D0). D0 of the SMR
controls a divide-by-16 prescaler of SCLK/TCLK. The pur-
pose of this control is to selectively reduce device power
consumption during normal processor execution (SCLK
control) and/or HALT mode (where TCLK sources
counter/timers and interrupt logic).
Stop-Mode Recovery Source (D4-D2). These three bits
of the SMR specify the wake-up source of the STOP re-
covery (Figure 27 and Table 8).
2
SMR D4 D3 D2
0
0
0
SMR D4 D3 D2 SMR D4 D3 D2 SMR D4 D3 D2
SMR D4 D3 D2
SMR D4 D3 D2
VDD
0
0
1
1
0
1
1
0
0
1
0
1
1
1
0
1
1
1
P20
P20
P31
P32
P33
HSEC
P23
P27
To POR
RESET
Stop Mode Recovery Edge
Select (SMR)
To P33 Data
Latch and IRQ1
MUX
P33 From Pads
Digital/Analog Mode
Select (P3M)
Figure 27. Stop-Mode Recovery Source
Table 8. Stop-Mode Recovery Source
Stop-Mode Recovery Delay Select (D5). When Low, this
bit disables the 5 ms /RESET delay after Stop-Mode Re-
covery. The default configuration of this bit is 1. If the “fast”
wake up is selected, the Stop-Mode Recovery source is
kept active for at least 5 TpC.
SMR:432
Operation
D4
D3
D2
Description of Action
0
0
0
POR and/or external reset
recovery
Stop-Mode Recovery Edge Select (D6). A 1 in this bit po-
sition indicates that a high level on any one of the recovery
sources wakes the Z89175/176 from STOP mode. A 0 in-
dicates low level recovery. The default is 0 on POR (Table
8).
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
No effect
P31 transition
P32 transition
P33 transition
HSEC
Cold or Warm Start (D7). This bit is set by the device
upon entering STOP mode. It is active High, and is 0 (cold)
on POR/WDT /RESET. This bit is Read-Only. It is used to
distinguish between a cold or warm start.
Logical NOR of P20 through
P23
1
1
1
Logical NOR of P20 through
P27
DSP Control Register (DSPCON). The DSPCON register
controls various aspects of the Z8 and the DSP. It can con-
figure the internal system clock (SCLK) or the Z8, /RE-
SET, and HALT of the DSP, and control the interrupt inter-
face between the Z8 and the DSP (Table 9).
DS97TAD0100
P R E L I M I N A R Y
41
Z89175/Z89176
Voice Processing Controllers
Zilog
®
Z8 FUNCTIONAL DESCRIPTION (Continued)
Table 9. DSP Control Register (F) OCH [Read/Write]
Field
DSPCON (F)0CH
Position
Attrib
Value
Label
Z8_SCLK
76------
R/W
00
01
1x
(OSC/8)
(OSC/4)
(OSC/2)
DSP_Reset
--5-----
R
Return “0”
No effect
W
0
1
0
1
Reset DSP
Halt_DSP
Run_DSP
No effect
DSP_Run
Reserved
---4----
----32--
R/W
W
R
Return “0”
No effect
DSP_INT2
Z8_IRQ3
------1-
-------0
R
FB_DSP_INT2
Set DSP_INT2
No effect
W
1
0
R
FB_Z8_IRQ3
Clear IRQ3
No effect
W
1
0
Z8 IRQ3 (D0). When read, this bit indicates the status of
the Z8 IRQ3. The Z8 IRQ3 is set by the DSP by writing to
D9 of DSP External Register 4 (ICR). By writing a 1 to this
bit, Z8 IRQ3 is Reset.
DSP RESET (D5). Setting this bit to 1 will reset the DSP.
If the DSP was in HALT mode, this bit is automatically pre-
set to 1. Writing a 0 has no effect.
Z8 SCLK (D7-D6). These bits define the SCLK frequency
of the Z8. The oscillator can be divided by 8, 4, or 2. After
a reset, both bits default to 00.
DSP INT2 (D1). This bit is linked to DSP INT2. Writing a 1
to this bit sets the DSP INT2. Reading this bit indicates the
status of the DSP INT2.
Watch-Dog Timer Mode Register (WDTMR). The WDT
is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. The WDT is initially enabled by
executing the WDT instruction and refreshed on subse-
quent executions of the WDT instruction. The WDT circuit
is driven by an on-board RC oscillator or external oscillator
from the XTAL1 pin. The POR clock source is selected
with bit 4 of the WDT register (Figure 29). The WDTMR
register is accessible only within 64 Z8 clock cycles after
POR.
DSP RUN (D4). This bit defines the HALT mode of the
DSP. If this bit is set to 0, then the DSP clock is turned off
to minimize power consumption. After this bit is set to 1,
then the DSP will continue code execution from where it
was halted. After a hardware reset, this bit is reset to 1.
42
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
WDTMR (F) 0F
2
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC EXTERNAL CLOCK
00
01*
10
11
5 ms
15 ms
25 ms
100 ms
256 Tpc
512 Tpc
1024 Tpc
4096 Tpc
WDT During HALT
0 OFF
1 ON*
WDT During STOP
0 OFF
1 ON*
XTAL1/INT RC Select for WDT
0 On-Board RC
1 XTAL
W No effect
R Always "1"
* Default setting after RESET
Figure 28. Watch-Dog Timer Mode Register
Half-Second Timer Status Register (HSEC). The half-
second timer status register (Figure 30) is a free-running
timer clocked by the external 32.768 kHz crystal. In normal
operation mode, every half-second, the timer will time-out
and set bit 0 (D0) of the HSEC register to 1. The user can
reset this bit for real timing. In Stop mode, this timer can be
used as a Stop-Mode Recovery source. Every half-sec-
ond, the timer will recover the Stop mode and bit 0 of the
HSEC register will be set to 1. Therefore, in Stop mode,
the user can keep real time.
HSEC (F) 0E
D7 D6 D5 D4 D3 D2 D1 D0
R
1 Half second time-out
0 No time-out
W
1 No effect
0 RESET the half second timer bit
Reserved R "0"
W No effect
Figure 29. Half-Second Timer Status Register
DS97TAD0100
P R E L I M I N A R Y
43
Z89175/Z89176
Voice Processing Controllers
Zilog
®
Z8 FUNCTIONAL DESCRIPTION (Continued)
WDT Time Select (D0, D1). These bits selects the WDT
time period. The configuration is shown in Table 10.
WDT During HALT (D2). This bit determines whether or
not the WDT is active during HALT mode. A 1 indicates ac-
tive during HALT. The default is 1.
Table 10. WDT Time Select
WDT During STOP (D3). This bit determines whether or
not the WDT is active during STOP mode. Since XTAL
clock is stopped during STOP mode, the on-board RC
must be selected as the clock source to the POR counter.
A 1 indicates active during STOP. The default is 1.
Time-out of
Time-out of
XTAL Clock
D1
D0‘
Internal RC OSC
0
0
1
0
1
5 ms min
15 ms min
25 ms min
100 ms min
256 TpC
512 TpC
1024 TpC
4096 TpC
0
Clock Source for WDT (D4). This bit determines which
oscillator source is used to clock the internal POR and
WDT counter chain. If the bit is a 1, the internal RC oscil-
lator is bypassed and the POR and WDT clock source is
driven from the external pin, XTAL1. The default configu-
ration of this bit is 0 which selects the RC oscillator.
1
1
Notes:
TpC = XTAL clock cycle.
Tolerance = ±10%
/RESET
4 Clock
Filter
Clear
CLK
18 Clock RESET
RESET
Generator
Internal
RESET
WDT Select
(WDTMR)
WDT TAP SELECT
CK Source
Select
(WDTMR)
5 ms 15 ms 25 ms 100 ms
WDT/POR Counter Chain
5 ms POR
CK
XTAL
M
U
X
CLR
RC
OSC.
2V Operating
Voltage Det.
+
-
VDD
2V REF.
From Stop
Mode
Recovery
Source
12 ns Glitch Filter
WDT
Stop Delay
Select (SMR)
Figure 30. Resets and WDT
P R E L I M I N A R Y
44
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
DSP REGISTERS DESCRIPTION
General. The DSP is a high-performance second genera-
tion CMOS Digital Signal Processor with a modified Har-
vard-type architecture with separate program and data
ports. The design has been optimized for processing pow-
er and saving silicon space.
and D/A converters, and the mailbox and interrupt interfac-
ing between DSP to the Z8. External registers are access-
ed in one machine cycle, the same as internal registers.
2
DSP Registers
There are 15 internal and extended 16-bit registers which
are defined in Table 11.
Registers. The DSP has eight internal registers and sev-
en external registers. The external registers are for the A/D
Table 11. DSP Registers
Register
Attribute
Register Definition
BUS
X
Read
Data-Bus
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read
X Multiplier Input, 16-Bit
Y
Y Multiplier Input, 16-Bit
A
Accumulator, 24-Bit
SR
SP
PC
P
Status Register
Stack Pointer
Program Counter
Output of MAC, 24-Bit
EXT0
Read
Z8 ERF Bank B, Register 00-01 (from Z8)
Z8 ERF Bank B, Register 08-09 (to Z8)
Z8 ERF Bank B, Register 02-03 (from Z8)
Z8 ERF Bank B, Register 0A-0B (to Z8)
Z8 ERF Bank B, Register 04-05 (from Z8)
Z8 ERF Bank B, Register 0C-0D (to Z8)
Z8 ERF Bank B, Register 06-07 (from Z8)
Z8 ERF Bank B, Register 0E-0F (to Z8)
DSP Interrupt Control Register
A/D Converter
Write
EXT1
EXT2
EXT3
Read
Write
Read
Write
Read
Write
EXT4
EXT5
Read/Write
Read
Write
D/A Converter
EXT6
Read/Write
Analog Control Register
EXT3-EXT0 (External Registers 3-0). These are the Mail-
box Registers used by the DSP and Z8 to communicate.
These four 16-bit registers correspond to the eight outgo-
ing and eight incoming 8-bit registers in Bank B of the Z8’s
Expanded Register File.
EXT6 (Analog Control Register). This register controls the
D/A and A/D converters. It is a read/write register accessi-
ble only by the DSP.
DSP Z8 Mail Box
To receive information from the DSP, the Z8 uses eight in-
coming registers which are mapped in the Z8 extended
Register File (Bank B, 08 to 0F). The DSP treats these as
four 16-bit registers that correspond to the eight incoming
Z8 registers (Figure 32).
EXT4 (DSP Interrupt Control Register (ICR)). This register
controls the interrupts in the DSP as well as the interrupts
in common between the DSP and the Z8. It is accessible
by the DSP only, except for bit F and bit 9.
EXT5 (D/A and A/D Data Register). This register is used
by both D/A and A/D converters. The D/A converter is
loaded by writing to this register, while the A/D converter is
addressed by reading from this register. The Register
EXT5 is accessible only by the DSP.
DS97TAD0100
P R E L I M I N A R Y
45
Z89175/Z89176
Voice Processing Controllers
Zilog
DSP REGISTERS DESCRIPTION (Continued)
The Z8 can supply the DSP with data through eight outgo-
ing registers mapped into both the Z8 Expanded Register
File (Bank B, Registers 00 to 07) and the external register
interface of the DSP. These registers are Read/Write and
can be used as general-purpose registers of the Z8. The
DSP can only read information from these registers. Since
the DSP uses a 16-bit data format and the Z8 an 8-bit data
format, eight outgoing registers of the Z8 correspond to
four DSP registers. The DSP can only read information
from the outgoing registers.
Both the outgoing registers and the incoming registers
share the same DSP address (EXT3-EXT0).
Note: The Z8 can read and write to ERF Bank B R00-R07,
Registers 08-0F are Read-Only from the Z8.
Outgoing Registers
(B)00, (B)01
(B)02, (B)03
EXT0
EXT1
EXT2
EXT3
(B)04, (B)05
(B)06, (B)07
Incoming Registers
(B)08, (B)09
(B)0A, (B)0B
EXT0
EXT1
EXT2
EXT3
(B)0C, (B)0D
(B)0E, (B)0F
DSP Interrupt Control Register
D/A and A/D Data Registers
EXT4
(F)0C
D7, D1
EXT5
D9
D2
Analog Control Register
EXT6
Figure 31. Z8-DSP Interface
Table 12. Z8 Outgoing Registers (Read-Only from DSP)
Field
Position
76543210
Attrib
Value
Label
Outgoing [0] (B)00
Outgoing [1] (B)01
Outgoing [2] (B)02
Outgoing [3] (B)03
Outgoing [4] (B)04
Outgoing [5] (B)05
Outgoing [6] (B)06
Outgoing [7] (B)07
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
%NN
%NN
%NN
%NN
%NN
%NN
%NN
%NN
(B)00/DSP_ext0_hi
(B)01/DSP_ext0_lo
(B)02/DSP_ext1_hi
(B)03/DSP_ext1_lo
(B)04/DSP_ext2_hi
(B)05/DSP_ext2_lo
(B)06/DSP_ext3_hi
(B)07/DSP_ext3_lo
76543210
76543210
76543210
76543210
76543210
76543210
76543210
46
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
Table 13. Z8 Incoming Registers (Write-Only from DSP)
Field
Position
76543210
Attrib
Value
Label
Incoming [8] (B)08
Incoming [9] (B)09
Incoming [a] (B)0A
Incoming [b] (B)0B
Incoming [c] (B)0C
Incoming [d] (B)0D
Incoming [e] (B)0E
Incoming [f] (B)0F
R
W
R
%NN
DSP_ext0_hi
No Effect
2
76543210
76543210
76543210
76543210
76543210
76543210
76543210
%NN
%NN
%NN
%NN
%NN
%NN
%NN
DSP_ext0_lo
No Effect
W
R
DSP_ext1_hi
No Effect
W
R
DSP_ext1_lo
No Effect
W
R
DSP_ext2_hi
No Effect
W
R
DSP_ext2_lo
No Effect
W
R
DSP_ext3_hi
No Effect
W
R
DSP_ext3_lo
No Effect
W
Table 14. DSP Incoming Registers
Attrib
Field
Position
Value
Label
DSP_ext0
Mail Box
DSP_ext1
Mail Box
DSP_ext2
Mail Box
DSP_ext3
Mail Box
fedcba9876543210
fedcba9876543210
fedcba9876543210
fedcba9876543210
R
W
R
%NNNN
(B)00, (B)01
(B)08, (B)09
(B)02, (B)03
(B)0A, (B)0B
(B)04, (B)05
(B)0C, (B)0D
(B)06, (B)07
(B)0E, (B)0F
%NNNN
%NNNN
%NNNN
W
R
W
R
W
DS97TAD0100
P R E L I M I N A R Y
47
Z89175/Z89176
Voice Processing Controllers
Zilog
and INT0, respectively (Figure 35). The DSP does not al-
low interrupt nesting (interrupting service routines that are
currently being executed). When two interrupt requests oc-
cur simultaneously the DSP starts servicing the interrupt
with the highest priority level.
DSP Interrupts
The DSP processor has three interrupt sources (INT2,
INT1, INT0) (Figure 33). These sources have different pri-
ority levels (Figure 34). The highest priority, the next lower
and the lowest priority level are assigned to INT2, INT1
INT2
INT1
INT0
INT2
INT1
INT0
Z8_INT
A/D INT
D/A INT
Interrupt Priority Logic
Interrupt Request Logic
Interrupt Mask Logic
IPR2
IPR1
IPR0
CLEAR_INT0
CLEAR_INT1
CLEAR_INT2
FB DSP
FeedBack Z8_INT MPX
ENABLE_INT
Figure 32. DSP Interrupts
INT0
INT1
INT2
INT2
INT0
INT1
INT2
DSP Execution
Figure 33. DSP Interrupt Priority Structure
48
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
Z8 Side
DSP Side
2
On the Z8, set D1 to
interrupt DSP via DSP INT2.
DSP INT2
DSP CON
1
0
After serving INT2,
set D4 to clear the
interrupt request.
After serving IRQ3,
set D0 to clear the
interrupt request.
ICR
(EXT4)
9
4
The DSP sets D9 to
interrupt Z8 via Z8 IRQ3.
IRQ3 of the Z8
Figure 34. Interprocessor Interrupts Structure
Table 15. EXT4 DSP Interrupt Control Register (ICR) Definition
Field
Position
Attrib
Value
Label
DSP_IRQ2
DSP_IRQ1
DSP_IRQ0
f---------------
R
1
0
Set_IRQ2
Reset_IRQ2
No effect
f---------------
-e--------------
W
R
1
0
Set_IRQ1
Reset_IRQ1
No effect
-e--------------
--d-------------
W
R
1
0
Set_IRQ0
Reset_IRQ0
No effect
--d-------------
---c------------
W
DSP_MaskINT2
DSP_MaskINT1
DSP_MaskINT0
Z8_IRQ3
R/W
1
0
1
0
1
0
Enable_INT2
Disable_INT2
Enable_INT1
Disable_INT1
Enable_INT0
Disable_INT0
Return "0"
Set_Z8_IRQ3
Reset_Z8_IRQ3
Enable
----b-----------
-----a----------
R/W
R/W
------9---------
------9---------
R
W
1
0
DSPintEnable
-------8--------
R/W
1
0
Disable
DSP_IPR2
DSP_IPR1
DSP_IPR0
Clear_IRQ2
--------7-------
---------6------
----------5-----
-----------4----
R/W
R/W
R/W
R
Binary
Binary
Binary
IPR2
IPR1
IPR0
Return "0"
DS97TAD0100
P R E L I M I N A R Y
49
Z89175/Z89176
Voice Processing Controllers
Zilog
DSP REGISTERS DESCRIPTION (Continued)
Table 15. EXT4 DSP Interrupt Control Register (ICR) Definition
Field
Position
Attrib
Value
Label
Clear_IRQ2
-----------4----
W
1
0
Has_no_effect
Return "0"
Clear_IRQ1
No effect
Clear_IRQ1
------------3---
------------3---
R
W
1
0
Clear_IRQ0
Reserved
-------------2--
-------------2--
R
Return "0"
Clear_IRQ0
No effect
W
1
0
--------------10
W
R
No effect "0"
Interrupt Control Register (ICR). The ICR is mapped into
EXT4 of the DSP (Table 15). The bits are defined as fol-
lows:
LD
OR
POP
IRET
;
;
;
;
RP,#%0F
r12,#%01
RP
DSP_IRQ2 (Z8 Interrupt). This bit is read by both Z8 and
DSP and is set only by writing to the Z8 expanded Register
File (Bank F, ROC, bit 0). This bit asserts IRQ2 of the DSP
and is cleared by writing to the Clear_IRQ2 bit.
DSP Enable_INT. Writing a 1 to this location enables glo-
bal interrupts of the DSP while writing 0 disables them. A
system Reset globally disables all interrupts.
DSP_IRQ1 (A/D Interrupt). This bit is read by the DSP only
and is set when valid data is present at the A/D output reg-
ister (conversion done). This bit asserts IRQ1 of the DSP
and is cleared by writing to the Clear_IRQ1bit.
DSP_IPRX. This three-bit group defines the Interrupt Se-
lection logic as shown in Table 16.
Clear_IRQX. These bits are accessed by the DSP only.
Writing a 1 to these locations resets the corresponding
DSP_IRQX bits to 0. Clear_IRQX are virtual bits and are
not implemented.
DSP_IRQ0 (D/A Interrupt). This bit is read by DSP only
and is set by Timer3. This bit assists IRQ0 of the DSP and
is cleared by writing to the Clear_IRQ0 bit.
Table 16. DSP Interrupt Selection
DSP_MaskIntX. These bits are accessed by the DSP
only. Writing a 1 to these locations allows the INT to be
serviced, while writing a 0 masks off the corresponding
INT.
DSP_IPR[2-0] Z8_INT is
A/D_INT is D/A_INT is
2 1 0
switched to switched to switched to
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
INT2
INT1
INT1
INT2
INT0
INT0
Z8_IRQ3. This bit can be read by both the Z8 and the DSP
but can only be set by the DSP. Addressing this location
accesses bit D3 of the Z8 IRQ register, hence, this bit is
not implemented in the ICR. During the interrupt service
routine executed on the Z8 side, the User must reset the
Z8_IRQ3 bit by writing a 1 to bit D0 of the DSPCON.
INT2
INT0
INT1
INT1
INT0
INT2
INT0
INT2
INT1
INT0
INT1
INT2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
The hardware of the Z89175/176 automatically resets
Z8_IRQ3 bit three instructions of the Z8 after 1 is written to
its location in register bank 0F. This delay provides the tim-
ing synchronization between the Z8 and the DSP sides
during interrupts. In summary, the interrupt service routine
of the Z8 for IRQ3 should be finished by:
50
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
A/D supplies 8-bit data to the DSP through the register
EXT5 of the DSP. From the 16 bits of EXT5, only bits 2
through 9 are used by the A/D (Figure 37). Bits 0 and 1 are
padded with zeroes.
DSP Analog Data Registers
The D/A conversion is DSP driven by sending 10-bit data
to the EXT5 of the DSP. The six remaining bits of EXT5 are
not used (Figure 36).
2
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Reserved
10-Bit Data for D/A
(Write Only)
Reserved
Figure 35. EXT5 Register D/A Mode Definition
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Reserved
8-Bit Data FromA/D Converter
(Read Only)
Reserved
Figure 36. EXT5 Register A/D Mode Definition
The 16-bit field of EXT6 defines modes of both the A/D and
the D/A. The High Byte configures the D/A while the Low
Byte controls the A/D mode.
Analog Control Register (ACR)
The Analog Control register is mapped to register EXT6 of
the DSP (Table 17). This read/write register is accessible
by the DSP only.
Table 17. EXT6 Analog Control Register (ACR)
20.48
MHz
29.49
MHz*
Field
Position
Attrib
Value
Label
MPX_DSP_INT0 f---------------
R/W
1
0
P26
Timer3
Reserved
Reserved
-edcba----------
------9---------
R
Return “0”
No effect
W
R
Return “1”
No effect
W
D/A_SamplingRate-------8--------
R/W
0
1
16 kHz
10 kHz
8.04 kHz
9.6 kHz
DS97TAD0100
P R E L I M I N A R Y
51
Z89175/Z89176
Voice Processing Controllers
Zilog
DSP REGISTERS DESCRIPTION (Continued)
Table 17. EXT6 Analog Control Register (ACR)
20.48
MHz
29.49
MHz*
Field
Position
Attrib
Value
Label
DSP_port (DSP1, --------76------
DSP0)
R/W
User-defined DSP
outputs
Enable A/D
----------5-----
R/W
1
0
A/D Enabled
A/D Disabled
ConversionDone -----------4----
StartConversion ------------3---
W
R
No effect
Done
1
0
Not Done
R/W
1
0
Start
Wait Timer
Reserved
-------------2--
R
Return “0”
No effect
W
20/29 MHz Select --------------1-
A/D_SamplingRate---------------0
R/W
R/W
1
0
29.49 MHz*
20.48 MHz†
1
0
16 kHz
8 kHz
16 kHz
9.6 kHz
Notes:
* Default value
† Optional feature
DSP IRQ0. This bit defines the source of the DSP IRQ0 in-
terrupt.
DSP0. DSP0 is a general-purpose output pin connected to
Bit 6. This bit has no special significance and can be used
to output data by writing to bit 6.
D/A_Sampling Rate. This field defines the sampling rate
of the D/A output. It changes the period to Timer3 interrupt
and the maximum possible accuracy of the D/A Sampling
Rate (Table 18).
Table 18. D/A Data Accuracy
D/A_Sampling Rate
Bit 8
Sampling Rate
20.48 MHz
29.49 MHz
0
1
16 kHz
10 kHz
8.04 kHz
9.6 kHz
52
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
DSP1. DSP1 is a general-purpose output pin connected to
Bit 7. This bit has no special significance and can be used
to output data by writing to bit 7.
input data is converted upon successive Timer2 time-outs.
A hardware reset forces this bit to 1.
A/D_Sampling Rate. This field defines the sampling rate
of the A/D. It changes the period of Timer2 interrupt (Table
19).
2
Enable A/D. Writing a 0 to this location disables the A/D
converter, a 1 will enable it. A hardware reset forces this
bit to 0.
Table 19. A/D Sampling Rate
Conversion Done. This Read-Only flag indicates that the
A/D conversion is complete. Upon reading EXT5 (A/D da-
ta), the Conversion Done flag is cleared.
A/D_Sampling Rate
Bit 0
Sampling Rate
20.48 MHz
29.49 MHz
1
0
16 kHz
8 kHz
16 kHz
9.6 kHz
Start A/D Conversion. Writing a 1 to this location immedi-
ately starts one conversion cycle. If this bit is reset to 0 the
DSP TIMERS
Timer2 is a free running counter that divides the XTAL fre-
quency (20.48 MHz) to support different sampling rates for
the A/D converter. The sampling rate is defined by the An-
alog Control Register. Upon reaching the end of a count,
the timer generates an interrupt request to the DSP.
Analogous to Timer2, Timer3 generates the different sam-
pling rates for the D/A converter. Timer3 also generates an
interrupt request to the DSP upon reaching its final count
value (Figure 37).
Timer2
A/D
D/A
8, 16 kHz
OSC
20.48 MHz
Timer3
16, 10 kHz
Timer2
A/D
D/A
16, 9.6 kHz
USC
29.49 MHz
Timer3
8.04, 9.6 kHz
Figure 37. Timer2 and Timer3
DS97TAD0100
P R E L I M I N A R Y
53
Z89175/Z89176
Voice Processing Controllers
Zilog
slot of each of the 32 groups represents Low_Val, while
High_Val is represented by the remaining 31 time slots in
each group.
Pulse Width Modulator (PWM)
The PWM supports two different sampling rates (10 and 16
kHz), according to the settings of bit 8 of the ACR. The out-
put of the PWM can be assigned to logic 1 only during the
active region (which is 4/5 of the output signal period). The
output will be at logic 0 for the rest of the time. An excep-
tion occurs in 10 kHz PWM, where the active region covers
the whole output signal period (Figure 39). The active re-
gion is divided into 1024 time slots. In each of these time
slots, the output can be set to logic 1 or logic 0.
For example, a value of %13a is loaded into PWM data
register EXT 5:
%13a = 01 0011 1010B = 314
High_Val = 01001B = 9
Low_Val = 11010B = 26
In order to increase the effective sampling rate, the PWM
employs a special technique of distributing the “logic 1” pe-
riod over the active region.
26 out of 32 groups will then have their first slots set to log-
ic 1. The remaining one slot in each group has nine time
slots set to logic 1.
The 10-bit PWM data is divided into two parts: the upper
five bits (High_Val) and the lower five bits (Low_Val). The
1024 time slots in the active region are divided into 32
equal groups, with 32 time slots in each group. The first
For 10 kHz PWM, the effective output frequency is 10K x
32 = 320 kHz. Figure 40 illustrates the waveform by using
a 6-bit PWM data (3-bit High_Val and 3-bit Low_Val).
250 µs
10 kHz
16 kHz
100 µs
Figure 38. PWM Waveform (shaded area shows the active region)
54
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
2
Figure 39. PWM Waveform of the Active Region
(for a 6-bit PWM data)
DS97TAD0100
P R E L I M I N A R Y
55
Z89175/Z89176
Voice Processing Controllers
Zilog
A/D CONVERTER (ADC)
roed before starting the conversion time depending on the
external clock frequency and the selection of the A/D sam-
pling rate (Figure 40). The sampling rates are 10 or 16 kHz
(XTAL = 20.48 MHz) in order to provide oversampling. The
rates are software controlled by the ACR (DSP External
Register 6). Timer2 supports the ADC. The maximum con-
version time is 2 µs.
Analog to Digital Converter
The A/D converter is an 8-bit half flash converter which
uses two reference resistor ladders for its upper four bits
(MSBs) and lower four bits (LSBs) conversion (Figure 41).
Two reference voltage pins, VREF+ (High) and VREF-
(Low), are provided for external reference voltage sup-
plies. During the sampling period, the converter is auto-ze-
AN IN
–
4-Bit
Flash
4-Bit
Flash
4-Bit
DAC
+
Auto Zero
Auto Zero m
4 MSB
4 LSB
Sample
Latch 4 MSB
Latch 4 LSB
Bits 9-2 Register 12 of DSP
Figure 40. A/D Converter
Conversion begins by writing to the appropriate bit in the
Analog Control Register (ACR). The start commands are
implemented in such a way as to begin a conversion at any
time. If a conversion is in progress and a new start com-
mand is received, then the conversion in progress is abort-
ed and a new conversion initiated. This allows the pro-
grammed values to be changed without affecting a
conversion in progress. The new values take effect only af-
ter a new start command is received.
The ADC can be disabled (for low power) or enabled by an
analog Control Register bit.
Though the ADC functions for a smaller input voltage and
voltage reference, the noise and offsets remain constant
over the specified electrical range. The errors of the con-
verter will increase and the conversion time can also take
slightly longer due to smaller input signals.
56
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
1
2
3
4
5
6
7
8
9
10
11
26
27
28
29
30
31
32
1
SCLK
2
P32
Input Sample
A/D Result
DSP INT
DSP Write
Notes:
1. SCLK = 10 MHz (XTAL =
20.48 MHz)
Figure 41. ADC Timing Diagram
Figure 42 shows the input circuit of the ADC. When con-
version starts, the analog input voltage from the input is
connected to the MSB and LSB flash converter inputs as
shown in the Input Impedance CKT diagram. Shunting 31
parallel internal resistances of the analog switches and si-
multaneously charging 31 parallel 1 pF capacitors is equiv-
alent to a 400 Ohms input impedance in parallel with a 31
pF capacitor. Other input stray capacitance adds about 10
pF to the input load. Input source resistances up to 2 kO-
hms can be used under normal operating conditions with-
out any degradation of the input settling time. For larger in-
put source resistance, longer conversion cycle times can
be required to compensate the input settling time problem.
V
is set using the V
+ pin.
REF
REF
CMOS Switch
on Resistance
2 - 5 k Ω
V Ref
C .5 pF
C .5 pF
C .5 pF
R Source
31 CMOS Digital
Comparators
V Ref
C Parasitic
V Ref
Figure 42. Input Impedance of ADC
DS97TAD0100
P R E L I M I N A R Y
57
Z89175/Z89176
Voice Processing Controllers
Zilog
®
Z8 EXPANDED REGISTER FILE REGISTERS
Expanded Register Bank B
(B) 04
D7 D6 D5 D4 D3 D2 D1 D0
(B) 00
D7 D6 D5 D4 D3 D2 D1 D0
DSP EXT2,
Bits D15-D8
DSP EXT0,
Bits D15-D8
Figure 47. Outgoing Register to DSP EXT2
(High Byte)
Figure 43. Outgoing Register to DSP EXT0
(High Byte) (B) 00H [Read/Write]
(B) 04H [Read/Write]
(B) 05
(B) 01
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
DSP EXT2,
Bits D7-D0
DSP EXT0,
Bits D7-D0
Figure 48. Outgoing Register to DSP EXT2
(Low Byte)
Figure 44. Outgoing Register to DSP EXT0
(Low Byte)
(B) 05H [Read/Write]
(B) 01H [Read/Write]
(B) 06
(B) 02
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
DSP EXT3,
Bits D15-D8
DSP EXT1,
Bits D15-D8
Figure 49. Outgoing Register to DSP EXT3
(High Byte)
Figure 45. Outgoing Register to DSP EXT1
(High Byte)
(B) 06H [Read/Write]
(B) 02H [Read/Write]
(B) 03
D7 D6 D5 D4 D3 D2 D1 D0
DSP EXT1,
Bits D7-D0
Figure 46. Outgoing Register to DSP EXT1
(Low Byte)
(B) 03H [Read/Write]
58
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
(B) 0B
D7 D6 D5 D4 D3 D2 D1 D0
(B) 07
D7 D6 D5 D4 D3 D2 D1 D0
2
DSP EXT1,
Bits D7-D0
DSP EXT3,
Bits D7-D0
Figure 54. Incoming Register from DSP EXT1
(Low Byte)
Figure 50. Outgoing Register to DSP EXT3
(Low Byte)
(B) 0BH [Read-Only]
(B) 07H [Read/Write]
(B) 08
(B) 0C
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
DSP EXT0,
Bits D15-D8
DSP EXT2,
Bits D15-D8
Figure 51. Incoming Register from DSP EXT0
(High Byte)
Figure 55. Incoming Register from DSP EXT2
(High Byte)
(B) 08H [Read-Only]
(B) 0CH [Read-Only]
(B) 09
(B) 0D
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
DSP EXT0,
Bits D7-D0
DSP EXT2,
Bits D7-D0
Figure 52. Incoming Register from DSP EXT0
(Low Byte)
Figure 56. Incoming Register from DSP EXT2
(Low Byte)
(B) 09H [Read-Only]
(B) 0DH [Read-Only]
(B) 0A
(B) 0E
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
DSP EXT1,
Bits D15-D8
DSP EXT3,
Bits D15-D8
Figure 53. Incoming Register from DSP EXT1
(High Byte)
Figure 57. Incoming Register from DSP EXT3
(High Byte)
(B) 0AH [Read-Only]
(B) 0EH [Read-Only]
DS97TAD0100
P R E L I M I N A R Y
59
Z89175/Z89176
Voice Processing Controllers
Zilog
®
Z8 EXPANDED REGISTER FILE REGISTERS (Continued)
(B) 0F
P5D (FH) 04H
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
DSP EXT3,
Bits D7-D0
Data
Figure 58. Incoming Register from DSP EXT3
(Low Byte)
Figure 62. Port 5 Data Register
(F) 04H [Read/Write]
(B) 0FH [Read-Only]
Expanded Register Bank F
P5M (FH) 05H
D7 D6 D5 D4 D3 D2 D1 D0
PCON (F) %00
P50-P57 I/O Definition
0 Defines Bit as Output
1 Defines Bit as Input*
D7 D6 D5 D4 D3 D2 D1 D0
Returns "FF" Upon Read
* Default setting after Reset
R Always "1"
W 0 P34,P37 Standard output
1 P34,P37 Comparator output
R
Always "1"
W No effect
Figure 63. Port 5 Mode Register
(F) 05H [Write-Only]
Note: Reset condition is 11111110
Figure 59. Port Configuration Register (PCON)
(F) 00H [Write-Only]
P45M (FH) 06H
(Write only)
D7 D6 D5 D4 D3 D2 D1 D0
P4D (FH) 02H
Port 4 Configuration Bit
0 Open-Drain
1 Push-pull
D7 D6 D5 D4 D3 D2 D1 D0
No effect
Data
Port 5 Configuration Bit
0 Open-Drain
1 Push-pull
No effect
Figure 60. Port 4 Data Register
(F) 02H [Read/Write]
Figure 64. Port 4 and 5 Configuration Register
(F) 06H [Write-Only]
P4M (FH) 03H
D7 D6 D5 D4 D3 D2 D1 D0
P40-P47 I/O Definition
0 Defines Bit as Output
1 Defines Bit as Input
Returns "FF" Upon Read
Figure 61. Port 4 Mode Register
(F) 03H [Write-Only]
60
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
SMR (FH) 0BH
2
D7 D6 D5 D4 D3 D2 D1 D0
W 0 SCLK/TCLK not divided by 16†
1 SCLK/TCLK divided by 16
R Always "1"
Reserved
W 000 POR only*
001 No effect
010 P31
011 P32
100 P33
101 Half second timeout from
33 kHz ext. osc.
110 P2 NOR 0-3
111 P2 NOR 0-7
R
Always "1"
W Stop Delay
0 OFF
1 ON*
R Always "1"
W 0 Low Stop Recovery Level*
1 High Stop Recovery Level
R Always "1"
W No effect
R 0 POR*
* Default Setting After Reset
† Reset After Stop-Mode Recovery
1 Stop-Mode Recovery
Figure 65. Stop-Mode Recovery Register (SMR)
(F) 0BH [Read/Write]
DS97TAD0100
P R E L I M I N A R Y
61
Z89175/Z89176
Voice Processing Controllers
Zilog
®
Z8 EXPANDED REGISTER FILE REGISTERS (Continued)
Table 20. DSP Control Register (F) 0CH [Read/Write]
Field
DSPCON (F) 0CH
Z8_SCLK
Position
76------
Attributes
Value
Label
R/W
00
01
1x
OSC/8
OSC/4
OSC/2
DSP_Reset
--5-----
R
Return “0”
No effect
W
0
1
Reset DSP
Halt_DSP
Run_DSP
DSP_Run
Reserved
---4----
----32--
R/W
0
1
xx
Return “0”
No effect
IntFeedback
------1-
-------0
R
FB_DSP_INT2
Set DSP_INT2
No effect
W
1
0
R
FB_Z8_IRQ3
Clear IRQ3
No effect
W
1
0
WDTMR (F) 0F
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC EXTERNAL CLOCK
00
01*
10
11
5 ms
15 ms
25 ms
100 ms
256 Tpc
512 Tpc
1024 Tpc
4096 Tpc
WDT During HALT
0 OFF
1 ON*
WDT During STOP
0 OFF
1 ON*
XTAL1/INT RC Select for WDT
0 On-Board RC
1 XTAL
W No effect
R Always "1"
* Default setting after RESET
Figure 66. Watch-Dog Timer Mode Register
(F) 0FH [Read/Write]
62
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
®
Z8 CONTROL REGISTERS
2
R243 PRE1
D7 D6 D5 D4 D3 D2 D1 D0
R240
D7 D6 D5 D4 D3 D2 D1 D0
Count Mode
0
1
T1 Single Pass
T1 Modulo N
RESERVED
Clock Source
1
0
T1Internal
T1External Timing Input
(TIN) Mode
Figure 67. Reserved (F0H)
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
R241 TMR
D7 D6 D5 D4 D3 D2 D1 D0
Figure 70. Prescaler 1 Register
(F3H:Write-Only)
0
1
No Function
Load T0
0
1
Disable T0 Count
Enable T0 Count
R244 T0
D7 D6 D5 D4 D3 D2 D1 D0
0
1
No Function
Load T1
0
1
Disable T1 Count
Enable T1 Count
T0 Low Byte Initial Value
(When Written)
TIN Modes
00 External Clock Input
01 Gate Input
10 Trigger Input
(Non-retriggerable)
11 Trigger Input
(Retriggerable)
T0 Low Byte Current Value
(When Read)
TOUT Modes
00 Not Used
01 T0 Out
10 T1 Out
Figure 71. Counter/Timer 0 Register
(F4H: Read/Write)
11 Internal Clock Out (P36)
R243 PRE1
D7 D6 D5 D4 D3 D2 D1 D0
Figure 68. Timer Mode Register
(F1H: Read/Write)
Count Mode
0
1
T1 Single Pass
T1 Modulo N
R242 T1
D7 D6 D5 D4 D3 D2 D1 D0
Clock Source
1
0
T1Internal
T1External Timing Input
(TIN) Mode
T1 Low Byte Initial Value
(When Written)
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
T1 Low Byte Current Value
(When Read)
Figure 72. Prescaler 0 Register
(F5H:Write-Only)
Figure 69. Counter/Timer 1 Register
(F2H: Read/Write)
DS97TAD0100
P R E L I M I N A R Y
63
Z89175/Z89176
Voice Processing Controllers
Zilog
®
Z8 CONTROL REGISTERS (Continued)
R248 P01M
R246 P2M
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
P00 - P03 Mode
00 Output
01 Input *
1X A11 - A8
P20 - P27 I/O Definition
0
Defines Bit as Output
1
Defines Bit as Input *
Stack Selection
* Default Setting After Reset
0
External
1
Internal *
P10 - P17 Mode
00 Byte Output
01 Byte Input *
10 AD7 - AD0
Figure 73. Port 2 Mode Register
(F6H:Write-Only)
11 High-ImpedanceAD7 - AD0,
/AS, /DS, /R//W, A11 - A8,
A15 - A12, If Selected
R247 P3M
D7 D6 D5 D4 D3 D2 D1 D0
External Memory Timing
0
1
Normal *
Extended
P04 - P07 Mode
00 Output
01 Input *
1X A15 - A12
0
1
Port 2 Pull-Ups Open Drain *
Port 2 Pull-UpsActive
* Default SettingAfter Reset
0
1
P31, P32 Digital Mode *
P31, P32Analog Mode
0
1
P32 = Input *
P35 = Output *
P32 = /DAV0/RDY0
P35 = RDY0//DAV0
Figure 75. Port 0 Mode Register
(F8H:Write-Only)
00 P33 = Input *
P34 = Output *
01 P33 = Input
P34 = /DM
10 P33 = Input
P34 = /DM
11 P33 = /DAV1/RDY1
P34 = RDY1//DAV1
R249 IPR
D7 D6 D5 D4 D3 D2 D1 D0
0
1
P31 = Input (TIN) *
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
P36 = Output (TOUT) *
P31 = /DAV2/RDY2
P36 = RDY2//DAV2
0
P30 = Input
P37 = Output
Reserved
* Default SettingAfter Reset
IRQ1, IRQ4 Priority (Group C)
0
1
IRQ1 > IRQ4
IRQ4 > IRQ1
IRQ0, IRQ2 Priority (Group B)
Figure 74. Port 3 Mode Register
(F7H:Write-Only)
0
1
IRQ2 > IRQ0
IRQ0 > IRQ2
IRQ3, IRQ5 Priority (GroupA)
0
1
IRQ5 > IRQ3
IRQ3 > IRQ5
Reserved
Figure 76. Interrupt Priority Register
(F9H:Write-Only)
64
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
R250 IRQ
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
2
Expanded Register File Bank
Working Register Group
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = DSP
IRQ4 = T0
IRQ5 = T1
Figure 80. Register Pointer
(FDH: Read/Write)
Inter Edge
P31 ↓ P32 ↓ = 00
P31 ↓ P32 ↑ = 01
P31 ↑ P32 ↓ = 10
P31 ↑↓ P32 ↑↓ = 11
R254 SPH
D7 D6 D5 D4 D3 D2 D1 D0
Figure 77. Interrupt Request Register
(FAH: Read/Write)
Stack Pointer Upper
Byte (SP8 - SP15)
R251 IMR
D7 D6 D5 D4 D3 D2 D1 D0
Figure 81. Stack Pointer High
(FEH: Read/Write)
1
Enables IRQ0-IRQ5
(D0 = IRQ0)
R255 SPL
D7 D6 D5 D4 D3 D2 D1 D0
1
1
Enables RAM Protect
Enables Interrupts
Stack Pointer Lower
Byte (SP0 - SP7)
Figure 78. Interrupt Mask Register
(FBH: Read/Write)
Figure 82. Stack Pointer Low
(FFH: Read/Write)
R252 FLAGS
D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
Figure 79. Flag Register
(FCH: Read/Write)
DS97TAD0100
P R E L I M I N A R Y
65
Z89175/Z89176
Voice Processing Controllers
Zilog
PACKAGE INFORMATION
Figure 83. 100-Pin QFP Package Diagram
66
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
2
Figure 84. 100-Pin VQFP Package Diagram
DS97TAD0100
P R E L I M I N A R Y
67
Z89175/Z89176
Voice Processing Controllers
Zilog
ORDERING INFORMATION
Z89175 (20 MHz)
Z89175 (29 MHz)
100-Pin QFP
100-Pin VQFP
100-Pin QFP
100-Pin VQFP
Z8917520FSC
Z8917520ASC
Z8917529FSC
Z8917529ASC
Z89176 (20 MHz)
Z89176 (29 MHz)
100-Pin QFP
100-Pin VQFP
100-Pin QFP
100-Pin VQFP
Z8917620FSC
Z8917620ASC
Z8917629FSC
Z8917629ASC
For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired.
Speeds
20 = 20.48 MHz
29 = 29.49 MHz
Codes
Packages
F = Quad Flatpack (QFP)
A = Very Small Quad Flatpack (VQFP)
Environmental
C = Plastic Standard
Temperature
S = 0°C to + 70°C
Example:
Z 89175 20 F S C
is a Z89175, 20.48 MHz, QFP, 0°C to +70°C, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
68
P R E L I M I N A R Y
DS97TAD0100
Z89175/Z89176
Voice Processing Controllers
Zilog
Pre-Characterization Product:
The product represented by this CPS is newly introduced
and Zilog has not completed the full characterization of the
product. The CPS states what Zilog knows about this
product at this time, but additional features or non-
conformance with some aspects of the CPS may be found,
either by Zilog or its customers in the course of further
application and characterization work. In addition, Zilog
cautions that delivery may be uncertain at times, due to
start-up yield issues.
2
Low Margin:
Customer is advised that this product does not meet
Zilog's internal guardbanded test policies for the
specification requested and is supplied on an exception
basis. Customer is cautioned that delivery may be
uncertain and that, in addition to all other limitations on
Zilog liability stated on the front and back of the
acknowledgement, Zilog makes no claim as to quality and
reliability under the CPS. The product remains subject to
standard warranty for replacement due to defects in
materials and workmanship.
© 1997 by Zilog, Inc. All rights reserved. No part of this
document may be copied or reproduced in any form or by
any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change
without notice. Devices sold by Zilog, Inc. are covered by
warranty and patent indemnification provisions appearing
in Zilog, Inc. Terms and Conditions of Sale only.
Zilog, Inc. shall not be responsible for any errors that may
appear in this document. Zilog, Inc. makes no commitment
to update or keep current the information contained in this
document.
Zilog’s products are not authorized for use as critical
components in life support devices or systems unless a
specific written agreement pertaining to such intended use
is executed between the customer and Zilog prior to use.
Life support devices or systems are those which are
intended for surgical implantation into the body, or which
sustains life whose failure to perform, when properly used
in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in
significant injury to the user.
ZILOG, INC. MAKES NO WARRANTY, EXPRESS,
STATUTORY, IMPLIED OR BY DESCRIPTION,
REGARDING THE INFORMATION SET FORTH HEREIN
OR REGARDING THE FREEDOM OF THE DESCRIBED
DEVICES
FROM
INTELLECTUAL
PROPERTY
INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY
OF MERCHANTABILITY OR FITNESS FOR ANY
PURPOSE.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
FAX 408 370-8056
Internet: http://www.zilog.com
DS97TAD0100
P R E L I M I N A R Y
69
Z89175/Z89176
Voice Processing Controllers
Zilog
70
P R E L I M I N A R Y
DS97TAD0100
相关型号:
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