Z8F2480PH020EC [IXYS]
IC 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDIP20, PLASTIC, DIP-20, Microcontroller;
| 型号： | Z8F2480PH020EC |
| 厂家： | 
IXYS CORPORATION |
| 描述： | IC 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDIP20, PLASTIC, DIP-20, Microcontroller 微控制器 光电二极管 |
| 文件： | 总409页 (文件大小：6651K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Z8 Encore! XP®F1680 Series
Advance Product Specification
i
High-Performance 8-Bit Microcontrollers
Z8 Encore! XP®F1680
Series
Advance Product Specification
PS025001-1105
P R E L I M I N A R Y
ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com
PS025001-1105
P R E L I M I N A R Y
Z8 Encore! XP®F1680 Series
Advance Product Specification
ii
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532 Race Street
San Jose, CA 95126
Telephone: 408.558.8500
Fax: 408.558.8300
www.ZiLOG.com
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products and/or service names mentioned herein may be trademarks of the companies with which
they are associated.
©2005 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded.
ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF
ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS
DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered
by warranty and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions
of Sale. ZiLOG, Inc. makes no warranty of merchantability or fitness for any purpose Except with the
express written approval of ZiLOG, use of information, devices, or technology as critical components
of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this
document under any intellectual property rights.
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Advance Product Specification
iii
Revision History
Each instance in the table reflects a change to this document from its previous
revision. To see more detail, click the appropriate link in the table.
Revision History of this Document
Revision
Level
Date
Oct 2005 01
Description
Original Issue
All
PS025001-1105
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Advance Product Specification
iv
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviii
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
CPU and Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
eZ8 CPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Non-Volatile Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Internal Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Secondary Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
10-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Enhanced SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
UART with LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Master/Slave I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Multi-channel Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Available Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Flash Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reset, STOP Mode Recovery and Low Voltage Detection . . . . . . . . . . . . . . . . 30
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Watch-Dog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
External Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
External Reset Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
On-Chip Debugger Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STOP Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
STOP Mode Recovery Using Watch-Dog Timer Time-Out . . . . . . . . . . . . . 38
STOP Mode Recovery Using Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . 39
STOP Mode Recovery Using Comparator Interrupt . . . . . . . . . . . . . . . . . . 39
STOP Mode Recovery Using a GPIO Port Pin Transition . . . . . . . . . . . . . . 39
STOP Mode Recovery Using the External RESET Pin . . . . . . . . . . . . . . . . 39
Low Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Reset Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Peripheral-Level Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Power Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
GPIO Port Availability By Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
GPIO Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Direct LED Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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Shared Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Crystal Oscillator Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
32KHz Secondary Oscillator Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5V Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
External Clock Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
GPIO Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Port A–E Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Port A–E Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Port A–E Data Direction Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Port A-E Alternate Function Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . 61
Port A–E Input Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Port A–E Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
LED Drive Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
LED Drive Level High Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LED Drive Level Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Interrupt Vector Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Master Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Interrupt Vectors and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Software Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Interrupt Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Interrupt Request 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Interrupt Request 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Interrupt Request 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
IRQ0 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 75
IRQ1 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 76
IRQ2 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Interrupt Edge Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Shared Interrupt Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
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Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Timer Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Reading the Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Timer Output Signal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Timer Noise Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Timer 0-2 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Timer Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . 103
Timer 0-2 PWM0 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . 104
Timer 0-2 PWM1 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . 106
Timer 0-2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Timer 0-2 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Timer 0-2 Noise Filter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Multi-Channel Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Multi-Channel Timer Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Multi-Channel Timer Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Multi-Channel Timer Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Multi-Channel Timer Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Count Modulo Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Count Up/Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Capture/Compare Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
One-Shot Compare Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Continuous Compare Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
PWM Output Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Capture Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Multi-Channel Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Capture/Compare Channel Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Operation in HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Operation in STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Power Reduction during operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Multi-Channel Timer Applications Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 120
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Advance Product Specification
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Multi-Channel Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . 122
Multi-Channel Timer Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Multi-Channel Timer High and Low Byte Registers . . . . . . . . . . . . . . . . . . 124
MCT Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . 124
Multi-Channel Timer Control 0, Control1 Registers . . . . . . . . . . . . . . . . . . 127
Multichannel Timer Channel Status 0 and Status 1 Registers . . . . . . . . . 129
Multi-Channel Timer Channel-y Control Registers. . . . . . . . . . . . . . . . . . . 130
One-Shot operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Continuous Compare operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
PWM Output operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Capture operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Multi-Channel Timer Channel-y High and Low Byte Registers . . . . . . . . . 133
Watch-Dog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Watch-Dog Timer Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Watch-Dog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Watch-Dog Timer Reload Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . 136
Watch-Dog Timer Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Watch-Dog Timer Reload High and Low Byte Registers . . . . . . . . . . . . . . 137
LIN-UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Data Format for Standard UART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Transmitting Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . 140
Transmitting Data Using the Interrupt-Driven Method . . . . . . . . . . . . . . . . 141
Receiving Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . 142
Receiving Data Using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . 143
Clear To Send Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
External Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
LIN-UART Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Multiprocessor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
LIN Protocol Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
LIN-UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
LIN-UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Noise Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
LIN-UART Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
LIN-UART Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
LIN-UART Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
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LIN-UART Status 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
LIN-UART Mode Select and Status Register . . . . . . . . . . . . . . . . . . . . . . 161
LIN-UART Control 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
LIN-UART Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
LIN-UART Address Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
LIN-UART Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . 170
Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Transmitting IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Receiving IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Infrared Encoder/Decoder Control Register Definitions . . . . . . . . . . . . . . . . . 178
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
ADC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
ADC Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Reference Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Internal Voltage Reference Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Calibration and Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
ADC Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
ADC Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
ADC Raw Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
ADC Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
ADC Data Low Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Sample Settling Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Sample Time Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
ADC Clock Prescale Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Transimpedance Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Enhanced Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
ESPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Master-In, Slave-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Master-Out, Slave-In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Slave Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
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ESPI Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Comparison with Basic SPI Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
ESPI Clock Phase and Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Slave Select Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
SPI Protocol Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
ESPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
ESPI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
ESPI Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
ESPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
ESPI Transmit Data Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . 207
ESPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
ESPI Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
ESPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
ESPI State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
ESPI Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . 214
I2C Master/Slave Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
I2C Master/Slave Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Comparison with the Master Mode Only I2C Controller . . . . . . . . . . . . . . 218
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
SDA and SCL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
I2C Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Software Control of I2C Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Master Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Slave Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
I2C Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
I2C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
I2C Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
I2C Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
I2C Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . 244
I2C State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
I2C Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
I2C Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
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Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Comparator Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Comparator 0 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Comparator 1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Flash Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Flash Operation Timing Using the Flash Frequency Registers . . . . . . . . . 263
Flash Code Protection Against External Access . . . . . . . . . . . . . . . . . . . . 263
Flash Code Protection Against Accidental Program and Erasure . . . . . . . 263
Byte Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Flash Controller Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Flash Controller Behavior in Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . 266
Flash Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Flash Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Flash Sector Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Flash Frequency High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . 269
Flash Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Option Bit Configuration By Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Option Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Flash Option Bit Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 273
Trim Bit Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Trim Bit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Flash Option Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Flash Program Memory Address 0000H . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Flash Program Memory Address 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Trim Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Trim Bit Address 0000H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
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Trim Bit Address 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Trim Bit Address 0002H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Trim Bit Address 0003H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Trim Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
ZiLOG Calibration Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Watchdog Timer Calibration Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
OCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
DEBUG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
OCD Auto-Baud Detector/Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
OCD Serial Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Runtime Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
On-Chip Debugger Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . 290
OCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
OCD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Non-Volatile Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
NVDS Code Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Power Failure Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Optimizing NVDS Memory Usage for Execution Speed . . . . . . . . . . . . . . 294
Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
System Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Clock Failure Detection and Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Peripheral Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Oscillator Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Oscillator Control0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Oscillator Control1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
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Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Main Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Main Oscillator Operation with an External RC Network . . . . . . . . . . . . . . . . . 304
Internal Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
eZ8 CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Assembly Language Programming Introduction . . . . . . . . . . . . . . . . . . . . . . . 308
Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
eZ8 CPU Instruction Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
eZ8 CPU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Opcode Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
On-Chip Peripheral AC and DC Electrical Characteristics . . . . . . . . . . . . . . . 334
General Purpose I/O Port Input Data Sample Timing . . . . . . . . . . . . . . . . 340
General Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . 342
On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
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List of Figures
Figure 1. Z8 Encore! XP® F1680 Series Block Diagram . . . . . . . . . . . . . . . . . . 4
Figure 2. Z8F2480, Z8F1680, Z8F0880, and Z8F0480 in 20-Pin SOIC, SSOP or
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3. Z8F2480, Z8F1680, Z8F0880, and Z8F0480 in 28-Pin SOIC, SSOP or
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Z8F2480, Z8F1680, Z8F0880, and Z8F0480 in 40-Pin Dual Inline Pack-
age (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Z8F2480, Z8F1680, Z8F0880, and Z8F0480 in 44-Pin Plastic Leaded
Chip Carrier (PLCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Z8F2480, Z8F1680, Z8F0880, and Z8F0480 in 44-Pin Low-Profile Quad
Flat Package (LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Power-On Reset and VBO Reset Operation in the power on case . . 34
Figure 8. Power-On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 9. Voltage Brown-Out Reset Operation in the voltage brown out case . 36
Figure 10. GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 11. Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 12. Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 13. Noise Filter System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 14. Noise Filter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 15. Multi-Channel Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 16. Count Modulo Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 17. Count Up/Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 18. Count Up/Down Mode with PWM Channel Outputs and Dead-Band .
121
Figure 19. Count Max Mode with Channel Compare . . . . . . . . . . . . . . . . . . . 122
Figure 20. LIN-UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 21. LIN-UART Asynchronous Data Format without Parity . . . . . . . . . . 140
Figure 22. LIN-UART Asynchronous Data Format with Parity . . . . . . . . . . . . 140
Figure 23. LIN-UART Driver Enable Signal Timing with 1 Stop Bit and Parity 145
Figure 24. LIN-UART Asynchronous Multiprocessor Mode Data Format . . . . 146
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Figure 25. LIN-UART Receiver Interrupt Service Routine Flow . . . . . . . . . . . 153
Figure 26. Noise Filter System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 27. Noise Filter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 28. Infrared Data Communication System Block Diagram . . . . . . . . . 175
Figure 29. Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 30. IrDA Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 31. Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . . . . . 180
Figure 32. ADC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 33. ADC Convert Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 34. ESPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 35. ESPI Timing When PHASE is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 36. ESPI Timing When PHASE is 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 37. SPI mode (SSMD = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 38. Synchronous Frame Sync Pulse mode (SSMD = 10) . . . . . . . . . . 199
Figure 39. Synchronous Message Framing mode (SSMD = 11), Multiple Frames
200
Figure 40. ESPI Configured as an SPI Master in a Single Master, Single Slave Sys-
tem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 41. ESPI Configured as an SPI Master in a Single Master, Multiple Slave
System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 42. ESPI Configured as an SPI Slave . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 43. I2C Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 44. Data Transfer Format—Master Write Transaction with a 7-Bit Address
224
Figure 45. Data Transfer Format—Master Write Transaction with a 10-Bit Address
225
Figure 46. Data Transfer Format—Master Read Transaction with a 7-Bit Address
227
Figure 47. Data Transfer Format—Master Read Transaction with a 10-Bit Address
228
Figure 48. Data Transfer Format—Slave Receive Transaction with 7-Bit Address
231
Figure 49. Data Transfer Format—Slave Receive Transaction with 10-Bit Address
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233
Figure 50. Data Transfer Format—Slave Transmit Transaction with 7-bit Address
234
Figure 51. Data Transfer Format—Slave Transmit Transaction with 10-Bit Address
235
Figure 52. Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Figure 53. Flash Controller Operation Flow Chart . . . . . . . . . . . . . . . . . . . . . . 262
Figure 54. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 280
Figure 55. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface
(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Figure 56. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface
(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Figure 57. OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Figure 58. Recommended 20 MHz Crystal Oscillator Configuration . . . . . . . . 303
Figure 59. Connecting the On-Chip Oscillator to an External RC Network . . . 304
Figure 60. Typical RC Oscillator Frequency as a Function of the External Capaci-
tance with a 45KOhm Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Figure 61. Opcode Map Cell Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Figure 62. First Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Figure 63. Second Opcode Map after 1FH . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Figure 64. ICC Versus System Clock Frequency . . . . . . . . . . . . . . . . . . . . . . 332
Figure 65. Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Figure 66. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Figure 67. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Figure 68. UART Timing With CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Figure 69. UART Timing Without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Figure 70. 20-Pin Plastic Dual Inline Package (PDIP) . . . . . . . . . . . . . . . . . . 346
Figure 71. 20-Pin Small Outline Integrated Circuit Package (SOIC) . . . . . . . . 347
Figure 72. 20-Pin Small Shrink Outline Package (SSOP) . . . . . . . . . . . . . . . . 348
Figure 73. 28-Pin Plastic Dual Inline Package (PDIP) . . . . . . . . . . . . . . . . . . 349
Figure 74. 28-Pin Small Outline Integrated Circuit Package (SOIC) . . . . . . . . 350
Figure 75. 28-Pin Small Shrink Outline Package (SSOP) . . . . . . . . . . . . . . . . 351
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Figure 76. 40-Lead Plastic Dual-Inline Package (PDIP) . . . . . . . . . . . . . . . . . 351
Figure 77. 40-Lead Plastic Dual-Inline Package (PDIP) . . . . . . . . . . . . . . . . . 352
Figure 78. 44-Lead Low-Profile Quad Flat Package (LQFP) . . . . . . . . . . . . . 352
Figure 79. 44-Lead Plastic Lead Chip Carrier Package (PLCC) . . . . . . . . . . . 353
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Z8 Encore! XP®F1680 Series
Advance Product Specification
xviii
List of Tables
Z8 Encore! XP® F1680 Series Family Part Selection Guide . . . . . . . . . . . . . . . . 2
Z8 Encore! XP® F1680 Series Package Options. . . . . . . . . . . . . . . . . . . . . . . . . 9
Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pin Characteristics (20-, 28-, 40- and 44-pin Devices). . . . . . . . . . . . . . . . . . . . 17
Z8 Encore! XP® F1680 Series Program Memory Maps. . . . . . . . . . . . . . . . . . . 20
Z8 Encore! XP® F1680 Series Flash Memory Information Area Map . . . . . . . . 22
Register File Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reset and STOP Mode Recovery Characteristics and Latency. . . . . . . . . . . . . 31
Reset Sources and Resulting Reset Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STOP Mode Recovery Sources and Resulting Action . . . . . . . . . . . . . . . . . . . . 38
Reset Status Register (RSTSTAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power Control Register 0 (PWRCTL0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Port Availability by Device and Package Type. . . . . . . . . . . . . . . . . . . . . . . . . . 45
Port Alternate Function Mapping (20-Pin Parts). . . . . . . . . . . . . . . . . . . . . . . . . 49
Port Alternate Function Mapping (28-Pin Parts). . . . . . . . . . . . . . . . . . . . . . . . . 51
Port Alternate Function Mapping (40-/44-Pin Parts) . . . . . . . . . . . . . . . . . . . . . 54
GPIO Port Registers and Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Port A–E GPIO Address Registers (PxADDR). . . . . . . . . . . . . . . . . . . . . . . . . . 59
Port A–E Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Port A–E Data Direction Sub-Registers (PxDD). . . . . . . . . . . . . . . . . . . . . . . . . 61
Port A–E Alternate Function Sub-Registers (PxAF). . . . . . . . . . . . . . . . . . . . . . 62
Port A–E Output Control Sub-Registers (PxOC) . . . . . . . . . . . . . . . . . . . . . . . . 62
Port A–E High Drive Enable Sub-Registers (PxHDE) . . . . . . . . . . . . . . . . . . . . 63
Port A–E STOP Mode Recovery Source Enable Sub-Registers (PxSMRE) . . . 63
Port A–E Pull-Up Enable Sub-Registers (PxPUE) . . . . . . . . . . . . . . . . . . . . . . . 64
Port A–E Alternate Function Set 1 Sub-Registers (PxAFS1). . . . . . . . . . . . . . . 64
Port A–E Alternate Function Set 2 Sub-Registers (PxAFS2). . . . . . . . . . . . . . . 65
Port A–E Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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xix
Port A–E Output Data Register (PxOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
LED Drive Enable (LEDEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
LED Drive Level High Register (LEDLVLH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LED Drive Level Low Register (LEDLVLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Trap and Interrupt Vectors in Order of Priority . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
IRQ0 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
IRQ0 Enable Low Bit Register (IRQ0ENL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
IRQ1 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
IRQ1 Enable Low Bit Register (IRQ1ENL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
IRQ2 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
IRQ2 Enable High Bit Register (IRQ2ENH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
IRQ2 Enable Low Bit Register (IRQ2ENL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Interrupt Edge Select Register (IRQES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Shared Interrupt Select Register (IRQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Interrupt Control Register (IRQCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Triggered One-Shot Mode Initialization Example. . . . . . . . . . . . . . . . . . . . . . . . 85
Demodulation Mode Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Timer 0-2 High Byte Register (TxH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Timer 0-2 Low Byte Register (TxL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Timer 0-2 Reload High Byte Register (TxRH) . . . . . . . . . . . . . . . . . . . . . . . . . 104
Timer 0-2 Reload Low Byte Register (TxRL) . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Timer 0-2 PWM0 High Byte Register (TxPWM0H) . . . . . . . . . . . . . . . . . . . . . 105
Timer 0-2 PWM0 Low Byte Register (TxPWM0L) . . . . . . . . . . . . . . . . . . . . . . 105
Timer 0-2 PWM1 High Byte Register (TxPWM1H) . . . . . . . . . . . . . . . . . . . . . 106
Timer 0-2 PWM1 Low Byte Register (TxPWM1L) . . . . . . . . . . . . . . . . . . . . . . 106
PS025001-1105
P R E L I M I N A R Y
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Z8 Encore! XP®F1680 Series
Advance Product Specification
xx
Timer 0-2 Control 0 Register (TxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Timer 0-2 Control 1 Register (TxCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Timer 0-2 Control 2 Register (TxCTL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Timer 0-2 Status Register (TxSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Timer 0-2 Noise Filter Control Register (TxNFC). . . . . . . . . . . . . . . . . . . . . . . 113
Timer Count Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Multi-channel Timer Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
MCT High Byte Register (MCTH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
MCT Low Byte Register (MCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
MCT Reload High Byte Register (MCTRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
MCT Reload Low Byte Register (MCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
MCT Sub Address Register (MCTSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
MCT Sub Register x (MCTSRx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Multi-Channel Timer Control 0 Register (MCTCTL0). . . . . . . . . . . . . . . . . . . . 127
Multi-Channel Timer Control 1 Register (MCTCTL1). . . . . . . . . . . . . . . . . . . . 128
Multi-Channel Timer Channel Status 0 Register (MCTCHS0) . . . . . . . . . . . . . 129
Multi-Channel Timer Channel Status 1 Register (MCTCHS1) . . . . . . . . . . . . . 130
Multi-Channel Timer Channel-x Control Register (MCTCHyCTL) . . . . . . . . . . . 131
Multi-Channel Timer Channel-y High Byte Registers (MCTCHyH) . . . . . . . . . 133
Multi-Channel Timer Channel-y Low Byte Registers (MCTCHyL) . . . . . . . . . . 133
Watch-Dog Timer Approximate Time-Out Delays . . . . . . . . . . . . . . . . . . . . . . 135
Watch-Dog Timer Reload High Byte Register (WDTH = FF2h) . . . . . . . . . . . . 137
Watch-Dog Timer Reload Low Byte Register (WDTL = FF3h). . . . . . . . . . . . . 137
LIN-UART Transmit Data Register (U0TXD = F40h) . . . . . . . . . . . . . . . . . . . . 157
LIN-UART Receive Data Register (U0RXD = F40h) . . . . . . . . . . . . . . . . . . . . 157
LIN-UART Status 0 Register—Standard UART Mode (U0STAT0 = F41h) . . . 158
LIN-UART Status 0 Register—LIN Mode (U0STAT0 = F41h) . . . . . . . . . . . . . 159
LIN-UART Mode Select and Status Register (U0MDSTAT = F44h) . . . . . . . . 161
Mode Status Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
LIN-UART Control 0 Register (U0CTL0 = F42h) . . . . . . . . . . . . . . . . . . . . . . . 163
PS025001-1105
P R E L I M I N A R Y
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Z8 Encore! XP®F1680 Series
Advance Product Specification
xxi
Multiprocessor Control Register (U0CTL1 = F43h with MSEL = 000b) . . . . . . 165
Noise Filter Control Register (U0CTL1 = F43h with MSEL = 001b). . . . . . . . . 167
LIN Control Register (U0CTL1 = F43h with MSEL = 010b) . . . . . . . . . . . . . . . 168
LIN-UART Address Compare Register (U0ADDR = F45h) . . . . . . . . . . . . . . . 170
LIN-UART Baud Rate High Byte Register (U0BRH = F46h) . . . . . . . . . . . . . . 170
LIN-UART Baud Rate Low Byte Register (U0BRL = F47h) . . . . . . . . . . . . . . . 171
LIN-UART Baud Rates, 20.0 MHz System Clock . . . . . . . . . . . . . . . . . . . . . . 172
LIN-UART Baud Rates, 10.0MHz System Clock . . . . . . . . . . . . . . . . . . . . . . . 173
LIN-UART Baud Rates, 5.5296 MHz System Clock. . . . . . . . . . . . . . . . . . . . . 173
LIN-UART Baud Rates, 3.579545 MHz System Clock . . . . . . . . . . . . . . . . . . 173
LIN-UART Baud Rates, 1.8432 MHz System Clock . . . . . . . . . . . . . . . . . . . . 174
ADC Control Register 0 (ADCCT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
ADC Raw Data High Byte Register (ADCRD_H) . . . . . . . . . . . . . . . . . . . . . . . 184
ADC Data High Byte Register (ADCD_H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
ADC Data Low Bits Register (ADCD_L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Sample and Settling Time (ADCSST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Sample Hold Time (ADCST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
ADC Clock Prescale Register (ADCCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
ESPI Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
ESPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation . . . . . . 195
ESPI Data Register (ESPIDATA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
ESPI Transmit Data Command Register (ESPITDCR) . . . . . . . . . . . . . . . . . . 207
ESPI Control Register (ESPICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
ESPI Mode Register (ESPIMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
ESPI Status Register (ESPISTAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
ESPI State Register (ESPISTATE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
ESPISTATE values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
ESPI Baud Rate High Byte Register (ESPIBRH). . . . . . . . . . . . . . . . . . . . . . . 215
ESPI Baud Rate Low Byte Register (ESPIBRL) . . . . . . . . . . . . . . . . . . . . . . . 215
I2C Master/Slave Controller Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
PS025001-1105
P R E L I M I N A R Y
List of Tables
Z8 Encore! XP®F1680 Series
Advance Product Specification
xxii
I2C Data Register (I2CDATA = F50h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
I2C Interrupt Status Register (I2CSTAT = F51h) . . . . . . . . . . . . . . . . . . . . . . . 238
I2C Control Register (I2CTL = 52h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
I2C Control Register (I2CCTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
I2C Baud Rate High Byte Register (I2CBRH = 53h) . . . . . . . . . . . . . . . . . . . . 244
I2C Baud Rate Low Byte Register (I2CBRL = F54h) . . . . . . . . . . . . . . . . . . . . 244
I2C State Register (I2CSTATE = F55h)—Description when DIAG = 0 . . . . . . 245
I2C State Register((I2CSTATE = F55h)—Description when DIAG = 1 . . . . . . 247
I2C State Register (I2CSTATE)—Description when DIAG = 0 . . . . . . . . . . . . 248
I2C State Register (I2CSTATE)—Description when DIAG = 1 . . . . . . . . . . . . 249
I2CSTATE_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
I2CSTATE_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
I2C Mode Register (I2C Mode = F56h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
I2C Slave Address Register (I2CSLVAD = 57h) . . . . . . . . . . . . . . . . . . . . . . . 253
I2C Slave Address Register (I2CSLVAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Comparator 0 Control Register (CMP0CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Comparator 1 Control Register (CMP1CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Z8 Encore! XP® F1680 Series Flash Memory Configurations . . . . . . . . . . . . . 259
Flash Code Protection Using the Flash Option Bits . . . . . . . . . . . . . . . . . . . . . 264
Flash Control Register (FCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Flash Page Select Register (FPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Flash Sector Protect Register (FPROT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Flash Frequency High Byte Register (FFREQH) . . . . . . . . . . . . . . . . . . . . . . . 270
Flash Frequency Low Byte Register (FFREQL). . . . . . . . . . . . . . . . . . . . . . . . 270
Trim Bit Address Register (TRMADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Trim Bit Data Register (TRMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Trim Bit Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Flash Option Bits at Program Memory Address 0000H . . . . . . . . . . . . . . . . . . 274
Flash Options Bits at Program Memory Address 0001H . . . . . . . . . . . . . . . . . 275
PS025001-1105
P R E L I M I N A R Y
List of Tables
Z8 Encore! XP®F1680 Series
Advance Product Specification
xxiii
Trim Bit Address Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Trim Options Bits at Address 0000H (TTEMP0) . . . . . . . . . . . . . . . . . . . . . . . 276
Trim Option Bits at 0001H (TTEMP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Trim Option Bits at 0002H (TIPO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Trim Option Bits at Address 0003H (TLVD_VBO) . . . . . . . . . . . . . . . . . . . . . . 278
Watchdog Calibration High Byte at 007EH (WDTCALH) . . . . . . . . . . . . . . . . . 279
Watchdog Calibration Low Byte at 007FH (WDTCALL). . . . . . . . . . . . . . . . . . 279
OCD Baud-Rate Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
OCD Control Register (OCDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
OCD Status Register (OCDSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Write Status Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
NVDS Read Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Oscillator Configuration and Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Peripheral Clock Source and Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Oscillator Control0 Register (OSCCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Oscillator Control1 Register (OSCCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Recommended Crystal Oscillator Specifications. . . . . . . . . . . . . . . . . . . . . . . 304
Assembly Language Syntax Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Assembly Language Syntax Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Notational Shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Additional Symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Block Transfer Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
CPU Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Logical Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
PS025001-1105
P R E L I M I N A R Y
List of Tables
Z8 Encore! XP®F1680 Series
Advance Product Specification
xxiv
eZ8 CPU Instruction Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Opcode Map Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing . .
334
Flash Memory Electrical Characteristics and Timing . . . . . . . . . . . . . . . . . . . . 334
Watch-Dog Timer Electrical Characteristics and Timing . . . . . . . . . . . . . . . . . 335
Non Volatile Data Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Analog-to-Digital Converter Electrical Characteristics and Timing. . . . . . . . . . 336
Comparator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Temperature Sensor Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 337
Low Power Operational Amplifier Characteristics . . . . . . . . . . . . . . . . . . . . . . 338
IPO Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Low Voltage Detect Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 339
Crystal Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Low Power 32 KHz Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
GPIO Port Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
UART Timing With CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
UART Timing Without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
PS025001-1105
P R E L I M I N A R Y
List of Tables
Z8 Encore! XP® F1680 Series
Advance Product Specification
1
Overview
The Z8 Encore! XP® F1680 Series MCU family is based on ZiLOG’s advanced 8-bit eZ8
CPU core. Optimized for low power applications, the Z8 Encore! XP® F1680 Series sup-
ports 1.8 - 3.6V operation with extremely low active, halt and stop mode currents and an
assortment of speed and low power options. The rich peripheral set of the Z8 Encore! XP®
F1680 Series makes it suitable for a variety of applications including sensors, security sys-
tems, personal electronic devices, home appliances, and motor control.
Features
•
•
•
•
•
•
•
•
•
•
•
20MHz eZ8 CPU
4KB, 8KB, 16KB, or 24KB Flash memory with in-circuit programming capability
1KB or 2KB Data RAM
0.5KB or 1KB Program RAM that can be programmed as Data RAM
Up to 128B or 256B Non-Volatile Data Storage (NVDS)
17 to 39 I/O Pins depending upon package
Internal Precision Oscillator
External crystal oscillator
32KHz Low Power Secondary Oscillator for Timers
Two full duplex LIN UARTs
Infrared Data Association (IrDA)-compliant infrared encoder/decoders, integrated with
UART
•
•
•
•
•
•
•
•
•
Three enhanced 16-bit timers with capture, compare, and PWM capability
Optional multi-channel timer(44-pin packages only)
Watch-Dog Timer (WDT) with dedicated internal RC oscillator
On-Chip Debugger
Optional fast 8-channel, 10-bit Analog-to-Digital Converter (ADC)
Optional SPI Controller (28-, 40- and 44-pin packages only)
Master/Slave I2C Controller
On-Chip temperature sensor
Two On-Chip analog comparators (20-, 28-pin have only one)
PS025001-1105
P R E L I M I N A R Y
Overview
Z8 Encore! XP® F1680 Series
Advance Product Specification
2
•
•
•
•
•
•
•
•
On-Chip operational amplifier
Up to 20 vectored interrupts
Voltage Brown-out Protection (VBO)
Programmable Low Battery Detection (VLB)
Power-On Reset (POR)
1.8 to 3.6V operating voltage
Up to thirty-nine 5V-tolerant input pins
Ultra low power operation
–
–
–
Active Mode:
1 MHz, 1.8 V : 325 µA
4 MHz, 1.8 V : 1.2 mA
Halt Mode:
1 MHz, 1.8 V : 200 µA
4 MHz, 1.8 V : 400 µA
Stop Mode:
1.8 V, all peripherals disabled: 0.05 µA
1.8 V, WDT running: 1 µA
1.8 V, 32 KHz timers, WDT: 10 µA
•
•
20-, 28-, 40- and 44-pin packages
0° to +70°C and -40° to +105°C for operating temperature ranges
Part Selection Guide
Table 1 identifies the basic features and package styles available for each device within the
Z8 Encore! XP® F1680 Series product line.
®
Table 1. Z8 Encore! XP F1680 Series Family Part Selection Guide
Part
Number (KB)
Flash RAM Program EEPROM
ADC
I/O Inputs SPI I C UARTs
2
(B)
RAM (B)
(B)
Packages
Z8F2480
Z8F2481
24
24
2048
1024
-
17-37
7-8
0-1
1
1
1-2
20-, 28-, 40- and
44pins
2048
512
-
17-39
0
0-1
1-2
20-, 28-, 40- and
44pins
PS025001-1105
P R E L I M I N A R Y
Overview
Z8 Encore! XP® F1680 Series
Advance Product Specification
3
®
Table 1. Z8 Encore! XP F1680 Series Family Part Selection Guide (Continued)
Part
Number (KB)
Flash RAM Program EEPROM
ADC
I/O Inputs SPI I C UARTs
2
(B)
RAM (B)
(B)
Packages
Z8F1680
Z8F1681
Z8F0880
Z8F0881
Z8F0480
Z8F0481
16
16
8
2048
1024
256
17-37
17-39
17-37
17-39
17-37
17-39
7-8
0-1
0-1
0-1
0-1
0-1
0-1
1
1
1
1
1
1
1-2
1-2
1-2
1-2
1-2
1-2
20-, 28-, 40- and
44pins
2048
1024
1024
1024
1024
512
1024
512
256
128
128
128
128
0
20-, 28-, 40- and
44pins
7-8
0
20-, 28-, 40- and
44pins
8
20-, 28-, 40- and
44pins
4
1024
512
7-8
0
20-, 28-, 40- and
44pins
4
20-, 28-, 40- and
44pins
Block Diagram
Figure 1 illustrates the block diagram of the architecture of the Z8 Encore! XP® F1680
Series devices.
PS025001-1105
P R E L I M I N A R Y
Overview
Z8 Encore! XP® F1680 Series
Advance Product Specification
4
Secondary
Oscillator
System
Clock
Oscillator
Control
XTAL/RC
Oscillator
Internal
Precision
Oscillator
Low Power
RC Oscillator
On-Chip
Debugger
POR/VBO
& Reset
Controller
eZ8
CPU
Interrupt
Controller
WDT
Memory Busses
Register Bus
RAM
Controller
Flash
Controller
NVDS
Controller
2 Analog
Comparators
ADC
Enhanced
SPI
Multi-channel
Timer
3
2 LIN
UARTs
Timers
IrDA
Temperature
Sensor
Master/Slave
2
Flash
Memory
RAM
I C
GPIO
®
Figure 1. Z8 Encore! XP F1680 Series Block Diagram
PS025001-1105
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5
CPU and Peripheral Overview
eZ8 CPU Features
The eZ8 CPU, ZiLOG’s latest 8-bit Central Processing Unit (CPU), meets the continuing
demand for faster and more code-efficient microcontrollers. The eZ8 CPU executes a
superset of the original Z8® instruction set. The eZ8 CPU features include:
•
•
Direct register-to-register architecture allows each register to function as an
accumulator, improving execution time and decreasing the required program memory
Software stack allows much greater depth in sub-routine calls and interrupts than
hardware stacks
•
•
•
Compatible with existing Z8®code
Expanded internal Register File allows access of up to 4KB
New instructions improve execution efficiency for code developed using higher-level
programming languages, including C
•
•
Pipelined instruction fetch and execution
New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC,
LDCI, LEA, MULT, and SRL
•
•
•
•
New instructions support 12-bit linear addressing of the Register File
Up to 10 MIPS operation
C-Compiler friendly
2 to 9 clock cycles per instruction
For more information regarding the eZ8 CPU, refer to the eZ8 CPU User Manual avail-
able for download at www.zilog.com.
General Purpose I/O
The Z8 Encore! XP® F1680 Series features 17 to 39 port pins (Ports A–E) for general pur-
pose I/O (GPIO). The number of GPIO pins available is a function of package. Each pin is
individually programmable.
Flash Controller
The Flash Controller programs and erases Flash memory. The Flash Controller supports
protection against accidental program and erasure.
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Non-Volatile Data Storage
The Non-Volatile Data Storage (NVDS) uses a hybrid hardware/software scheme to
implement a byte programmable data memory, and is capable of over 100,000 write
cycles.
Internal Precision Oscillator
The Internal Precision Oscillator (IPO) is a trimmable clock source that requires no exter-
nal components. IPO frequency is user selectable as one of eight frequencies (11.0592
MHz - 43.2 KHz) and is available with factory-trimmed calibration data.
Crystal Oscillator
The crystal oscillator circuit provides highly accurate clock frequencies with the use of an
external crystal, ceramic resonator or RC network.
Secondary Oscillator
The secondary oscillator is a low power oscillator, which is optimized for use with a
32KHz watch crystal. It can be used as timer/counter clock source in active and stop
mode.
10-Bit Analog-to-Digital Converter
The optional Analog-to-Digital Converter (ADC) converts an analog input signal to a 10-
bit binary number. The ADC accepts inputs from eight different analog input pins in sin-
gle-ended mode.
Analog Comparator
The analog comparator compares the signal at an input pin with either an internal pro-
grammable voltage reference or a second-input pin. The comparator output can be used to
drive either an output pin or to generate an interrupt.
Temperature Sensor
The Temperature Sensor produces an analog output proportional to the device tempera-
ture. This signal can be sent to either the ADC or the analog comparator.
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Low Battery Detector
The Low Battery Detector is able to generate an interrupt when the supply voltage drops
below a user-programmable level.
Enhanced SPI
The enhanced SPI is a full duplex, buffered, synchronous character-oriented channel that
supports a four-wire interface.
UART with LIN
A full-duplex 9-bit UART provides serial, asynchronous communication and supports the
Local Interconnect Network (LIN) serial communications protocol. The UART communi-
cation is full-duplex and capable of handling asynchronous data transfers. The UART sup-
ports 8- and 9-bit data modes, selectable parity and an efficient bus transceiver Driver
Enable signal for controlling a multi-transceiver bus, such as RS-485. The LIN bus is a
cost-efficient, single-master, multiple-slave organization that supports speeds up to 20-
Kbits.
2
Master/Slave I C
The inter-integrated circuit (I2C) controller makes the Z8 Encore! XP® F1680 Series prod-
ucts compatible with the I2C protocol. The I2C controller consists of two bi-directional
bus lines, a serial data (SDA) line and a serial clock (SCL) line. It also supports Master,
Slave, and Multi-Master operations.
Timers
Three enhanced 16-bit reloadable timers can be used for timing/counting events or for
motor control operations. These timers provide a 16-bit programmable reload counter and
operate in One-Shot, Continuous, Gated, Capture, Capture Restart, Compare, Capture and
Compare, PWM Single Output, PWM Dual Output, Triggered One-Shot and Demodula-
tion modes.
Multi-channel Timer
The Multi-channel Timer has a 16-bit up/down counter and a Capture/Compare channel
array. This enables support of multiple synchronous Capture/Compare channels based on a
single timer.
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Interrupt Controller
The Z8 Encore! XP® F1680 Series products support up to 20 interrupts. These interrupts
consist of 8 internal peripheral interrupts and 12 general-purpose I/O pin interrupt sources.
The interrupts have 3 levels of programmable-interrupt priority.
Reset Controller
The Z8 Encore! XP® F1680 Series products can be reset using the RESET pin, power-on
reset, Watch-Dog Timer (WDT) time-out, STOP mode exit, or Voltage Brown-Out (VBO)
warning signal. The RESET pin is bi-directional, meaning it functions as reset source as
well as a reset indicator.
On-Chip Debugger
The Z8 Encore! XP® F1680 Series products feature an integrated On-Chip Debugger
(OCD). The OCD provides a rich set of debugging capabilities, such as reading and writ-
ing registers, programming Flash memory, setting breakpoints and executing code. A sin-
gle-pin interface provides communication to the OCD.
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Pin Description
Overview
The Z8 Encore! XP® F1680 Series products are available in a variety of packages styles
and pin configurations. This chapter describes the signals and available pin configurations
for each of the package styles. For information regarding the physical package specifica-
tions, refer to the chapter “Packaging” on page 346.
Available Packages
Table 2 identifies the package styles that are available for each device in the Z8 Encore!
XP® F1680 Series product line.
®
Table 2. Z8 Encore! XP F1680 Series Package Options
20-pin 20-pin 20-pin 28-pin 28-pin 28-pin 40-pin 44-pin 44-pin
Part Number ADC PDIP
SOIC
SSOP
PDIP
SOIC
SSOP PDIP PLCC LQFP
Z8F2480
Z8F2481
Z8F1680
Z8F1681
Z8F0880
Z8F0881
Z8F0480
Z8F0481
Yes
No
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Yes
No
X
X
X
X
X
X
Yes
No
X
X
X
X
X
X
Yes
No
X
X
X
X
X
X
Pin Configurations
Figures 2 through Figures 6 illustrate the pin configurations for all of the packages avail-
able in the Z8 Encore! XP® F1680 Series. Refer to Table 3 for a description of the signals.
The analog input alternate functions (ANAx) are not available on the Z8F2481, Z8F1681,
Z8F0881, and Z8F0481 devices. The analog supply pins (AVDD and AVSS) are also not
available on these parts, and are replaced by GPIO pins.
At reset, all port pins default to an input state. In addition, any alternate functionality is not
enabled, so the pins function as general-purpose-input ports until programmed otherwise.
At powerup, the Port D0 pin defaults to the RESET alternate function.
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The pin configurations listed are preliminary and subject to change based on manufactur-
ing limitations.
PB1/ANA1/AMPINN
PB2/ANA2/AMPINP
PB3/CLKIN/ANA3
VDD
PB0/ANA0/AMPOUT
PC3/C0OUT/LED
1
20
19
18
17
16
15
14
13
12
11
2
3
PC2/ANA6/LED/VREF
PC1/ANA5/C0INN/LED
PC0/ANA4/C0INP/LED
4
PA0/T0IN/T0OUT/XIN
PA1/T0OUT/XOUT
VSS
5
6
DBG
7
RESET/PD0
8
PA7/T1OUT/SDA
PA6/T1IN/T1OUT/SCL
PA5/TXD0/IRTX0/T2OUT
PA2/DE0/X2IN
9
PA3/CTS0/X2OUT
PA4/RXD0/IRRX0/T2IN/T2OUT
10
Figure 2.Z8F2480, Z8F1680, Z8F0880, and Z8F0480 in 20-Pin SOIC, SSOP or PDIP Package
PB2/ANA2/AMPINP
PB1/ANA1/AMPINN
PB0/ANA0/AMPOUT
PC3/C0OUT/LED
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
PB4/ANA7
PB5/VREF
3
PB3/CLKIN/ANA3
(PB6) AVDD
PC2/ANA6/LED/SS
4
PC1/ANA5/C0INN/LED/MISO
5
6
PC0/ANA4/C0INP/LED
DBG
VDD
PA0/T0IN/T0OUT/XIN
PA1/T0OUT/XOUT
VSS
7
8
RESET/PD0
9
PC7/LED/T2OUT
PC6/LED/T2IN/T2OUT
PA7/T1OUT/SDA
PC5/LED/SCK
(PB7) AVSS
10
11
12
13
14
PA2/DE0/X2IN
PA3/CTS0/X2OUT
PA4/RXD0/IRRX0
PA5/TXD0/IRTX0
PC4/LED/MOSI
PA6/T1IN/T1OUT/SCL
Figure 3.Z8F2480, Z8F1680, Z8F0880, and Z8F0480 in 28-Pin SOIC, SSOP or PDIP Package
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P R E L I M I N A R Y
Pin Description
Z8 Encore! XP® F1680 Series
Advance Product Specification
11
PB1/AMPINN/ANA1
PB2/AMPINP/ANA2
PB4/ANA7
1
5
40
35
PB0/AMPOUT/ANA0
PD1/C1INN
PD2/C1INP
PC3/MISO/LED
PC2/ANA6/SS/LED
PB5/VREF
PB3/CLKIN/ANA3
PE0
PC1/ANA5/C0INN/LED
PC0/ANA4/C0INP/LED
VSS
(PB6) AVDD
VDD
PA0/T0IN/T0OUT/XIN
PA1/T0OUT/XOUT
VSS
PD3/CTS0/C1OUT
VDD
10
15
20
30
DBG
(PB7) AVSS
PD0/RESET
PE1/SCL
PC7/T2OUT/LED
PC6/T2IN/T2OUT/LED
PD4/RXD1/IRRX1
PA7/T1OUT
PE2/SDA
PD7/C0OUT
25
21
PA2/DE0/X2IN
PA3/CTS0/X2OUT
PD6/DE1
PC5/SCK/LED
PC4/MOSI/LED
PA6/T1IN/T1OUT
PD5/TXD1/IRTX1
PA4/RXD0/IRRX0
PA5/TXD0/IRTX0
Figure 4. Z8F2480, Z8F1680, Z8F0880, and Z8F0480 in 40-Pin Dual Inline Package
(PDIP)
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Z8 Encore! XP® F1680 Series
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12
6
1
40
39
PE4/T4CHB
PE6/T4CHD
PE0/T4IN
7
PC1/ANA5/C0INN/LED
PC0/ANA4/C0INP/LED
VSS
AVDD (PB6)
VDD
PD3/CTS1/C1OUT
PA0/T0IN/T0OUT/XIN
34
12
VDD
PA1/T0OUT/XOUT
VSS
DBG
AVSS (PB7)
PE1/SCL
PD0/RESET
PC7/T2OUT/LED
PC6/T2IN/T2OUT/LED
PD4/RXD1/IRRX1
PE2/SDA
29
28
PD7/C0OUT
17
18
23
Figure 5.Z8F2480, Z8F1680, Z8F0880, and Z8F0480 in 44-Pin Plastic Leaded Chip Carrier (PLCC)
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Pin Description
Z8 Encore! XP® F1680 Series
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13
33
34
23
22
28
PE4/T4CHB
PE6/T4CHD
PE0/T4IN
PC1/ANA5/C0INN/LED
PC0/ANA4/C0INP/LED
VSS
AVDD (PB6)
VDD
PA0/T0IN/T0OUT/XIN
PD3/CTS1/C1OUT
VDD
39
44
17
PA1/T0OUT/XOUT
VSS
DBG
AVSS (PB7)
PE1/SCL
PD0/RESET
PC7/T2OUT/LED
PE2/SDA
PC6/T2IN/T2OUT/LED
PD4/RXD1/IRRX1
12
11
PD7/C0OUT
1
6
Figure 6. Z8F2480, Z8F1680, Z8F0880, and Z8F0480 in 44-Pin Low-Profile Quad Flat
Package (LQFP)
Signal Descriptions
Table 3 describes the Z8 Encore! XP® F1680 Series signals. Refer to the section “Pin Con-
figurations” on page 9 to determine the signals available for the specific package styles.
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Z8 Encore! XP® F1680 Series
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14
Table 3. Signal Descriptions
Description
Signal Mnemonic
I/O
General-Purpose I/O Ports A–D
PA[7:0]
PB[7:0]
I/O
I/O
Port A. These pins are used for general-purpose I/O.
Port B. These pins are used for general-purpose I/O. PB6 and PB7 are
available only in those devices without an ADC.
PC[7:0]
PD[7:0]
PE[6:0]
I/O
I/O
I/O
Port C. These pins are used for general-purpose I/O.
Port D. These pins are used for general-purpose I/O. PD0 is output only.
Port E. These pins are used for general purpose I/O.
Note: In 29-pin, 40-pin and 44-pin with ADC, PB6 and PB7 are replaced by AV and AV
.
SS
DD
LIN-UART Controllers
TXD0/TXD1
RXD0/RXD1
CTS0/CTS1
DE0/DE1
O
I
Transmit Data 0-1. These signals are the transmit output from the UART0/
1 and IrDA0/1.
Receive Data 0-1. These signals are the receive input for the UART0/1
and IrDA0/1.
I
Clear To Send 0-1. These signals are the flow control input for the UART0/
1.
O
Driver Enable 0-1. These signals allow automatic control of external RS-
485 drivers. These signals are approximately the inverse of the TXE
(Transmit Empty) bit in the UART Status 0/1 register. The DE0/1 signal
may be used to ensure the external RS-485 driver is enabled when data is
transmitted by the UART0/1.
2
I C Controller
®
2
2
SCL
I/O
I C Serial Clock. The I C Master supplies this signal. If the XP F1680
®
2
Series is the I C Master, this pin is an output. If the XP F1680 Series is
the SPI slave, this pin is an input. When the general-purpose I/O pin is
configured for alternate function to enable the SCL function, this pin is
open-drain.
2
SDA
I/O
I/O
Serial Data. This open-drain pin transfers data between the I C and an
2
external I C Master/Slave. When the general-purpose I/O pin is configured
for alternate function to enable the SDA function, this pin is open-drain.
ESPI Controller
®
SS
Slave Select. This signal can be an output or an input. If the XP F1680
Series is the SPI master, this pin may be configured as the Slave Select
®
output. If the XP F1680 Series is the SPI slave, this pin is the input slave
select.
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15
Table 3. Signal Descriptions (Continued)
Description
Signal Mnemonic
I/O
®
SCK
I/O
SPI Serial Clock. The SPI master supplies this signal. If the XP F1680
®
Series is the SPI master, this pin is an output. If the XP F1680 Series is
the SPI slave, this pin is an input.
MOSI
MISO
I/O
I/O
Master Out Slave In. This signal is the data output from the SPI master
device and the data input to the SPI slave device.
Master In Slave Out. This pin is the data input to the SPI master device
and the data output from the SPI slave device.
Timers
T0OUT/T1OUT/
T2OUT
O
O
I
Timer Output 0–2. These signals are output from the timers.
T0OUT/T1OUT/
T2OUT
Timer Complement Output 0–2. These signals are output from the timers
in PWM Dual Output mode.
T0IN/T1IN/T2IN
Timer Input 0–2. These signals are used as the capture, gating and
counter inputs. The T0IN/T1IN/T2IN signal is multiplexed with T0OUT/
T1OUT/T2OUT signals.
Multi-channel Timers
TACHA, TACHB,
TACHC, TACHD
I/O
I
Multi-channel Timer Input/Output. These signals function as Capture input
or Compare output for channels CHA, CHB, CHC, and CHD.
T4IN
Multi-channel Timer clock input. This signal allows external input to serve
as the clock source for the Multi-channel timer.
Comparators
C0INP/C0INN,
C1INP/C1INN
I
Comparator Inputs. These signals are the positive and negative inputs to
the comparator 0 and comparator 1.
C0OUT/C1OUT
O
Comparator Outputs. These are the output of the comparator 0 and the
comparator 1.
Analog
ANA[7:0]
I
Analog Port. These signals are used as inputs to the analog-to-digital
converter (ADC). The ANA0, ANA1 and ANA2 pins can also access the
inputs and output of the integrated transimpedance amplifier.
VREF
I/O
Analog-to-digital converter reference voltage input.
Transimpedance Amplifier
AMPINP/AMPINN
I
Transimpedance amplifier inputs. If enabled, these pins drive the positive
and negative amplifier inputs respectively.
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16
Table 3. Signal Descriptions (Continued)
Signal Mnemonic
I/O
Description
AMPOUT
O
Transimpedance amplifier output. If enabled, this pin is driven by the on-
chip transimpedance amplifier.
Oscillators
XIN
I
External Crystal Input. This is the input pin to the crystal oscillator. A
crystal can be connected between it and the XOUT pin to form the
oscillator. In addition, this pin is used with external RC networks or external
clock drivers to provide the system clock.
XOUT
X2IN
O
I
External Crystal Output. This pin is the output of the crystal oscillator. A
crystal can be connected between it and the XIN pin to form the oscillator.
Watch crystal input. This is the input pin to the low power 32KHz oscillator.
A watch crystal can be connected between the X2IN and the X2OUT pin to
form the oscillator.
X2OUT
O
Watch Crystal Output. This pin is the output from the low power 32KHz
oscillator. A watch crystal can be connected between the X2IN and the
X2OUT pin to form the oscillator.
Clock Input
CLKIN
I
Clock Input Signal. This pin may be used to input a TTL-level signal to be
used as the system clock.
LED Drivers
LED
O
Direct LED drive capability. All port C pins have the capability to drive an
LED without any other external components. These pins have
programmable drive strengths set by the GPIO block.
On-Chip Debugger
DBG
I/O
I/O
Debug. This signal is the control and data input and output to and from the
On-Chip Debugger.
The DBG pin is open-drain and requires an external pull-up resistor to
ensure proper operation.
Caution:
Reset
RESET. Generates a Reset when asserted (driven Low). Also serves as a
RESET
®
reset indicator; the Z8 Encore! XP forces this pin low when in reset. This
pin is open-drain and features an enabled internal pull-up resistor.
Power Supply
V
I
I
Digital Power Supply.
Analog Power Supply.
DD
AV
DD
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17
Table 3. Signal Descriptions (Continued)
Signal Mnemonic
I/O
Description
V
I
I
Digital Ground.
Analog Ground.
SS
AV
SS
Note: The AV and AV signals are available only in 28-, 40- and 44-pin packages with ADC. They are
DD
SS
replaced by PB6 and PB7 on these packages without ADC.
Pin Characteristics
Table 4 provides detailed information about the characteristics for each pin available on
the Z8 Encore! XP® F1680 Series 20-, 28-, 40- and 44-pin devices. Data in Table 4 is
sorted alphabetically by the pin symbol mnemonic.
Table 4. Pin Characteristics (20-, 28-, 40- and 44-pin Devices)
Active Low
or
Active
High
Internal Pull- Schmitt
up Trigger Open Drain
Output or Pull-down Input
Symbol
Reset
Tristate
Mnemonic Direction Direction
Output
N/A
5V Tolerance
AVDD
AVSS
DBG
N/A
N/A
I/O
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Yes
Yes
N/A
N/A
Yes
N/A
N/A
Yes
Yes
N/A
NA
N/A
N/A
I
I
Yes
No
PA[7:0]
I/O
Programmable
Pull-up
Yes,
Yes, 5V
Programmable tolerantinputs
unlesspullups
are enabled
PB[7:0]
PC[7:0]
PD[7:1]
I/O
I/O
I/O
I
I
I
N/A
N/A
N/A
Yes
Yes
Yes
Programmable
Pull-up
Yes
Yes
Yes
Yes,
Yes, 5V
Programmable tolerantinputs
unlesspullups
are enabled
Programmable
Pull-up
Yes,
Yes, 5V
Programmable tolerantinputs
unlesspullups
are enabled
Programmable
Pull-up
Yes,
Yes, 5V
Programmable tolerantinputs
unlesspullups
are enabled
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Advance Product Specification
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Table 4. Pin Characteristics (20-, 28-, 40- and 44-pin Devices) (Continued)
Active Low
or
Internal Pull- Schmitt
up Trigger Open Drain
Output or Pull-down Input
Symbol
Reset
Active
High
Tristate
Mnemonic Direction Direction
Output
5V Tolerance
PE[6:0]
I/O
I/O
I
N/A
Yes
Programmable
Pull-up
Yes
Yes,
Yes, 5V
Programmable tolerantinputs
unlesspullups
are enabled
RESET/
PD0
I/O
(defaults
to
Low (in
Reset
mode)
Yes
(PD0
only)
programmable
for PD0;
always on for
RESET
Yes
programmable
Yes,5V
forPD0;always tolerantinputs
on for RESET unlesspullups
are enabled
RESET)
VDD
VSS
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
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Advance Product Specification
19
Address Space
Overview
The eZ8 CPU can access three distinct address spaces:
•
•
•
The Register File contains addresses for general-purpose registers and eZ8 CPU, periph-
eral, and general-purpose I/O port control registers.
The Program Memory contains addresses for all memory locations having executable
code and/or data.
The Data Memory contains addresses for all memory locations that contain data only.
These three address spaces are covered briefly in the following subsections. For more
detailed information regarding the eZ8 CPU and its address space, refer to the eZ8 CPU
User Manual available for download at www.zilog.com.
Register File
The Register File address space in the Z8 Encore!® MCU is 4KB (4096 bytes). The Regis-
ter File is composed of two sections: control registers and general-purpose registers. When
instructions are executed, registers defined as sources are read, and registers defined as
destinations are written. The architecture of the eZ8 CPU allows all general-purpose regis-
ters to function as accumulators, address pointers, index registers, stack areas, or scratch
pad memory.
The upper 256 bytes of the 4KB Register File address space are reserved for control of the
eZ8 CPU, the on-chip peripherals, and the I/O ports. These registers are located at
addresses from F00H to FFFH. Some of the addresses within the 256B control register
section are reserved (unavailable). Reading from a reserved Register File address returns
an undefined value. Writing to reserved Register File addresses is not recommended and
can produce unpredictable results.
The on-chip RAM always begins at address 000H in the Register File address space. The
Z8 Encore! XP® F1680 Series devices contain 1KB to 2KB of on-chip RAM. Reading
from Register File addresses outside the available RAM addresses (and not within the con-
trol register address space) returns an undefined value. Writing to these Register File
addresses produces no effect.
In addition, Z8 Encore! XP® F1680 Series devices contain 1KB of on-chip Program
RAM. Normally, it is used as Program RAM and is in Program Memory address space
(See Program Memory for detail). However, it also can be used as on-chip RAM that is in
Register File address space 800H - 9FFH (0.5KB Program RAM) or 800 - BFF (1KB Pro-
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Z8 Encore! XP® F1680 Series
Advance Product Specification
20
gram RAM), if you do not need to use this on-chip Program RAM as Program RAM. For
using this feature. For details, see PRAM_M user option bit of page 275.
Program Memory
The eZ8 CPU supports 64KB of Program Memory address space. The Z8 Encore! XP®
F1680 Series devices contain 4KB to 16KB of on-chip flash memory in the Program
Memory address space, depending on the device.
In addition, Z8 Encore! XP® F1680 Series devices contain 1KB of on-chip Program
RAM. The Program RAM is mapped in the Program Memory address space beyond the
on-chip flash memory. The Program RAM is entirely under user control and is meant to
store interrupt service routines of high-frequency interrupts. Since interrupts bring the
CPU out of low power mode, it is important to ensure interrupts that occur very often use
as low current as possible. For battery operated systems, Program RAM based handling of
high frequency interrupts provides power savings by keeping the flash block disabled.
Program RAM (PRAM) is optimized for low current operation and can be easily boot-
strapped with interrupt code at power up.
Reading from Program Memory addresses outside the available Flash memory and PRAM
addresses returns FFH. Writing to these unimplemented Program Memory addresses pro-
duces no effect. Table 5 describes the Program Memory Maps for the Z8 Encore! XP®
F1680 Series products.
®
Table 5. Z8 Encore! XP F1680 Series Program Memory Maps
Program Memory Address (Hex)
Function
Z8F2480 and Z8F2481 Products
0000–0001
Flash Option Bits
Reset Vector
0002–0003
0004–0005
WDT Interrupt Vector
Illegal Instruction Trap
Interrupt Vectors*
Oscillator Fail Traps*
Program Flash
0006–0007
0008–0037
0038–003D
003E–5FFF
E000–E3FF
1KB PRAM
E000–E1FF
512B PRAM
Z8F1680 and Z8F1681 Products
* See Table 33 on page 69 for a list of the interrupt vectors and traps.
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21
®
Table 5. Z8 Encore! XP F1680 Series Program Memory Maps (Continued)
Program Memory Address (Hex)
0000–0001
Function
Flash Option Bits
Reset Vector
0002–0003
0004–0005
WDT Interrupt Vector
Illegal Instruction Trap
Interrupt Vectors*
Oscillator Fail Traps*
Program Flash
1KB PRAM
0006–0007
0008–0037
0038–003D
003E–3FFF
E000–E3FF
E000–E1FF
512B PRAM
Z8F0880 and Z8F0881 Products
0000–0001
Flash Option Bits
Reset Vector
0002–0003
0004–0005
WDT Interrupt Vector
Illegal Instruction Trap
Interrupt Vectors*
Oscillator Fail Traps*
Program Flash
0006–0007
0008–0037
0038–003D
003E–1FFF
E000–E3FF
1KB PRAM
E000–E1FF
512B PRAM
Z8F0480 and Z8F0481 Products
0000–0001
Flash Option Bits
Reset Vector
0002–0003
0004–0005
WDT Interrupt Vector
Illegal Instruction Trap
Interrupt Vectors*
Oscillator Fail Traps*
Program Flash
0006–0007
0008–0037
0038–003D
003E–0FFF
* See Table 33 on page 69 for a list of the interrupt vectors and traps.
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Advance Product Specification
22
®
Table 5. Z8 Encore! XP F1680 Series Program Memory Maps (Continued)
Program Memory Address (Hex)
E000–E3FF
Function
1KB PRAM
512B PRAM
E000–E1FF
* See Table 33 on page 69 for a list of the interrupt vectors and traps.
Data Memory
The Z8 Encore! XP® F1680 Series does not use the eZ8 CPU’s 64KB Data Memory
address space.
Flash Information Area
Table 6 describes the Z8 Encore! XP® F1680 Series Flash Information Area. This 128B
Information Area is accessed by setting bit 7 of the Flash Page Select Register to 1. When
access is enabled, the Flash Information Area is mapped into the Program Memory and
overlays the 128 bytes at addresses FE00Hto FF7FH. When the Information Area access is
enabled, all reads from these Program Memory addresses return the Information Area data
rather than the Program Memory data. Access to the Flash Information Area is read-only.
®
Table 6. Z8 Encore! XP F1680 Series Flash Memory Information Area Map
Program Memory Address (Hex) Function
FE00–FE3F
FE40–FE53
ZiLOG Option Bits
Part Number
20-character ASCII alphanumeric code
Left justified and filled with FH
FE54–FE5F
FE60–FE7F
FE80–FFFF
Reserved
ZiLOG Calibration Data
Reserved
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Z8 Encore! XP® F1680 Series
Advance Product Specification
23
Register Map
Table 7 provides the address map for the Register File of the Z8 Encore! XP® F1680
Series devices. Not all devices and package styles in the Z8 Encore! XP® F1680 Series
support the ADC, or all of the GPIO Ports. Consider registers for unimplemented periph-
erals as Reserved.
Table 7. Register File Address Map
Address (Hex) Register Description
General Purpose RAM
Mnemonic
Reset (Hex)
Page #
Z8F2480/Z8F2481 Devices
000–7FF
800–BFF
General-Purpose Register File RAM
—
XX
XX
General-Purpose Register File RAM if on- —
chip Program RAM is used as Register
File RAM
C00–EFF
Reserved
—
—
XX
Z8F1680/Z8F1681 Devices
000–7FF
400–7FF
General-Purpose Register File RAM
XX
XX
General-Purpose Register File RAM if on- —
chip Program RAM is used as Register
File RAM
C00–EFF
Reserved
—
XX
Z8F0880/Z8F0881 Devices
000–3FF
400–7FF
General-Purpose Register File RAM
—
XX
XX
General-Purpose Register File RAM if on- —
chip Program RAM is used as Register
File RAM
800–EFF
Reserved
—
XX
Z8F0480/Z8F0481 Devices
000–3FF
400–7FF
General-Purpose Register File RAM
—
XX
XX
General-Purpose Register File RAM if on- —
chip Program RAM is used as Register
File RAM
800–EFF
Reserved
—
XX
00
Timer 0
F00
Timer 0 High Byte
T0H
103
XX=Undefined
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Z8 Encore! XP® F1680 Series
Advance Product Specification
24
Table 7. Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic
T0L
Reset (Hex)
Page #
103
104
104
105
105
107
108
106
106
111
112
113
F01
F02
F03
F04
F05
F06
F07
F20
F21
F22
F23
F2C
Timer 0 Low Byte
01
FF
FF
00
00
00
00
00
00
00
00
00
Timer 0 Reload High Byte
Timer 0 Reload Low Byte
Timer 0 PWM0 High Byte
Timer 0 PWM0 Low Byte
Timer 0 Control 0
T0RH
T0RL
T0PWM0H
T0PWM0L
T0CTL0
T0CTL1
T0PWM1H
T0PWM1L
T0CTL2
T0STA
Timer 0 Control 1
Timer 0 PWM1 High Byte
Timer 0 PWM1 Low Byte
Timer 0 Control 2
Timer 0 Status
Timer 0 Noise Filter Control
T0NFC
Timer 1
F08
Timer 1 High Byte
T1H
00
01
FF
FF
00
00
00
00
00
00
00
00
00
103
103
104
104
105
105
107
108
106
106
111
112
113
F09
Timer 1 Low Byte
T1L
F0A
Timer 1 Reload High Byte
Timer 1 Reload Low Byte
Timer 1 PWM0 High Byte
Timer 1 PWM0 Low Byte
Timer 1 Control 0
T1RH
F0B
T1RL
F0C
T1PWM0H
T1PWM0L
T1CTL0
T1CTL1
T1PWM1H
T1PWM1L
T1CTL2
T1STA
F0D
F0E
F0F
Timer 1 Control 1
F24
Timer 1 PWM1 High Byte
Timer 1 PWM1 Low Byte
Timer 1 Control 2
F25
F26
F27
Timer 1 Status
F2D
Timer 1 Noise Filter Control
T1NFC
Timer 2
F10
Timer 2 High Byte
T2H
00
01
FF
FF
00
00
00
00
103
104
104
104
105
105
107
108
F11
Timer 2 Low Byte
T2L
F12
Timer 2 Reload High Byte
Timer 2 Reload Low Byte
Timer 2 PWM0 High Byte
Timer 2 PWM0 Low Byte
Timer 2 Control 0
T2RH
F13
T1RL
F14
T2PWM0H
T2PWM0L
T2CTL0
T2CTL1
F15
F16
F17
Timer 2 Control 1
XX=Undefined
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Z8 Encore! XP® F1680 Series
Advance Product Specification
25
Table 7. Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic
T2PWM1H
T2PWM1L
T2CTL2
T2STA
Reset (Hex)
Page #
106
F28
Timer 2 PWM1 High Byte
Timer 2 PWM1 Low Byte
Timer 2 Control 2
00
00
00
00
00
XX
F29
106
F2A
111
F2B
Timer 2 Status
112
F2E
Timer 2 Noise Filter Control
Reserved
T2NFC
113
F2F–F3F
—
LIN UART 0
F40
LIN UART0 Transmit Data
LIN UART0 Receive Data
U0TXD
U0RXD
XX
157
157
158
XX
F41
LIN UART0 Status 0 --- Standard UART U0STAT0
Mode
0000011Xb
LIN UART0 Status 0 --- LIN Mode
LIN UART0 Control 0
U0STAT0
U0CTL0
00000110b
159
163
165
F42
F43
00
00
LIN UART0 Control 1 --- Multiprocessor U0CTL1
Control
LIN UART0 Control 1 --- Noise Filter
Control
U0CTL1
00
00
167
LIN UART0 Control 1 --- LIN Control
LIN UART0 Mode Select and Status
UART0 Address Compare
U0CTL1
168
161
170
170
171
F44
F45
F46
F47
U0MDSTAT 00
U0ADDR
U0BRH
U0BRL
00
FF
FF
UART0 Baud Rate High Byte
UART0 Baud Rate Low Byte
LIN UART 1
F48
LIN UART1 Transmit Data
LIN UART1 Receive Data
U0TXD
U0RXD
XX
157
157
158
XX
F49
LIN UART1 Status 0 --- Standard UART U0STAT0
Mode
0000011Xb
LIN UART1 Status 0 --- LIN Mode
LIN UART1 Control 0
U0STAT0
U0CTL0
00000110b
159
163
165
F4A
F4B
00
00
LIN UART1 Control 1 --- Multiprocessor U0CTL1
Control
LIN UART1 Control 1 --- Noise Filter
Control
U0CTL1
00
00
167
LIN UART1 Control 1 --- LIN Control
LIN UART1 Mode Select and Status
UART1 Address Compare
U0CTL1
168
161
170
F4C
U0MDSTAT 00
U0ADDR 00
F4D
XX=Undefined
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Z8 Encore! XP® F1680 Series
Advance Product Specification
26
Table 7. Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic
U0BRH
Reset (Hex)
Page #
170
F4E
F4F
UART1 Baud Rate High Byte
FF
FF
UART1 Baud Rate Low Byte
U0BRL
171
2
I C
2
F50
I C Data
I2CDATA
I2CSTAT
I2CCTL
I2CBRH
I2CBRL
I2CDST
I2CDIAG
—
00
80
00
FF
FF
C0
00
XX
237
238
240
244
244
245
249
2
F51
I C Status
2
F52
I C Control
2
F53
I C Baud Rate High Byte
2
F54
I C Baud Rate Low Byte
2
F55
I C Diagnostic State
2
F56
I C Diagnostic Control
F57-F5F
Reserved
Enhanced Serial Peripheral Interface (ESPI)
F60
ESPI Data
ESPIDATA
ESPITDCR
ESPICTLT
ESPIMODE
ESPISTAT
XX
00
00
00
01
206
207
208
210
212
213
213
213
F61
ESPI Transmit Data Command
ESPI Control
F62
F63
ESPI Mode
F64
ESPI Status
F65
ESPI State
ESPISTATE 00
F66
ESPI Baud Rate High Byte
ESPI Baud Rate Low Byte
Reserved
ESPIBRH
ESPIBRL
—
FF
FF
XX
F67
F68–F6F
Analog-to-Digital Converter (ADC)
F70
ADC Control 0
ADCCTL0
ADCRD_H
ADCD_H
ADCD_L
ADCSST
ADCST
ADCCP
—
00
182
184
184
185
186
187
188
F71
ADC Raw Data High Byte
ADC Data High Byte
ADC Data Low Bits
80
F72
XX
XX
FF
XX
00
F73
F74
ADC Sample and Settling Time
Sample Time Reset
ADC Clock Prescale Register
Reserved
F75
F76
F77–F7F
XX
Low Power Control
F80
F81
Power Control 0
Reserved
PWRCTL0
—
80
44
XX
LED Controller
XX=Undefined
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Z8 Encore! XP® F1680 Series
Advance Product Specification
27
Table 7. Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic
LEDEN
LEDLVLH
LEDLVLL
—
Reset (Hex)
Page #
66
F82
F83
F84
F85
LED Drive Enable
00
00
00
XX
LED Drive Level High Byte
LED Drive Level Low Byte
Reserved
67
67
Oscillator Control
F86
Oscillator Control0
Oscillator Control1
Reserved
OSCCTL0
OSCCTL1
A0
00
300
301
F87
F88–F8F
Comparator 0
F90
Comparator 0 Control
CMP0
14
255
256
Comparator 1
F91
Comparator 1 Control
Reserved
CMP1
—
14
F92–F9F
XX
Multi-channel Timer
FA0
MCT High Byte
MCTH
00
124
124
125
125
126
126
126
126
FA1
MCT Low Byte
MCTL
00
FA2
MCT Reload High Byte
MCT Reload Low Byte
MCT Sub Address
MCT Sub Register 0
MCT Sub Register 1
MCT Sub Register 2
Reserved
MCTRH
MCTLH
MCTSA
MCTSR0
MCTSR1
MCTSR2
—
FF
FF
XX
XX
XX
XX
XX
FA3
FA4
FA5
FA6
FA7
FA8 - FBF
Interrupt Controller
FC0
Interrupt Request 0
IRQ0
00
00
00
00
00
00
00
00
00
XX
73
76
76
74
77
77
75
78
78
FC1
IRQ0 Enable High Bit
IRQ0 Enable Low Bit
Interrupt Request 1
IRQ1 Enable High Bit
IRQ1 Enable Low Bit
Interrupt Request 2
IRQ2 Enable High Bit
IRQ2 Enable Low Bit
Reserved
IRQ0ENH
IRQ0ENL
IRQ1
FC2
FC3
FC4
IRQ1ENH
IRQ1ENL
IRQ2
FC5
FC6
FC7
IRQ2ENH
IRQ2ENL
—
FC8
FC9–FCC
XX=Undefined
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Z8 Encore! XP® F1680 Series
Advance Product Specification
28
Table 7. Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic
IRQES
Reset (Hex)
Page #
79
FCD
FCE
FCF
Interrupt Edge Select
Shared Interrupt Select
Interrupt Control
00
00
00
IRQSS
79
IRQCTL
80
GPIO Port A
FD0
Port A Address
Port A Control
PAADDR
PACTL
PAIN
00
00
XX
00
59
60
61
61
FD1
FD2
Port A Input Data
Port A Output Data
FD3
PAOUT
GPIO Port B
FD4
Port B Address
Port B Control
PBADDR
PBCTL
PBIN
00
00
XX
00
59
60
61
61
FD5
FD6
Port B Input Data
Port B Output Data
FD7
PBOUT
GPIO Port C
FD8
Port C Address
Port C Control
PCADDR
PCCTL
PCIN
00
00
XX
00
59
60
61
61
FD9
FDA
Port C Input Data
Port C Output Data
FDB
PCOUT
GPIO Port D
FDC
Port D Address
Port D Control
PDADDR
PDCTL
PDIN
00
00
XX
00
59
60
61
61
FDD
FDE
Port D Input Data
Port D Output Data
FDF
PDOUT
GPIO Port E
FE0
Port E Address
Port E Control
Port E Input Data
Port E Output Data
Reserved
PEADDR
PECTL
PEIN
00
00
XX
00
XX
59
60
61
61
FE1
FE2
FE3
PEOUT
—
FE4–FEF
Reset
FF0
Reset Status
Reserved
RSTSTAT
—
XX
XX
40
FF1
Watch-Dog Timer (WDT)
FF2
Watch-Dog Timer Reload High Byte
WDTH
FF
137
XX=Undefined
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Z8 Encore! XP® F1680 Series
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29
Table 7. Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic
WDTL
—
Reset (Hex)
Page #
FF3
Watch-Dog Timer Reload Low Byte
FF
XX
137
FF4–FF5
Reserved
Trim Bit Control
FF6
FF7
Trim Bit Address
Trim Data
TRMADR
TRMDR
00
273
273
XX
Flash Memory Controller
FF8
Flash Control
FCTL
00
00
00
00
00
00
267
268
268
269
270
270
Flash Status
FSTAT
FPS
FF9
Flash Page Select
Flash Sector Protect
FPROT
FFA
FFB
Flash Programming Frequency High Byte FFREQH
Flash Programming Frequency Low Byte FFREQL
eZ8 CPU
FFC
Flags
—
XX
XX
XX
XX
Refer to the
eZ8 CPU User
Manual
FFD
Register Pointer
Stack Pointer High Byte
Stack Pointer Low Byte
RP
FFE
SPH
SPL
FFF
XX=Undefined
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Z8 Encore! XP® F1680 Series
Advance Product Specification
30
Reset, STOP Mode Recovery and Low
Voltage Detection
Overview
The Reset Controller within the Z8 Encore! XP® F1680 Series device controls Reset and
STOP Mode Recovery operation and provides indication of low supply voltage condi-
tions. In typical operation, the following events cause a Reset:
•
•
•
Power-On Reset (POR)
Voltage Brown-Out (VBO)
Watch-Dog Timer time-out (when configured by the WDT_RES Flash Option Bit to
initiate a reset)
•
•
External RESET pin assertion (when the alternate RESET function is enabled by the
GPIO register)
On-Chip Debugger initiated Reset (OCDCTL[0] set to 1)
When the device is in STOP mode, a STOP Mode Recovery is initiated by either of the
following:
•
•
•
Watch-Dog Timer time-out
GPIO Port input pin transition on an enabled STOP Mode Recovery source
Interrupt from a timer or comparator enabled for Stop Mode operation.
The low-voltage-detection circuitry on the device performs the following functions
•
Generates an interrupt when the supply voltage drops below a user-defined level
Reset Types
The Z8 Encore! XP® F1680 Series provides several different types of Reset operation.
STOP Mode Recovery is considered a form of Reset. Table 8 lists the types of Reset and
their operating characteristics. The System Reset is longer if the external crystal oscillator
is enabled by the Flash option bits, allowing additional time for oscillator start-up.
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Advance Product Specification
31
Table 8. Reset and STOP Mode Recovery Characteristics and Latency
Reset Characteristics and Latency
eZ8
Reset Type
Control Registers
CPU Reset Latency (Delay)
System Reset
Reset (as applicable)
Reset 68 Internal Precision Oscillator Cycles
System Reset with Crystal Reset (as applicable)
Oscillator Enabled
Reset 500 - 10000 Internal Precision Oscillator
Cycles, see EXTLTMG—External Crystal
Reset Timing 00 = 3,000 Internal
Precision Oscillator Cycles 01 = 5,000
Internal Precision Oscillator Cycles 10 =
10,000 Internal Precision Oscillator
Cycles 11 = 20,000 Internal Precision
Oscillator Cycles Reserved—Must be 1.
user option bit for detail
STOP Mode Recovery
Unaffected, except
WDT_CTL and
Reset 68 Internal Precision Oscillator Cycles
OSC_CTL registers
STOP Mode Recovery with Unaffected, except
Crystal Oscillator Enabled WDT_CTL and
OSC_CTL registers
Reset 5000 Internal Precision Oscillator Cycles
During a System Reset or STOP Mode Recovery, the Internal Precision Oscillator requires
4μs to start up. Then the Z8 Encore! XP® F1680 Series device is held in Reset for 68
cycles of the Internal Precision Oscillator. If the crystal oscillator is enabled in the flash
option bits, this reset period is increased to 500 - 10000 IPO cycles, according to
EXTLTMG—External Crystal Reset Timing 00 = 3,000 Internal Precision Oscillator
Cycles 01 = 5,000 Internal Precision Oscillator Cycles 10 = 10,000 Internal Precision
Oscillator Cycles 11 = 20,000 Internal Precision Oscillator Cycles Reserved—Must
be 1. user option bit. When a reset occurs because of a low voltage condition or power on
reset, this delay is measured from the time that the supply voltage first exceeds the POR
level (discussed later in this chapter). If the external pin reset remains asserted at the end
of the reset period, the device remains in reset until the pin is deassert.
At the beginning of Reset, all GPIO pins are configured as inputs with pull-up resistor dis-
abled, except PD0 which is shared with the reset pin. On reset, the Port D0 pin is config-
ured as a bidirectional open-drain reset. The pin is internally driven low during port reset,
after which the user code may reconfigure this pin as a general-purpose output.
During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watch-Dog Timer oscillator continue to run.
Upon Reset, control registers within the Register File that have a defined Reset value are
loaded with their reset values. Other control registers (including the Stack Pointer, Regis-
PS025001-1105
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Z8 Encore! XP® F1680 Series
Advance Product Specification
32
ter Pointer, and Flags) and general-purpose RAM are undefined following Reset. The eZ8
CPU fetches the Reset vector at Program Memory addresses 0002Hand 0003Hand loads
that value into the Program Counter. Program execution begins at the Reset vector
address.
Because the control registers are re-initialized by a system reset, the system clock after
reset is always the IPO. User software must reconfigure the oscillator control block, such
that the correct system clock source is enabled and selected.
Reset Sources
Table 9 lists the possible sources of a system reset.
Table 9. Reset Sources and Resulting Reset Type
Operating Mode
Reset Source
Special Conditions
NORMAL or HALT
modes
Power-On Reset / Voltage Brown- Reset delay begins after supply voltage
Out
exceeds VBO level
None
Watch-Dog Timer time-out
when configured for Reset
RESET pin assertion
All reset pulses less than three system clocks
in width are ignored.
On-Chip Debugger initiated Reset System Reset, except the On-Chip Debugger
(OCDCTL[0] set to 1) is unaffected by the reset
STOP mode
Power-On Reset / Voltage Brown- Reset delay begins after supply voltage
Out
exceeds VBO level
RESET pin assertion
All reset pulses less than the specified analog
delay are ignored. See “Electrical
Characteristics” on page 329.
DBG pin driven Low
None
Power-On Reset
Each device in the Z8 Encore! XP® F1680 Series contains an internal Power-On Reset
(POR) circuit. The POR circuit monitors the supply voltage and holds the whole device
(include internal option bit register and VBO enable register) in the Reset state until the
supply voltage reaches a safe VBO operating level when the device is powered on.
After the supply voltage exceeds the POR voltage threshold (VPOR), the POR circuit deas-
serts its reset output and VBO circuit begin to assert VBO’s reset output to hold the whole
device (exclude internal option bit register and VBO enable register) in the Reset state
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Advance Product Specification
33
(We call it "Power-On initiated VBO Reset state") until the supply voltage reached the
default VBO voltage threshold (VminVBO+) .
After the supply voltage exceeds the VBO voltage threshold (VminVBO+), the device is
held in the Reset state until the Reset Counter has timed out. If the crystal oscillator is
enabled by the option bits, this time-out is longer. Figure 7 illustrates Power-On Reset
operation.
After powered on, the POR circuit keep idle until the supply voltage drops below Vth volt-
age. Figure 8 illustrate this POR timing.
After the Z8 Encore! XP® F1680 Series device exits the Power-On initiated VBO Reset
state, the eZ8 CPU fetches the Reset vector. Following this Power-On initiated VBO
Reset, the POR/VBO status bit in the Reset Status Register is set to 1.
Refer to the Electrical Characteristics for the POR threshold voltage (VPOR) and POR start
voltage Vth..
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VCC = 3.3V
VVBO+
VVBO-
VPOR
Program
Execution
VCC = 0.0V
VTH
Internal Precision
Oscillator
Crystal
Oscillator
Oscillator
Start-up
Internal RESET
signal
POR
counter delay
optional XTAL
counter delay
Internal POR
Reset
Internal VBO
Reset
undefined
Note: Not to Scale
Note: Internal POR Reset and VBO Reset are low active
Figure 7.Power-On Reset and VBO Reset Operation in the power on case
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V
Vcc
VCC(min)
VPOR
POR
POR
No POR
Vth
t(POR_DELAY)
t(POR_DELAY)
POR
Reset
Figure 8.Power-On Reset Timing
Voltage Brown-Out Reset
The devices in the Z8 Encore! XP® F1680 Series provide low Voltage Brown-Out (VBO)
Reset to help Power-On Reset and provide low voltage protection.
The VBO circuit have a programmable voltage threshold (VVBO), which can be set
through writing option bit, and a hysterisis Vhys. Its low trigger voltage (VVBO-) is
"VVBO _ 0.5Vhys"; and the high trigger voltage (VVBO+) is "VVBO + 0.5Vhys". The
VBO circuit senses when the supply voltage is below its VVBO- voltage and asserts the
VBO Reset output, and when the supply voltage is up its VVBO+ voltage and deasserts
the VBO Reset output. Between these selections of the programmable VBO voltage thesh-
old, the lowest ann default one VminVBO- is greater than VPOR, which is 0.7*Vmin-
VBO-. The VminVBO+ is "VminVBO- + Vhys", which is the safe working voltage of the
whole chip above. This ensure the VBO ciucuit can work correctly to make the device
progress through a full System Reset sequence above the chip’s safe working voltage after
the POR ciucuit stop working.
In the power on case, VBO circuit begin to work with its default setting after the supply
voltage exceeds the POR voltage threshold, and stop working after the supply voltage
exceeds VVBO+. And then, the device progresses through a full System Reset sequence, as
described in the Power-On Reset section. Following this System Reset sequence, the POR/
VBO status bit in the Reset Status (RSTSTAT) register is set to 1.Figure 7 illustrates the
whole power on case.
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In the voltage brown out case, The VBO circuit senses when the supply voltage drops to
its programmable trigger point VVBO- (below the VBO low threshold voltage) and forces
the device into the Reset state. After the supply voltage again exceeds its programmable
trigger point VVBO+ (up the VBO high threshold voltage), the device progresses through a
full System Reset sequence also, just like power on case. Following this System Reset
sequence, the POR/VBO status bit in the Reset Status (RSTSTAT) register is set to 1.
Figure 9 illustrates Voltage Brown-Out operation in the voltage brown out case.
Refer to the chapter Electrical Characteristics for the all kinds of VBO threshold voltages
(VVBO) and VBO hysterisis (Vhys).
The Voltage Brown-Out circuit can be either enabled or disabled during STOP mode.
Operation during STOP mode is set by the VBO_AO Flash Option Bit. Refer to the Flash
Option Bits chapter for information about configuring VBO_AO.
VCC = 3.3V
VCC = 3.3V
VVBO+
VVBO-
Program
Voltage
Program
Execution
Brownout
Execution
WDT Clock
System Clock
Internal RESET
signal
POR
counter delay
Internal VBO
Reset
Note: Not to Scale
Figure 9.Voltage Brown-Out Reset Operation in the voltage brown out case
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Watch-Dog Timer Reset
If the device is in NORMAL or STOP mode, the Watch-Dog Timer can initiate a System
Reset at time-out if the WDT_RES Flash Option Bit is programmed to 1. This is the
unprogrammed state of the WDT_RES Flash Option Bit. If the bit is programmed to 0, it
configures the Watch-Dog Timer to cause an interrupt, not a System Reset, at time-out.
The WDT status bit in the WDT Control register is set to signify that the reset was initi-
ated by the Watch-Dog Timer.
External Reset Input
The RESET pin has a Schmitt-triggered input and an internal pull-up resistor. Once the
RESET pin is asserted for a minimum of four system clock cycles, the device progresses
through the System Reset sequence. Because of the possible asynchronicity of the system
clock and reset signals, the required reset duration may be as short as 3 clock periods and
as long as 4. A reset pulse 3 clock cycles in duration might trigger a reset; a pulse 4 cycles
in duration always triggers a reset.
While the RESET input pin is asserted Low, the Z8 Encore! XP® F1680 Series devices
remain in the Reset state. If the RESET pin is held Low beyond the System Reset time-
out, the device exits the Reset state on the system clock rising edge following RESET pin
deassertion. Following a System Reset initiated by the external RESET pin, the EXT sta-
tus bit in the Watch-Dog Timer Control (WDTCTL) register is set to 1.
External Reset Indicator
During System Reset or when enabled by the GPIO logic (see Port A–E Control Registers),
the RESET pin functions as an open-drain (active low) reset mode indicator in addition to
the input functionality. This reset output feature allows an Z8 Encore! XP® F1680 Series
device to reset other components to which it is connected, even if that reset is caused by
internal sources such as POR, VBO or WDT events.
After an internal reset event occurs, the internal circuitry begins driving the RESET pin
Low. The RESET pin is held Low by the internal circuitry until the appropriate delay
listed in Table 8 has elapsed.
On-Chip Debugger Initiated Reset
A Power-On Reset can be initiated using the On-Chip Debugger by setting the RSTbit in
the OCD Control register. The On-Chip Debugger block is not reset but the rest of the chip
goes through a normal system reset. The RSTbit automatically clears during the system
reset. Following the system reset the PORbit in the WDT Control register is set.
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STOP Mode Recovery
STOP mode is entered by execution of a STOP instruction by the eZ8 CPU. Refer to the
chapter Low-Power Modes for detailed STOP mode information. During STOP Mode
Recovery, the CPU is held in reset for 66 IPO cycles if the crystal oscillator is disabled or
500-10,000 cycles (dependent on user selection in EXTLTMG field of Flash Option bits)
if it is enabled.
STOP Mode Recovery does not affect onchip registers other than the Watchdog Timer
Control register (WDTCTL) and the Oscillator Control register (OSCCTL). After any
STOP Mode Recovery, the IPO is enabled and selected as the system clock. If another sys-
tem clock source is required or IPO disabling is required, the STOP Mode Recovery code
must reconfigure the oscillator control block such that the correct system clock source is
enabled and selected.
The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002Hand 0003H
and loads that value into the Program Counter. Program execution begins at the Reset vec-
tor address. Following STOP Mode Recovery, the STOP bit in the Watch-Dog Timer Con-
trol Register is set to 1. Table 10 lists the STOP Mode Recovery sources and resulting
actions. The text following provides more detailed information about each of the STOP
Mode Recovery sources.
Table 10. STOP Mode Recovery Sources and Resulting Action
Operating Mode STOP Mode Recovery Source
Action
STOP mode
Watch-Dog Timer time-out
when configured for Reset
STOP Mode Recovery
Watch-Dog Timer time-out
when configured for interrupt
STOP Mode Recovery followed by
interrupt (if interrupts are enabled)
Interrupt from Timer enabled for STOP
Mode operation
STOP Mode Recovery followed by
interrupt (if interrupts are enabled)
Interrupt from Comparator enabled for
STOP Mode operation
STOP Mode Recovery followed by
interrupt (if interrupts are enabled)
Data transition on any GPIO Port pin
STOP Mode Recovery
enabled as a STOP Mode Recovery source
Assertion of external RESET Pin
Debug Pin driven Low
System Reset
System Reset
STOP Mode Recovery Using Watch-Dog Timer Time-Out
If the Watch-Dog Timer times out during STOP mode, the device undergoes a STOP
Mode Recovery sequence. In the Reset Status register, the WDT and STOP bits are set to
1. If the Watch-Dog Timer is configured to generate an interrupt upon time-out and the Z8
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Encore! XP® F1680 Series device is configured to respond to interrupts, the eZ8 CPU ser-
vices the Watch-Dog Timer interrupt request following the normal STOP Mode Recovery
sequence.
STOP Mode Recovery Using Timer Interrupt
If a Timer enabled for STOP Mode operation interrupts during STOP Mode, the device
undergoes a STOP Mode Recovery sequence. In the Reset Status Register, the STOP bit is
set to 1. If the Z8 Encore! XP® F1680 Series device is configured to respond to interrupts,
the eZ8 CPU services the Timer interrupt request following the normal STOP Mode
Recovery sequence.
STOP Mode Recovery Using Comparator Interrupt
If Comparator enabled for STOP Mode operation interrupts during STOP Mode, the
device undergoes a STOP Mode Recovery sequence. In the Reset Status Register, the
STOP bit is set to 1. If the Z8 Encore! XP® F1680 Series device is configured to respond
to interrupts, the eZ8 CPU services the Comparator interrupt request following the normal
STOP Mode Recovery sequence.
STOP Mode Recovery Using a GPIO Port Pin Transition
Each of the GPIO Port pins may be configured as a STOP Mode Recovery input source.
On any GPIO pin enabled as a STOP Mode Recovery source, a change in the input pin
value (from high to low or from low to high) initiates STOP Mode Recovery. In the
Watch-Dog Timer Control register, the STOPbit is set to 1.
In STOP mode, the GPIO Port Input Data registers (PxIN) are disabled. The Port Input
Data registers record the Port transition only if the signal stays on the Port pin through
the end of the STOP Mode Recovery delay. As a result, short pulses on the Port pin can
initiate STOP Mode Recovery without being written to the Port Input Data register or
without initiating an interrupt (if enabled for that pin).
Caution:
STOP Mode Recovery Using the External RESET Pin
When the Z8 Encore! XP® F1680 Series device is in STOP Mode and the external RESET
pin is driven low, a system reset occurs. Because of a glitch filter operating on the RESET
pin, the low pulse must be greater than the minimum width specified, or it is ignored. See
Electrical Characteristics for details.
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Low Voltage Detection
In addition to the Voltage Brown-out Reset (VBO) described above, it is also possible to
generate an interrupt when the supply voltage drops below a user-selected value. See Trim
Bit Address 0000H for details about the Low-Voltage Detection (LVD) threshold levels
available.
When the supply voltage drops below the LVD threshold, the LVD bit of the RSTSTAT
register is set to 1. This bit remains 1 until the low-voltage condition goes away. Reading
or writing this bit does not clear it. The LVD circuit can also generate an interrupt when so
enabled. (Interrupt Vectors and Priority) The LVD is NOT latched, so enabling the interrupt
is the only way to guarantee detection of a transient low-voltage event.
The LVD functionality depends on circuitry shared with the VBO block; therefore dis-
abling the VBO also disables the LVD.
Reset Register Definitions
Reset Status Register
The Reset Status (RSTSTAT) register is a read-only register that indicates the source of
the most recent Reset event, indicates a STOP Mode Recovery event, and denotes a
Watch-Dog Timer time-out. Reading this register resets the upper 4 bits to 0.
This register shares its address with the Watch-Dog Timer control register, which is write-
only (Table 11).
Table 11. Reset Status Register (RSTSTAT)
BITS
7
6
5
4
3
2
1
0
POR/VBO
STOP
WDT
EXT
Reserved
LVD
FIELD
RESET
R/W
See descriptions below
0
0
0
0
0
R
R
R
R
R
R
R
R
FF0H
ADDR
Reset or STOP Mode Recovery Event
Power-On Reset or VBO Reset
POR
STOP
WDT
EXT
1
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
Reset using RESET pin assertion
Reset using Watch-Dog Timer time-out
Reset using the On-Chip Debugger (OCTCTL[1] set to 1)
Reset from STOP Mode using DBG Pin driven Low
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Reset or STOP Mode Recovery Event
POR
STOP
WDT
EXT
STOP Mode Recovery using GPIO pin transition
STOP Mode Recovery using Watch-Dog Timer time-out
0
0
1
1
0
1
0
0
POR/VBO—Power-On initiated VBO Reset or general VBO Reset Indicator
If this bit is set to 1, a VBO Reset event occurred. This bit is reset to 0 if a WDT time-out
or STOP Mode Recovery occurs. This bit is also reset to 0 when the register is read.
STOP—STOP Mode Recovery Indicator
If this bit is set to 1, a STOP Mode Recovery occurred. If the STOPand WDTbits are both
set to 1, the STOP Mode Recovery occurred because of a WDT time-out. If the STOPbit
is 1 and the WDTbit is 0, the STOP Mode Recovery was not caused by a WDT time-out.
This bit is reset by a Power-On Reset or a WDT time-out that occurred while not in STOP
mode. Reading this register also resets this bit.
WDT—Watch-Dog Timer Time-Out Indicator
If this bit is set to 1, a WDT time-out occurred. A Power-On Reset resets this pin. A STOP
Mode Recovery from a change in an input pin also resets this bit. Reading this register
resets this bit. This read must occur before clearing the WDT interrupt.
EXT—External Reset Indicator
If this bit is set to 1, a Reset initiated by the external RESET pin occurred. A Power-On
Reset or a STOP Mode Recovery from a change in an input pin resets this bit. Reading this
register resets this bit.
Reserved—Must be 0.
LVD—Low-Voltage Detection Indicator
If this bit is set to 1 the current state of the supply voltage is below the low voltage detec-
tion threshold. This value is not latched but is a real-time indicator of the supply voltage
level.
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Low-Power Modes
Overview
The Z8 Encore! XP® F1680 Series products contain power-saving features. The highest
level of power reduction is provided by the STOP mode. The next lower level of power
reduction is provided by the HALT mode.
Further power savings can be implemented by disabling individual peripheral blocks
while in Normal mode.
STOP Mode
Executing the eZ8 CPU’s STOP instruction places the device into STOP mode. In STOP
mode, the operating characteristics are:
•
Primary crystal oscillator and internal-precision oscillator are stopped; XIN and XOUT (if
previously enabled) are disabled, and PA0/PA1 revert to the states programmed by the
GPIO registers
•
•
•
•
System clock is stopped
eZ8 CPU is stopped
Program counter (PC) stops incrementing
Watch-Dog Timer’s internal RC oscillator continues to operate if enabled by the Oscillator
Control Register
•
•
•
If enabled, the Watch-Dog Timer logic continues to operate
If enabled, the 32KHz secondary oscillator continues to operate
If enabled for operation in STOP Mode, the Timer logic continues to operate with 32KHz
secondary oscillator as the Timer clock source
•
•
•
If enabled for operation in STOP mode by the associated Flash Option Bit, the Voltage-
brown-out protection circuit continues to operate
Transimpedance amplifier and Comparator continue to operate if enabled by the Power
Control Register to do so
All other on-chip peripherals are idle
To minimize current in STOP mode, all GPIO pins that are configured as digital inputs
must be driven to one of the supply rails (VCC or GND). The device can be brought out of
STOP mode using STOP Mode Recovery. For more information about STOP Mode
Recovery refer to Reset, STOP Mode Recovery and Low Voltage Detection.
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HALT Mode
Executing the eZ8 CPU’s HALT instruction places the device into HALT mode. In HALT
mode, the operating characteristics are:
•
•
•
•
•
•
•
•
Primary oscillator is enabled and continues to operate
System clock is enabled and continues to operate
eZ8 CPU is stopped
Program counter (PC) stops incrementing
Watch-Dog Timer’s internal RC oscillator continues to operate
If enabled, the Watch-Dog Timer continues to operate
If enabled, the 32KHz secondary oscillator for Timers continues to operate
All other on-chip peripherals continue to operate
The eZ8 CPU can be brought out of HALT mode by any of the following operations:
•
•
•
•
•
Interrupt
Watch-Dog Timer time-out (interrupt or reset)
Power-on reset
Voltage brown-out reset
External RESET pin assertion
To minimize current in HALT mode, all GPIO pins that are configured as inputs must be
driven to one of the supply rails (VCC or GND).
Peripheral-Level Power Control
In addition to the STOP and Halt modes, it is possible to disable each peripheral on each
of the Z8 Encore! XP® F1680 Series devices. Disabling a given peripheral minimizes its
power consumption.
Power Control Register Definitions
Power Control Register 0
Each bit of the following registers disables a peripheral block, either by gating its system
clock input or by removing power from the block.
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The default state of the transimpedance amplifier is OFF. To use the transimpedance
amplifier, clear the TRAM bit, turning it ON. Clearing this bit might interfere with normal
ADC measurements on ANA0 (the transimpedance output). This bit enables the amplifier
even in STOP mode. If the amplifier is not required in STOP mode, disable it. Failure to
perform this results in STOP mode currents greater than specified.
This register is only reset during a power-on reset sequence. Other system reset events do
not affect it.
Note:
Table 12. Power Control Register 0 (PWRCTL0)
BITS
7
6
5
4
3
2
1
0
TRAM
Reserved
VBO
TEMP
ADC
COMP0
COMP1
FIELD
RESET
R/W
1
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F80H
ADDR
TRAM— Transimpedance Amplifier Disable
0 = Transimpedance Amplifier is enabled (this applies even in STOP mode).
1 = Transimpedance Amplifier is disabled.
Reserved—Must be 0.
VBO—Voltage Brown-Out Detector Disable
This bit and the VBO_AO Flash option bit must both enable the VBO for the VBO to be
active.
0 = VBO Enabled
1 = VBO Disabled
TEMP—Temperature Sensor Disable
0 = Temperature Sensor Enabled
1 = Temperature Sensor Disabled
ADC—Analog-to-Digital Converter Disable
0 = Analog-to-Digital Converter Enabled
1 = Analog-to-Digital Converter Disabled
COMP0—Comparator 0 Disable
0 = Comparator 0 is Enabled (this applies even in STOP Mode)
1 = Comparator 0 is Disabled
COMP1—Comparator 1 Disable
0 = Comparator 1 is Enabled (this applies even in STOP Mode)
1 = Comparator 1 is Disabled
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General-Purpose I/O
Overview
The Z8 Encore! XP® F1680 Series products support a maximum of 39 port pins (Ports A–
E) for general-purpose input/output (GPIO) operations. Each port contains control and
data registers. The GPIO control registers determine data direction, open-drain, output
drive current, programmable pull-ups, STOP Mode Recovery functionality, and alternate
pin functions. Each port pin is individually programmable. In addition, the Port C pins are
capable of direct LED drive at programmable drive strengths.
GPIO Port Availability By Device
Table 13 lists the port pins available with each device and package type.
Table 13. Port Availability by Device and Package Type
Devices
Package 10-Bit ADC SPI Port A Port B Port C Port D Port E Total I/O
Z8F2480PH, Z8F2480HH
Z8F1680PH, Z8F1680HH
Z8F0880PH, Z8F0880HH
Z8F0480PH, Z8F0480HH
Z8F2480SH, Z8F1680SH,
Z8F0880SH,Z8F0480SH
20-pin
PDIP
SOIC
SSOP
Yes
No
No
No
[7:0]
[7:0]
[7:0]
[3:0]
[3:0]
[5:0]
[3:0]
[3:0]
[7:0]
[0]
[0]
[0]
-
-
-
17
17
23
Z8F2481PH, Z8F2481HH
Z8F1681PH, Z8F1681HH
Z8F0881PH, Z8F0881HH
Z8F0481PH, Z8F0481HH
Z8F2481SH, Z8F1681SH,
Z8F0881SH, Z8F0481SH
20-pin
PDIP
SOIC
SSOP
No
Z8F2480PJ, Z8F2480PJ
Z8F1680PJ, Z8F1680SJ
Z8F0880PJ, Z8F0880SJ
Z8F0480PJ, Z8F0480SJ
Z8F2480HJ, Z8F1680HJ,
Z8F0880HJ, Z8F0480HJ
28-pin
PDIP
SOIC
SSOP
Yes
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Table 13. Port Availability by Device and Package Type (Continued)
Package 10-Bit ADC SPI Port A Port B Port C Port D Port E Total I/O
Devices
Z8F2481PJ, Z8F1681PJ,
Z8F1681SJ, Z8F0881PJ,
Z8F0881SJ, Z8F0481PJ,
Z8F2481SJ, Z8F0481SJ
Z8F2481HJ, Z8F1681HJ,
Z8F0881HJ, Z8F0481HJ
28-pin
PDIP
SOIC
SSOP
No
No
[7:0]
[7:0]
[7:0]
[0]
-
25
Z8F2480PM, Z8F1680PM, 40-pin
Z8F0880PM, Z8F0480PM PDIP
Yes
No
1
2
1
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[0]
33
35
37
Z8F2481PM, Z8F1681PM, 40-pin
[2:0]
[4:0]
Z8F0881PM, Z8F0481PM
PDIP
Z8F2480AN, Z8F2480VN
Z8F1680AN, Z8F1680VN
Z8F0880AN, Z8F0880VN
Z8F0480AN, Z8F0880VN
44-pin
LQFP
PLCC
Yes
Z8F2481AN, Z8F2481VN
Z8F1681AN, Z8F1681VN
Z8F0881AN, Z8F0881VN
Z8F0481AN, Z8F0481VN
44-pin
LQFP
PLCC
No
2
[7:0]
[7:0]
[7:0]
[7:0]
[6:0]
39
Architecture
Figure 10 illustrates a simplified block diagram of a GPIO port pin. In this figure, the abil-
ity to accommodate alternate functions and variable port current drive strength is not illus-
trated.
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Port Input
Data Register
Schmitt Trigger
Q
D
Q
D
System
Clock
VDD
Port Output Control
Port Output
Data Register
DATA
Bus
D
Q
Port
Pin
System
Clock
Port Data Direction
GND
Figure 10.GPIO Port Pin Block Diagram
GPIO Alternate Functions
Many of the GPIO port pins can be used for general-purpose I/O and access to on-chip
peripheral functions such as the timers and serial-communication devices. The Port A–E
Alternate Function sub-registers configure these pins for either General-Purpose I/O or
alternate-function operation. When a pin is configured for alternate function, control of the
port-pin direction (input/output) is passed from the Port A–E Data Direction registers to
the alternate function assigned to this pin. Table 14 Port Alternate Function Mapping (20-Pin
Parts) , Table 15 Port Alternate Function Mapping (28-Pin Parts) and Table 16 Port Alternate
Function Mapping (40-/44-Pin Parts) list the alternate functions possible with each port pin
for every package. The alternate function associated at a pin is defined through Alternate
Function Sets sub-registers AFS1 and AFS2.
The crystal oscillator and the 32KHz secondary oscillator functionalities are not controlled
by the GPIO block. When the crystal oscillator or the 32KHz secondary oscillator is
enabled in the oscillator control block, the GPIO functionality of PA0 and PA1, or PA2 and
PA3, is overridden. In that case, those pins function as input and output for the crystal
oscillator.
PA0 and PA7 contain two or three different timer functions (according to different pack-
age), a timer input and a complementary timer output. Both of these functions require the
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same GPIO configuration, the selection between the two or three is based on the timer
mode. See “Timers” on page 81 for more details.
Direct LED Drive
The Port C pins provide a current synched output capable of driving an LED without
requiring an external resistor. The output synchs current at programmable levels of 3mA,
7mA, 13mA and 20mA. This mode is enabled through the Alternate Function sub-register
AFS1 and is programmable through the LED control registers.
For correct function, the LED anode must be connected to VDD and the cathode to the
GPIO pin.
Using all Port C pins in LED drive mode with maximum current may result in excessive
total current. Refer to the Electrical Characteristics for the maximum total current for the
applicable package.
Shared Reset Pin
On all of the devices, the Port D0 pin shares function with a bi-directional reset pin.
Unlike all other I/O pins, this pin does not default to GPIO function on power-up. This pin
acts as a bi-directional reset until user software re-configures it. The Port D0 pin is output-
only when in GPIO mode.
Crystal Oscillator Override
For systems using the crystal oscillator, PA0 and PA1 are used to connect the crystal.
When the main crystal oscillator is enabled (see Oscillator Control0 Register), the GPIO
settings are overridden and PA0 and PA1 are disabled.
32KHz Secondary Oscillator Override
For systems using a 32KHz secondary oscillator, PA2 and PA3 are used to connect a watch
crystal. When the 32KHz secondary oscillator is enabled (See Oscillator Control1 Regis-
ter), the GPIO settings are overridden and PA2 and PA3 are disabled.
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5V Tolerance
All GPIO pins, including those that share functionality with an ADC, crystal or compara-
tor signal are 5V-tolerant and can safely handle inputs higher than VDD even with the pull-
ups enabled.
Note:
External Clock Setup
For systems using an external TTL drive, PB3 is the clock source for 20-, 28-, 40- and 44-
pin devices. In this case, configure PB3 for alternate function CLKIN. Write the Oscillator
Control Register (page 299) such that the external oscillator is selected as the system
clock.
Table 14. Port Alternate Function Mapping (20-Pin Parts)
AlternateFunction
Port
Pin
Mnemonic
T0IN/T0OUT
Reserved
T0OUT
Alternate Function Description
Set Register AFS1
PA0
Timer 0 Input/Timer 0 Output Complement AFS1[0]: 0
AFS1[0]: 1
Port A
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Timer 0 Output
AFS1[1]: 0
AFS1[1]: 1
AFS1[2]: 0
AFS1[2]: 1
AFS1[3]: 0
AFS1[3]: 1
AFS1[4]: 0
Reserved
DE0
UART 0 Driver Enable
UART 0 Clear to Send
UART 0 / IrDA 0 Receive Data
Reserved
CTS0
Reserved
RXD0/IRRX0
T2IN/T2OUT
TXD0/IRTX0
T2OUT
Timer 2 Input/Timer 2 Output Complement AFS1[4]: 1
UART 0 / IrDA 0 Transmit Data
Timer 2 Output
AFS1[5]: 0
AFS1[5]: 1
T1IN/T1OUT
SCL
Timer 1 Input/Timer 1 Output Complement AFS1[6]: 0
2
I C Serial Clock
AFS1[6]: 1
AFS1[7]: 0
AFS1[7]: 1
T1OUT
Timer 1 Output
2
SDA
I C Serial Data
Note: Because there are at most two choices of alternate function for some pins of Port A, the Alternate
Function Set register AFS2 is implemented but not used to select the function. Also, alternate function
selection as described in “Port A-E Alternate Function Sub-Registers” on page 61 must also be enabled.
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Table 14. Port Alternate Function Mapping (20-Pin Parts) (Continued)
AlternateFunction
Set Register AFS1
Port
Pin
Mnemonic
Reserved
Alternate Function Description
PB0
AFS1[0]: 0
AFS1[0]: 1
AFS1[1]: 0
AFS1[1]: 1
AFS1[2]: 0
AFS1[2]: 1
AFS1[3]: 0
AFS1[3]: 1
Port B
ANA0/AMPOUT
Reserved
ADC Analog Input/Transamp Output
ADC Analog Input/Transamp Input (N)
PB1
PB2
PB3
ANA1/AMPINN
Reserved
ANA2/AMPINP
CLKIN
ADC Analog Input/Transamp Input (P)
External Clock Input
ANA3
ADC Analog Input
Note: Because there are at most two choices of alternate function for some pins of Port B, the Alternate
Function Set register AFS2 is implemented but not used to select the function. Also, alternate function
selection as described in “Port A-E Alternate Function Sub-Registers” on page 61 must also be enabled.
PC0
PC1
PC2
PC3
Reserved
AFS1[0]: 0
Port C
ANA4/C0INP/LED ADC or Comparator 0 Input (P), or LED drive AFS1[0]: 1
Drive
Reserved
AFS1[1]: 0
ANA5/C0INN/LED ADC or Comparator 0 Input (N), or LED drive AFS1[1]: 1
Drive
Reserved
AFS1[2]: 0
VREF/ANA6/LED Voltage Reference or ADC Analog Input or AFS1[2]: 1
LED Drive
COUT0
LED
Comparator 0 Output
LED drive
AFS1[3]: 0
AFS1[3]: 1
Note: Because there are at most two choices of alternate function for some pins of Port C, the Alternate
Function Set register AFS2 is implemented but not used to select the function. Also, alternate function
selection as described in “Port A-E Alternate Function Sub-Registers” on page 61 must also be enabled.
PD0
RESET
External Reset
N/A
Port D
Reserved
Note: Because there is only a single alternate function for each Port D pin, the Alternate Function Set
registers are not implemented for Port D. Enabling alternate function selections as described in “Port A-E
Alternate Function Sub-Registers” on page 61 automatically enables the associated alternate function.
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Table 15. Port Alternate Function Mapping (28-Pin Parts)
Alternate
Function Set
Register AFS1
Port
Pin
Mnemonic
T0IN/T0OUT
Reserved
T0OUT
Alternate Function Description
PA0
Timer 0 Input/Timer 0 Output Complement AFS1[0]: 0
AFS1[0]: 1
Port A
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Timer 0 Output
AFS1[1]: 0
AFS1[1]: 1
AFS1[2]: 0
AFS1[2]: 1
AFS1[3]: 0
AFS1[3]: 1
AFS1[4]: 0
AFS1[4]: 1
AFS1[5]: 0
AFS1[5]: 1
Reserved
DE0
UART 0 Driver Enable
UART 0 Clear to Send
UART 0 / IrDA 0 Receive Data
UART 0 / IrDA 0 Transmit Data
Reserved
CTS0
Reserved
RXD0/IRRX0
Reserved
TXD0/IRTX0
Reserved
T1IN/T1OUT
SCL
Timer 1 Input/Timer 1 Output Complement AFS1[6]: 0
2
I C Serial Clock
Timer 1 Output
AFS1[6]: 1
AFS1[7]: 0
AFS1[7]: 1
T1OUT
2
SDA
I C Serial Data
Note: Because there are at most two choices of alternate function for some pins of Port A, the
Alternate Function Set register AFS2 is implemented but not used to select the function. Also,
alternate function selection as described in “Port A-E Alternate Function Sub-Registers” on page 61
must also be enabled.
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Table 15. Port Alternate Function Mapping (28-Pin Parts) (Continued)
Alternate
Function Set
Register AFS1
Port
Pin
Mnemonic
Alternate Function Description
PB0
Reserved
AFS1[0]: 0
AFS1[0]: 1
AFS1[1]: 0
AFS1[1]: 1
AFS1[2]: 0
AFS1[2]: 1
AFS1[3]: 0
AFS1[3]: 1
AFS1[4]: 0
AFS1[4]: 1
AFS1[5]: 0
AFS1[5]: 1
AFS1[6]: 0
AFS1[6]: 1
AFS1[7]: 0
AFS1[7]: 1
Port B
ANA0/AMPOUT ADC Analog Input/Transamp Output
Reserved
PB1
PB2
PB3
PB4
PB5
PB6
PB7
ANA1/AMPINN
Reserved
ANA2/AMPINP
CLKIN
ADC Analog Input/Transamp Input (N)
ADC Analog Input/Transamp Input (P)
External Clock Input
ANA3
ADC Analog Input
Reserved
ANA7
ADC Analog Input
Voltage Reference
Reserved
VREF
Reserved
Reserved
Reserved
Reserved
Note: Because there are at most two choices of alternate function for some pins of Port B, the
Alternate Function Set register AFS2 is implemented but not used to select the function. Also,
alternate function selection as described in “Port A-E Alternate Function Sub-Registers” on page 61
must also be enabled.
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Table 15. Port Alternate Function Mapping (28-Pin Parts) (Continued)
Alternate
Function Set
Register AFS1
Port
Pin
Mnemonic
Alternate Function Description
PC0
Reserved
AFS1[0]: 0
AFS1[0]: 1
Port C
ANA4/C0INP/
LED
ADC or Comparator 0 Input (P), or LED
drive
PC1
MISO
SPI Master In Slave Out
AFS1[1]: 0
AFS1[1]: 1
ANA5/C0INN/
LED
ADC or Comparator 0 Input (N), or LED
Drive
PC2
PC3
PC4
PC5
PC6
PC7
SS
SPI Slave Select
ADC Analog Input or LED Drive
Comparator 0 Output
LED drive
AFS1[2]: 0
AFS1[2]: 1
AFS1[3]: 0
AFS1[3]: 1
AFS1[4]: 0
AFS1[4]: 1
AFS1[5]: 0
AFS1[5]: 1
ANA6/LED
COUT0
LED
MOSI
LED
SPI Master Out Slave In
LED Drive
SCK
SPI Serial Clock
LED Drive
LED
T2IN/T2OUT
LED
Timer 2 Input/Timer2 Output Complement AFS1[6]: 0
LED Drive
AFS1[6]: 1
AFS1[7]: 0
AFS1[7]: 1
T2OUT
LED
Timer 2 Output
LED Drive
Note: Because there are at most two choices of alternate function for some pins of Port C, the
Alternate Function Set register AFS2 is implemented but not used to select the function. Also,
alternate function selection as described in “Port A-E Alternate Function Sub-Registers” on page 61
must also be enabled.
PD0
RESET
External Reset
N/A
Port D
Reserved
Note: Because there is only a single alternate function for each Port D pin, the Alternate Function
Set registers are not implemented for Port D. Enabling alternate function selections as described in
“Port A-E Alternate Function Sub-Registers” on page 61 automatically enables the associated
alternate function.
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Table 16. Port Alternate Function Mapping (40-/44-Pin Parts)
Alternate
Function Set
Register AFS1
Port
Pin
Mnemonic
T0IN/T0OUT
Reserved
T0OUT
Alternate Function Description
PA0
Timer 0 Input/Timer 0 Output Complement AFS1[0]: 0
AFS1[0]: 1
Port A
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Timer 0 Output
AFS1[1]: 0
AFS1[1]: 1
AFS1[2]: 0
AFS1[2]: 1
AFS1[3]: 0
AFS1[3]: 1
AFS1[4]: 0
AFS1[4]: 1
AFS1[5]: 0
AFS1[5]: 1
Reserved
DE0
UART 0 Driver Enable
UART 0 Clear to Send
UART 0 / IrDA 0 Receive Data
UART 0 / IrDA 0 Transmit Data
Reserved
CTS0
Reserved
RXD0/IRRX0
TXD0/IRTX0
T1IN/T1OUT
Reserved
T1OUT
Timer 1 Input/Timer 1 Output Complement AFS1[6]: 0
AFS1[6]: 1
Timer 1 Output
AFS1[7]: 0
AFS1[7]: 1
Reserved
Note: Because there are at most two choices of alternate function for some pins of Port A, the
Alternate Function Set register AFS2 is implemented but not used to select the function. Also,
alternate function selection as described in “Port A-E Alternate Function Sub-Registers” on page 61
must also be enabled.
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Table 16. Port Alternate Function Mapping (40-/44-Pin Parts) (Continued)
Alternate
Function Set
Register AFS1
Port
Pin
Mnemonic
Alternate Function Description
PB0
Reserved
AFS1[0]: 0
AFS1[0]: 1
AFS1[1]: 0
AFS1[1]: 1
AFS1[2]: 0
AFS1[2]: 1
AFS1[3]: 0
AFS1[3]: 1
AFS1[4]: 0
AFS1[4]: 1
AFS1[5]: 0
AFS1[5]: 1
AFS1[6]: 0
AFS1[6]: 1
AFS1[7]: 0
AFS1[7]: 1
Port B
ANA0/AMPOUT ADC Analog Input/Transamp Output
Reserved
PB1
PB2
PB3
PB4
PB5
PB6
PB7
ANA1/AMPINN
Reserved
ANA2/AMPINP
CLKIN
ADC Analog Input/Transamp Input (N)
ADC Analog Input/Transamp Input (P)
External Clock Input
ANA3
ADC Analog Input
Reserved
ANA7
ADC Analog Input
Voltage Reference
Reserved
VREF
Reserved
Reserved
Reserved
Reserved
Note: Because there are at most two choices of alternate function for some pins of Port B, the
Alternate Function Set register AFS2 is implemented but not used to select the function. Also,
alternate function selection as described in “Port A-E Alternate Function Sub-Registers” on page 61
must also be enabled.
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Table 16. Port Alternate Function Mapping (40-/44-Pin Parts) (Continued)
Alternate
Function Set
Register AFS1
Port
Pin
Mnemonic
Alternate Function Description
PC0
Reserved
AFS1[0]: 0
AFS1[0]: 1
Port C
ANA4/C0INP/
LED
ADC or Comparator 0 Input (P), or LED
drive
PC1
Reserved
AFS1[1]: 0
AFS1[1]: 1
ANA5/C0INN/
LED
ADC or Comparator 0 Input (N), or LED
Drive
PC2
PC3
PC4
PC5
PC6
PC7
SS
SPI Slave Select
ADC Analog Input or LED Drive
SPI Master In Slave Out
LED drive
AFS1[2]: 0
AFS1[2]: 1
AFS1[3]: 0
AFS1[3]: 1
AFS1[4]: 0
AFS1[4]: 1
AFS1[5]: 0
AFS1[5]: 1
ANA6/LED
MISO
LED
MOSI
LED
SPI Master Out Slave In
LED Drive
SCK
SPI Serial Clock
LED
LED Drive
T2IN/T2OUT
LED
Timer 2 Input/Timer2 Output Complement AFS1[6]: 0
LED Drive
AFS1[6]: 1
AFS1[7]: 0
AFS1[7]: 1
T2OUT
LED
Timer 2 Output
LED Drive
Note: Because there are at most two choices of alternate function for some pins of Port C, the
Alternate Function Set register AFS2 is implemented but not used to select the function. Also,
alternate function selection as described in “Port A-E Alternate Function Sub-Registers” on page 61
must also be enabled.
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Table 16. Port Alternate Function Mapping (40-/44-Pin Parts) (Continued)
Alternate
Function Set
Register AFS1
Port
Pin
Mnemonic
RESET
Alternate Function Description
PD0
External Reset
N/A
Port D
Reserved
C1INN
PD1
PD2
PD3
Comparator 1 Input (N)
Comparator 1 Input (P)
Reserved
C1INP
Reserved
CTS1/COUT1
UART 1 Clear to Send or Comparator 1
Output
Reserved
RXD1/IRRX1
Reserved
TXD1/IRTX1
Reserved
DE1
PD4
PD5
PD6
PD7
UART 1 / IrDA 1 Receive Data
UART 1 / IrDA 1 Transmit Data
Reserved
COUT0
UART 1 Driver Enable
Comparator 0 Output
Reserved
Note: Because there is only a single alternate function for each Port D pin, the Alternate Function
Set registers are not implemented for Port D. Enabling alternate function selections as described in
“Port A-E Alternate Function Sub-Registers” on page 61 automatically enables the associated
alternate function.
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Table 16. Port Alternate Function Mapping (40-/44-Pin Parts) (Continued)
Alternate
Function Set
Register AFS1
Port
Pin
Mnemonic
T4IN*
Alternate Function Description
PE0
N/A
Port E
Reserved
SCL
2
PE1
PE2
PE3
PE4
PE5
PE6
I C Serial Clock
Reserved
SDA
2
I C Serial Data
Reserved
T4CHA*
Reserved
T4CHB*
Reserved
T4CHC*
Reserved
T4CHD*
Reserved
Note: Because there is only a single alternate function for each Port E pin, the Alternate Function
Set registers are not implemented for Port E. Enabling alternate function selections as described in
“Port A-E Alternate Function Sub-Registers” on page 61 automatically enables the associated
alternate function.
* Multi-Channel Function only is available in 44-pin package. These alternative functions are
reserved in 40-pin package.
GPIO Interrupts
Many of the GPIO port pins can be used as interrupt sources. Some port pins can be con-
figured to generate an interrupt request on either the rising edge or falling edge of the pin-
input signal. Other port-pin interrupt sources generate an interrupt when any edge occurs
(both rising and falling). Refer to the chapter Interrupt Controller for more information
about interrupts using the GPIO pins.
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GPIO Control Register Definitions
Four registers for each Port provide access to GPIO control, input data, and output data.
Table 17 lists these Port registers. Use the Port A–E Address and Control registers
together to provide access to sub-registers for Port configuration and control.
Table 17. GPIO Port Registers and Sub-Registers
Port Register Mnemonic
Port Register Name
PxADDR
Port A–E Address Register
(Selects sub-registers)
PxCTL
Port A–E Control Register
(Provides access to sub-registers)
PxIN
Port A–E Input Data Register
Port A–E Output Data Register
PxOUT
Port Sub-Register Mnemonic
Port Register Name
PxDD
PxAF
Data Direction
Alternate Function
PxOC
Output Control (Open-Drain)
High Drive Enable
PxHDE
PxSMRE
PxPUE
PxAFS1
PxAFS2
STOP Mode Recovery Source Enable
Pull-up Enable
Alternate Function Set 1
Alternate Function Set 2
Port A–E Address Registers
The Port A–E Address registers select the GPIO Port functionality accessible through the
Port A–E Control registers. The Port A–E Address and Control registers combine to pro-
vide access to all GPIO Port controls (Table 18).
Table 18. Port A–E GPIO Address Registers (PxADDR)
BITS
7
6
5
4
3
2
1
0
PADDR[7:0]
00H
FIELD
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FD0H, FD4H, FD8H, FDCH, FE0H
ADDR
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PADDR[7:0]—Port Address
The Port Address selects one of the sub-registers accessible through the Port Control reg-
ister.
PADDR[7:0] Port Control sub-register accessible using the Port A–E Control Registers
00H
01H
No function. Provides some protection against accidental Port reconfiguration.
Data Direction
02H
Alternate Function
03H
Output Control (Open-Drain)
High Drive Enable
04H
05H
STOP Mode Recovery Source Enable.
Pull-up Enable
06H
07H
Alternate Function Set 1
Alternate Function Set 2
No function
08H
09H–FFH
Port A–E Control Registers
The Port A–E Control registers set the GPIO port operation. The value in the correspond-
ing Port A–E Address register determines which sub-register is read from or written to by
a Port A–E Control register transaction (Table 19).
Table 19. Port A–E Control Registers (PxCTL)
BITS
7
6
5
4
3
2
1
0
PCTL
00H
FIELD
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FD1H, FD5H, FD9H, FDDH, FE1H
ADDR
PCTL[7:0]—Port Control
The Port Control register provides access to all sub-registers that configure the GPIO Port
operation.
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Port A–E Data Direction Sub-Registers
The Port A–E Data Direction sub-register is accessed through the Port A–E Control regis-
ter by writing 01H to the Port A–E Address register (Table 20).
Table 20. Port A–E Data Direction Sub-Registers (PxDD)
BITS
7
6
5
4
3
2
1
0
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
FIELD
RESET
R/W
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 01H in Port A–E Address Register, accessible through the Port A–E Control Register
ADDR
DD[7:0]—Data Direction
These bits control the direction of the associated port pin. Port Alternate Function opera-
tion overrides the Data Direction register setting.
0 = Output. Data in the Port A–E Output Data register is driven onto the port pin.
1 = Input. The port pin is sampled and the value written into the Port A–E Input Data Reg-
ister. The output driver is tristated.
Port A-E Alternate Function Sub-Registers
The Port A–E Alternate Function sub-register (Table 21) is accessed through the Port A–E
Control register by writing 02Hto the Port A–E Address register. The Port A–E Alternate
Function sub-registers enable the alternate function selection on pins. If disabled, pins
functions as GPIO. If enabled, select one of four alternate functions using alternate func-
tion set sub-registers 1 and 2 as described in the “Port A–E Alternate Function Set 1 Sub-
Registers” on page 64 and “Port A–E Alternate Function Set 2 Sub-Registers” on page 64.
Refer to the “GPIO Alternate Functions” on page 47 to determine the alternate function asso-
ciated with each port pin.
Caution:
Do not enable alternate functions for GPIO port pins for which there is no
associated alternate function. Failure to follow this guideline can result in
unpredictable operation.
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Table 21. Port A–E Alternate Function Sub-Registers (PxAF)
BITS
7
6
5
4
3
2
1
0
AF7
AF6
AF5
AF4
AF3
AF2
AF1
AF0
FIELD
RESET
R/W
00H (Ports A–C); 01H (Port D); 00H (Port E);
R/W
If 02H in Port A–D Address Register, accessible through the Port A–E Control Register
ADDR
AF[7:0]—Port Alternate Function enabled
0 = The port pin is in normal mode and the DDxbit in the Port A–E Data Direction sub-
register determines the direction of the pin.
1 = The alternate function selected through Alternate Function Set sub-registers is
enabled. Port-pin operation is controlled by the alternate function.
Port A–E Output Control Sub-Registers
The Port A–E Output Control sub-register (Table 22) is accessed through the Port A–E
Control register by writing 03Hto the Port A–E Address register. Setting the bits in the
Port A–E Output Control sub-registers to 1 configures the specified port pins for open-
drain operation. These sub-registers affect the pins directly and, as a result, alternate func-
tions are also affected.
Table 22. Port A–E Output Control Sub-Registers (PxOC)
BITS
7
6
5
4
3
2
1
0
POC7
POC6
POC5
POC4
POC3
POC2
POC1
POC0
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 03H in Port A–E Address Register, accessible through the Port A–E Control Register
ADDR
POC[7:0]—Port Output Control
These bits function independently of the alternate function bit and always disable the
drains if set to 1.
0 = The drains are enabled for any output mode (unless overridden by the alternate func-
tion).
1 = The drain of the associated pin is disabled (open-drain mode).
Port A–E High Drive Enable Sub-Registers
The Port A–E High Drive Enable sub-register (Table 23) is accessed through the Port
A–E Control register by writing 04Hto the Port A–E Address register. Setting the bits in
the Port A–E High Drive Enable sub-registers to 1 configures the specified port pins for
high-current output drive operation. The Port A–E High Drive Enable sub-register affects
the pins directly and, as a result, alternate functions are also affected.
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Table 23. Port A–E High Drive Enable Sub-Registers (PxHDE)
BITS
7
6
5
4
3
2
1
0
PHDE7
PHDE6
PHDE5
PHDE4
PHDE3
PHDE2
PHDE1
PHDE0
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 04H in Port A–E Address Register, accessible through the Port A–E Control Register
ADDR
PHDE[7:0]—Port High Drive Enabled
0 = The Port pin is configured for standard output current drive.
1 = The Port pin is configured for high output current drive.
Port A–E STOP Mode Recovery Source Enable Sub-Registers
The Port A–E STOP Mode Recovery Source Enable sub-register (Table 24) is accessed
through the Port A–E Control register by writing 05Hto the Port A–E Address register.
Setting the bits in the Port A–E STOP Mode Recovery Source Enable sub-registers to 1
configures the specified Port pins as a STOP Mode Recovery source. During STOP Mode,
any logic transition on a Port pin enabled as a STOP Mode Recovery source initiates
STOP Mode Recovery.
Table 24. Port A–E STOP Mode Recovery Source Enable Sub-Registers (PxSMRE)
BITS
7
6
5
4
3
2
1
0
PSMRE7 PSMRE6 PSMRE5 PSMRE4 PSMRE3 PSMRE2 PSMRE1 PSMRE0
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 05H in Port A–E Address Register, accessible through the Port A–E Control Register
ADDR
PSMRE[7:0]—Port STOP Mode Recovery Source Enabled
0 = The Port pin is not configured as a STOP Mode Recovery source. Transitions on this
pin during STOP mode do not initiate STOP Mode Recovery.
1 = The Port pin is configured as a STOP Mode Recovery source. Any logic transition on
this pin during STOP mode initiates STOP Mode Recovery.
Port A–E Pull-up Enable Sub-Registers
The Port A–E Pull-up Enable sub-register (Table 25) is accessed through the Port A–E
Control register by writing 06Hto the Port A–E Address register. Setting the bits in the
Port A–E Pull-up Enable sub-registers enables a weak internal resistive pull-up on the
specified Port pins.
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Table 25. Port A–E Pull-Up Enable Sub-Registers (PxPUE)
BITS
7
6
5
4
3
2
1
0
PPUE7
PPUE6
PPUE5
PPUE4
PPUE3
PPUE2
PPUE1
PPUE0
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 06H in Port A–E Address Register, accessible through the Port A–E Control Register
ADDR
PPUE[7:0]—Port Pull-up Enabled
0 = The weak pull-up on the Port pin is disabled.
1 = The weak pull-up on the Port pin is enabled.
Port A–E Alternate Function Set 1 Sub-Registers
The Port A–E Alternate Function Set1 sub-register (Table 26) is accessed through the Port
A–E Control register by writing 07Hto the Port A–E Address register. The Alternate
Function Set 1 sub-registers selects the alternate function available at a port pin. Alternate
Functions selected by setting or clearing bits of this register are defined in “GPIO Alternate
Functions” on page 47.
Alternate function selection on port pins must also be enabled as described in “Port A-E
Note:
Alternate Function Sub-Registers” on page 61.
Table 26. Port A–E Alternate Function Set 1 Sub-Registers (PxAFS1)
BITS
7
6
5
4
3
2
1
0
PAFS17
PAFS16
PAFS15
PAFS14
PAFS13
PAFS12
PAFS11
PAFS10
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 07H in Port A–E Address Register, accessible through the Port A–E Control Register
ADDR
PAFS1[7:0]—Port Alternate Function Set 1
0 = Port Alternate Function selected as defined in Table 13 in the GPIO Alternate Functions
section.
1 = Port Alternate Function selected as defined in Table 13 in the GPIO Alternate Functions
section.
Port A–E Alternate Function Set 2 Sub-Registers
The Port A–E Alternate Function Set 2 sub-register (Table 27) is accessed through the Port
A–E Control register by writing 08Hto the Port A–E Address register. The Alternate
Function Set 2 sub-registers selects the alternate function available at a port pin. Alternate
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Functions selected by setting or clearing bits of this register is defined in Table 13 in the
section “GPIO Alternate Functions” on page 47.
Alternate function selection on port pins must also be enabled as described in “Port A-E
Note:
Alternate Function Sub-Registers” on page 61.
Table 27. Port A–E Alternate Function Set 2 Sub-Registers (PxAFS2)
BITS
7
6
5
4
3
2
1
0
PAFS27
PAFS26
PAFS25
PAFS24
PAFS23
PAFS22
PAFS21
PAFS20
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 08H in Port A–E Address Register, accessible through the Port A–E Control Register
ADDR
PAFS2[7:0]—Port Alternate Function Set 2
0 = Port Alternate Function selected as defined in Table 13 GPIO Alternate Functions sec-
tion.
1 = Port Alternate Function selected as defined in Table 13 GPIO Alternate Functions sec-
tion.
Port A–E Input Data Registers
Reading from the Port A–E Input Data registers (Table 28) returns the sampled values
from the corresponding port pins. The Port A–E Input Data registers are read-only. The
value returned for any unused ports is 0. Unused ports include those missing on the 8- and
28-pin packages, as well as those missing on the ADC-enabled 28-pin packages.
Table 28. Port A–E Input Data Registers (PxIN)
7
PIN7
X
6
PIN6
X
5
PIN5
X
4
PIN4
X
3
PIN3
X
2
PIN2
X
1
PIN1
X
0
PIN0
X
BITS
FIELD
RESET
R/W
R
R
R
R
R
R
R
R
FD2H, FD6H, FDAH, FDEH, FE2H
ADDR
PIN[7:0]—Port Input Data
Sampled data from the corresponding port pin input.
0 = Input data is logical 0 (Low).
1 = Input data is logical 1 (High).
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Port A–E Output Data Register
The Port A–E Output Data register (Table 29) controls the output data to the pins.
Table 29. Port A–E Output Data Register (PxOUT)
BITS
7
6
5
4
3
2
1
0
POUT7
POUT6
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FD3H, FD7H, FDBH, FDFH, FE3H
ADDR
POUT[7:0]—Port Output Data
These bits contain the data to be driven to the port pins. The values are only driven if the
corresponding pin is configured as an output and the pin is not configured for alternate
function operation.
0 = Drive a logical 0 (Low).
1= Drive a logical 1 (High). High value is not driven if the drain has been disabled by set-
ting the corresponding Port Output Control register bit to 1.
LED Drive Enable Register
The LED Drive Enable register (Table 30) activates the controlled current drive. The Port
C pin must first be enabled by setting the Alternate Function register to select the LED
function.
.
Table 30. LED Drive Enable (LEDEN)
BITS
7
6
5
4
3
2
1
0
LEDEN[7:0]
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F82H
ADDR
LEDEN[7:0]—LED Drive Enable
These bits determine which Port C pins are connected to an internal current sink.
0 = Tristate the Port C pin.
1= Connect controlled current synch to Port C pin.
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LED Drive Level High Register
The LED Drive Level registers contain two control bits for each Port C pin (Table 31).
These two bits select between four programmable drive levels. Each pin is individually
programmable.
Table 31. LED Drive Level High Register (LEDLVLH)
BITS
7
6
5
4
3
2
1
0
LEDLVLH[7:0]
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F83H
ADDR
LEDLVLH[7:0]—LED Level High Bit
{LEDLVLH, LEDLVLL} select one of four programmable current drive levels for each
Port C pin.
00 = 3 mA
01= 7 mA
10= 13 mA
11= 20 mA
LED Drive Level Low Register
The LED Drive Level registers contain two control bits for each Port C pin (Table 32).
These two bits select between four programmable drive levels. Each pin is individually
programmable.
Table 32. LED Drive Level Low Register (LEDLVLL)
BITS
7
6
5
4
3
2
1
0
LEDLVLL[7:0]
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F84H
ADDR
LEDLVLH[7:0]—LED Level High Bit
{LEDLVLH, LEDLVLL} select one of four programmable current drive levels for each
Port C pin.
00 = 3 mA
01 = 7 mA
10 = 13 mA
11 = 20 mA
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Interrupt Controller
Overview
The interrupt controller on the Z8 Encore! XP® F1680 Series products prioritizes the
interrupt requests from the on-chip peripherals and the GPIO port pins. The features of the
interrupt controller include the following:
•
23 unique interrupt vectors:
–
–
16 GPIO port pin interrupt sources (seven are shared)
14 on-chip peripheral interrupt sources (three are shared)
•
Flexible GPIO interrupts
–
–
8 selectable rising and falling edge GPIO interrupts
4 dual-edge interrupts
•
•
3 levels of individually programmable interrupt priority
Watch-Dog Timer can be configured to generate an interrupt
Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly
manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt
service routine is involved with the exchange of data, status information, or control infor-
mation between the CPU and the interrupting peripheral. When the service routine is com-
pleted, the CPU returns to the operation from which it was interrupted.
The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,
the interrupt controller has no effect on operation. Refer to the eZ8 CPU User Manual for
more information regarding interrupt servicing by the eZ8 CPU. The eZ8 CPU User Man-
ual is available for download at www.zilog.com.
Interrupt Vector Listing
Table 33 lists all of the interrupts available in order of priority. The interrupt vector is
stored with the most significant byte (MSB) at the even Program Memory address and the
least significant byte (LSB) at the following odd Program Memory address.
Some port interrupts are not available on the 20- and 28-pin packages. The ADC interrupt
is unavailable on devices not containing an ADC.
Note:
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Table 33. Trap and Interrupt Vectors in Order of Priority
Program Memory
Priority Vector Address
Highest 0002H
0004H
Interrupt or Trap Source
Reset (not an interrupt)
Watch-Dog Timer (see Watch-Dog Timer chapter)
Primary Oscillator Fail Trap (not an interrupt)
Watchdog Oscillator Fail Trap (not an interrupt)
Illegal Instruction Trap (not an interrupt)
Timer 2
003AH
003CH
0006H
0008H
000AH
Timer 1
000CH
Timer 0
000EH
UART 0 receiver
0010H
UART 0 transmitter
2
0012H
I C
0014H
SPI
0016H
ADC
0018H
Port A7, selectable rising or falling input edge or LVD (see the chapter “Reset,
STOP Mode Recovery and Low Voltage Detection” on page 30)
001AH
001CH
001EH
0020H
0022H
0024H
0026H
0028H
002AH
002CH
002EH
0030H
0032H
0034H
Port A6, selectable rising or falling input edge or Comparator 0 Output
Port A5, selectable rising or falling input edge or Comparator 1 Output
Port A4 or Port D4, selectable rising or falling input edge
Port A3 or Port D3, selectable rising or falling input edge
Port A2 or Port D2, selectable rising or falling input edge
Port A1 or Port D1, selectable rising or falling input edge
Port A0, selectable rising or falling input edge
Reserved
Multi-channel Timer
UART 1 receiver
UART 1 transmitter
Port C3, both input edges
Port C2, both input edges
Port C1, both input edges
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Table 33. Trap and Interrupt Vectors in Order of Priority (Continued)
Program Memory
Priority Vector Address
Lowest 0036H
0038H
Interrupt or Trap Source
Port C0, both input edges
Reserved
Architecture
Figure 11 illustrates the interrupt controller block diagram.
High
Port Interrupts
Priority
Vector
Priority
Mux
IRQ Request
Medium
Priority
Internal Interrupts
Low
Priority
Figure 11.Interrupt Controller Block Diagram
Operation
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
•
•
Execution of an EI (Enable Interrupt) instruction
Execution of an IRET (Return from Interrupt) instruction
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•
Writing a 1 to the IRQEbit in the Interrupt Control register
Interrupts are globally disabled by any of the following actions:
•
•
•
•
•
•
•
•
Execution of a DI (Disable Interrupt) instruction
eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller
Writing a 0 to the IRQEbit in the Interrupt Control register
Reset
Execution of a Trap instruction
Illegal Instruction Trap
Primary Oscillator Fail Trap
Watch-Dog Oscillator Fail Trap
Interrupt Vectors and Priority
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest
priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all of
the interrupts are enabled with identical interrupt priority (all as Level 2 interrupts, for
example), the interrupt priority is assigned from highest to lowest as specified in Table 33
on page 69. Level 3 interrupts are always assigned higher priority than Level 2 interrupts
which, in turn, always are assigned higher priority than Level 1 interrupts. Within each
interrupt priority level (Level 1, Level 2, or Level 3), priority is assigned as specified in
Table 33, above. Reset, Watch-Dog Timer interrupt (if enabled), Primary Oscillator Fail
Trap, Watchdog Oscillator Fail Trap, and Illegal Instruction Trap always have highest
(level 3) priority.
Interrupt Assertion
Interrupt sources assert their interrupt requests for only a single-system clock period (sin-
gle pulse). When the interrupt request is acknowledged by the eZ8 CPU, the correspond-
ing bit in the Interrupt Request register is cleared until the next interrupt occurs. Writing a
0 to the corresponding bit in the Interrupt Request register likewise clears the interrupt
request.
The following coding style that clears bits in the Interrupt Request registers is NOT rec-
ommended. All incoming interrupts received between execution of the first LDX com-
mand and the final LDX command are lost.
Caution:
Poor coding style that can result in lost interrupt requests:
LDX r0, IRQ0
AND r0, MASK
LDX IRQ0, r0
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To avoid missing interrupts, use the following coding style to clear bits in
the Interrupt Request 0 register:
Caution:
Good coding style that avoids lost interrupt requests:
ANDX IRQ0, MASK
Software Interrupt Assertion
Program code can generate interrupts directly. Writing a 1 to the correct bit in the Interrupt
Request register triggers an interrupt (assuming that interrupt is enabled). When the inter-
rupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request register is
automatically cleared to 0.
The following coding style used to generate software interrupts by setting bits in the In-
terrupt Request registers is NOT recommended. All incoming interrupts received be-
tween execution of the first LDX command and the final LDX command are lost.
Caution:
Poor coding style that can result in lost interrupt requests:
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
To avoid missing interrupts, use the following coding style to set bits in the Interrupt
Request registers:
Caution:
Good coding style that avoids lost-interrupt requests:
ORX IRQ0, MASK
Interrupt Control Register Definitions
For all interrupts other than the Watch-Dog Timer interrupt, the Primary Oscillator Fail
Trap, and the Watchdog Oscillator Fail Trap, the interrupt control registers enable individ-
ual interrupts, set interrupt priorities, and indicate interrupt requests.
Interrupt Request 0 Register
The Interrupt Request 0 (IRQ0) register (Table 34) stores the interrupt requests for both
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ0 register becomes 1. If interrupts are globally enabled (vec-
tored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 0 register to determine if any interrupt requests are pending.
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Table 34. Interrupt Request 0 Register (IRQ0)
BITS
7
6
5
4
3
2
1
0
T2I
T1I
T0I
U0RXI
U0TXI
I2CI
SPII
ADCI
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC0H
ADDR
T2I—Timer 2 Interrupt Request
0 = No interrupt request is pending for Timer 2.
1 = An interrupt request from Timer 2 is awaiting service.
T1I—Timer 1 Interrupt Request
0 = No interrupt request is pending for Timer 1.
1 = An interrupt request from Timer 1 is awaiting service.
T0I—Timer 0 Interrupt Request
0 = No interrupt request is pending for Timer 0.
1 = An interrupt request from Timer 0 is awaiting service.
U0RXI—UART 0 Receiver Interrupt Request
0 = No interrupt request is pending for the UART 0 receiver.
1 = An interrupt request from the UART 0 receiver is awaiting service.
U0TXI—UART 0 Transmitter Interrupt Request
0 = No interrupt request is pending for the UART 0 transmitter.
1 = An interrupt request from the UART 0 transmitter is awaiting service.
I2CI—I2C Interrupt Request
0 = No interrupt request is pending for the I2C.
1 = An interrupt request from I2C is awaiting service.
SPII—SPI Interrupt Request
0 = No interrupt request is pending for the SPI.
1 = An interrupt request from the SPI is awaiting service.
ADCI—ADC Interrupt Request
0 = No interrupt request is pending for the Analog-to-Digital Converter.
1 = An interrupt request from the Analog-to-Digital Converter is awaiting service.
Interrupt Request 1 Register
The Interrupt Request 1 (IRQ1) register (Table 35) stores interrupt requests for both vec-
tored and polled interrupts. When a request is presented to the interrupt controller, the cor-
responding bit in the IRQ1 register becomes 1. If interrupts are globally enabled (vectored
interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts
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are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 1
register to determine if any interrupt requests are pending.
Table 35. Interrupt Request 1 Register (IRQ1)
BITS
7
6
5
4
3
2
1
0
PA7VI
PA6CI
PA5CI
PAD4I
PAD3I
PAD2I
PAD1I
PA0I
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC3H
ADDR
PA7VI—Port A7 or LVD Interrupt Request
0 = No interrupt request is pending for GPIO Port A7 or LVD.
1 = An interrupt request from GPIO Port A7 or LVD.
PA6CI—Port A6 or Comparator 0 Interrupt Request
0 = No interrupt request is pending for GPIO Port A6 or Comparator 0.
1 = An interrupt request from GPIO Port A6 or Comparator 0.
PA5CI—Port A5 or Comparator 1 Interrupt Request
0 = No interrupt request is pending for GPIO Port A5 or Comparator 1.
1 = An interrupt request from GPIO Port A5 or Comparator 1.
PADxI—Port A or Port D Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port A or Port D pin x.
1 = An interrupt request from GPIO Port A or Port D pin x is awaiting service.
where x indicates the specific GPIO Port pin number (1–4).
PA0I—Port A Pin 0 Interrupt Request
0 = No interrupt request is pending for GPIO Port A0.
1 = An interrupt request from GPIO Port A0 is awaiting service.
See Shared Interrupt Select Register for interrupt source select description.
Interrupt Request 2 Register
The Interrupt Request 2 (IRQ2) register (Table 36) stores interrupt requests for both vec-
tored and polled interrupts. When a request is presented to the interrupt controller, the cor-
responding bit in the IRQ2 register becomes 1. If interrupts are globally enabled (vectored
interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts
are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 2
register to determine if any interrupt requests are pending.
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Table 36. Interrupt Request 2 Register (IRQ2)
BITS
7
6
5
4
3
2
1
0
Reserved
MCTI
U1RXI
U1TXI
PC3I
PC2I
PC1I
PC0I
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC6H
ADDR
Reserved—Must be 0.
MCTI—Multi-channel timer Interrupt Request
0 = No interrupt request is pending for multi-channel timer.
1 = An interrupt request from multi-channel timer is awaiting service.
U1RXI—UART 1 Receiver Interrupt Request
0 = No interrupt request is pending for the UART 1 receiver.
1 = An interrupt request from the UART 1 receiver is awaiting service.
U1TXI—UART 1 Transmitter Interrupt Request
0 = No interrupt request is pending for the UART 1 transmitter.
1 = An interrupt request from the UART 1 transmitter is awaiting service.
PCxI—Port C Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port C pin x.
1 = An interrupt request from GPIO Port C pin x is awaiting service.
where x indicates the specific GPIO Port C pin number (0–3).
IRQ0 Enable High and Low Bit Registers
Table 37 describes the priority control for IRQ0. The IRQ0 Enable High and Low Bit reg-
isters (Tables 38 and 39) form a priority encoded enabling for interrupts in the Interrupt
Request 0 register. Priority is generated by setting bits in each register.
Table 37. IRQ0 Enable and Priority Encoding
IRQ0ENH[x] IRQ0ENL[x] Priority
Description
Disabled
Low
0
0
1
1
0
1
0
1
Disabled
Level 1
Level 2
Level 3
Nominal
High
where x indicates the register bits from 0–7.
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Table 38. IRQ0 Enable High Bit Register (IRQ0ENH)
BITS
7
6
5
4
3
2
1
0
T2ENH
T1ENH
T0ENH
U0RENH U0TENH I2CENH
SPIENH ADCENH
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC1H
ADDR
T2ENH—Timer 2 Interrupt Request Enable High Bit
T1ENH—Timer 1 Interrupt Request Enable High Bit
T0ENH—Timer 0 Interrupt Request Enable High Bit
U0RENH—UART 0 Receive Interrupt Request Enable High Bit
U0TENH—UART 0 Transmit Interrupt Request Enable High Bit
I2CENH—I2C Interrupt Request Enable High Bit
SPIENH—SPI Interrupt Request Enable High Bit
ADCENH—ADC Interrupt Request Enable High Bit
Table 39. IRQ0 Enable Low Bit Register (IRQ0ENL)
BITS
7
6
5
4
3
2
1
0
T2ENL
T1ENL
T0ENL
U0RENL U0TENL
I2CENL
SPIENL
ADCENL
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R
R
R/W
FC2H
ADDR
T2ENL—Timer 2 Interrupt Request Enable Low Bit
T1ENL—Timer 1 Interrupt Request Enable Low Bit
T0ENL—Timer 0 Interrupt Request Enable Low Bit
U0RENL—UART 0 Receive Interrupt Request Enable Low Bit
U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit
I2CENL—I2C Interrupt Request Enable Low Bit
SPIENL—SPI Interrupt Request Enable Low Bit
ADCENL—ADC Interrupt Request Enable Low Bit
IRQ1 Enable High and Low Bit Registers
Table 40 describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit reg-
isters (Tables 41 and 42) form a priority encoded enabling for interrupts in the Interrupt
Request 1 register. Priority is generated by setting bits in each register.
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Table 40. IRQ1 Enable and Priority Encoding
IRQ1ENH[x] IRQ1ENL[x] Priority
Description
Disabled
Low
0
0
1
1
0
1
0
1
Disabled
Level 1
Level 2
Level 3
Nominal
High
where x indicates the register bits from 0–7.
Table 41. IRQ1 Enable High Bit Register (IRQ1ENH)
BITS
7
6
5
4
3
2
1
0
PA6C0ENH PA5C1ENH
PA7VENH
PA4ENH PAD3ENH PAD2ENH PA1ENH PA0ENH
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC4H
ADDR
PA7VENH—Port A Bit[7] or LVD Interrupt Request Enable High Bit
PA6C0ENH—Port A Bit[6] or Comparator 0 Interrupt Request Enable High Bit
PA5C1ENH—Port A Bit[5] or Comparator 1 Interrupt Request Enable High Bit
PADxENH—Port A or Port D Bit[x] Interrupt Request Enable High Bit
PA0ENH—Port A Bit[0] Interrupt Request Enable High Bit
Refer to the Interrupt Port Select register for selection of either Port A or Port D as the
interrupt source.
Table 42. IRQ1 Enable Low Bit Register (IRQ1ENL)
BITS
7
6
5
4
3
2
1
0
PA6C0ENL PA5C1ENL
PA7VENL
PA4ENL
PA3ENL
PA2ENL
PA1ENL
PA0ENL
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC5H
ADDR
PA7VENL—Port A Bit[7] or LVD Interrupt Request Enable Low Bit
PA6C0ENL—Port A Bit[6] or Comparator 0 Interrupt Request Enable Low Bit
PA5C1ENL—Port A Bit[5] or Comparator 1 Interrupt Request Enable Low Bit
PADxENL—Port A or Port D Bit[x] Interrupt Request Enable Low Bit
PA0ENL—Port A Bit[0] Interrupt Request Enable Low Bit
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IRQ2 Enable High and Low Bit Registers
Table 43 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit reg-
isters (Tables 44 and 45) form a priority encoded enabling for interrupts in the Interrupt
Request 2 register. Priority is generated by setting bits in each register.
Table 43. IRQ2 Enable and Priority Encoding
IRQ2ENH[x] IRQ2ENL[x] Priority
Description
Disabled
Low
0
0
1
1
0
1
0
1
Disabled
Level 1
Level 2
Level 3
Nominal
High
where x indicates the register bits from 0–7.
Table 44. IRQ2 Enable High Bit Register (IRQ2ENH)
BITS
7
6
5
4
3
2
1
0
Reserved MCTENH U1RENH U1TENH
C3ENH
C2ENH
C1ENH
C0ENH
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC7H
ADDR
Reserved—Must be 0.
SPI1ENH—SPI1ENH Interrupt Request Enable High Bit
C3ENH—Port C3 Interrupt Request Enable High Bit
C2ENH—Port C2 Interrupt Request Enable High Bit
C1ENH—Port C1 Interrupt Request Enable High Bit
C0ENH—Port C0 Interrupt Request Enable High Bit
Table 45. IRQ2 Enable Low Bit Register (IRQ2ENL)
BITS
7
6
5
4
3
2
1
0
Reserved
SPI1ENL Reserved
C3ENL
0
C2ENL
0
C1ENL
0
C0ENL
0
FIELD
RESET
R/W
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC8H
ADDR
Reserved—Must be 0.
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SPI1ENL—SPI1ENL Interrupt Request Enable Low Bit
C3ENL—Port C3 Interrupt Request Enable Low Bit
C2ENL—Port C2 Interrupt Request Enable Low Bit
C1ENL—Port C1 Interrupt Request Enable Low Bit
C0ENL—Port C0 Interrupt Request Enable Low Bit
Interrupt Edge Select Register
The Interrupt Edge Select (IRQES) register (Table 46) determines whether an interrupt is
generated for the rising edge or falling edge on the selected GPIO Port A or Port D input
pin.
Table 46. Interrupt Edge Select Register (IRQES)
BITS
7
6
5
4
3
2
1
0
IES7
IES6
IES5
IES4
IES3
IES2
IES1
IES0
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FCDH
ADDR
IESx—Interrupt Edge Select x
0 = An interrupt request is generated on the falling edge of the PAx input or PDx.
1 = An interrupt request is generated on the rising edge of the PAx input PDx.
where x indicates the specific GPIO Port pin number (0 through 7).
Shared Interrupt Select Register
The Shared Interrupt Select (IRQSS) register (Table 47) determines the source of the
PADxS interrupts. The Shared Interrupt Select register selects between Port A and alter-
nate sources for the individual interrupts.
Because these shared interrupts are edge-triggered, it is possible to generate an interrupt
by switching from one shared source to another. For this reason, an interrupt must be dis-
abled before switching between sources.
Table 47. Shared Interrupt Select Register (IRQSS)
BITS
7
6
5
4
3
2
1
0
PA7VS
PA6CS
PA5CS
PAD4S
PAD3S
PAD2S
PAD1S
Reserved
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FCEH
ADDR
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PA7VS—PA7/LVD Selection
0 = PA7 is used for the interrupt for PA7VS interrupt request.
1 = The LVD is used for the interrupt for PA7VS interrupt request.
PA6CS—PA6/Comparator 0 Selection
0 = PA6 is used for the interrupt for PA6CS interrupt request.
1 = The Comparator 0 is used for the interrupt for PA6CS interrupt request.
PA5CS—PA5/Comparator 1 Selection
0 = PA5 is used for the interrupt for PA5CS interrupt request.
1 = The Comparator 1 is used for the interrupt for PA5CS interrupt request.
PADxS—PAx/PDx Selection
0 = PAx is used for the interrupt for PAx/PDx interrupt request
1 = PDx is used for the interrupt for PAx/PDx interrupt request
where x indicates the specific GPIO Port pin number (1–4).
Reserved—Must be 0.
Interrupt Control Register
The Interrupt Control (IRQCTL) register (Table 48) contains the master enable bit for all
interrupts.
Table 48. Interrupt Control Register (IRQCTL)
BITS
7
6
5
4
3
2
1
0
IRQE
Reserved
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
FCFH
ADDR
IRQE—Interrupt Request Enable
This bit is set to 1 by executing an EI (Enable Interrupts) or IRET (Interrupt Return)
instruction, or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI
instruction, eZ8 CPU acknowledgement of an interrupt request, Reset or by a direct regis-
ter write of a 0 to this bit.
0 = Interrupts are disabled.
1 = Interrupts are enabled.
Reserved—Must be 0.
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Timers
Overview
The Z8 Encore! XP® F1680 Series products contain three 16-bit reloadable timers that can
be used for timing, event counting, or generation of pulse-width modulated (PWM) sig-
nals. The timers’ features include:
•
•
•
•
•
•
16-bit reload counter
Programmable prescaler with prescale values from 1 to 128
PWM output generation
Capture and compare capability
2 independent capture/compare channels which reference the common timer
External input pin for timer input, clock gating, or capture signal. External input pin signal
frequency is limited to a maximum of one-fourth the timer clock frequency.
•
•
•
•
Timer output pin
Timer interrupt
Noise Filter on Timer input signal
Operation in Stop Mode with 32KHz secondary oscillator
In addition to the timers described in this chapter, the Baud Rate Generator of unused
UART peripheral may also be used to provide basic timing functionality. Refer to the
UART chapter for information on using the Baud Rate Generator as additional timers.
Architecture
Figure 12 illustrates the architecture of the timers.
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Timer Block
Timer
Control
Data
Bus
Block
Control
16-Bit
Reload Register
Interrupt,
PWM,
Timer
Interrupt
and
Peripheral
Clock
System
Clock
Timer Output
Control
TOUT
TOUT
16-Bit Counter
with Prescaler
Timer
Input
Gate
Input
2 16-Bit
PWM/Compare
Capture
Input
Figure 12.Timer Block Diagram
Operation
The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value
0001H into the Timer Reload High and Low Byte registers and setting the prescale value
to 1. Maximum time-out delay is set by loading the value 0000H into the Timer Reload
High and Low Byte registers and setting the prescale value to 128. If the Timer reaches
FFFFH, the timer rolls over to 0000H and continues counting.
Timer Clock Source
The timer clock source can come from either the peripheral clock or the system clock.
Peripheral clock is based on a low frequency/low power 32 KHz secondary oscillator that
can be used with external watch crystal. Peripheral clock source is only available for driv-
ing Timer and Noise Filter operation. It is not supported for other peripherals.
For timer operation in Stop Mode peripheral clock should be selected as the clock source.
Peripheral clock can be selected as source for both active and stop-mode operation. Sys-
tem clock is only for operation in active and Halt modes. System clock is software select-
able in Oscillator Control Module as external high frequency crystal or internal precision
oscillator.
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The TCLKS field in the Timer Control 2 register selects the timer clock source.
To ensure error-free operation, disable the timer before modifying its operation or
changing the timer clock source. This is recommended especially when the timer is op-
erating on a peripheral clock. In this case, the timer clock is asynchronous to the CPU
clock and any write to the timer control register should be done only after disabling the
timer to avoid erroneous operation. When Timer use peripheral clock and Timer is enal-
bed, read from Timer is not recommended.
Caution:
Low Power Modes
Operation in Halt Mode
When the eZ8 CPU enters Halt Mode, the timer will continue to operate if enabled. To
minimize current in Halt mode, the timer can be disabled by clearing the TEN control bit.
The noise filter, if enabled, will also continue to operate in halt mode and rejects any noise
on the timer input pin.
Operation in Stop Mode
When the eZ8 CPU enters Stop Mode, the timer will continue to operate if enabled and
peripheral clock is chosen as the clock source. In Stop Mode, the timer interrupt (if
enabled) automatically initiates a Stop Mode Recovery and generates an interrupt request.
In the Reset Status Register, the stop bit is set to 1. Also, timer interrupt request bit in
Interrupt Request 0 register is set. Following completion of the Stop Mode Recovery, if
interrupts are enabled, the CPU responds to the interrupt request by fetching the timer
interrupt vector. The noise filter, if enabled, will also continue to operate in stop mode and
rejects any noise on the timer input pin.
If system clock is chosen as the clock source the timer ceases to operate as the system
clock and is put into Stop Mode. In this case the registers are not reset and operation will
resume once stop-mode recovery occurs.
Power Reduction during operation
Removal of the TEN bit will inhibit clocking of the entire timer block. The CPU can still
read/write registers when the enable bit(s) are taken out.
Timer Operating Modes
The timers can be configured to operate in the following modes:
One-Shot Mode
In One-Shot mode, the timer counts up to the 16-bit Reload value stored in the Timer
Reload High and Low Byte registers. The Timer counts timer clocks up to the 16-bit
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Reload value. Upon reaching the Reload value, the timer generates an interrupt and the
count value in the Timer High and Low Byte registers is reset to 0001H. Then, the timer is
automatically disabled and stops counting.
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
for one clock cycle (from Low to High or from High to Low) upon timer Reload. If it is
desired to have the Timer Output make a permanent state change upon One-Shot time-out,
first set the TPOL bit in the Timer Control 1 register to the start value before beginning
One-Shot mode. Then, after starting the timer, set TPOL to the opposite bit value.
The steps for configuring a timer for One-Shot mode and initiating the count are as fol-
lows:
1. Write to the Timer Control 1 register to:
–
–
–
–
Disable the timer
Configure the timer for One-Shot mode.
Set the prescale value.
If using the Timer Output alternate function, set the initial output level (High or
Low).
2. Write to the Timer Control 2 register to choose the timer clock source
3. Write to the Timer Control 0 register to set the timer interrupt configuration field
TICONFIG
4. Write to the Timer High and Low Byte registers to set the starting count value.
5. Write to the Timer Reload High and Low Byte registers to set the Reload value.
6. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
7. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
8. Write to the Timer Control 1 register to enable the timer and initiate counting.
In One-Shot mode, the timer clock always provides the timer input. The timer period is
given by the following equation:
(Reload Value - Start Value) × Prescale
One-Shot Mode Time-Out Period (s) = -----------------------------------------------------------------------------------------------
Timer Clock Frequency (Hz)
Triggered One-Shot Mode
In Triggered One-Shot mode, the Timer operates as follows:
1. The Timer idles until a trigger is received. The Timer trigger is taken from the GPIO
Port pin Timer Input alternate function. The TPOL bit in the Timer Control 1 register
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selects whether the trigger occurs on the rising edge or the falling edge of the Timer
Input signal.
2. Following the trigger event, the Timer counts timer clocks up to the 16-bit Reload
value stored in the Timer Reload High and Low Byte registers.
3. Upon reaching the Reload value, the Timer outputs a pulse on the Timer Output pin,
generates an interrupt, and resets the count value in the Timer High and Low Byte
registers to 0001H. The period of the output pulse is a single timer clock. The TPOL
bit also sets the polarity of the output pulse.
4. The Timer now idles until the next trigger event.
In Triggered One-Shot mode, the timer clock always provides the timer input. The timer
period is given by the following equation:
(Reload Value - Start Value) × Prescale
Triggered One-Shot Mode Time-Out Period (s) = -----------------------------------------------------------------------------------------------
Timer Clock Frequency (Hz)
Table 49 provides an example initialization sequence for configuring Timer 0 in Triggered
One-Shot mode and initiating operation.
Table 49. Triggered One-Shot Mode Initialization Example
Register
T0CTL0
T0CTL1
T0CTL2
Value
E0H
03H
01H
Comment
TMODE[3:0] = 1011Bselects Triggered One-Shot
mode.
TICONFIG[1:0] = 11B enables interrupts on Timer
reload only.
CSC = 0 selects the Timer Input (Trigger) from the GPIO
pin.
PWMD[2:0] = 000B has no effect.
INPCAP = 0 has no effect.
TEN = 0 disables the timer.
TPOL = 0 enables triggering on rising edge of Timer
Input and sets Timer Out signal to 0.
PRES[2:0] = 000B sets prescaler to divide by 1.
TCLKS = 1 sets 32KHz peripheral clock as the Timer
clock source
T0H
T0L
00H
01H
ABH
CDH
02H
11B
Timer starting value = 0001H.
T0RH
Timer reload value = ABCDH.
T0RL
PAADDR
PACTL[1:0]
Selects Port A Alternate Function control register.
PACTL[0] enables Timer 0 Input alternate function.
PACTL[1] enables Timer 0 Output alternate function.
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Table 49. Triggered One-Shot Mode Initialization Example (Continued)
Register
IRQ0ENH[5]
IRQ0ENL[5]
T0CTL1
Value
0B
Comment
Disables the Timer 0 interrupt.
0B
83H
TEN = 1 enables the timer. All other bits left in desired
settings.
Note: After receiving the input trigger, Timer 0 will:
1) Count ABCDH timer clocks.
2) Upon Timer 0 reload, generate single clock cycle active High output pulse on Timer 0
Ouput pin.
3) Wait for next input trigger event.
Continuous Mode
In Continuous mode, the timer counts up to the 16-bit Reload value stored in the Timer
Reload High and Low Byte registers. The Timer counts timer clocks up to the 16-bit
Reload value.. Upon reaching the Reload value, the timer generates an interrupt, the count
value in the Timer High and Low Byte registers is reset to 0001H and counting resumes.
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
(from Low to High or from High to Low) upon timer Reload.
The steps for configuring a timer for Continuous mode and initiating the count are as fol-
lows:
1. Write to the Timer Control 1 register to:
–
–
–
–
Disable the timer
Configure the timer for Continuous mode.
Set the prescale value.
If using the Timer Output alternate function, set the initial output level (High or
Low).
2. Write to the Timer Control 2 register to choose the timer clock source
3. Write to the Timer Control 0 register to set the timer interrupt-configuration field
TICONFIG
4. Write to the Timer High and Low Byte registers to set the starting count value (usually
0001H). This only affects the first pass in Continuous mode. After the first timer
Reload in Continuous mode, counting always begins at the reset value of 0001H.
5. Write to the Timer Reload High and Low Byte registers to set the Reload value.
6. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
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7. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
8. Write to the Timer Control 1 register to enable the timer and initiate counting.
In Continuous mode, the timer clock always provides the timer input. The timer period is
given by the following equation:
Reload Value × Prescale
Continuous Mode Time-Out Period (s) = ---------------------------------------------------------------------
Timer Clock Frequency (Hz)
If an initial starting value other than 0001H is loaded into the Timer High and Low Byte
registers, the One-Shot mode equation must be used to determine the first time-out period.
Counter Mode
In Counter mode, the timer counts input transitions from a GPIO port pin. The timer input
is taken from the GPIO Port pin Timer Input alternate function. The TPOL bit in the Timer
Control 1 register selects whether the count occurs on the rising edge or the falling edge of
the Timer Input signal. In Counter mode, the prescaler is disabled.
The input frequency of the Timer Input signal must not exceed one-fourth the timer
clock frequency.
Caution:
Upon reaching the Reload value stored in the Timer Reload High and Low Byte registers,
the timer generates an interrupt, the count value in the Timer High and Low Byte registers
is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is
enabled, the Timer Output pin changes state (from Low to High or from High to Low) at
timer Reload.
The steps for configuring a timer for Counter mode and initiating the count are as follows:
1. Write to the Timer Control 1 register to:
–
–
–
Disable the timer
Configure the timer for Counter mode.
Select either the rising edge or falling edge of the Timer Input signal for the count.
This also sets the initial logic level (High or Low) for the Timer Output alternate
function. However, the Timer Output function does not have to be enabled.
2. Write to the Timer Control 2 register to choose the timer clock source
3. Write to the Timer Control 0 register to set the timer interrupt configuration field
TICONFIG
4. Write to the Timer High and Low Byte registers to set the starting count value. This
only affects the first pass in Counter mode. After the first timer Reload in Counter
mode, counting always begins at the reset value of 0001H. Generally, in Counter
mode the Timer High and Low Byte registers must be written with the value 0001H.
5. Write to the Timer Reload High and Low Byte registers to set the Reload value.
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6. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
7. Configure the associated GPIO port pin for the Timer Input alternate function.
8. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
9. Write to the Timer Control 1 register to enable the timer.
In Counter mode, the number of Timer Input transitions since the timer start is given by
the following equation:
Counter Mode Timer Input Transitions = Current Count Value - Start Value
Comparator Counter Mode
In Comparator Counter mode, the timer counts output transitions from an analog compar-
ator output. Timer 0 takes its input from the output of Comparator 0. Timer 1 takes its
input from the output of Comparator 1. The TPOL bit in the Timer Control 1 register
selects whether the count occurs on the rising edge or the falling edge of the comparator-
output signal. In Comparator Counter mode, the prescaler is disabled.
The frequency of the comparator-output signal must not exceed one-fourth the timer
clock frequency.
Caution:
Upon reaching the Reload value stored in the Timer Reload High and Low Byte registers,
the timer generates an interrupt, the count value in the Timer High and Low Byte registers
is reset to 0001H and counting resumes. Also, if the Timer Output alternate function is
enabled, the Timer Output pin changes state (from Low to High or from High to Low) at
timer Reload.
The steps for configuring a timer for Comparator Counter mode and initiating the count
are as follows:
1. Write to the Timer Control 1 register to:
–
–
–
Disable the timer
Configure the timer for Comparator Counter mode.
Select either the rising edge or falling edge of the comparator output signal for the
count. This also sets the initial logic level (High or Low) for the Timer Output
alternate function. However, the Timer Output function does not have to be
enabled.
2. Write to the Timer Control 2 register to choose the timer clock source
3. Write to the Timer Control 0 register to set the timer interrupt configuration field
TICONFIG
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4. Write to the Timer High and Low Byte registers to set the starting count value. This
only affects the first pass in Comparator Counter mode. After the first timer Reload in
Comparator Counter mode, counting always begins at the reset value of 0001H.
Generally, in Comparator Counter mode the Timer High and Low Byte registers must
be written with the value 0001H.
5. Write to the Timer Reload High and Low Byte registers to set the Reload value.
6. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
7. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
8. Write to the Timer Control 1 register to enable the timer.
In Comparator Counter mode, the number of comparator output transitions since the timer
start is given by the following equation:
Comparator Output Transitions = Current Count Value - Start Value
PWM Single Output Mode
In PWM Single Output mode, the timer outputs a Pulse-Width Modulator (PWM) output
signal through a GPIO Port pin. The Timer counts timer clocks up to the 16-bit Reload
value. The timer first counts up to the 16-bit PWM match value stored in the Timer
PWM0 High and Low Byte registers. When the timer count value matches the PWM
value, the Timer Output toggles. The timer continues counting until it reaches the Reload
value stored in the Timer Reload High and Low Byte registers. Upon reaching the Reload
value, the timer generates an interrupt, the count value in the Timer High and Low Byte
registers is reset to 0001H and counting resumes.
If the TPOL bit in the Timer Control 1 register is set to 1, the Timer Output signal begins
as a High (1) and then transitions to a Low (0) when the timer value matches the PWM
value. The Timer Output signal returns to a High (1) after the timer reaches the Reload
value and is reset to 0001H.
If the TPOL bit in the Timer Control 1 register is set to 0, the Timer Output signal begins
as a Low (0) and then transitions to a High (1) when the timer value matches the PWM
value. The Timer Output signal returns to a Low (0) after the timer reaches the Reload
value and is reset to 0001H.
The steps for configuring a timer for PWM Single Output mode and initiating the PWM
operation are as follows:
1. Write to the Timer Control 1 register to:
–
–
Disable the timer
Configure the timer for PWM mode.
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–
–
Set the prescale value.
Set the initial logic level (High or Low) and PWM High/Low transition for the
Timer Output alternate function.
2. Write to the Timer Control 2 register to choose the timer clock source
3. Write to the Timer Control 0 register to set the timer interrupt configuration field
TICONFIG
4. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H). This only affects the first pass in PWM mode. After the first timer
reset in PWM mode, counting always begins at the reset value of 0001H.
5. Write to the Timer PWM0 High and Low Byte registers to set the PWM value.
6. Write to the Timer Reload High and Low Byte registers to set the Reload value (PWM
period). The Reload value must be greater than the PWM value.
7. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
8. Configure the associated GPIO port pin for the Timer Output alternate function.
9. Write to the Timer Control 1 register to enable the timer and initiate counting.
The PWM period is given by the following equation:
Reload Value × Prescale
PWM Period (s) = ---------------------------------------------------------------------
Timer Clock Frequency (Hz)
If an initial starting value other than 0001H is loaded into the Timer High and Low Byte
registers, the One-Shot mode equation must be used to determine the first PWM time-out
period.
If TPOL is set to 0, the ratio of the PWM output High time to the total period is given by:
Reload Value - PWM Value
-------------------------------------------------------------------
PWM Output High Time Ratio (%) =
× 100
Reload Value
If TPOL is set to 1, the ratio of the PWM output High time to the total period is given by:
PWM Value
Reload Value
--------------------------------
PWM Output High Time Ratio (%) =
× 100
PWM Dual Output Mode
In PWM Dual Output mode, the timer outputs a Pulse-Width Modulator (PWM) output
signal and also its complement through two GPIO Port pins. The Timer counts timer
clocks up to the 16-bit Reload value. The timer first counts up to the 16-bit PWM match
value stored in the Timer PWM0 High and Low Byte registers. When the timer count
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value matches the PWM value, the Timer Outputs (TOUT and TOUT) toggle. The timer
continues counting until it reaches the Reload value stored in the Timer Reload High and
Low Byte registers. Upon reaching the Reload value, the timer generates an interrupt, the
count value in the Timer High and Low Byte registers is reset to 0001H, TOUT and
TOUT toggling again, and counting resumes.
If the TPOL bit in the Timer Control 1 register is set to 1, the Timer Output signal begins
as a High (1) and then transitions to a Low (0) when the timer value matches the PWM
value. The Timer Output signal returns to a High (1) after the timer reaches the Reload
value and is reset to 0001H.
If the TPOL bit in the Timer Control 1 register is set to 0, the Timer Output signal begins
as a Low (0) and then transitions to a High (1) when the timer value matches the PWM
value. The Timer Output signal returns to a Low (0) after the timer reaches the Reload
value and is reset to 0001H.
The timer also generates a second PWM output signal, Timer Output Complement
(TOUT). TOUT is the complement of the Timer Output PWM signal (TOUT). A pro-
grammable deadband delay can be configured to time delay (0 to 128 timer clock cycles)
PWM output transitions on these two pins from a Low to a High (inactive to active). This
ensures a time gap between the removal of one PWM output to the assertion of its comple-
ment.
The steps for configuring a timer for PWM Dual Output mode and initiating the PWM
operation are as follows:
1. Write to the Timer Control 1 register to:
–
–
Disable the timer
Configure the timer for PWM Dual Output mode. Setting the mode also involves
writing to TMODEHI bit in TxCTL0 register.
–
–
Set the prescale value.
Set the initial logic level (High or Low) and PWM High/Low transition for the
Timer Output alternate function.
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H). This only affects the first pass in PWM mode. After the first timer
reset in PWM mode, counting always begins at the reset value of 0001H.
3. Write to the Timer PWM0 High and Low Byte registers to set the PWM value.
4. Write to the Timer Control 0 register:
–
–
to set the PWM dead band delay value
to choose the timer clock source
5. Write to the Timer Control 0 register to set the timer interrupt configuration field
TICONFIG
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6. Write to the Timer Reload High and Low Byte registers to set the Reload value (PWM
period). The Reload value must be greater than the PWM value.
7. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
8. Configure the associated GPIO port pin for the Timer Output and Timer Output
Complement alternate functions.
9. Write to the Timer Control 1 register to enable the timer and initiate counting.
The PWM period is given by the following equation:
Reload Value × Prescale
PWM Period (s) = ----------------------------------------------------------------------
Timer Clock Frequency (Hz)
If an initial starting value other than 0001H is loaded into the Timer High and Low Byte
registers, the One-Shot mode equation must be used to determine the first PWM time-out
period.
If TPOL is set to 0, the ratio of the PWM output High time to the total period is given by:
Reload Value - PWM Value
-------------------------------------------------------------------
PWM Output High Time Ratio (%) =
× 100
Reload Value
If TPOL is set to 1, the ratio of the PWM output High time to the total period is given by:
PWM Value
Reload Value
--------------------------------
PWM Output High Time Ratio (%) =
× 100
Capture Mode
In Capture mode, the current timer count value is recorded when the desired external
Timer Input transition occurs. The Capture count value is written to the Timer PWM0
High and Low Byte Registers. The Timer counts timer clocks up to the 16-bit Reload
value. The TPOL bit in the Timer Control 1 register determines if the Capture occurs on a
rising edge or a falling edge of the Timer Input signal. When the Capture event occurs, an
interrupt is generated and the timer continues counting. The INPCAP bit in Timer Control
0 register is set to indicate the timer interrupt is due to an input capture event.
The timer continues counting up to the 16-bit Reload value stored in the Timer Reload
High and Low Byte registers. Upon reaching the Reload value, the timer generates an
interrupt and continues counting. The INPCAP bit in Timer Control 0 register is cleared to
indicate the timer interrupt is not due to an input capture event.
The steps for configuring a timer for Capture mode and initiating the count are as follows:
1. Write to the Timer Control 1 register to:
–
Disable the timer
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–
–
–
Configure the timer for Capture mode.
Set the prescale value.
Set the Capture edge (rising or falling) for the Timer Input.
2. Write to the Timer Control 2 register to choose the timer clock source
3. Write to the Timer Control 0 register to set the timer interrupt configuration field
TICONFIG
4. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H).
5. Write to the Timer Reload High and Low Byte registers to set the Reload value.
6. Clear the Timer PWM High and Low Byte registers to 0000H. This allows user
software to determine if interrupts were generated by either a capture event or a
reload. If the PWM High and Low Byte registers still contain 0000H after the
interrupt, then the interrupt was generated by a Reload.
7. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers. By default, the timer interrupt will be generated for
both input capture and reload events. If desired, configure the timer interrupt to be
generated only at the input capture event or the reload event by setting TICONFIG
field of the Timer Control 0 register.
8. Configure the associated GPIO port pin for the Timer Input alternate function.
9. Write to the Timer Control 1 register to enable the timer and initiate counting.
In Capture mode, the elapsed time from timer start to Capture event can be calculated
using the following equation:
(Capture Value - Start Value) × Prescale
Capture Elapsed Time (s) = -------------------------------------------------------------------------------------------------
Timer Clock Frequency (Hz)
Capture Restart Mode
In Capture Restart mode, the current timer count value is recorded when the desired exter-
nal Timer Input transition occurs. The Capture count value is written to the Timer PWM
High and Low Byte Registers. The Timer counts timer clocks up to the 16-bit Reload
value. The TPOL bit in the Timer Control 1 register determines if the Capture occurs on a
rising edge or a falling edge of the Timer Input signal. When the Capture event occurs, an
interrupt is generated and the count value in the Timer High and Low Byte registers is
reset to 0001H and counting resumes. The INPCAP bit in Timer Control 0 register is set to
indicate the timer interrupt is due to an input capture event.
If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer
generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
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0001H and counting resumes. The INPCAP bit in Timer Control 0 register is cleared to
indicate the timer interrupt is not due to an input capture event.
The steps for configuring a timer for Capture Restart mode and initiating the count are as
follows:
1. Write to the Timer Control 1 register to:
–
–
Disable the timer
Configure the timer for Capture Restart mode. Setting the mode also involves
writing to TMODEHI bit in TxCTL1 register.
–
–
Set the prescale value.
Set the Capture edge (rising or falling) for the Timer Input.
2. Write to the Timer Control 2 register to choose the timer clock source
3. Write to the Timer Control 0 register to set the timer interrupt configuration field
TICONFIG
4. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H).
5. Write to the Timer Reload High and Low Byte registers to set the Reload value.
6. Clear the Timer PWM High and Low Byte registers to 0000H. This allows user
software to determine if interrupts were generated by either a capture event or a
reload. If the PWM High and Low Byte registers still contain 0000H after the
interrupt, then the interrupt was generated by a Reload.
7. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers. By default, the timer interrupt will be generated for
both input capture and reload events. If desired, configure the timer interrupt to be
generated only at the input capture event or the reload event by setting TICONFIG
field of the Timer Control 0 register.
8. Configure the associated GPIO port pin for the Timer Input alternate function.
9. Write to the Timer Control 1 register to enable the timer and initiate counting.
In Capture mode, the elapsed time from timer start to Capture event can be calculated
using the following equation:
(Capture Value - Start Value) × Prescale
Capture Elapsed Time (s) = -------------------------------------------------------------------------------------------------
Timer Clock Frequency (Hz)
Compare Mode
In Compare mode, the timer counts up to the 16-bit maximum Compare value stored in the
Timer Reload High and Low Byte registers. The Timer counts timer clocks up to the 16-
bit Reload value. Upon reaching the Compare value, the timer generates an interrupt and
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counting continues (the timer value is not reset to 0001H). Also, if the Timer Output alter-
nate function is enabled, the Timer Output pin changes state (from Low to High or from
High to Low) upon Compare.
If the Timer reaches FFFFH, the timer rolls over to 0000H and continue counting.
The steps for configuring a timer for Compare mode and initiating the count are as fol-
lows:
1. Write to the Timer Control 1 register to:
–
–
–
–
Disable the timer
Configure the timer for Compare mode.
Set the prescale value.
Set the initial logic level (High or Low) for the Timer Output alternate function, if
desired.
2. Write to the Timer Control 2 register to choose the timer clock source
3. Write to the Timer Control 0 register to set the timer interrupt configuration field
TICONFIG
4. Write to the Timer High and Low Byte registers to set the starting count value.
5. Write to the Timer Reload High and Low Byte registers to set the Compare value.
6. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
7. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
8. Write to the Timer Control 1 register to enable the timer and initiate counting.
In Compare mode, the timer clock always provides the timer input. The Compare time is
given by the following equation:
(Compare Value - Start Value) × Prescale
Compare Mode Time (s) = ----------------------------------------------------------------------------------------------------
Timer Clock Frequency (Hz)
Gated Mode
In Gated mode, the timer counts only when the Timer Input signal is in its active state
(asserted), as determined by the TPOL bit in the Timer Control 1 register. When the Timer
Input signal is asserted, counting begins. A timer interrupt is generated when the Timer
Input signal is deassertedeassertd or a timer reload occurs. To determine if a Timer Input
signal removal generated the interrupt, read the associated GPIO input value and compare
to the value stored in the TPOL bit.
The timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low
Byte registers. The timer input is the timer clock. When reaching the Reload value, the
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timer generates an interrupt, the count value in the Timer High and Low Byte registers is
reset to 0001H and counting resumes (assuming the Timer Input signal is still asserted).
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
(from Low to High or from High to Low) at timer reset.
The steps for configuring a timer for Gated mode and initiating the count are as follows:
1. Write to the Timer Control 1 register to:
–
–
–
Disable the timer
Configure the timer for Gated mode.
Set the prescale value.
2. Write to the Timer Control 2 register to choose the timer clock source
3. Write to the Timer Control 0 register to set the timer interrupt configuration field
TICONFIG
4. Write to the Timer High and Low Byte registers to set the starting count value. This
only affects the first pass in Gated mode. After the first timer reset in Gated mode,
counting always begins at the reset value of 0001H.
5. Write to the Timer Reload High and Low Byte registers to set the Reload value.
6. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers. By default, the timer interrupt will be generated for
both input deassertion and reload events. If desired, configure the timer interrupt to be
generated only at the input deassertion event or the reload event by setting TICONFIG
field of the Timer Control 0 register.
7. Configure the associated GPIO port pin for the Timer Input alternate function.
8. Write to the Timer Control 1 register to enable the timer.
9. Assert the Timer Input signal to initiate the counting.
Capture/Compare Mode
In Capture/Compare mode, the timer begins counting on the first external Timer Input
transition. The desired transition (rising edge or falling edge) is set by the TPOL bit in the
Timer Control 1 register. The Timer counts timer clocks up to the 16-bit Reload value.
Every subsequent desired transition (after the first) of the Timer Input signal captures the
current count value. The Capture value is written to the Timer PWM0 High and Low Byte
Registers. When the Capture event occurs, an interrupt is generated, the count value in the
Timer High and Low Byte registers is reset to 0001H, and counting resumes. The INPCAP
bit in Timer Control 0 register is set to indicate the timer interrupt is due to an input cap-
ture event.
If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the Compare value, the timer
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generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
0001H and counting resumes. The INPCAP bit in Timer Control 0 register is cleared to
indicate the timer interrupt is not due to an input capture event.
The steps for configuring a timer for Capture/Compare mode and initiating the count are
as follows:
1. Write to the Timer Control 1 register to:
–
–
–
–
Disable the timer
Configure the timer for Capture/Compare mode.
Set the prescale value.
Set the Capture edge (rising or falling) for the Timer Input.
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H).
3. Write to the Timer Control 2 register to choose the timer clock source
4. Write to the Timer Control 0 register to set the timer interrupt configuration field
TICONFIG
5. Write to the Timer Reload High and Low Byte registers to set the Compare value.
6. If desired, enable the timer interrupt and set the timer-interrupt priority by writing to
the relevant interrupt registers.By default, the timer interrupt will be generated for
both input capture and reload events. If desired, configure the timer interrupt to be
generated only at the input capture event or the reload event by setting TICONFIG
field of the Timer Control 0 register.
7. Configure the associated GPIO port pin for the Timer Input alternate function.
8. Write to the Timer Control 1 register to enable the timer.
9. Counting begins on the first appropriate transition of the Timer Input signal. No
interrupt is generated by this first edge.
In Capture/Compare mode, the elapsed time from timer start to Capture event can be cal-
culated using the following equation:
(Capture Value - Start Value) × Prescale
Capture Elapsed Time (s) = -------------------------------------------------------------------------------------------------
Timer Clock Frequency (Hz)
Demodulation Mode
In Demodulation mode, the timer begins counting on the first external Timer Input transi-
tion. The desired transition (rising edge or falling edge or both) is set by the TPOL bit in
the Timer Control 1 register and TPOLHI bit in the Timer Control 2 register. The Timer
counts timer clocks up to the 16-bit Reload value.
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Every subsequent desired transition (after the first) of the Timer Input signal captures the
current count value. The Capture value is written to the Timer PWM0 High and Low Byte
Registers for rising input edges of the timer input signal. For falling edges the capture
count value is written to the Timer PWM1 High and Low Byte Registers. The TPOL bit in
the Timer Control 1 register determines if the Capture occurs on a rising edge or a falling
edge of the Timer Input signal. If the TPOLHI bit in the Timer Control 2 register is set,
Capture is done on both the rising and falling edges of the input signal.
Whenever the Capture event occurs, an interrupt is generated and the timer continues
counting. The corresponding event flag bit PWMxEF in Timer Status register is set to
indicate the timer interrupt is due to an input capture event.
The timer counts up to the 16-bit Compare value stored in the Timer Reload High and
Low Byte registers. Upon reaching the Reload value, the timer generates an interrupt, the
count value in the Timer High and Low Byte registers is reset to 0001H and counting
resumes. The RTOEF event flag bit in Timer Status register is set to indicate the timer
interrupt is due to a reload event. Software can use this bit to determine if a reload
occurred prior to a Capture.
The steps for configuring a timer for Demodulation mode and initiating the count are as
follows:
1. Write to the Timer Control 1 register to:
–
–
Disable the timer
Configure the timer for Demodulation mode. Setting the mode also involves
writing to TMODEHI bit in TxCTL0 register.
–
–
Set the prescale value.
Set TPOL bit to set the Capture edge (rising or falling) for the Timer Input. This
applies only if TPOLHI bit in TxCTL2 register is not set.
2. Write to the Timer Control 2 register to:
–
–
Choose the timer clock source
Set the TPOLHI bit if the Capture required on both edges of the input signal.
3. Write to the Timer Control 0 register to set the timer interrupt configuration field
TICONFIG
4. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H).
5. Write to the Timer Reload High and Low Byte registers to set the Reload value.
6. Clear the Timer TxPWM0 and TxPWM1 High and Low Byte registers to 0000H.
7. If desired, enable the noise filter and set the noise filter control by writing to the
relevant bits in the Noise Filter Control Register.
8. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers. By default, the timer interrupt will be generated for
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both input capture and reload events. If desired, configure the timer interrupt to be
generated only at the input capture event or the reload event by setting TICONFIG
field of the Timer Control 0 register.
9. Configure the associated GPIO port pin for the Timer Input alternate function.
10. Write to the Timer Control 1 register to enable the timer. Counting will start on the
occurrence of the first external input transition.
In Demodulation mode, the elapsed time from timer start to Capture event can be calcu-
lated using the following equation:
(Capture Value - Start Value) × Prescale
Capture Elapsed Time (s) = -------------------------------------------------------------------------------------------------
Timer Clock Frequency (Hz)
Table 50 provides an example initialization sequence for configuring Timer 0 in Demodu-
lation mode and initiating operation.
Table 50. Demodulation Mode Initialization Example
Register
T0CTL0
T0CTL1
T0CTL2
Value
C0H
04H
11H
Comment
TMODE[3:0] = 1100B selects Demodulation mode.
TICONFIG[1:0] = 10B enables interrupt only on Capture
events.
CSC = 0 selects the Timer Input from the GPIO pin.
PWMD[2:0] = 000B has no effect.
INPCAP = 0 has no effect.
TEN = 0 disables the timer.
PRES[2:0] = 000B sets prescaler to divide by 1.
TPOLHI,TPOL = 10 enables trigger and Capture on
both rising and fallling edges of Timer Input.
TCLKS = 1 enables 32KHz peripheral clock as timer
clock source
T0H
T0L
00H
01H
ABH
CDH
00H
00H
00H
00H
C0H
Timer starting value = 0001H.
Timer reload value = ABCDH.
Initial PWM0 value = 0000H
Initial PWM1 value = 0000H
T0RH
T0RL
T0PWM0H
T0PWM0L
T0PWM1H
T0PWM1H
T0NFC
NFEN = 1 enables noise filter
NFCTL = 100B enables 8-bit up/down counter
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Table 50. Demodulation Mode Initialization Example (Continued)
Register
PAADDR
Value
02H
11B
Comment
Selects Port A Alternate Function control register.
PACTL[1:0]
PACTL[0] enables Timer 0 Input alternate function.
PACTL[1] enables Timer 0 Output alternate function.
IRQ0ENH[5]
IRQ0ENL[5]
T0CTL1
0B
0B
Disables the Timer 0 interrupt.
84H
TEN = 1 enables the timer. All other bits left in desired
settings.
Notes: After receiving the input trigger (rising or falling edge), Timer 0 will:
1) Start counting on timer clock
2) Upon receiving a Timer 0 Input rising edge, save Capture value in T0PWM0 registers,
generate interrupt, and continue to count
3) Upon receiving a Timer 0 Input falling edge, save Capture value in T0PWM1 registers,
generate interrupt, and continue to count
4)Once timer count to ABCD clocks, set reload event flag, and reset Timer count to start
value
Reading the Timer Count Values
The current count value in the timers can be read while counting (enabled). This capability
has no effect on timer operation. When the timer is enabled and the Timer High Byte reg-
ister is read, the contents of the Timer Low Byte register are placed in a holding register. A
subsequent read from the Timer Low Byte register returns the value in the holding regis-
ter. This operation allows accurate reads of the full 16-bit timer count value while enabled.
When the timers are not enabled, a read from the Timer Low Byte register returns the
actual value in the counter.
Timer Output Signal Operation
Timer Output is a GPIO Port pin alternate function. Generally, the Timer Output is tog-
gled every time the counter is reloaded.
Timer Noise Filter
A Noise Filter circuit is included which filters noise on a Timer Input signal before the
data is sampled by the block.
The Noise Filter has the following features:
•
Synchronizes the receive input data to the Timer Clock
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•
•
NFEN (Noise Filter Enable) input selects whether the Noise Filter is bypassed (NFEN=0)
or included (NFEN=1) in the receive data path.
NFCTL (Noise Filter Control) input selects the width of the up/down saturating counter
digital filter. The available widths range from 4-bits to 11 bits.
•
•
The digital filter output has hysteresis
Provides an active low “Saturated State” output (FiltSatB) which can be used as an indi-
cation of the presence of noise.
•
Available for operation in Stop Mode
Architecture
Figure 13 illustrates how the Noise Filter is integrated with the Timer. Noise filter uses
Timer
Clock
TxIN
TxIN
NEF
Noise Filter
NFEN, NFCTL
Timer
TxOUT
TxOUT
Figure 13.Noise Filter System Block Diagram
Operation
The figure below illustrates the operation of the Noise Filter both with and without noise.
The Noise Filter in this example is a 2-bit up/down counter which saturates at 00 and 11.
A 2-bit counter is shown for convenience, the operation of wider counters is similar. The
output of the filter switches from 1 to 0 when the counter counts down from 01 to 00 and
switches from 0 to 1 when the counter counts up from 10 to11. The Noise Filter delays the
receive data by three Timer Clock cycles.
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The NEF output signal can be checked when the filtered TxIN input signal is sampled.
The Timer will sample the filtered TxIN input near the center of the bit time. The NEF sig-
nal should be sampled at the same time to detect whether there is noise near the center of
the bit time. The presence of noise (NEF = 1 at center of bit time) does not mean the sam-
pled data is incorrect, rather it is intended to be an indicator of the level of noise in the net-
work.
Timer
Clock
Input
TxIN (ideal)
Data Bit = 0
Data Bit = 1
Clean TxIN
example
Noise Filter
Up/Dn Cntr
3 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Noise Filter
Output
nominal filter delay
Input
TxIN (noisy)
Data Bit = 0
Data Bit = 1
Noise TxIN
example.
Noise Filter
Up/Dn Cntr
3 3 2 1 0 0 0 0 0 0 1 2 1 0 0 0 0 0 1 0 1 2 3 3 3 3 2 3 3 3 3 3 3 3
Noise Filter
Output
NEF
output
Figure 14.Noise Filter Operation
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Timer Control Register Definitions
Timer 0-2 High and Low Byte Registers
The Timer 0-2 High and Low Byte (TxH and TxL) registers (Tables 51 and 51) contain the
current 16-bit timer count value. When the timer is enabled, a read from TxH causes the
value in TxL to be stored in a temporary holding register. A read from TxL always returns
this temporary register when the timers are enabled. When the timer is disabled, reads
from the TxL reads the register directly.
Writing to the Timer High and Low Byte registers while the timer is enabled is not recom-
mended. There are no temporary holding registers available for write operations, so simul-
taneous 16-bit writes are not possible. If either the Timer High or Low Byte registers are
written during counting, the 8-bit written value is placed in the counter (High or Low
Byte) at the next clock edge. The counter continues counting from the new value.
Table 51. Timer 0-2 High Byte Register (TxH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TH
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F00H, F08H, F10H
ADDR
Table 52. Timer 0-2 Low Byte Register (TxL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TL
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F01H, F09H, F11H
ADDR
TH and TL—Timer High and Low Bytes
These 2 bytes, {TH[7:0], TL[7:0]}, contain the current 16-bit timer count value.
Timer Reload High and Low Byte Registers
The Timer 0-2 Reload High and Low Byte (TxRH and TxRL) registers (Tables 53 and 53)
store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the Timer Reload
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High Byte register are stored in a temporary holding register. When a write to the Timer
Reload Low Byte register occurs, the temporary holding register value is written to the
Timer High Byte register. This operation allows simultaneous updates of the 16-bit Timer
Reload value.
In Compare mode, the Timer Reload High and Low Byte registers store the 16-bit Com-
pare value.
Table 53. Timer 0-2 Reload High Byte Register (TxRH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TRH
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F02H, F0AH, F12H
ADDR
Table 54. Timer 0-2 Reload Low Byte Register (TxRL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TRL
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F03H, F0BH, F13H
ADDR
TRH and TRL—Timer Reload Register High and Low
These two bytes form the 16-bit Reload value, {TRH[7:0], TRL[7:0]}. This value is used
to set the maximum count value which initiates a timer reload to 0001H. In Compare
mode, these two byte form the 16-bit Compare value.
Timer 0-2 PWM0 High and Low Byte Registers
The Timer 0-2 PWM0 High and Low Byte (TxPWM0H and TxPWM0L) registers
(Tables 55 and 55) are used for Pulse-Width Modulator (PWM) operations. These regis-
ters also store the Capture values for the Capture, Capture/Compare and Demodulation
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modes. When the timer is enabled, writes to these registers are buffered and loading of the
registers is delayed until a timer reload to 0001H unless PWM0UE = 1.
Table 55. Timer 0-2 PWM0 High Byte Register (TxPWM0H)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PWM0H
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F04H, F0CH, F14H
ADDR
Table 56. Timer 0-2 PWM0 Low Byte Register (TxPWM0L)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PWM0L
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F05H, F0DH, F15H
ADDR
PWM0H and PWM0L—Pulse-Width Modulator 0 High and Low Bytes
These two bytes, {PWM0H[7:0], PWM0L[7:0]}, form a 16-bit value that is compared to
the current 16-bit timer count. When a match occurs, the PWM output changes state. The
PWM output value is set by the TPOL bit in the Timer Control 1 register (TxCTL1) regis-
ter.
The TxPWM0H and TxPWM0L registers also store the 16-bit captured timer value when
operating in Capture, Capture/Compare and Demodulation modes.
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Timer 0-2 PWM1 High and Low Byte Registers
The Timer 0-2 PWM1 High and Low Byte (TxPWM1H and TxPWM1L) registers
(Tables 57 and 57) store Capture values for Demodulation mode.
Table 57. Timer 0-2 PWM1 High Byte Register (TxPWM1H)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PWM1H
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F20H, F24H, F28H
ADDR
Table 58. Timer 0-2 PWM1 Low Byte Register (TxPWM1L)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PWM1L
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F21H, F25H, F29H
ADDR
PWM1H and PWM1L—Pulse-Width Modulator 1 High and Low Bytes
These two bytes, {PWM1H[7:0], PWM1L[7:0]}, store the 16-bit captured timer value for
the Demodulation mode.
Timer 0-2 Control Registers
Time 0-2 Control 0 Register
The Timer 0-2 Control 0 (TxCTL0) register together with TxCTL1 register determines the
timer operating mode. It also includes a programmable PWM deadband delay, two bits to
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configure timer interrupt definition, and a status bit to identify if the last timer interrupt is
due to an input capture event.
Table 59. Timer 0-2 Control 0 Register (TxCTL0)
BITS
FIELD
RESET
R/W
7
TMODE[3]
0
6
5
4
3
2
PWMD
0
1
0
INPCAP
0
TICONFIG
CSC
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F06H, F0EH, F16H
ADDR
TMODE[3]—Timer Mode High Bit
This bit along with the TMODE[2:0] field in TxCTL1 register determines the operating
mode of the timer. This is the most significant bit of the Timer mode selection value. See
the TxCTL1 register description for additional details.
TICONFIG—Timer Interrupt Configuration
This field configures timer interrupt definition.
0x = Timer Interrupt occurs on all defined Reload, Compare and Input Events
10 = Timer Interrupt only on defined Input Capture/Deassertion Events
11 = Timer Interrupt only on defined Reload/Compare Events
CSC—Cascade Timers
0 = Timer Input signal comes from the pin.
1 =For Timer 0, Input signal is connected to Timer 2 output.
For Timer 1, Input signal is connected to Timer 0 output.
For Timer 2, Input signal is connected to Timer 1 output.
PWMD—PWM Delay Value
This field is a programmable delay to control the number of timer clock cycles time delay
before the Timer Output and the Timer Output Complement is forced to their active state.
000 = No delay
001 = 2 cycles delay
010 = 4 cycles delay
011 = 8 cycles delay
100 = 16 cycles delay
101 = 32 cycles delay
110 = 64 cycles delay
111 = 128 cycles delay
INPCAP—Input Capture Event
This bit indicates if the last timer interrupt is due to a Timer Input Capture Event.
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0 = Previous timer interrupt is not a result of Timer Input Capture Event
1 = Previous timer interrupt is a result of Timer Input Capture Event
Timer 0-2 Control 1 Register
The Timer 0-2 Control 1 (TxCTL1) registers enable/disable the timers, set the prescaler
value, and determine the timer operating mode.
Table 60. Timer 0-2 Control 1 Register (TxCTL1)
BITS
FIELD
RESET
R/W
7
6
TPOL
0
5
4
PRES
0
3
2
1
TMODE
0
0
TEN
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F07H, F0FH, F17H
ADDR
TEN—Timer Enable
0 = Timer is disabled.
1 = Timer enabled to count.
TPOL—Timer Input/Output Polarity
Operation of this field is a function of the current operating mode of the timer.
One-Shot mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
Continuous mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
Counter mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
PWM Single Output mode
0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the
Timer Output is forced High (1) upon PWM count match and forced Low (0) upon
Reload.
1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the
Timer Output is forced Low (0) upon PWM count match and forced High (1) upon
Reload.
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Capture mode
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
Compare mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
Gated mode
0 = Timer counts when the Timer Input signal is High (1) and interrupts are generated
on the falling edge of the Timer Input.
1 = Timer counts when the Timer Input signal is Low (0) and interrupts are generated
on the rising edge of the Timer Input.
Capture/Compare mode
0 = Counting is started on the first rising edge of the Timer Input signal. The current
count is captured on subsequent rising edges of the Timer Input signal.
1 = Counting is started on the first falling edge of the Timer Input signal. The current
count is captured on subsequent falling edges of the Timer Input signal.
PWM Dual Output mode
0 = Timer Output is forced Low (0) and Timer Output Complement is forced High (1)
when the timer is disabled. When enabled, the Timer Output is forced High (1) upon
PWM count match and forced Low (0) upon Reload. When enabled, the Timer Output
Complement is forced Low (0) upon PWM count match and forced High (1) upon
Reload. The PWMD field in Timer Control 0 register is a programmable delay to
control the number of cycles time delay before the Timer Output and the Timer
Output Complement is forced to High (1).
1 = Timer Output is forced High (1) and Timer Output Complement is forced Low (0)
when the timer is disabled. When enabled, the Timer Output is forced Low (0) upon
PWM count match and forced High (1) upon Reload.When enabled, the Timer Output
Complement is forced High (1) upon PWM count match and forced Low (0) upon
Reload. The PWMD field in Timer Control 0 register is a programmable delay to
control the number of cycles time delay before the Timer Output and the Timer
Output Complement is forced to Low (0).
Capture Restart mode
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
Comparator Counter mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
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Triggered One Shot mode
0 = Timer counting is triggered on the rising edge of the Timer Input signal.
1 = Timer counting is triggered on the falling edge of the Timer Input signal.
Demodulation mode
0 = Timer counting is triggered on the rising edge of the Timer Input signal. The
current count is captured into PWM0 High and Low byte registers on subsequent
rising edges of the Timer Input signal.
1 = Timer counting is triggered on the falling edge of the Timer Input signal.The
current count is captured into PWM1 High and Low byte registers on subsequent
falling edges of the Timer Input signal.
The above functionality applies only if TPOLHI bit in Timer Control 2 register is 0. If
TPOLHI bit is 1 then timer counting is triggered on any edge of the Timer Input signal
and the current count is captured on both edges. The current count is captured into
PWM0 registers on rising edges and PWM1 registers on falling edges of the Timer
Input signal.
PRES—Prescale value.
The timer input clock is divided by 2PRES, where PRES can be set from 0 to 7. The
prescaler is reset each time the Timer is disabled. This insures proper clock division
each time the Timer is restarted.
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
TMODE[2:0]—Timer mode
This field along with the TMODE[3] bit in TxCTL1 register determines the operating
mode of the timer. TMODE[3:0] selects among the following modes:
0000 = One-Shot mode
0001 = Continuous mode
0010 = Counter mode
0011 = PWM Single Output mode
0100 = Capture mode
0101 = Compare mode
0110 = Gated mode
0111 = Capture/Compare mode
1000 = PWM Dual Output mode
1001 = Capture Restart mode
1010 = Comparator Counter mode
1011 = Triggered One-Shot mode
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1100 = Demodulation mode
Timer 0-2 Control 2 Register
The Timer 0-2 Control 2 (TxCTL2) registers allow selection of timer clock source and
control of timer input polarity in Demodulation mode..
Table 61. Timer 0-2 Control 2 Register (TxCTL2)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
Reserved
0
1
0
TCLKS
0
Reserved
PWM0UE TPOLHI
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F22H, F26H, F2AH
ADDR
TCLKS—Timer Clock Source
0 = System Clock
1 = Peripheral Clock
TPOLHI—Timer Input/Output Polarity High Bit
This bit determines if timer count is triggered and captured on both edges of the input sig-
nal. This applies only to Demodulation mode.
0 = Count is captured only on one edge in Demodulation mode. In this case, edge polarity
is determined by TPOL bit in TxCTL1 register.
1 = Count is triggered on any edge and captured on both rising and falling edges of the
Timer Input signal in Demodulation mode
PWM0UE - PWM0 Update Enable
This bit determines whether writes to the PWM0 High and Low Byte registers are buff-
ered when TEN = 1. Writes to these registers are not buffered when TEN = 0 regardless of
the value of this bit.
0 = Writes to the Channel High and Low Byte registers are buffered when TEN = 1 and
only take affect on a timer reload to 0001H
1 = Writes to the Channel High and Low Byte registers are not buffered when TEN = 1.
Reserved—Must be 0
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Timer 0-2 Status Registers
The Timer 0-2 Status (TxSTAT) indicates PWM capture/compare event occurrence, over-
run errors, noise event occurrence and reload time-out status.
Table 62. Timer 0-2 Status Register (TxSTAT)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
NEF
0
Reserved PWM1EO PWM0EO RTOEF Reserved PWM1EF PWM0EF
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F23H, F27H, F2BH
ADDR
NEF—Noise Event Flag
This status is applicable only if the Timer Noise Filter is enabled. The NEF bit will be
asserted if digital noise is detected on the Timer input (TxIN) line when the data is being
sampled (center of bit time). If this bit is set, it does not mean that the timer input data is
corrupted (though it may be in extreme cases), just that one or more of the Noise Filter
data samples near the center of the bit time did not match the average data value.
PWMxEF—PWM x Event Flag
This bit indicates if a capture/compare event occurred for this PWM channel. Software
can use this bit to determine the PWM channel responsible for generating the timer inter-
rupt. This event flag is cleared by writing a 1 to the bit. These bits will be set when an
event occurs independent of the setting of the timer interrupt enable bit.
0 = No Capture/Compare Event occurred for this PWM channel
1 = A Capture/Compare Event occurred for this PWM channel
RTOEF—Reload Time-out Event Flag
This flag is set if timer counts up to the reload value and is reset to 0001H. Software can
use this bit to determine if a reload occurred prior to a capture. It can also determine if
timer interrupt is due to a reload event.
0 = No Reload Time-out event occurred
1 = A Reload Time-out event occurred
PWMxEO—PWM x Event Overrun
This bit indicates that an overrun error has occurred. An overrun occurs when a new cap-
ture/compare event occurs before the previous PWMxEF bit was cleared. Clearing the
associated PWMxEF bit in the TxSTAT register clears this bit.
0 = No Overrun
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1 = Capture/Compare Even Flag Overrun
Reserved—Must be 0
Timer 0-2 Noise Filter Control Register
Table 63. Timer 0-2 Noise Filter Control Register (TxNFC)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
NFEN
NFCTL
Reserved
R
0
0
0
0
0
0
0
0
R/W
R/W
F2CH, F2DH, F2EH
ADDR
NFEN—Noise Filter Enable
0 = Noise Filter is disabled.
1 = Noise Filter is enabled. Receive data is preprocessed by the noise filter.
NFCTL—Noise Filter Control
This field controls the delay and noise rejection characteristics of the Noise Filter. The
wider the counter the more delay that is introduced by the filter and the wider the noise
event that will be filtered.
000 = 2-bit up/down counter
001 = 3-bit up/down counter
010 = 4-bit up/down counter
011 = 5-bit up/down counter
100 = 6-bit up/down counter
101 = 7-bit up/down counter
110 = 8-bit up/down counter
111 = 9-bit up/down counter
Reserved—Must be 0
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Multi-Channel Timer
Overview
The Multi-Channel timer has a 16-bit up/down counter and a capture/compare channel
array. This enables support of multiple synchronous capture/compare channels based on a
single timer. The Multi-Channel Timer features include:
•
•
•
•
•
16-bit up/down timer counter with programmable prescale
Selectable clock source (system clock or external input pin)
Count Modulo and Count Up/Down counter modes
4 independent capture/compare channels which reference the common timer
Channel modes:
–
–
–
–
One-shot compare mode
Continuous compare mode
PWM Output compare mode
Capture mode
Architecture
Figure 15 illustrates the Multi-Channel Timer architecture.
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Data
Bus
Timer & Channel
Control
Block
Control
C
O
M
P
A
R
E
16-Bit
Reload Register
Timer
Interrupt
System Clock
Timer
Interrupt,
PWM,
and
Timer
Output
Control
16-Bit Counter
with Prescaler
0
1
Timer Channel
Outputs
Input
(TxIN)
C
O
M
P
A
R
E
2
3
(TxOutA - TxOutD)
Gate
Input
4 16-Bit PWM
Capture Compare
Channels
0
1
2
3
Timer Channel
Inputs
(TxInA - TxInD)
Figure 15.Multi-Channel Timer Block Diagram
Timer Operation
Multi-Channel Timer Counter
The Multi-Channel Timer is based around a 16-bit up/down counter. The counter, depend-
ing on the timer mode, counts up or down with each rising edge of the clock signal. Timer
Counter Registers MCTH and MCTL can be read/written by software.
Clock Source
The Multi-Channel Timer clock source can come from either the system clock or the sys-
tem clock gated by the alternate function TxIn pin, the alternate function TxIn input pin
operating as a clock input. The TCLKS field in the MCTCTL0 register selects the timer
clock source. When using the TxIn pin, the associated GPIO pin must be configured as an
input. The MCTxIN frequency cannot exceed one-fourth the system clock frequency.
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Multi-Channel Timer Clock Prescaler
The prescaler allows the system clock signal to be decreased by factors of 1, 2, 4, 8, 16,
32, 64, or 128. The PRES[2:0] bit field in the MCTCTL1 register controls prescaler oper-
ation. The PRES field is buffered so that the prescale value will only change upon a MCT
end of cycle count. The prescaler has no affect when the MCTxIN is selected as the clock
source.
Multi-Channel Timer Start
The Multi-Channel Timer starts counting when TEN bit in MCTCTL1 register is set and
the clock source is active. In Count Modulo or Count Up/Down mode the timer counting
can be stopped, without disabling the timer, by setting the Reload Register to 0. The timer
will then stop when the counter next reaches 0. Writing a nonzero value to the Reload
Register restarts the timer counting.
Multi-Channel Timer Mode Control
The Multi-Channel Timer supports two modes of operation: Count Modulo and Count Up/
down. The operating mode is selected with the TMODE[1:0] field in MCTCTL1 register.
The timer modes are described below in Table 64.
Table 64. Timer Count Modes
Timer Mode
Description
TMODE
00
Count Modulo
Timer counts up to Reload Register value. Then
it is reset to 0000H and counting up resumes.
01
10
reserved
Count Up/Down
Timer counts up to Reload and then counts
down to 0000H. The count up and count down
cycle continues.
11
reserved
Count Modulo Mode
In the Count Modulo mode, the Timer counts up to the Reload Register value (max value
= FFFFH). Then it is reset to 0000H and counting resumes. As shown in Figure 16 the
counting cycle continues with Reload + 1 as the period. A timer count interrupt request is
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generated when the timer count resets from Reload to 0000H. If Count Modulo is selected
when the timer count is greater than Reload, the timer immediately restarts counting from
zero.
Figure 16.Count Modulo Mode
FFFFH
Reload
0H
Count Up/Down Mode
In the Count Up/Down mode, the timer counts up to the Reload Register value and then
counts down to 0000H. As shown in Figures 17, the counting cycle continues with twice
the reload value as the period. A timer count interrupt is generated when the timer count
decrements to zero.
Figure 17.Count Up/Down Mode
Reload
0H
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Capture/Compare Channel Operation
The Multi-Channel timer supports four capture/compare channels CHA, CHB, CHC and
CHD. Each channel has the following features:
•
A 16-bit Capture/Compare Register (MCTCHxH and MCTCHxL registers) used to
capture input event times or to generate time intervals. Any user software update of
the Capture/Compare Register value while the timer is running takes effect only at the
end of the counting cycle, not immediately. The end of the counting cycle is when the
counter transitions from the Reload value to 0 (count modulo mode) or from 1 to 0
(count up/down mode).
•
A dedicated bidirectional pin (TxInA, B, C or D) which can be configured for the
input capture function or to generate an output compare match or one-shot pulse.
Each channel can be configured to operate in either One Shot Compare, Continuous Com-
pare, PWM Output or Input Capture mode.
One-Shot Compare Operation
In One-Shot compare operation, a channel interrupt is generated when the channel com-
pare value matches the timer count. The channel event flag (CHxEF) is set in the Channel
Status1 register (MCTCHS1) to identify the responsible channel. Then the channel is
automatically disabled. The timer continues counting according to the programmed mode.
If the timer channel output alternate function is enabled, the channel output pin
(TxOutA,B,C or D) changes state for one system clock cycle (from Low to High then back
Low or from High to Low then back High as determined by the CHPOL bit) upon match.
Continuous Compare Operation
In Continuous Compare operation, a channel interrupt is generated whenever the channel
compare value matches the timer count. The channel event flag (CHxEF ) is set in the
Channel Status1 register (MCTCHS1). The channel remains enabled. The timer continues
counting according to the programmed mode. If the channel output alternate function is
enabled, the channel output pin (TxOutA,B,C or D) changes state for one system clock
cycle (from Low to High then back to Low or from High to Low then back to High as
determined by the CHPOL bit) upon match.
PWM Output Operation
In PWM Output operation, the timer generates a PWM output signal on the channel out-
put pin (TxOutA,B,C or D). The channel output toggles whenever the timer count matches
the channel compare value (defined in the MCTCHxH and MCTCHxL) registers. In addi-
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tion, a channel interrupt is generated and the channel event flag is set in the status register.
The timer continues counting according to its programmed mode.
The channel output signal begins with the output value = CHPOL and then transitions to
CHPOL when the timer value matches the PWM value. If timer mode is Count Modulo,
the channel output signal returns to output = CHPOL after the timer reaches the Reload
value and is reset. If timer mode is Count Up/Down, the channel output signal returns to
output = CHPOL when the timer count matches the PWM value again (when counting
down).
Capture Operation
In Capture operation, the current timer count is recorded when the selected transition
occurs on TxInA, B, C or D. The Capture count value is written to the Channel High and
Low Byte Registers. In addition, a channel interrupt is generated and the channel event
flag (CHxEF) is set in the Channel Status register. The CHPOL bit in the Channel Control
register determines if the Capture occurs on a rising edge or a falling edge of the Channel
Input signal. The timer continues counting according to the programmed mode.
Multi-Channel Timer Interrupts
The Multi-Channel Timer provides a single interrupt which has 5 possible sources. These
sources are the timer and the 4 channels.
Timer Interrupt
If enabled by TCIEN bit of the MCTCTL0 register, the timer interrupt will be generated
when the timer completes a count cycle. This occurs upon transitioning from counter =
reload register value to counter = 0 in count modulo mode, and occurs upon transitioning
from counter = 1 to counter = 0 in count up/down mode.
Capture/Compare Channel Interrupt
A channel interrupt is generated whenever there is a successful Capture/Compare Event
on the Timer Channel and the associated CHIEN bit is set.
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Low Power Modes
Operation in HALT Mode
When the eZ8 CPU is operating in HALT mode, the Multi-Channel Timer will continue to
operate if enabled. To minimize current in HALT mode, the Multi-Channel Timer can be
disabled by clearing the TEN control bit.
Operation in STOP Mode
When the eZ8 CPU is operating in STOP mode, the Multi-Channel Timer ceases to oper-
ate since the system clock is stopped. The registers are not reset and operation will resume
once stop mode recovery occurs.
Power Reduction during operation
Deassertion of the TEN bit will inhibit clocking of the entire Multi-Channel Timer block.
Deassertion of the CHEN bit of individual channels will inhibit clocking of channel spe-
cific logic to minimize power consumption of unused channels. The CPU can still read/
write registers when the enable bit(s) are deasserted.
Multi-Channel Timer Applications Examples
PWM Programmable Dead Band Generation
The count up/down mode supports motor control applications that require dead time
between output signals. Figure 18 illustrates dead time generation between two channels
operating in count up/down mode.
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Figure 18.Count Up/Down Mode with PWM Channel Outputs and Dead-Band
FFFFH
Reload
MCTCH0
MCTCH1
0H
Dead Time
TCH0 Output
TCH1 Output
CI
CI
CI
CI
Channel Interrupts (CI)
Timer Interrupts (TI)
TI
CI
CI
CI
TI
CI
Multiple Timer Intervals Generation
Figure 19 illustrates generation of two constant time intervals t0 and t1. The timer is in
Count Modulo mode with reload = FFFFH. Channels 0 and 1 are set up for Continuous
Compare operation. After every channel compare interrupt, the channel capture/compare
registers are updated in the interrupt service routine by adding a constant equal to the time
interval required. This operation requires that the CHUE bit (Channel Update Enable) be
set in channel 0 and 1 so that writes to the capture/compare registers take affect immedi-
ately.
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Figure 19.Count Max Mode with Channel Compare
FFFFH
0H
t0
t0
t0
t0
t1
t1
t1
Multi-Channel Timer Control Register Definitions
Multi-Channel Timer Address Map
below defines the byte address offsets for the Multi-channel Timer registers. For saving
address room, sub-address is used for Timer Control 0 register, Timer Control 1 register,
Channel status 0 register, Channel Status 1 register, Channel-x Control register, Channel-y
High and Low Byte register. Only Timer High and Low Byte register and Reload High
and Low Byte register can be direct access.
When write sub-register, first write sub-address to Timer Sub Address Register, then wirte
data to sub-register0, sub-register1 or sub-register2. Read is same with write.
Table 65. Multi-channel Timer Address Map
Address/
Register/Sub-register Name
Sub-address
Direct Access Register
FA0
FA1
FA2
FA3
Timer (Counter) High
Timer (Counter) Low
Timer Reload High
Timer Reload Low
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Table 65. Multi-channel Timer Address Map
Register/Sub-register Name
Address/
Sub-address
FA4
Timer Sub Address
Sub Register 0
Sub Register 1
Sub Register 2
FA5
FA6
FA7
Sub-register 0
0
Timer Control0
1
Channel Status0
2
Channel A Capture/Compare High
Channel B Capture/Compare High
Channel C Capture/Compare High
Channel D Capture/Compare High
3
4
5
Sub-register1
0
1
2
3
4
5
Timer Control1
Channel Status1
Channel A Capture/Compare Low
Channel B Capture/Compare Low
Channel C Capture/Compare Low
Channel D Capture/Compare High
Sub-register 2
0
1
2
3
4
5
Reserved
Reserved
Channel A Control
Channel B Control
Channel C Control
Channel D Control
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Multi-Channel Timer High and Low Byte Registers
The High and Low Byte (MCTH and MCTL) registers (Tables 66 and 67) contain the cur-
rent 16-bit MCT count value.
Writing to the MCT High and Low Byte registers while the MCT is enabled is not recom-
mended. If either or both of the MCT High or Low Byte registers are written during count-
ing, the 8-bit written value is placed in the counter (High and/or Low Byte) at the next
system clock edge. The counter continues counting from the new value.
Table 66. MCT High Byte Register (MCTH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
MCTH
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FA0H
ADDR
Table 67. MCT Low Byte Register (MCTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
MCTL
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FA1H
ADDR
When MCT is enabled, a read from MCTH causes the value in MCTL to be stored in a
temporary holding register. A read from MCTL returns this temporary register when MCT
is enabled. When MCT is Disabled, reads from MCTL reads the register directory.
The MCT High and Low byte registers are not reset when TEN = 0.
MCTH and MCTL—MCT High and Low Bytes
These 2 bytes, {MCTH[7:0], MCTL[7:0]}, contain the current 16-bit MCT count value.
MCT Reload High and Low Byte Registers
The MCT Reload High and Low Byte (MCTRH and MCTRL) registers (Tables 68 and
69) store a 16-bit reload value, {MCTRH[7:0], MCTRL[7:0]}. When TEN = 0, writes to
this address update the register on the next clock cycle. When TEN = 1, writes to this reg-
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ister are buffered and are transferred into the register when the counter reaches the end of
the count cycle.
Prescaler × (Reload Value + 1)
Modulo Mode Period = --------------------------------------------------------------------------
fMCTclk
2 × Prescaler × Reload Value
Up/Down Mode Period = ---------------------------------------------------------------------
fMCTclk
Table 68. MCT Reload High Byte Register (MCTRH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
MCTRH
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FA2H
ADDR
Table 69. MCT Reload Low Byte Register (MCTRL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
MCTRL
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FA3H
ADDR
Value written to the MCTRH is stored in a temporary holding register. When a write to the
MCTRL occurs, the temporary holding register value is written to the MCTRH. This oper-
ation allows simultaneous updates of the 16-bit MCT Reload value.
MCTRH and MCTRL—MCT Reload Register High and Low
These two bytes form the 16-bit Reload value, {MCTRH[7:0], MCTRL[7:0]}. This value
sets the MCT period in Modulo and Up/Down count modes.
MCT Sub Adress Register
The MCT Sub Address Register store 3-bits sub-address for sub-registers. These 3-bits
from MCTSAR[2:0], all other bits are reserved. When access sub-register, write or read,
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set MCTSAR right value first, then access sub-register by write or read Sub Register 0, 1
or 2.
Table 70. MCT Sub Address Register (MCTSA)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
MCTSA
FA4H
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
MCT Sub Register x (0, 1 or 2)
The MCT Sub Register 0, 1, or 2 store the 8-bit data write to sub-register or 8-bit data read
from sub-register. The MCT Sub Address reigster select the sub-register to be write or
read from.
Table 71. MCT Sub Register x (MCTSRx)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
MCTSRx
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FA5H, FA6H, FA7H
ADDR
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Multi-Channel Timer Control 0, Control1 Registers
The Multi-Channel Timer Control registers (MCTCTL0, MCTCTL1) control Multi-
Channel Timer operation. Writes to the PRES field of MCTCTL1 register are buffered
when TEN = 1 and will not take affect until the next end of cycle count occurs.
Table 72. Multi-Channel Timer Control 0 Register (MCTCTL0)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TCTST
CHST
TCIEN
reserved
reserved
TCLKS
0
0
0
0
0
0
0
0
R/W1C
R
R/W
R
R
R/W
R/W
R/W
00H in Sub Address Register, accessible through Sub Register 0
ADDR
TCTST – Timer Count Status
This bit indicates if a timer count cycle is complete. This bit is cleared by writing a 1 to the
bit and is cleared when TEN = 0.
0 = Timer count cycle is not complete
1 = Timer count cycle is complete
CHST – Channel Status
This bit indicates if a channel capture/compare event occurred. This bit is the logical OR
of the CHyEF bits in the MCTCHS1 register. This bit is cleared when TEN=0.
0 = No channel capture/compare event has occurred
1 = A channel capture/compare event has occurred. One or more of the CHDEF, CHCEF,
CHBEF and CHAEF bits in the MCTCHS1 register is set.
TCIEN – Timer Count Interrupt Enable
This bit enables generation of timer count interrupt. A timer count interrupt is generated
whenever the timer completes a count cycle: counting up to Reload Register value or
counting down to zero depending on whether the timer mode is Count Modulo or Count
Up/Down.
0 = Timer Count Interrupt is disabled
1 = Timer Count Interrupt is enabled
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TCLKS – Timer Clock Source
000 = System Clock (Prescaling enabled)
001 = Reserved
010 = System Clock gated by active High Timer Input signal (Prescaling enabled)
011 = System Clock gated by active Low Timer Input signal (Prescaling enabled)
100 = Timer I/O pin input rising edge (Prescaler disabled)
101 = Timer I/O pin input falling edge (Prescaler disabled)
110 = Reserved
111 = Reserved
Note: The input frequency of the Timer Input Signal must not exceed one-fourth the sys-
tem clock frequency.
Note: General Purpose Timer0 cascade input is from Multi-Channel Timer3, Channel A
output
General Purpose Timer1 cascade input is from General Purpose Timer 0 non-inverting
output
Multi-Channel Timer2 cascade input is from General Purpose Timer1 non-inverting out-
put.
Multi-Channel Timer3 cascade input is from Multi-Channel Timer2 Channel A output.
Table 73. Multi-Channel Timer Control 1 Register (MCTCTL1)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TEN
reserved
PRES
reserved
TMODE
0
0
0
0
0
0
0
0
R/W
R
R/W
R/W
R/W
R
R/W
R/W
00H in Sub Address Register, accessible through Sub Register 1
ADDR
TEN – Timer Enable
0 = Timer is disabled and the counter is reset.
1 = Timer is enabled to count
PRES – Prescale value
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The system clock is divided by 2PRES, where PRES can be set from 0 to 7. The prescaling
operation is not applied when the alternate function input pin is selected as the timer clock
source.
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
TMODE – Timer Mode
00 = Count Modulo: Timer Counts up to Reload Register value. Then it is reset to 0000H
and counting up resumes.
01 = reserved
10 = Count Up/Down: Timer Counts up to Reload and then counts down to 0000H. The
count up and count down cycle continues.
11 = Reserved
Multichannel Timer Channel Status 0 and Status 1 Registers
Table 74. Multi-Channel Timer Channel Status 0 Register (MCTCHS0)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
Reserved
CHDEO
CHCEO
CHBEO
CHAEO
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
01H in Sub Address Register, accessible through Sub Register 0
ADDR
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CHyEO – Channel y Event Flag Overrun
This bit indicates that an overrun error has occurred. An overrun occurs when a new cap-
ture/compare event occurs before the previous CHyEF bit was cleared. Clearing the asso-
ciated CHyEF bit in the MCTxCHS1 register clears this bit. This bit is cleared when
TEN=0 (TEN is the MSB of MCTxCTL1).
0 = No Overrun
1 = Capture/Compare Event Flag Overrun
Table 75. Multi-Channel Timer Channel Status 1 Register (MCTCHS1)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
Reserved
CHDEF
CHCEF
CHBEF
CHAEF
0
0
0
0
0
0
0
0
R
R
R
R
R/W1C
R/W1C
R/W1C
R/W1C
01H in Sub Address Register, accessible through Sub Register 1
ADDR
CHyEF – Channel y Event Flag
This bit indicates if a capture/compare event occurred for this channel. Software can use
this bit to determine the channel(s) responsible for generating the MCT channel interrupt.
This event flag is cleared by writing a 1 to the bit. These bits will be set when an event
occurs independent of the setting of the CHIEN bit. This bit is cleared when TEN=0 (TEN
is the MSB of MCTxCTL1).
0 = No Capture/Compare Event occurred for this channel
1 = A Capture/Compare Event occurred for this channel
Multi-Channel Timer Channel-y Control Registers.
Each channel has a control register to enable the channel, select the input/output polarity,
enable channel interrupts and select the channel mode of operation.
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Table 76. Multi-Channel Timer Channel-x Control Register (MCTCHyCTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
CHEN
CHPOL
CHIEN
CHUE
Reserved
CHOP
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
02H, 03H, 04H, 05H in Sub Address Register, accessible through Sub Register 2
ADDR
x = 2, 3
y = A, B, C, D
CHEN – Channel Enable
0 = Channel is disabled
1 = Channel is enabled
CHPOL – Channel Input/Output Polarity
Operation of this bit is a function of the current operating method of the channel.
One-Shot operation
When the channel is disabled, the Channel Output signal is set to the value of this bit.
When the channel is enabled, the Channel Output signal toggles for one system clock
upon reaching the Channel Capture/Compare Register value.
Continuous Compare operation
When the channel is disabled, the Channel Output signal is set to the value of this bit.
When the channel is enabled, the Channel Output signal toggles (from low to high or from
high to low) upon reaching the Channel Capture/Compare Register value.
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PWM Output operation
0= Channel Output is forced Low when the channel is disabled. When enabled, the Chan-
nel Output is forced High upon Channel Capture/Compare Register value match and
forced Low upon reaching the Timer Reload Register value (modulo mode) or counting
down through the channel Capture/Compare register value (count up/down mode).
1 = Channel Output is forced High when the channel is disabled. When enabled, the
Channel Output is forced Low upon Channel Capture/Compare Register value match and
forced High upon reaching the Timer Reload Register value (modulo mode) or counting
down through the channel Capture/Compare register value (count up/down mode).
Capture operation
0 = Count is captured on the rising edge of the Channel Input signal.
1 = Count is captured on the falling edge of the Channel Input signal.
CHIEN – Channel Interrupt Enable
This bit enables generation of channel interrupt. A channel interrupt is generated when-
ever there is a capture/compare event on the Timer Channel.
0 = Channel Interrupt is disabled
1 = Channel Interrupt is enabled
CHUE - Channel Update Enable
This bit determines whether writes to the Channel High and Low Byte registers are buff-
ered when TEN = 1. Writes to these registers are not buffered when TEN = 0 regardless of
the value of this bit.
0 = Writes to the Channel High and Low Byte registers are buffered when TEN = 1 and
only take affect on the next end of cycle count
1 = Writes to the Channel High and Low Byte registers are not buffered when TEN = 1.
CHOP – Channel Operation method
This field determines the operating mode of the channel. Refer to the“” on page 117 for a
detailed description of the operating modes.
000 = One-Shot Compare operation
001 = Continuous Compare operation
010 = PWM Output operation
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011 = Capture operation
100 – 111 = Reserved
Multi-Channel Timer Channel-y High and Low Byte Registers
Each channel has a 16 bit capture/compare register defined here as the Channel-y High
and Low byte registers. When the timer is enabled, writes to these registers are buffered
and loading of the registers is delayed until the next timer end count unless CHUE = 1.
Table 77. Multi-Channel Timer Channel-y High Byte Registers (MCTCHyH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
CHyH
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
02H, 03H, 04H, 05H in Sub Address Register, accessible through Sub Register 0
ADDR
Table 78. Multi-Channel Timer Channel-y Low Byte Registers (MCTCHyL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
CHyL
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
02H, 03H, 04H, 05H in Sub Address Register, accessible through Sub Register 1
ADDR
x = 2, 3 y = A, B, C, D CHyH and CHyL – Multi-Channel Timer Channel-y High and Low
Bytes. During a compare operation, these two bytes, {CHyH[7:0], CHyL[7:0]}, form a
16-bit value that is compared to the current 16-bit timer count. When a match occurs, the
Channel Output changes state. The Channel Output value is set by the TPOL bit in the
Channel-y Control sub-register.
During a capture operation, the current Timer Count is recorded in these two bytes when
the desired Channel Input transition occurs.
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Watch-Dog Timer
The Watch-Dog Timer (WDT) helps protect against corrupted or unreliable software and
other system-level problems which may place the Z8 Encore! XP® F1680 Series into
unsuitable operating states. The Watch-Dog Timer includes the following features:
•
•
•
On-chip RC oscillator
A selectable time-out response: Reset or System Exception
16-bit programmable time-out value
Operation
The Watch-Dog Timer (WDT) is a re-triggerable one-shot timer that resets or interrupts
the Z8 Encore! XP® F1680 Series when the WDT reaches its terminal count. The Watch-
Dog Timer uses its own dedicated on-chip RC oscillator as its clock source. The Watch-
Dog Timer has only two modes of operation—on and off. Once enabled, it always counts
and must be refreshed to prevent a time-out. An enable can be performed by executing the
WDT instruction or by setting the WDT_AOOption Bit. The WDT_AObit enables the Watch-
Dog Timer to operate all the time, even if a WDT instruction has not been executed.
To minimize power consumption, the RC oscillator can be disabled. The RC oscillator is
disabled by clearing the WDTENbit in the Table 164 on page 300. If the RC oscillator is
disabled, the WDT will not operate.
The Watch-Dog Timer is a 16-bit reloadable downcounter that uses two 8-bit registers in
the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is
calculated by the following equation:
WDT Time-Out Period (ms)
WDT Reload Value
10
=
where the WDT reload value is given by {WDTH[7:0], WDTL[7:0]} and the typical
Watch-Dog Timer RC oscillator frequency is 10KHz.The user should consider system
requirements when selecting the time-out delay. Table 79 provides information on approx-
imate time-out delays for the default and maximum WDT reload values.
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Table 79. Watch-Dog Timer Approximate Time-Out Delays
Approximate Time-Out Delay
(with 10KHz Typical WDT Oscillator Frequency)
WDT Reload
Value
WDT Reload
Value (Hex)
(Decimal)
Typical
102ms
6.55s
Description
0400
1024
Reset default value time-out delay.
Maximum time-out delay.
FFFF
65,536
Watch-Dog Timer Refresh
When first enabled, the Watch-Dog Timer is loaded with the value in the Watch-Dog
Timer Reload registers. The Watch-Dog Timer then counts down to 0000hunless a WDT
instruction is executed by the eZ8 CPU. Execution of the WDTinstruction causes the down-
counter to be reloaded with the WDT Reload value stored in the Watch-Dog Timer Reload
registers. Counting resumes following the reload operation.
When the Z8 Encore! is operating in DEBUG Mode (through the On-Chip Debugger), the
Watch-Dog Timer is continuously refreshed to prevent unwanted Watch-Dog Timer time-
outs.
Watch-Dog Timer Time-Out Response
The Watch-Dog Timer times out when the counter reaches 0000h. A time-out of the
Watch-Dog Timer generates either a system exception or a Reset. The WDT_RESOption
Bit determines the time-out response of the Watch-Dog Timer. Refer to the Flash Option
Bits chapter on page 271 for information regarding programming of the WDT_RESOption
Bit.
WDT System Exception in Normal Operation
If configured to generate a system exception when a time-out occurs, the Watch-Dog
Timer issues an exception request to the interrupt controller. The eZ8 CPU responds to the
request by fetching the System Exception vector and executing code from the vector
address. After time-out and system exception generation, the Watch-Dog Timer is
reloaded automatically and continues counting.
WDT System Exception in Stop Mode
If configured to generate a system exception when a time-out occurs and the Z8 Encore!
XP® F1680 Series is in STOP mode, the Watch-Dog Timer automatically initiates a Stop-
Mode Recovery and generates a system exception request. Both the WDT status bit and
the STOPbit in the are set to 1 following WDT time-out in STOP mode.
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Following completion of the Stop-Mode Recovery the eZ8 CPU responds to the system
exception request by fetching the System Exception vector and executing code from the
vector address.
WDT Reset in Normal Operation
If configured to generate a Reset when a time-out occurs, the Watch-Dog Timer forces the
device into the Reset state. The WDTstatus bit is set to 1. See “Reset Status Register” on
page 40. Refer to the Reset, STOP Mode Recovery and Low Voltage Detection chapter on
page 30 for more information on Reset and the WDTstatus bit. Following a Reset sequence,
the WDT Counter is initialized with its reset value.
WDT Reset in Stop Mode
If enabled in STOP mode and configured to generate a Reset when a time-out occurs and
the device is in STOP mode, the Watch-Dog Timer initiates a Stop-Mode Recovery. Both
the WDTstatus bit and the STOPbit in Table 11 on page 40 are set to 1 following WDT
time-out in STOP mode. Refer to the Reset, STOP Mode Recovery and Low Voltage
Detection chapter on page 30 for more information.
Watch-Dog Timer Reload Unlock Sequence
Writing the unlock sequence to the Watch-Dog Timer Reload High (WDTH) register
address unlocks the two Watch-Dog Timer Reload registers (WDTH, and WDTL) to
allow changes to the time-out period. These write operations to the WDTH register
address produce no effect on the bits in the WDTH register. The locking mechanism pre-
vents unwarranted writes to the Reload registers. The following sequence is required to
unlock the Watch-Dog Timer Reload registers (WDTH, and WDTL) for write access.
1. Write 55Hto the Watch-Dog Timer Reload High register (WDTH).
2. Write AAHto the Watch-Dog Timer Reload High register (WDTH).
3. Write the desired value to the Watch-Dog Timer Reload High register (WDTH).
4. Write the desired value to the Watch-Dog Timer Reload Low register (WDTL).
All steps of the Watch-Dog Timer Reload Unlock sequence must be written in the order
just listed. The value in the Watch-Dog Timer Reload registers is loaded into the counter
every time a WDTinstruction is executed.
Watch-Dog Timer Register Definitions
The two Watch-Dog Timer Reload registers (WDTH, and WDTL) are described in the
following tables.
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Watch-Dog Timer Reload High and Low Byte Registers
The Watch-Dog Timer Reload High and Low Byte (WDTH, WDTL) registers (Tables 80
and Table 81) form the 16-bit reload value that is loaded into the Watch-Dog Timer when
a WDTinstruction executes. The 16-bit reload value is {WDTH[7:0], WDTL[7:0]}. Writ-
ing to these registers following the unlock sequence sets the desired Reload Value. Read-
ing from these registers returns the current Watch-Dog Timer count value.
Table 80. Watch-Dog Timer Reload High Byte Register (WDTH = FF2h)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
WDTH
04h
04h
04h
04h
04h
04h
04h
04h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FF2H
ADDR
Table 81. Watch-Dog Timer Reload Low Byte Register (WDTL = FF3h)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
WDTL
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FF3H
ADDR
WDTH and WDTL —Watch Dog Timer Reload High and Low Bytes
WDTH —The WDT Reload High Byte is the most significant byte, or bits [15:8] of the
16-bit WDT reload value.
WDTL —The WDT Reload Low Byte is the least significant byte, or bits [7:0] of the 16-
bit WDT reload value.
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LIN-UART
The Local Interconnect Network Universal Asynchronous Receiver/Transmitter (LIN-
UART) is a full-duplex communication channel capable of handling asynchronous data
transfers in standard UART applications, as well as providing LIN protocol support. The
LIN-UART is a superset of the standard Z8 Encore!® UART, providing all its standard
features as well as the LIN protocol support and a digital noise filter.
Features of the LIN-UART include:
•
•
•
•
•
•
•
8-bit asynchronous data transfer
Selectable even- and odd-parity generation and checking
Option of 1or 2 stopbits
Selectable Multiprocessor (9-bit) mode with three configurable interrupt schemes
Separate transmit and receive interrupts
Framing, parity, overrun and break detection
16-bit Baud Rate Generator (BRG) which may function as a general purpose timer with
interrupt.
•
•
Driver Enable output for external bus transceivers
LIN protocol support for both master and slave modes
–
–
–
Break generation and detection
Selectable Slave Autobaud
Check Tx vs. Rx data when sending
•
Configuring digital-noise filter on Receive Data line.
Architecture
The LIN-UART consists of three primary functional blocks: transmitter, receiver, and
baud-rate generator. The LIN-UART’s transmitter and receiver function independently,
but employ the same baud rate and data format. The basic UART operation is enhanced by
the Noise Filter and IrDA blocks. Figure 20 illustrates the LIN-UART architecture.
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Figure 20.LIN-UART Block Diagram
Data Format for Standard UART Modes
The LIN-UART always transmits and receives data in an 8-bit data format, least-signifi-
cant bit first. An even-or-odd parity bit or multiprocessor address/data bit can be option-
ally added to the data stream. Each character begins with an active low start bit and ends
with either 1 or 2 active high stop bits. Figures 21 and 22 illustrate the asynchronous data
format employed by the LIN-UART without parity and with parity, respectively.
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Figure 21.LIN-UART Asynchronous Data Format without Parity
Figure 22.LIN-UART Asynchronous Data Format with Parity
Transmitting Data using the Polled Method
Follow these steps to transmit data using the polled-operating method:
1. Write to the LIN-UART Baud Rate High and Low Byte registers to set the appropriate
baud rate.
2. Enable the LIN-UART pin functions by configuring the associated GPIO port pins for
alternate-function operation.
3. If MULTIPROCESSOR mode is appropriate, write to the LIN-UART Control 1
Register to enable MULTIPROCESSOR (9-bit) mode functions.
Set the MULTIPROCESSOR Mode Select (MPEN) to Enable MULTIPROCESSOR
mode.
4. Write to the LIN-UART Control 0 Register to:
a. Set the transmit enable bit (TEN) to enable the LIN-UART for data transmission
b. If parity is appropriate and multiprocessor mode is not enabled, set the
parity enable bit (PEN) and select either even-or-odd parity (PSEL).
c. Set or clear the CTSEbit to enable or disable control from the remote
receiver using the CTS pin.
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5. Check the TDREbit in the LIN-UART Status 0 register to determine if the Transmit
Data Register is empty (indicated by a 1). If empty, continue to Step 6. If the Transmit
Data Register is full (indicated by a 0), continue to monitor the TDREbit until the
Transmit Data Register becomes available to receive new data.
6. If in MULTIPROCESSOR mode, write the LIN-UART Control 1 Register to select
the outgoing address bit.
Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte; clear it if
sending a data byte.
7. Write the data byte to the LIN-UART Transmit Data Register. The transmitter
automatically transfers the data to the Transmit Shift register and transmits the data.
8. If appropriate, and if MULTIPROCESSOR mode is enabled, make any changes to the
Multiprocessor Bit Transmitter (MPBT) value.
9. To transmit additional bytes, return to Step 5.
Transmitting Data Using the Interrupt-Driven Method
The LIN-UART Transmitter interrupt indicates the availability of the Transmit Data Reg-
ister to accept new data for transmission. Follow these steps to configure the LIN-UART
for interrupt-driven data transmission:
1. Write to the LIN-UART Baud Rate High and Low Byte registers to set the appropriate
baud rate.
2. Enable the LIN-UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt control registers to enable the LIN-UART Transmitter interrupt
and set the appropriate priority.
5. If multiprocessor mode is appropriate, write to the LIN-UART Control 1 Register to
enable Multiprocessor (9-bit) mode functions.
Set the MULTIPROCESSOR Mode Select (MPEN) to Enable MULTIPROCESSOR
mode.
6. Write to the LIN-UART Control 0 Register to:
a. Set the transmit enable bit (TEN) to enable the LIN-UART for data transmission
b. If multiprocessor mode is not enabled, enable parity, if appropriate, and
select either even or odd parity.
c. Set or clear the CTSEbit to enable or disable control from the remote
receiver via the CTS pin.
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7. Execute an EI instruction to enable interrupts.
The LIN-UART is now configured for interrupt-driven data transmission. Because the
LIN-UART Transmit Data Register is empty, an interrupt is generated immediately. When
the LIN-UART Transmit interrupt is detected, and there is transmit data ready to send, the
associated interrupt service routine (ISR) performs the following:
1. If in MULTIPROCESSOR mode, write the LIN-UART Control 1 Register to select
the outgoing address bit:
Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte, clear it if
sending a data byte.
2. Write the data byte to the LIN-UART Transmit Data Register. The transmitter
automatically transfers the data to the Transmit Shift register and transmits the data.
3. Execute the IRET instruction to return from the interrupt-service routine and wait for
the Transmit Data Register to again become empty.
If a transmit interrupt occurs and there is no transmit data ready to send the interrupt-ser-
vice routine will execute the IRET instruction. When the application does have data to
transmit, software can set the appropriate interrupt request bit in the Interrupt Controller to
initiate a new transmit interrupt. Another alternative would be for software to write the
data to the Transmit Data Register instead of invoking the interrupt-service routine.
Receiving Data using the Polled Method
Follow these steps to configure the LIN-UART for polled data reception:
1. Write to the LIN-UART Baud Rate High and Low Byte registers to set the appropriate
baud rate.
2. Enable the LIN-UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. Write to the LIN-UART Control 1 Register to enable MULTIPROCESSOR mode
functions, if appropriate.
4. Write to the LIN-UART Control 0 Register to:
a. Set the Receive Enable Bit (REN) to enable the LIN-UART for data reception
b. If multiprocessor mode is not enabled, enable parity, if appropriate, and
select either even or odd parity.
5. Check the RDAbit in the LIN-UART Status 0 register to determine if the Receive Data
Register contains a valid data byte (indicated by a 1). If RDAis set to 1 to indicate
available data, continue to Step 6. If the Receive Data Register is empty (indicated by
a 0), continue to monitor the RDA bit awaiting reception of the valid data.
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6. Read data from the LIN-UART Receive Data Register. If operating in
MULTIPROCESSOR (9-bit) mode, further actions may be required depending on the
Multiprocessor Mode bits MPMD[1:0].
7. Return to Step 5 to receive additional data.
Receiving Data Using the Interrupt-Driven Method
The LIN-UART Receiver interrupt indicates the availability of new data (as well as error
conditions). Follow these steps to configure the LIN-UART receiver for interrupt-driven
operation:
1. Write to the LIN-UART Baud Rate High and Low Byte registers to set the appropriate
baud rate.
2. Enable the LIN-UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt Control registers to enable the LIN-UART Receiver interrupt
and set the appropriate priority.
5. Clear the LIN-UART Receiver interrupt in the applicable Interrupt Request Register.
6. Write to the LIN-UART Control 1 Register to enable MULTIPROCESSOR (9-bit)
mode functions, if appropriate.
a. Set the MULTIPROCESSOR Mode Select (MPEN) to Enable Multiprocessor
mode.
b. Set the MULTIPROCESSOR Mode Bits, MPMD[1:0]to select the
appropriate address matching scheme.
c. Configure the LIN-UART to interrupt on received data and errors or errors
only (interrupt on errors only is unlikely to be useful for Z8 Encore! devices
without a DMA block),
7. Write the device address to the Address Compare Register (automatic multiprocessor
modes only).
8. Write to the LIN-UART Control 0 Register to:
a. Set the receive enable bit (REN) to enable the LIN-UART for data reception
b. If MULTIPROCESSOR mode is not enabled, enable parity, if appropriate,
and select either even or odd parity.
9. Execute an EI instruction to enable interrupts.
The LIN-UART is now configured for interrupt-driven data reception. When the LIN-
UART Receiver interrupt is detected, the associated interrupt service routine (ISR) per-
forms the following:
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1. Check the LIN-UART Status 0 register to determine the source of the interrupt - error,
break, or received data.
2. If the interrupt was due to data available, read the data from the LIN-UART Receive
Data Register. If operating in MULTIPROCESSOR (9-bit) mode, further actions may
be required depending on the multiprocessor mode bits MPMD[1:0].
3. Execute the IRET instruction to return from the interrupt-service routine and await
more data.
Clear To Send Operation
The Clear To Send (CTS) pin, if enabled by the CTSEbit of the LIN-UART Control 0
Register, performs flow control on the outgoing transmit data stream. The Clear To Send
(CTS) input pin is sampled one system clock before beginning any new character trans-
mission. To delay transmission of the next data character, an external receiver must reduce
CTS at least one system clock cycle before a new data transmission begins. For multiple
character transmissions, this operation is typically performed during the Stop Bit transmis-
sion. If CTS stops in the middle of a character transmission, the current character is sent
completely.
External Driver Enable
The LIN-UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This
feature reduces the software overhead associated with using a GPIO pin to control the
transceiver when communicating on a multitransceiver bus, such as RS-485.
Driver Enable is a programmable polarity signal that envelopes the entire transmitted data
frame including parity and stop bits as illustrated in Figure 23. The Driver Enable signal
asserts when a byte is written to the LIN-UART Transmit Data Register. The Driver
Enable signal asserts at least one bit period and no greater than two bit periods before the
start bit is transmitted. This allows a setup time to enable the transceiver. The Driver
Enable signal deassertdeasserts one system clock period after the last stopbit is transmit-
ted. This one system clock delay allows both time for data to clear the transceiver before
disabling it, as well as the ability to determine if another character follows the current
character. In the event of back-to-back characters (new data must be written to the Trans-
mit Data Register before the previous character is completely transmitted) the DE signal is
not deassertd between characters. The DEPOLbit in the LIN-UART Control Register 1 sets
the polarity of the Driver Enable signal.
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Figure 23.LIN-UART Driver Enable Signal Timing with 1 Stop Bit and Parity
The Driver Enable to STARTbit set-up time is calculated as follows:
1
2
ð DE to Start Bit Setup Time(s) ð
Baud Rate (Hz)
Baud Rate (Hz)
LIN-UART Special Modes
The special modes of the LIN-UART are:
•
•
Multiprocessor Mode
LIN Mode
The LIN-UART features a common control register (Control 0) that contains a unique reg-
ister address and several mode-specific control registers (Multiprocessor Control, Noise
Filter Control, and LIN Control) that share a common register address (Control 1). When
the Control 1 address is read or written, the MSEL[2:0](Mode Select) field of the Mode
Select and Status Register determines which physical register is accessed. Similarly, there
are mode-specific status registers, one of which is returned when the Status 0 Register is
read, depending on the MSELfield.
Multiprocessor Mode
The LIN-UART features a MULTIPROCESSOR (9-bit) mode that uses an extra (9th) bit
for selective communication when a number of processors share a common UART bus. In
MULTIPROCESSOR mode (also referred to as 9-Bit mode), the multiprocessor bit (MP) is
transmitted immediately following the 8-bits of data and immediately preceding the Stop
bit(s) as illustrated in Figure 24. The character format is:
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Figure 24.LIN-UART Asynchronous Multiprocessor Mode Data Format
In Multiprocessor (9-bit) mode, the Parity bit location (9th bit) becomes the MULTIPRO-
CESSOR control bit. The LIN-UART Control 1 and Status 1 registers provide MULTI-
PROCESSOR (9-bit) mode control and status information. If an automatic address
matching scheme is enabled, the LIN-UART Address Compare register holds the network
address of the device.
Multiprocessor Mode Receive Interrupts
When MULTIPROCESSOR (9-bit) mode is enabled, the LIN-UART processes only
frames addressed to it. The determination of whether a frame of data is addressed to the
LIN-UART can be made in hardware, software or a combination of the two, depending on
the multiprocessor configuration bits. In general, the address compare feature reduces the
load on the CPU, because it does not need to access the LIN-UART when it receives data
directed to other devices on the multinode network. The following three MULTIPRO-
CESSOR modes are available in hardware:
•
•
•
Interrupt on all address bytes
Interrupt on matched address bytes and correctly framed data bytes
Interrupt only on correctly framed data bytes
These modes are selected with MPMD[1:0]in the LIN-UART Control 1 Register. For all
multiprocessor modes, bit MPENof the LIN-UART Control 1 Register must be set to 1.
The first scheme is enabled by writing 01bto MPMD[1:0]. In this mode, all incoming
address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt
service routine checks the address byte that triggered the interrupt. If it matches the LIN-
UART address, the software clears MPMD[0]. At this point, each new incoming byte
interrupts the CPU. The software determines the end of the frame and checks for it by
reading the MPRXbit of the LIN-UART Status 1 Register for each incoming byte. If
MPRX=1, a new frame has begun. If the address of this new frame is different from the
LIN-UART’s address, then MPMD[0]must be set to 1 by software, causing the LIN-
UART interrupts to go inactive until the next address byte. If the new frame’s address
matches the LIN-UART’s, then the data in the new frame is processed as well.
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The second scheme is enabled by setting MPMD[1:0] to 10B and writing the LIN-
UART’s address into the LIN-UART Address Compare Register. This mode introduces
more hardware control, interrupting only on frames that match the LIN-UART’s address.
When an incoming address byte does not match the LIN-UART’s address, it is ignored.
All successive data bytes in this frame are also ignored. When a matching address byte
occurs, an interrupt is issued and further interrupts occur on each successive data byte. The
first data byte in the frame has NEWFRM=1 in the LIN-UART Status 1 Register. When the
next address byte occurs, the hardware compares it to the LIN-UART’s address. If there is
a match, the interrupt occurs and the NEWFRMbit is set for the first byte of the new frame.
If there is no match, the LIN-UART ignores all incoming bytes until the next address
match.
The third scheme is enabled by setting MPMD[1:0] to 11B and by writing the LIN-UART’s
address into the LIN-UART Address Compare Register. This mode is identical to the sec-
ond scheme, except that there are no interrupts on address bytes. The first data byte of
each frame remains accompanied by a NEWFRMassertion.
LIN Protocol Mode
The LIN (Local Interconnect Network) protocol as supported by the LIN-UART module
is defined in rev 2.0 of the LIN Specification Package. The LIN protocol specification
covers all aspects of transferring information between LIN Master and Slave devices using
message frames including error detection and recovery, sleep mode and wake up from
sleep mode. The LIN-UART hardware in LIN mode provides character transfers to sup-
port the LIN protocol including BREAK transmission and detection, WAKE-UP transmis-
sion and detection, and slave autobauding. Part of the error detection of the LIN protocol
is for both master and slave devices to monitor their receive data when transmitting. If the
receive and transmit data streams do not match, the LIN-UART asserts the PLEbit (phys-
ical layer error bit in Status0 register). The message frame time-out aspect of the protocol
is left to software, requiring the use of an additional general purpose timer. The LIN mode
of the LIN-UART does not provide any hardware support for computing/verifying the
checksum field or verifying the contents of the Identifier field. These fields are treated as
data and are not interpreted by hardware. The checksum calculation/verification can easily
be implemented in software via the ADC (Add with Carry) instruction.
The LIN bus contains a single master and one or more slaves. The LIN master is responsi-
ble for transmitting the message frame header which consists of the Break, Synch and
Identifier fields. Either the master or one of the slaves transmits the associated response
section of the message which consists of data characters followed by a checksum charac-
ter.
In LIN mode, the interrupts defined for normal UART operation still apply with the fol-
lowing changes.
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•
•
Parity Error (PEbit in Status0 register) is redefined as the Physical Layer Error (PLE) bit.
The PLEbit indicates that receive data does not match transmit data when the LIN-UART
is transmitting. This applies to both Master and Slave operating modes.
The Break Detect interrupt (BRKDbit in Status0 register) indicates when a Break is detect-
ed by the slave (break condition for at least 11 bit times). Software can use this interrupt
to start a timer checking for message frame time-out. The duration of the break can be read
in the RxBreakLength[3:0]field of the Mode Status Register.
•
•
The Break Detect interrupt (BRKDbit in Status0 register) indicates when a Wake-up mes-
sage has been received if the LIN-UART is in LinSleep state.
In LIN slave mode, if the BRG counter overflows while measuring the autobaud period
(Start bit to beginning of bit 7 of autobaud character) an Overrun Error is indicated (OEbit
in the Status0 register). In this case, software sets the LinState field back to 10b, where the
slave ignores the current message and waits for the next break. The Baud Reload High and
Low registers are not updated by hardware if this autobaud error occurs. The OEbit is also
set if a data overrun error occurs.
LIN System Clock Requirements
The LIN master provides the timing reference for the LIN network and is required to have
a clock source with a tolerance of ±0.5%. A slave with autobaud capability is required to
have a baud clock matching the master oscillator within ±14%. The slave nodes autobaud
to lock onto the master timing reference with an accuracy of ±2%. If a slave does not con-
tain autobaud capability it must include a baud clock which deviates from the masters by
no more than ±1.5%. These accuracy requirements must include affects such as voltage
and temperature drift during operation.
Before sending/receiving messages, the Baud Reload High/Low registers must be initial-
ized. Unlike standard UART modes, the Baud Reload High/Low registers must be loaded
with the baud interval rather than 1/16 of the baud interval.
In order to autobaud with the required accuracy, the LIN slave system clock must be at
least 100 times the baud rate.
LIN Mode Initialization and Operation
The LIN protocol mode is selected by setting either the LMST(LIN Master) or LSLV(LIN
Slave), and optionally (for LIN slave) the ABEN(Autobaud Enable) bits in the LIN Control
Register. To access the LIN Control Register, the MSEL(Mode Select) field of the LIN-
UART Mode Select/Status register must be = 010B. The LIN-UART Control0 register
must be initialized with TEN= 1, REN= 1, all other bits = 0.
In addition to the LMST, LSLVand ABENbits in the LIN Control Register, a Lin-
State[1:0] field exists that defines the current state of the LIN logic. This field is initially
set by software. In the LIN Slave mode, the LinStatefield is updated by hardware as the
slave moves through the Wait For Break, AutoBaud, and Active states.
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The Noise Filter may also need to be enabled and configured when interfacing to a LIN
bus.
LIN MASTER Mode Operation
LIN MASTER mode is selected by setting LMST= 1, LSLV= 0, ABEN= 0, LinState[1:0]
= 11B.If the LIN bus protocol indicates the bus is required go into the LIN sleep state, the
LinState[1:0] bits must be set = 00B by software.
The Break is the first part of the message frame transmitted by the master, consisting of at
least 13 bit periods of logical zero on the LIN bus. During initialization of the LIN master,
the duration (in bit times) of the Break is written to the TxBreakLengthfield of the LIN
Control Register. The transmission of the Break is performed by setting the SBRKbit in the
Control 0 Register. The LIN-UART starts the Break once the SBRKbit is set and any char-
acter transmission currently underway has completed. The SBRKbit is deasserted by hard-
ware once the break is completed.
If it is necessary to generate a Break longer than 15 bit times, the SBRKbit can be used in
normal UART mode where software times the duration of the Break.
The Synch character is transmitted by writing a 55Hto the Transmit Data Register (TDRE
must = 1 before writing). The Synch character is not transmitted by the hardware until
after the Break is complete.
The Identifier character is transmitted by writing the appropriate value to the Transmit
Data Register (TDREmust = 1 before writing).
If the master is sending the response portion of the message, these data and checksum
characters are written to the Transmit Data Register when the TDREbit asserts. If the trans-
mit data register is written after TDREasserts, but before TXEasserts, the hardware inserts
one or two stop bits between each character as determined by the Stopbit in the Control0
register. Additional idle time occurs between characters if TXEasserts before the next
character is written.
If the selected slave is sending the response portion of the frame to the master, each
receive byte will be signalled by the receive data interrupt (RDA bit will be set in the
Status0 register).
If the selected slave is sending the response to a different slave, the master can ignore the
response characters by deasserting the RENbit in the Control0 register until the frame time
slot has completed.
LIN Sleep Mode
While the LIN bus is in the sleep state, the CPU can be in either low power STOP mode,
in HALT mode, or in normal operational state. Any device on the LIN bus may issue a
Wake-up message if it requires the master to initiate a LIN message frame. Following the
Wake-up message, the master wakes up and initiates a new message. A Wake-up message
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is accomplished by pulling the bus low for at least 250µs but less than 5ms. Transmitting
a 00hcharacter is one way to transmit the wake-up message.
If the CPU is in STOP mode, the LIN-UART is not active and the Wake-up message must
be detected by a GPIO edge detect Stop-Mode Recovery. The duration of the Stop-Mode
Recovery sequence may preclude making an accurate measurement of the Wake-up mes-
sage duration.
If the CPU is in HALT or operational mode, the LIN-UART (if enabled) times the dura-
tion of the Wake-up and provides an interrupt following the end of the break sequence if
the duration is ≥ 3 bit times. The total duration of the Wake-up message in bit times may
be obtained by reading the RxBreakLengthfield in the Mode Status register. After a
Wake-up message has been detected, the LIN-UART can be placed (by software) into
either LIN Master or LIN Slave Wait for Break states as appropriate. If the break duration
exceeds 15 bit times, the RxBreakLengthfield contains the value Fh. If the LIN-UART
is disabled, the Wake-up message can be detected via a port pin interrupt and timed by
software. If the device is in STOP mode, the high to low transition on the port pin will
bring the device out of STOP mode.
The LIN Sleep state is selected by software setting LinState[1:0] = 00. The decision to
move from an active state to sleep state is based on the LIN messages as interpreted by
software.
LIN Slave Operation
LIN Slave mode is selected by setting LMST= 0, LSLV= 1, ABEN= 1 or 0 and Lin-
State[1:0] = 01b(Wait for Break State). The LIN slave detects the start of a new mes-
sage by the Break which appears to the Slave as a break of at least 11 bit times in duration.
The LIN-UART detects the Break and generates an interrupt to the CPU. The duration of
the Break is observable in the RxBreakLengthfield of the Mode Status register. A Break
of less than 11 bit times in duration does not generate a break interrupt when the LIN-
UART is in Wait for Break state. If the Break duration exceeds 15 bit times, the
RxBreakLengthfield contains the value Fh.
Following the Break the LIN-UART hardware automatically transitions to the Autobaud
state, where it autobauds by timing the duration of the first 8 bit times of the Synch charac-
ter as defined in the standard.The duration of the autobaud period is measured by the BRG
Counter which will update every 8th system clock cycle between the start bit and the
beginning of bit 7 of the autobaud sequence. At the end of the autobaud period, the dura-
tion measured by the BRG counter (auto baud period divided by 8) is automatically trans-
ferred to the Baud Reload High and Low registers if the ABENbit of the LIN control
register is set. If the BRG Counter overflows before reaching the start of bit 7 in the auto-
baud sequence the Autobaud Overrun Error interrupt occurs, the OEbit in the Status0 reg-
ister is set and the Baud Reload registers are not updated. To autobaud within 2% of the
master’s baud rate, the slave system clock must be a minimum of 100 times the baud rate.
To avoid an autobaud overrun error, the system clock must not be greater than 219 times
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the baud rate (16 bit counter following 3-bit prescaler when counting the 8 bit times of the
Autobaud sequence).
Following the Synch character, the LIN-UART hardware transitions to the Active state
where the Identifier character is received and the characters of the Response section of the
message are sent or received. The slave remains in the active state until a Break is received
or software forces a state change. Once in Active State (autobaud has completed), a Break
of 10 or more bit times is recognized and will cause a transition to the Autobaud state.
If the Identifier character indicates that this slave device is not participating in the mes-
sage, software can set the LinState[1:0]= 01b(Wait for Break State) to ignore the rest
of the message. No further receive interrupts will occur until the next Break.
LIN-UART Interrupts
The LIN-UART features separate interrupts for the transmitter and receiver. In addition,
when the LIN-UART primary functionality is disabled, the Baud Rate Generator can also
function as a basic timer with interrupt capability.
Transmitter Interrupts
The transmitter generates a single interrupt when the Transmit Data Register Empty bit
(TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for trans-
mission. The TDRE interrupt occurs when the transmitter is initially enabled and after the
Transmit shift register has shifted the first bit of a character out. At this point, the Transmit
Data Register may be written with the next character to send. This provides 7 bit periods
of latency to load the Transmit Data Register before the Transmit shift register completes
shifting the current character. Writing to the LIN-UART Transmit Data Register clears the
TDREbit to 0.
Receiver Interrupts
The receiver generates an interrupt when any of the following occurs:
•
A data byte has been received and is available in the LIN-UART Receive Data Register.
This interrupt can be disabled independent of the other receiver interrupt sources via the
RDAIRQbit (this feature is useful in devices which support DMA). The received data in-
terrupt occurs once the receive character has been placed in the Receive Data Register.
Software must respond to this received data available condition before the next character
is completely received to avoid an overrun error.
In MULTIPROCESSOR mode (MPEN= 1), the receive-data interrupts are dependent on
Note:
the multiprocessor configuration and the most recent address byte
•
•
A break is received
A receive data overrun or LIN slave autobaud overrun error is detected.
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•
•
A data framing error is detected
A parity error is detected (physical layer error in LIN mode)
LIN-UART Overrun Errors
When an overrun error condition occurs the LIN-UART prevents overwriting of the valid
data currently in the Receive Data Register. The Break Detect and Overrun status bits are
not displayed until after the valid data has been read.
After the valid data has been read, the OEbit of the Status 0 register is updated to indicate
the overrun condition (and Break Detect, if applicable). The RDAbit is set to 1 to indicate
that the Receive Data Register contains a data byte. However, because the overrun error
occurred, this byte may not contain valid data and must be ignored. The BRKDbit indicates
if the overrun was caused by a break condition on the line. After reading the status byte
indicating an overrun error, the Receive Data Register must be read again to clear the error
bits in the LIN-UART Status 0 register.
In LIN mode, an Overrun Error is signaled for receive-data overruns as described above
and in the LIN Slave if the BRG Counter overflows during the autobaud sequence (the
ATBbit will also be set in this case). There is no data associated with the autobaud over-
flow interrupt, however the Receive Data Register must be read to clear the OEbit. In this
case software must write a 10B to the LinStatefield, forcing the LIN slave back to a
Wait for Break state.
LIN-UART Data- and Error-Handling Procedure
Figure 25 illustrates the recommended procedure for use in LIN-UART receiver interrupt
service routines.
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Figure 25.LIN-UART Receiver Interrupt Service Routine Flow
Baud Rate Generator Interrupts
If the BRGCTLbit of the Multiprocessor Control Register (LIN-UART Control 1 Register
with MSEL = 000b) register is set, and the RENbit of the Control 0 Register is 0, the LIN-
UART Receiver interrupt asserts when the LIN-UART Baud Rate Generator reloads. This
action allows the Baud Rate Generator to function as an additional counter if the LIN-
UART receiver functionality is not employed. The transmitter can be enabled in this
mode.
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LIN-UART Baud Rate Generator
The LIN-UART Baud Rate Generator creates a lower frequency baud rate clock for data
transmission. The input to the Baud Rate Generator is the system clock. The LIN-UART
Baud Rate High and Low Byte registers combine to create a 16-bit baud rate divisor value
(BRG[15:0]) that sets the data-transmission rate (baud rate) of the LIN-UART. The LIN-
UART data rate is calculated using the following equation for normal UART operation:
System Clock Frequency (Hz)
UART Data Rate (bits/s) =
16 x UART Baud Rate Divisor Value
The LIN-UART data rate is calculated using the following equation for LIN mode UART
operation:
System Clock Frequency (Hz)
UART Data Rate (bits/s) =
UART Baud Rate Divisor Value
When the LIN-UART is disabled, the Baud Rate Generator can function as a basic 16-bit
timer with interrupt on time-out. To configure the Baud Rate Generator as a timer with
interrupt on time-out, complete the following procedure:
1. Disable the LIN-UART receiver by clearing the RENbit in the LIN-UART Control 0
Register to 0 (TENbit may be asserted, transmit activity may occur).
2. Load the appropriate 16-bit count value into the LIN-UART Baud Rate High and Low
Byte registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BRGCTLbit in the LIN-UART Control 1 Register to 1.
Noise Filter
A noise filter circuit is included which filters noise on a digital input signal (such as
UART Receive Data) before the data is sampled by the block. This is likely to be a
requirement for protocols with a noisy environment.
The noise filter contains the following features:
•
•
Synchronizes the receive input data to the System Clock
Noise Filter Enable (NFEN) input selects whether the noise filter is bypassed (NFEN = 0)
or included (NFEN = 1) in the receive data path.
•
Noise Filter Control (NFCTL[2:0]) input selects the width of the up/down saturating
counter digital filter. The available widths range from 4 bits to 11 bits.
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•
•
The digital filter output features hysteresis
Provides an active low Saturated State output (FiltSatB) which is used as an indication
of the presence of noise.
Architecture
Figure 26 illustrates how the noise filter is integrated with the LIN-UART for use on a
LIN network.
Figure 26.Noise Filter System Block Diagram
Operation
The figure below illustrates the operation of the noise filter both with and without noise.
The noise filter in this example is a 2-bit up/down counter which saturates at 00b and
11b.A 2-bit counter is shown for convenience, the operation of wider counters is similar.
The output of the filter switches from 1 to 0 when the counter counts down from 01b to
00b and switches from 0 to 1 when the counter counts up from 10b to 11b.The noise
filter delays the receive data by three System Clock cycles.
The FiltSatB signal is checked when the filtered RxD is sampled in the center of the bit
time. The presence of noise (FiltSatB = 1at center of bit time) does not mean the sam-
pled data is incorrect, just that the filter is not in its "saturated" state of all 1’s or all 0’s. If
FiltSatB = 1 when RxD is sampled during a receive character, the NEbit in the ModeSta-
tus[4:0]field is set. By observing this bit, an indication of the level of noise in the net-
work can be obtained.
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Figure 27.Noise Filter Operation
LIN-UART Control Register Definitions
The LIN-UART control registers support the LIN-UART, the associated Infrared
Encoder/Decoder and the noise filter. For more information on the infrared operation,
refer to the Infrared Encoder/Decoder chapter on page 175.
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LIN-UART Transmit Data Register
Data bytes written to the LIN-UART Transmit Data Register, shown in Table 82, are
shifted out on the TxD pin. The Write-only LIN-UART Transmit Data Register shares a
Register File address with the read-only LIN-UART Receive Data Register.
Table 82. LIN-UART Transmit Data Register (U0TXD = F40h)
BITS
7
6
5
4
3
2
1
0
TxD
FIELD
RESET
R/W
X
X
X
X
X
X
X
X
W
W
W
W
W
W
W
W
F40H, F48H
ADDR
Note: W = Write; X = undefined.
TXD—Transmit Data
LIN-UART transmitter data byte to be shifted out through the TxD pin.
LIN-UART Receive Data Register
Data bytes received through the RxD pin are stored in the LIN-UART Receive Data Reg-
ister, shown in Table 83. The read-only LIN-UART Receive Data Register shares a Regis-
ter File address with the Write-only LIN-UART Transmit Data Register.
Table 83. LIN-UART Receive Data Register (U0RXD = F40h)
BITS
7
6
5
4
3
2
1
0
RxD
FIELD
RESET
R/W
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
F40H, F48H
ADDR
Note: R = Read.
RXD—Receive Data
LIN-UART receiver data byte from the RxD pin
LIN-UART Status 0 Register
The LIN-UART Status 0 Register identifies the current LIN-UART operating configura-
tion and status. Table 84 describes the Status 0 Register for standard UART mode.
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Table 85, which follows on page 159, describes the Status0 Register for LIN mode. A
more detailed discussion of each bit follows each table.
Table 84. LIN-UART Status 0 Register—Standard UART Mode (U0STAT0 = F41h)
BITS
7
6
5
4
3
2
1
0
RDA
PE
OE
FE
BRKD TDRE TXE
CTS
FIELD
RESET
R/W
0
0
0
0
0
1
1
X
R
R
R
R
R
R
R
R
F41H, F49H
ADDR
Note: R = Read; X = undefined.
RDA— Receive Data Available
0 = The LIN-UART Receive Data Register is empty.
1 = There is a byte in the LIN-UART Receive Data Register
PE— Parity Error
0 = No parity error occurred
1 = A parity error occurred
OE— Overrun Error
0 = No overrun error occurred
1 = An overrun error occurred
FE— Framing Error
0 = No framing error occurred
1 = A framing error occurred
BRKD— Break Detect
0 = No break occurred
1 = A break occurred
TDRE— Transmitter Data Register Empty
0 = Data is currently transmitting
1 = Transmission is complete
TXE— Transmitter Empty
0 = No overrun error occurred
1 = An overrun error occurred
CTS— Cleat to Send Signal
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. Receive Data Available (RDA). This bit indicates that the LIN-UART Receive Data
Register has received data. Reading the LIN-UART Receive Data Register clears this bit.
Parity Error (PE). This bit indicates that a parity error has occurred. Reading the Receive
Data Register clears this bit.
Overrun Error (OE). This bit indicates that an overrun error has occurred. An overrun
occurs when new data is received and the Receive Data Register has not been read. Read-
ing the Receive Data Register clears this bit.
Framing Error (FE). This bit indicates that a framing error (no STOP bit following data
reception) was detected. Reading the Receive Data Register clears this bit.
Break Detect (BRKD). This bit indicates that a break occurred. If the data bits, parity/
multiprocessor bit, and STOP bit(s) are all zeros then this bit is set to 1. Reading the
Receive Data Register clears this bit.
Transmitter Data Register Empty (TDRE). This bit indicates that the Transmit Data
Register is empty and ready for additional data. Writing to the Transmit Data Register
resets this bit.
Transmitter Empty (TXE). This bit indicates that the transmit shift register is empty and
character transmission is finished.
Clear To Send Signal (CTS). When this bit is read it returns the level of the CTS signal.
If LBEN = 1, the CTS input signal is replaced by the internal Receive Data Available sig-
nal to provide flow control in loopback mode. CTS only affects transmission if the CTSE
bit = 1.
Table 85. LIN-UART Status 0 Register—LIN Mode (U0STAT0 = F41h)
BITS
7
6
5
4
3
2
1
0
RDA
PLE
OE
FE
BRKD TDRE TXE
ATB
FIELD
RESET
R/W
0
0
0
0
0
1
1
0
R
R
R
R
R
R
R
R
F41H, F49H
ADDR
Note: R = Read.
RDA— Receive Data Available
0 = The Receive Data Register is empty.
1 = There is a byte in the Receive Data Register
PE— Physical Layer Error
0 = Transmit and Receive data match
1 = Transmit and Receive data do not match
OE— Receive Data and Autobaud Overrun Error
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0 = No autobaud or data overrun error occurred
1 = An autobaud or data overrun error occurred
FE— Framing Error
0 = No framing error occurred
1 = A framing error occurred
BRKD— Break Detect
0 = No LIN break occurred
1 = A LIN break occurred
TDRE— Transmitter Data Register Empty
0 = Do not write to the Transmit Data Register
1 = The Transmit Data Register is ready to receive an additional byte to be transmitted
TXE— Transmitter Empty
0 = Data is currently transmitting
1 = Transmission is complete
ATB— LIN Slave Autobaud complete
Receive Data Available (RDA). This bit indicates that the Receive Data Register has
received data. Reading the Receive Data Register clears this bit.
Physical Layer Error (PLE). This bit indicates that transmit and receive data do not
match when a LIN slave or master is transmitting. This could be caused by a fault in the
physical layer or multiple devices driving the bus simultaneously. Reading the Status 0
Register or the Receive Data Register clears this bit.
Receive Data and Autobaud Overrun Error (OE). This bit is set just as in normal UART
operation if a receive data overrun error occurs. This bit is also set during LIN Slave auto-
baud if the BRG counter overflows before the end of the autobaud sequence, indicating
the receive activity was not an autobaud character or the master baud rate is too slow. The
ATB status bit will also be set in this case. This bit is cleared by reading the Receive Data
Register.
Framing Error (FE). This bit indicates that a framing error (no STOP bit following data
reception) was detected. Reading the Receive Data Register clears this bit.
Break Detect (BRKD). This bit is set in LIN mode if (a) in LinSleep state and a break of at
least 4 bit times occurred (Wake-up event) or (b) in Slave Wait Break state and a break of
at least 11 bit times occurred (Break event) or (c) in Slave Active state and a break of at
least 10 bit times occurs. Reading the Status 0 Register or the Receive Data Register clears
this bit.
Transmitter Data Register Empty (TDRE). This bit indicates that the Transmit Data
Register is empty and ready for additional data. Writing to the Transmit Data Register
resets this bit.
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Transmitter Empty (TXE). This bit indicates that the transmit shift register is empty and
character transmission is finished.
LIN Slave Autobaud Complete (ATB). This bit is set in LIN SLAVE mode when an
autobaud character is received. If the ABIEN bit is set in the LIN Control Register, then a
receive interrupt is generated when this bit is set. Reading the Status 0 Register clears this
bit. This bit will be 0 in LIN MASTER mode.
LIN-UART Mode Select and Status Register
The LIN-UART Mode Select and Status Register, shown in Table 86, contains mode select
and status bits. A more detailed discussion of each bit follows the table.
Table 86. LIN-UART Mode Select and Status Register (U0MDSTAT = F44h)
BITS
7
6
5
4
3
2
1
0
MSEL
MODE STATUS
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R
R
R
R
R
F44H, F4CH
ADDR
Note: R = Read; R/W = Read/Write.
7— 5 Mode Select
000 = Multiprocessor and normal UART control/status
001 = Noise filter control/status
010 = LIN protocol control/status
011 = Reserved
100 = Reserved
101 = Reserved
110 = Reserved
111 = LIN-UART hardware revision (allows hardware revision to be read in the
Mode Status field
4—0 Mode Status
000 = Multiprocessor mode status = {0,0,0,NEWFRM, MPRX}
001 = Noise filter status = {NE,0,0,0,0}
010 = LIN mode status = {NE, RxBreakLength}
011 = Reserved; must be 00000
100 = Reserved; must be 00000
101 = Reserved; must be 00000
110 = Reserved; must be 00000
111 = LIN-UART hardware revision
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Mode Select (MSEL). This R/W field determines which control register is accessed when
performing a write or read to the Uart Control 1 Register address. This field also deter-
mines which status is returned in the Mode Status field when reading this register.
Mode Status. This read-only field returns status corresponding to one of four modes
selected by MSEL. These four modes are described in Table 87.
Table 87. Mode Status Fields
Multiprocessor Mode
NEWFRM
Status Field
Status bit denoting the start of a new frame. Reading the LIN-UART Receive
Data Register resets this bit to 0.
0 = The current byte is not the first data byte of a new frame.
1 = The current byte is the first data byte of a new frame.
Multiprocessor Receive (MPRX)
Returns the value of the last multiprocessor bit received. Reading from the LIN-
UART Receive Data Register resets this bit to 0.
Digital Noise Filter
Mode Status Field
Noise Event (NE); MSEL = 001b
This bit is asserted if digital noise is detected on the receive data line while the
data is sampled (center of bit-time). If this bit is set, it does not mean that the
receive data is corrupted (though it may be in extreme cases), just that one or
more of the noise filter data samples near the center of the bit-time did not match
the average data value.
LIN Mode Status
Field
Noise Event (NE); MSEL = 010b
This bit is asserted if some noise level is detected on the receive data line while
the data is sampled (center of bit-time). If this bit is set, it does not indicate that
the receive data is corrupt (though it may be in extreme cases), just that one or
more of the 16x data samples near the center of the bit-time did not match the
average data value.
RxBreakLength
LIN mode received break length. This field may be read following a break (LIN
WAKE-UP or BREAK) so software can determine the measured duration of the
break. If the break exceeds 15 bit times the value saturates at 1111b.
Hardware Revision
Mode Status Field
Noise Event (NE); MSEL = 111b
This field indicates the hardware revision of the LIN-UART block.
00_xxx LIN UART hardware revision.
01_xxx Reserved.
10_xxx Reserved.
11_xxx Reserved.
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LIN-UART Control 0 Register
The LIN-UART Control 0 Register, shown in Table 87, configures the basic properties of
the LIN-UART’s transmit and receive operations. A more detailed discussion of each bit
follows the table.
Table 88. LIN-UART Control 0 Register (U0CTL0 = F42h)
BITS
7
6
5
4
3
2
1
0
TEN
REN CTSE PEN PSEL SBRK STOP LBEN
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F42H, F4AH
ADDR
Note: R/W = Read/Write.
TEN—Transmit Enable
0 = Transmitter disabled
1 = Transmitter enabled
REN—Receive Enable
0 = Receiver disabled
1 = REceiver enabled
CTSE—Clear To Send Enable
0 = The CTS signal has no effect on the transmitter
1 = The LIN-UART recognizes the CTS signal as an enable control for the transmitter.
PEN—Parity Enable
0 = Parity is disabled. This bit is overridden by the MPEN bit.
1 = The transmitter sends data with an additional parity bit and the receiver receives an
additional parity bit.
PSEL—Parity Select
0 = Even parity is expected is transmitted and expected on all received data.
1 = Odd parity is expected is transmitted and expected on all received data.
SBRK—Send Break
0 = No break is sent.
1 = The output of the transmitter is 0.
STOP—Stop Bit Select
0 = The transmitter sends one STOP bit.
1 = The transmitter sends two STOP bits.
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LBEN—Loop Back Enable
0 = Normal operation.
1 = All transmitted data is looped back to the receiver within the IrDA module.
Transmit Enable (TEN). This bit enables or disables the transmitter. The enable is also
controlled by the CTS signal and the CTSE bit. If the CTS signal is Low and the CTSE bit
is 1, the transmitter is enabled.
Receive Enable (REN). This bit enables or disables the receiver.
Clear To Send Enable (CTSE). See the bit descriptions in Table 88.
Parity Enable (PEN). This bit enables or disables parity. Even or odd is determined by the
PSEL bit.
Parity Select (PSEL). See the bit descriptions in Table 88.
Send Break (SBRK). This bit pauses or breaks data transmission. Sending a break inter-
rupts any transmission in progress, so ensure that the transmitter has finished sending data
before setting this bit. In standard UART mode, the duration of the break is determined by
how long software leaves this bit asserted. Also the duration of any required STOP bits
following the break must be timed by software before writing a new byte to be transmitted
to the Transmit Data Register. In LIN mode, the master sends a Break character by assert-
ing SBRK. The duration of the break is timed by hardware, and the SBRK bit is deasserted
by hardware when the Break is completed. The duration of the Break is determined by the
TxBreakLength field of the LIN Control Register. One or two STOP bits are automatically
provided by the hardware in LIN mode as defined by the STOP bit.
Stop Bit Select (STOP). See the bit descriptions in Table 88.
Loop Back Enable (LBEN). See the bit descriptions in Table 88.
LIN-UART Control 1 Registers
Multiple registers, shown in Tables 89 through 91) are accessible by a single bus address.
The register selected is determined by the Mode Select (MSEL) field. These registers pro-
vide additional control over LIN-UART operation.
Multiprocessor Control Register
When MSEL = 000b, the Multiprocessor Control Register, shown in 89, provides control
for UART multiprocessor mode, IRDA mode, baud rate timer mode as well as other fea-
tures that may apply to multiple modes. A more detailed discussion of each bit follows the
table.
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Table 89. Multiprocessor Control Register (U0CTL1 = F43h with MSEL = 000b)
BITS
7
6
5
4
3
2
1
0
MPMD1 MPEN MPMD0 MPBD DEPOL BRGCTL RDAIRQ IREN
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F43H, F4BH
ADDR
Note: R/W = Read/Write.
Bit
Position
Value
Description
[7,5]
Multiprocessor Mode
MPMD[1:0]
00
01
10
The LIN-UART generates an interrupt request on all received
bytes (data and address).
The LIN-UART generates an interrupt request only on received
address bytes.
The LIN-UART generates an interrupt request when a received
address byte matches the value stored in the Address Compare
Register and on all successive data bytes until an address
mismatch occurs.
11
The LIN-UART generates an interrupt request on all received
data bytes for which the most recent address byte matched the
value in the Address Compare Register.
6
Multiprocessor Enable
MPEN
0
1
Disable Multiprocessor (9-bit) mode.
Enable Multiprocessor (9-bit) mode.
4
Multiprocessor Bit Transmit
MPBT
0
Send a 0 in the multiprocessor bit location of the data stream
(9th bit).
1
Send a 1 in the multiprocessor bit location of the data stream
(9th bit).
3
Driver Enable Polarity
DEPOL
0
1
DE signal is active High.
DE signal is active Low.
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Bit
Position
Value
Description
2
Baud Rate Generator Control, when LIN-UART receiver not enabled
BRGCTL
0
1
BRG is disabled. Reads from the Baud Rate High and Low Byte
registers return the BRG reload value.
BRG is enabled and counting. The Baud Rate Generator
generates a receive interrupt when it counts down to 0. Reads
from the Baud Rate High and Low Byte registers return the
current BRG count value.
Baud Rate Generator Control, when LIN-UART receiver enabled
0
Reads from the Baud Rate High and Low Byte registers return
the BRG reload value.
1
Reads from the Baud Rate High and Low Byte registers return
the current BRG count value. Unlike the timers, there is no
mechanism to latch the High Byte when the Low Byte is read.
1
Stop Bit Select
RDAIRQ
0
Received data and receiver errors generates an interrupt
request to the Interrupt controller.
1
Received data does not generate an interrupt request to the
Interrupt controller. Only receiver errors generate an interrupt
request.
0
Loop Back Enable
IREN
0
Infrared Encoder/Decoder is disabled. LIN-UART operates
normally.
1
Infrared Encoder/Decoder is enabled. The LIN-UART transmits
and receives data through the Infrared Encoder/Decoder.
MPMD—Multiprocessor Mode
00 = The LIN-UART generates an interrupt request on all received bytes (data and
address)
01 = The LIN-UART generates an interrupt request on all received address bytes.
10 = The LIN-UART generates an interrupt request when a received address byte matches
the value stored in the Address Compare Register and on all successive data bytes
until an address mismatch occurs.
11 = The LIN-UART generates an interrupt request on all received data bytes for which
the most recent address byte matches the value in the Address Compare Register.
MPEN—Multiprocessor Enable
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0 = Disable multiprocessor (9-bit) mode
1 = Enable multiprocessor (9-bit) mode
Multiprocessor Mode (MPMD[1:0]). MULTIPROCESSOR (9-bit) mode—bits 7 and 5.
Multiprocessor (9-Bit) Enable (MPEN). This bit is used to enable MULTIPROCESSOR
(9-bit) mode.
Multiprocessor Bit Transmit (MPBT). This bit is applicable only when MULTIPRO-
CESSOR (9-bit) mode is enabled.
Driver Enable Polarity (DEPOL). See the bit descriptions in Table 89.
Baud Rate Generator Control (BRGCTL). This bit causes different LIN-UART behavior
depending on whether the LIN-UART receiver is enabled (REN = 1 in the LIN-UART
Control 0 Register).
When the LIN-UART receiver is not enabled, this bit determines whether the Baud Rate
Generator issues interrupts. When the LIN-UART receiver is enabled, this bit allows
Reads from the baud rate registers to return the BRG count value instead of the reload
value.
Receive Data Interrupt Enable (RDAIRQ). See the bit descriptions in Table 89.
Infrared Encoder/Decoder Enable (IREN). See the bit descriptions in Table 89.
Noise Filter Control Register
When MSEL = 001b, the Noise Filter Control Register, shown in Table 90, provides con-
trol for the digital noise filter. A more detailed discussion of each bit follows the table.
Table 90. Noise Filter Control Register (U0CTL1 = F43h with MSEL = 001b)
Bits
7
6
5
4
3
2
1
0
NFEN
NFCTL
—
Field
0
0
0
0
0
0
0
0
Reset
R/W
R/W
R/W
R/W
R
R
R
R
CPU Access
ADDR
F43H, F4BH
Note: R = Read; R/W = Read/Write.
Bit
Position
Value
Description
7
Noise Filter Enable
NFEN
0
1
Noise filter is disabled.
Noise filter is enabled. Receive data is preprocessed by the
noise filter.
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Bit
Position
Value
Description
[6:4]
Noise Filter Control
NFCTL
000
001
010
011
100
101
110
111
—
4-bit up/down counter.
5-bit up/down counter.
6-bit up/down counter.
7-bit up/down counter.
8-bit up/down counter.
9-bit up/down counter.
10-bit up/down counter.
11-bit up/down counter.
Reserved; must be 0000.
[3:0]
Reserved
Noise Filter Enable (NFEN). See the bit descriptions in Table 90.
Noise Filter Control (NFCTL). This field controls the delay and noise rejection character-
istics of the noise filter. The wider the counter the more delay that is introduced by the fil-
ter and the wider the noise event that is filtered.
LIN Control Register
When MSEL= 010b, the LIN Control Register provides control for the LIN mode of oper-
ation. A more detailed discussion of each bit follows the table.
Table 91. LIN Control Register (U0CTL1 = F43h with MSEL = 010b)
Bits
7
6
5
4
3
2
1
0
LMST LSLV ABEN ABIEN LinState[1:0] TxBreakLength
Field
0
0
0
0
0
0
0
0
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CPU Access
F43H, F4BH
ADDR
Note: R/W = Read/Write.
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Bit
Position
Value
Description
7
LIN Master Mode
LMST
0
1
LIN MASTER mode not selected.
LIN MASTER mode selected (if MPEN, PEN, LSLV = 0).
6
LIN Slave Mode
LSLV
0
1
LIN SLAVE mode not selected
LIN SLAVE mode selected (if MPEN, PEN, LMST = 0)
5
Autobaud Enable
ABEN
0
1
Autobaud not enabled.
Autobaud enabled if in LIN SLAVE mode.
4
Autobaud Interrupt Enable
ABIEN
0
1
Interrupt following autobaud does not occur.
Interrupt following autobaud enabled if in LIN SLAVE mode.
When the autobaud character is received, a receive interrupt
is generated and the ATB bit is set in the Status0 Register.
[3:2]
LIN State Machine
LinState[1:0]
00
01
10
11
Sleep state (either LMST or LSLV can be set).
Wait for Break state (only valid for LSLV = 1).
Autobaud state (only valid for LSLV = 1).
Active state (either LMST or LSLV can be set).
[1:0]
TxBreakLength
TxBreakLength
00
01
10
11
13 bit-times.
14 bit-times.
15 bit-times.
16 bit-times.
LIN Master Mode (LMST). See the bit descriptions in Table 91.
LIN Slave Mode (LSLV). See the bit descriptions in Table 91.
Autobaud Enable (ABEN). See the bit descriptions in Table 91.
Autobaud Interrupt Enable (ABIEN). See the bit descriptions in Table 91.
LIN State Machine (LinState[1:0]). The LinState is controlled by both hardware and soft-
ware. Software can force a state change at any time if necessary. In normal operation, soft-
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ware moves the state in and out of Sleep state. For a LIN slave, software changes the state
from Sleep to Wait for Break, after which hardware cycles through the Wait for Break,
Autobaud, and Active states. Software changes the state from one of the active states to
Sleep state if the LIN bus goes into SLEEP mode. For a LIN master, software changes the
state from Sleep to Active, where it remains until software sets it back to the Sleep state.
After configuration, software does not alter the LinState field during operation.
Transmit Break Length (TxBreakLength). Used in LIN mode by the master to control
the duration of the transmitted break.
LIN-UART Address Compare Register
The LIN-UART Address Compare Register stores the multinode network address of the
LIN-UART. When the MPMD[1] bit of the LIN-UART Control Register 0 is set, all
incoming address bytes are compared to the value stored in this Address Compare Register.
Receive interrupts and RDA assertions only occur in the event of a match. See Table 92.
Table 92. LIN-UART Address Compare Register (U0ADDR = F45h)
Bits
7
6
5
4
3
2
1
0
COMP_ADDR
Field
0
0
0
0
0
0
0
0
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CPU Access
F45H, F4DH
ADDR
Note: R/W = Read/Write.
Bit
Position
Value
Description
Compare Address
This 8-bit value is compared to the incoming address bytes.
[7:0]
COMP_ADDR
—
LIN-UART Baud Rate High and Low Byte Registers
The LIN-UART Baud Rate High and Low Byte registers, shown in Tables 93 and 94)
combine to create a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmis-
sion rate (baud rate) of the LIN-UART.
Table 93. LIN-UART Baud Rate High Byte Register (U0BRH = F46h)
Bits
7
6
5
4
3
2
1
0
BRH
Field
1
1
1
1
1
1
1
1
Reset
Note: R/W = Read/Write.
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Table 93. LIN-UART Baud Rate High Byte Register (U0BRH = F46h)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CPU Access
F45H, F4DH
ADDR
Note: R/W = Read/Write.
Bit
Position
Value
Description
Baud Rate High
High byte of baud rate divisor value.
[7:0]
BRH
—
Table 94. LIN-UART Baud Rate Low Byte Register (U0BRL = F47h)
Bits
7
6
5
4
3
2
1
0
BRL
Field
Reset
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CPU Access
Note: R/W = Read/Write.
Bit
Position
Value
Description
Baud Rate Low
Low byte of baud rate divisor value.
[7:0]
BRL
—
The LIN-UART data rate is calculated using the following equation for standard UART
modes. For LIN protocol, the Baud Rate registers must be programmed with the baud
period rather than 1/16 baud period.
The UART must be disabled when updating the Baud Rate registers because the high and
low registers must be written independently.
Note:
The LIN-UART data rate is calculated using the following equation for standard UART
operation:
UART Data Rate (bits per second) = System Clock Frequency (Hz)
16 x UART Baud Rate Divisor Value
The LIN-UART data rate is calculated using the following equation for LIN mode UART
operation:
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UART Data Rate (bits per second) = System Clock Frequency (Hz)
UART Baud Rate Divisor Value
For a given LIN-UART data rate, the integer baud rate divisor value is calculated using
the following equation for standard UART operation:
System Clock Frequency (Hz)
⎛
⎝
⎞
⎠
-------------------------------------------------------------------------------
16xUART Data Rate (bits/s)
UART Baud Rate Divisor Value (BRG) = Round
For a given LIN-UART data rate, the integer baud rate divisor value is calculated using
the following equation for LIN mode UART operation:
System Clock Frequency (Hz)
⎛
⎝
⎞
⎠
-------------------------------------------------------------------------------
UART Baud Rate Divisor Value (BRG) = Round
UART Data Rate (bits/s)
The baud rate error relative to the appropriate baud rate is calculated using the following
equation:
Actual Data Rate – Desired Data Rate
⎛
⎝
⎞
⎠
----------------------------------------------------------------------------------------------------
UART Baud Rate Error (%) = 100 ×
Desired Data Rate
For reliable communication, the LIN-UART baud rate error must never exceed 5 percent.
Tables 95 through 99 provide error data for popular baud rates and commonly-used crystal
oscillator frequencies for normal UART modes of operation.
Table 95. LIN-UART Baud Rates, 20.0 MHz System Clock
Applicable BRGDivisor Actual Rate Error(
Applicable BRGDivisor Actual Rate Error(
Rate (kHz)
1250.0
625.0
250.0
115.2
57.6
(Decimal)
(kHz)
1250.0
625.0
250.0
113.64
56.82
37.88
19.23
%)
Rate (kHz)
(Decimal)
(kHz)
%)
1
2
0.00
9.60
130
9.62
0.16
0.00
4.80
260
4.81
0.16
5
0.00
2.40
521
2.399
1.199
0.60
–0.03
–0.03
0.02
11
22
33
65
–1.19
–1.36
–1.36
0.16
1.20
1042
2083
4167
0.60
38.4
0.30
0.299
–0.01
19.2
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Table 96. LIN-UART Baud Rates, 10.0MHz System Clock
Applicable BRGDivisor Actual Rate Error( Applicable BRGDivisor Actual Rate Error(
Rate (kHz)
1250.0
625.0
250.0
115.2
57.6
(Decimal)
(kHz)
%)
Rate (kHz)
(Decimal)
(kHz)
9.62
4.81
2.40
1.20
0.60
0.30
%)
0.16
0.16
–0.03
–0.03
–0.03
0.2
N/A
1
N/A
N/A
9.60
65
625.0
208.33
125.0
56.8
0.00
4.80
130
3
–16.67
8.51
2.40
260
5
1.20
521
11
16
33
–1.36
1.73
0.60
1042
2083
38.4
39.1
0.30
19.2
18.9
0.16
Table 97. LIN-UART Baud Rates, 5.5296 MHz System Clock
Applicable BRGDivisor Actual Rate Error( Applicable BRGDivisor Actual Rate Error(
Rate (kHz)
1250.0
625.0
250.0
115.2
57.6
(Decimal)
(kHz)
%)
Rate (kHz)
(Decimal)
(kHz)
9.60
4.80
2.40
1.20
0.60
0.30
%)
N/A
N/A
1
N/A
N/A
9.60
36
0.00
0.00
0.00
0.00
0.00
0.00
N/A
N/A
4.80
72
345.6
115.2
57.6
38.4
19.2
38.24
0.00
0.00
0.00
0.00
2.40
144
3
1.20
288
6
0.60
576
38.4
9
0.30
1152
19.2
18
Table 98. LIN-UART Baud Rates, 3.579545 MHz System Clock
Applicable BRGDivisor Actual Rate Error( Applicable BRGDivisor Actual Rate Error(
Rate (kHz)
1250.0
625.0
250.0
115.2
57.6
(Decimal)
(kHz)
%)
Rate (kHz)
(Decimal)
(kHz)
9.73
4.76
2.41
1.20
0.60
0.30
%)
N/A
N/A
1
N/A
N/A
9.60
23
1.32
N/A
N/A
4.80
47
–0.83
0.23
223.72
111.9
55.9
–10.51
–2.90
–2.90
–2.90
–2.90
2.40
93
2
1.20
186
373
746
0.23
4
0.60
–0.04
–0.04
38.4
6
37.3
0.30
19.2
12
18.6
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Table 99. LIN-UART Baud Rates, 1.8432 MHz System Clock
Applicable BRGDivisor Actual Rate Error( Applicable BRGDivisor Actual Rate Error(
Rate (kHz)
1250.0
625.0
250.0
115.2
57.6
(Decimal)
(kHz)
%)
N/A
N/A
N/A
0.00
0.00
0.00
0.00
Rate (kHz)
(Decimal)
(kHz)
9.60
4.80
2.40
1.20
0.60
0.30
%)
N/A
N/A
N/A
1
N/A
9.60
12
0.00
0.00
0.00
0.00
0.00
0.00
N/A
4.80
24
N/A
2.40
48
115.2
57.6
38.4
19.2
1.20
96
2
0.60
192
384
38.4
3
0.30
19.2
6
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Infrared Encoder/Decoder
Overview
The Z8 Encore! XP® F1680 Series products contain a fully-functional, high-performance
UART to Infrared Encoder/Decoder (Endec). The Infrared Endec is integrated with an on-
chip UART to allow easy communication between the Z8 Encore! and IrDA Physical
Layer Specification, Version 1.3-compliant infrared transceivers. Infrared communication
provides secure, reliable, low-cost, point-to-point communication between PCs, PDAs,
cell phones, printers and other infrared enabled devices.
Architecture
Figure 28 illustrates the architecture of the Infrared Endec.
System
Clock
Infrared
Transceiver
RxD
RXD
TXD
RXD
TXD
Infrared
TxD
Encoder/Decoder
(Endec)
UART
Baud Rate
Clock
Interrupt
I/O
Data
Signal Address
Figure 28.Infrared Data Communication System Block Diagram
Operation
When the Infrared Endec is enabled, the transmit data from the associated on-chip UART
is encoded as digital signals in accordance with the IrDA standard and output to the infra-
red transceiver through the TXD pin. Likewise, data received from the infrared transceiver
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is passed to the Infrared Endec through the RXD pin, decoded by the Infrared Endec, and
passed to the UART. Communication is half-duplex, which means simultaneous data
transmission and reception is not allowed.
The baud rate is set by the UART’s Baud Rate Generator and supports IrDA standard baud
rates from 9600 baud to 115.2 Kbaud. Higher baud rates are possible, but do not meet
IrDA specifications. The UART must be enabled to use the Infrared Endec. The Infrared
Endec data rate is calculated using the following equation:
:
System Clock Frequency (Hz)
Infrared Data Rate (bits/s) = ----------------------------------------------------------------------------------------------
16 × UART Baud Rate Divisor Value
Transmitting IrDA Data
The data to be transmitted using the infrared transceiver is first sent to the UART. The
UART’s transmit signal (TXD) and baud rate clock are used by the IrDA to generate the
modulation signal (IR_TXD) that drives the infrared transceiver. Each UART/Infrared
data bit is 16 clocks wide. If the data to be transmitted is 1, the IR_TXD signal remains low
for the full 16 clock period. If the data to be transmitted is 0, the transmitter first outputs a
7 clock low period, followed by a 3 clock high pulse. Finally, a 6 clock low pulse is output
to complete the full 16 clock data period. Figure 29 illustrates IrDA data transmission.
When the Infrared Endec is enabled, the UART’s TXD signal is internal to the Z8 Encore!
XP® F1680 Series products while the IR_TXD signal is output through the TXD pin.
16 clock
period
Baud Rate
Clock
UART’s
TXD
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
3 clock
pulse
IR_TXD
7-clock
delay
Figure 29.Infrared Data Transmission
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Receiving IrDA Data
Data received from the infrared transceiver using the IR_RXD signal through the RXD pin
is decoded by the Infrared Endec and passed to the UART. The UART’s baud rate clock is
used by the Infrared Endec to generate the demodulated signal (RXD) that drives the
UART. Each UART/Infrared data bit is 16-clocks wide. Figure 30 illustrates data recep-
tion. When the Infrared Endec is enabled, the UART’s RXD signal is internal to the Z8
Encore! XP® F1680 Series products while the IR_RXD signal is received through the
RXD pin.
16 clock
period
Baud Rate
Clock
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
IR_RXD
min. 1.4μs
pulse
UART’s
RXD
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
8 clock
delay
16 clock
period
16 clock
period
16 clock
period
16 clock
period
Figure 30.IrDA Data Reception
Infrared Data Reception
The system clock frequency must be at least 1.0MHz to ensure proper reception of the
Caution:
1.4μs minimum width pulses allowed by the IrDA standard.
Endec Receiver Synchronization
The IrDA receiver uses a local baud rate clock counter (0 to 15 clock periods) to generate
an input stream for the UART and to create a sampling window for detection of incoming
pulses. The generated UART input (UART RXD) is delayed by 8 baud rate clock periods
with respect to the incoming IrDA data stream. When a falling edge in the input data
stream is detected, the Endec counter is reset. When the count reaches a value of 8, the
UART RXD value is updated to reflect the value of the decoded data. When the count
reaches 12 baud clock periods, the sampling window for the next incoming pulse opens.
The window remains open until the count again reaches 8 (in other words, 24 baud clock
periods since the previous pulse was detected), giving the Endec a sampling window of
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minus 4 baud rate clocks to plus eight baud rate clocks around the expected time of an
incoming pulse. If an incoming pulse is detected inside this window this process is
repeated. If the incoming data is a logical 1 (no pulse), the Endec returns to the initial state
and waits for the next falling edge. As each falling edge is detected, the Endec clock
counter is reset, resynchronizing the Endec to the incoming signal, allowing the Endec to
tolerate jitter and baud rate errors in the incoming datastream. Resynchronizing the Endec
does not alter the operation of the UART, which ultimately receives the data. The UART
is only synchronized to the incoming data stream when a Start bit is received.
Infrared Encoder/Decoder Control Register Definitions
All Infrared Endec configuration and status information is set by the UART control regis-
ters as defined beginning on page 156.
To prevent spurious signals during IrDA data transmission, set the IREN bit in the
UART Control 1 register to 1 to enable the Infrared Encoder/Decoder before enabling
the GPIO Port alternate function for the corresponding pin.
Caution:
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Analog-to-Digital Converter
The Z8 Encore! includes an eight-channel analog-to-digital converter (ADC). The ADC
converts an analog input signal to a 10-bit binary number. The features of the successive-
approximation ADC include:
•
•
•
•
•
•
•
Eight analog input sources multiplexed with general-purpose I/O ports
Fast conversion time, less than 5µs
Programmable timing controls
Interrupt upon conversion complete
Internal voltage reference generator
Internal reference voltage available externally
Ability to supply external reference voltage
Architecture
The ADC architecture, as shown in Figure 31, consists of an 8-input multiplexer, sample-
and-hold amplifier, and 10-bit successive-approximation analog-to-digital converter. The
ADC digitizes the signal on a selected channel and stores the digitized data in the ADC
data registers. In environments with high electrical noise, an external RC filter must be
added at the input pins to reduce high-frequency noise.
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REFEN
VREF
VR2
Internal Voltage
Reference Generator
RBUF
Analog Input
Multiplexer
Analog-to-Digital
Converter
ANA0
ANA1
ANA2
ANA3
ANA4
ANA5
ANA6
ANA7
Reference Input
10
Data
S&H
Amp
Output
Sample-and-Hold
Amplifier
Analog Input
BUSY
ANA3SH
ADCLK
ANAIN[2:0]
ADCEN
START
SAMPLE/HOLD
Figure 31.Analog-to-Digital Converter Block Diagram
Operation
The ADC converts the analog input, ANAX, to a 10-bit digital representation. The equa-
tion for calculating the digital value is represented by:
ADC Output = 1024 x (ANAx ÷ VREF
)
Assuming zero gain and offset errors, any voltage outside the ADC input limits of AVSS
and VREF returns all 0s or 1s, respectively.
A new conversion can be initiated by either software write to the ADC Control Register’s
STARTbit.
Initiating a new conversion stops any conversion currently in progress and begins a new
conversion. To avoid disrupting a conversion already in progress, the STARTbit can be
read to indicate ADC operation status (busy or available).
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ADC Timing
Each ADC measurement consists of 3 phases:
1. Input sampling (programmable, minimum of 1.0µs)
2. Sample-and-hold amplifier settling (programmable, minimum of 0.5µs)
3. Conversion is 13 ADCLK cycles.
Figure 32 illustrates the timing of an ADC conversion.
conversion period
START
1.0µs min
sample period
Programable
settling period
SAMPLE/HOLD
BUSY
13 clock
convert period
Figure 32.ADC Timing Diagram
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
ADC Clock
BUSY
13 clocks
convert period
Figure 33.ADC Convert Timing
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ADC Interrupt
The ADC can generate an interrupt request when a conversion has been completed. An
interrupt request that is pending when the ADC is disabled is not automatically cleared.
Reference Buffer
The reference buffer, RBUF, supplies the reference voltage for the ADC. When enabled,
the internal voltage reference generator supplies the ADC and the voltage is available on
the VREF pin. When RBUF is disabled, the ADC must have the reference voltage supplied
externally through the VREF pin. RBUF is controlled by the REFENbit in the ADC Control
Register.
Internal Voltage Reference Generator
The Internal Voltage Reference Generator provides the voltage, VR2, for the RBUF. VR2
is 2 volts.
Calibration and Compensation
A user can perform calibration and store the values into Flash, or the user code can per-
form a manual offset calibration. There is no provision for manual gain calibration.
ADC Control Register Definitions
The ADC Control Register are described in the following paragraphs.
ADC Control Register 0
The ADC Control Register 0 initiates the A/D conversion and provides ADC status infor-
mation. See Table 100.
Table 100. ADC Control Register 0 (ADCCT0)
BITS
7
6
5
4
3
2
1
0
START
Reserved REFEN
ADCEN
ANAIN[3:0]
FIELD
0
0
0
0
0
0
0
0
RESET
R/W
R/W1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F70h
ADDR
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Bit
Position
Value
(H)
Description
[7]
ADC Start/Busy
START
0
1
Writing to 0 has no effect.
Reading a 0 indicates the ADC is available to begin a conversion.
Writing to 1 starts a conversion.
Reading a 1 indicates a conversion is currently in progress.
[6:5]
Reference Enable
REFEN
00
10
10
Internal reference voltage is disabled allowing an external reference voltage to be
used by the ADC.
Internal Reference Voltage for the ADC is disabled. AVDD is used as the
Reference Voltage
Internal Reference Voltage for the ADC is disabled. AVDD is used as the
Reference Voltage
11
11
01
Reserved
[4]
ADCEN
Reserved
ADC is enabled for normal use.
[3:0]
Analog Input Select
ANAIN
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1100
1101
Others
ANA0 input is selected for analog to digital conversion.
ANA1 input is selected for analog to digital conversion.
ANA2 input is selected for analog to digital conversion.
ANA3 input is selected for analog to digital conversion.
ANA4 input is selected for analog to digital conversion.
ANA5 input is selected for analog to digital conversion.
ANA6 input is selected for analog to digital conversion.
ANA7 input is selected for analog to digital conversion.
Hold transimpedance input nodes (ANA1 and ANA2) to ground
Temperature Sensor
Temperature Sensor output to ANA3 PAD
vbg_chop signal output to ANA3 PAD
Reserved
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ADC Raw Data High Byte Register
The ADC Raw Data High Byte Register, shown in Table 101, contains the upper 8 bits of
raw data from the ADC output. Access to the ADC Raw Data High Byte register is Read-
Only. This register is used for test only.
Table 101. ADC Raw Data High Byte Register (ADCRD_H)
BITS
7
6
5
4
3
2
1
0
ADCRDH
FIELD
RESET
R/W
X
R
F71H
ADDR
Bit
Position
Value
(H)
Description
[7:0]
00h–FFh ADC Raw Data High Byte
The data in this register is the raw data coming from the SAR Block. It will change
as the conversion is in progress. This register is used for testing only.
ADC Data High Byte Register
The ADC Data High Byte Register, shown in Table 102, contains the upper eight bits of
the ADC output. Access to the ADC Data High Byte Register is Read-Only. Reading the
ADC Data High Byte Register latches data in the ADC Low Bits Register.
Table 102. ADC Data High Byte Register (ADCD_H)
BITS
7
6
5
4
3
2
1
0
ADCDH
FIELD
RESET
R/W
X
R
F72H
ADDR
Bit
Position
Value
(H)
Description
[7:0]
00h–FFh ADC High Byte
The last conversion output is held in the data registers until the next ADC
conversion has completed.
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ADC Data Low Bits Register
The ADC Data Low Bits Register, shown in Table 103, contain the lower bits of the ADC
output as well as an overflow status bit. Access to the ADC Data Low Bits Register is
Read-Only. Reading the ADC Data High Byte Register latches data in the ADC Low Bits
Register.
Table 103. ADC Data Low Bits Register (ADCD_L)
BITS
7
6
5
4
3
2
1
0
ADCDL
Reserved
FIELD
RESET
R/W
X
R
X
R
F73H
ADDR
Bit
Position
Value
(H)
Description
[7:6]
ADC Low Bits
00–11b These bits are the 2 least significant bits of the 10-bit ADC output. These bits are
undefined after a Reset. The low bits are latched into this register whenever the
ADC Data High Byte register is read.
[5:0]
Reserved
Reserved—Must Be 0.
0
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Sample Settling Time Register
The Sample Settling Time Register, shown in Table 104, is used to program the length of
time from the SAMPLE/HOLD signal to the START signal, when the conversion can
begin. The number of clock cycles required for settling will vary from system to system
depending on the system clock period used. The system designer should program this reg-
ister to contain the number of clocks required to meet a 0.5µs minimum settling time.
Table 104. Sample and Settling Time (ADCSST)
BITS
7
6
5
4
3
2
1
0
Resevered
SST
R/W
FIELD
RESET
R/W
0
1
1
1
1
R
F74H
ADDR
Bit
Position
Value
(H)
Description
[7:4]
0h
Reserved - Must be 0.
[3:0]
SST
0h - Fh
Sample settling time in number of system clock periods to meet 0.5µs minimum.
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Sample Time Register
The Sample Time Register, shown in Table 105, is used to program the length of active
time for the sample after a conversion has begun by setting the STARTbit in the ADC
Control Register or initiated by the PWM. The number of system clock cycles required for
sample time varies from system to system, depending on the clock period used. The sys-
tem designer should program this register to contain the number of system clocks required
to meet a 1µs minimum sample time.
Table 105. Sample Hold Time (ADCST)
BITS
7
6
5
4
3
2
1
0
Reserved
ST
FIELD
RESET
R/W
0
1
1
1
1
1
1
R/W
R/W
F75H
ADDR
Bit
Position
Value
(H)
Description
[7:5]
0h
Reserved - Must be 0.
Sample Hold time in number of system clock periods to meet 1µs minimum.
[4:0]
SHT
0h - Fh
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ADC Clock Prescale Register
The ADC Clock Prescale Register, shown in Table 106, is used to provide a divided sys-
tem clock to the ADC. When this register is programmed with 0h, the System Clock is
used for the ADC Clock.
Table 106. ADC Clock Prescale Register (ADCCP)
BITS
7
6
5
4
3
DIV16
0
2
DIV8
0
1
DIV4
0
0
Reserved
0
DIV2
FIELD
RESET
R/W
0
R/W
F76H
ADDR
Bit
Position
Value
(H)
Description
[0]
DIV2
DIV2
0
1
Clock is not divided
System Clock is divided by 2 for ADC Clock
[1]
DIV4
DIV4
0
1
Clock is not divided
System Clock is divided by 4 for ADC Clock
[2]
DIV8
DIV8
0
1
Clock is not divided
System Clock is divided by 8 for ADC Clock
[3]
DIV16
DIV16
0
Clock is not divided
1
System Clock is divided by 16 for ADC Clock
Reserved - must be 0.
[7:4]
0h
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Transimpedance Amplifier
The transimpedance amplifier is a standard operational amplifier designed for current
measurements. Each of the three ports of the amplifier is accessible from the package pins.
The inverting input is commonly used to connect to the current source. The output node
connects an external feedback network to the inverting input. The non-inverting output is
required to apply a non-zero bias point. In a standard, single-supply system, this bias point
must be substantially above ground to measure positive input currents. The non-inverting
input may also be used for offset correction.
Note that this is a voltage gain operational amplifier. Its transimpedance nature is deter-
mined by the feedback network.
Note:
The trans impedance amplifier contains only one pin configuration: ANA0 is the output/
feedback node, ANA1 is the inverting input and ANA2 is the non-inverting input.
To use the transimpedance amplifier, it must be enabled in the Power Control Register Def-
initions. The default state of the transimpedance amplifier is OFF. To use the transimped-
ance amplifier, the TRAM bit must be cleared, turning it ON (“Power Control Register 0”
on page 43). When making normal ADC measurements on ANA0 (not transimpedance
measurements), the TRAM bit must be OFF. Turning the TRAM bit ON interferes with
normal ADC measurements. Finally, this bit enables the amplifier even in STOP mode. If
the amplifier is not required in STOP mode, disable it. Failing to perform this results in
STOP mode currents greater than specified.
As with other ADC measurements, any pins used for analog purposes must be configured
as such in the GPIO registers (see “Port A-E Alternate Function Sub-Registers” on page 61).
Standard transimpedance measurements are made on ANA0, as selected by the
ANAIN[3:0] bits of ADC Control Register 0. It is also possible to make single-ended mea-
surements on ANA1 and ANA2 while the amplifier is enabled, which is often useful for
determining offset conditions.
The BUFFMODE[2:0] bits of ADC Control/Status Register 1 must also be configured for sin-
gle-ended, unity-gain buffered operation. Using the transimpedance amplifier in an unbuf-
fered or differential mode is not recommended.
When either input is overdriven, the amplifier output saturates at the positive or negative
supply voltage. No instability results.
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Enhanced Serial Peripheral Interface
Overview
TM
The Enhanced Serial Peripheral Interface supports SPI (Serial Peripheral Interface ) and
other synchronous serial interface modes such as I2S (Inter IC Sound) and TDM (Time
Division Multiplexing). Features of the ESPI include:
•
•
•
•
•
•
•
•
Full-duplex, synchronous, character-oriented communication
Four-wire interface (SS, SCK, MOSI, MISO)
Data shift register is buffered to enable high throughput
Master transfer rates up to a maximum of one-half the system clock frequency
Slave transfer rates up to a maximum of one-fourth the system clock frequency
Error detection
Dedicated Programmable Baud Rate Generator
Data transfer control via polling, interrupt.
Architecture
The ESPI is a full-duplex, synchronous, character-oriented channel that supports a four-
wire interface (serial clock, transmit data, receive data and slave select). The ESPI block
consists of a shift register, data buffer register, a Baud Rate (clock) Generator, control/sta-
tus registers and a control state machine. Transmit and receive transfers are in synch since
there is a single shift register for both transmit and receive data. Figure 34 provides a
block diagram of the ESPI.
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Peripheral Bus
Interrupt
ESPI BRH
Register
ESPI Control
Register
ESPI Status
Register
ESPI State
Register
ESPI BRL
Register
ESPI Mode
Register
ESPI State
Machine
Baud
Rate
Generator
Interrupt/
count = 1
Data Register
SCK
Logic
Shift Register
0
1
2
3
4
5
6
7
data_out
SCK
in
SCK
out
SS out SS in
MISO
out
MOSI
out
Pin Direction
Control
MISO MOSI
in in
GPIO Logic and Port Pins
SS
MISO
MOSI
SCK
Figure 34.ESPI Block Diagram
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ESPI Signals
The four ESPI signals are:
•
•
•
•
MISO (Master-In, Slave-Out)
MOSI (Master-Out, Slave-In)
SCK (Serial Clock)
SS (Slave Select)
The following paragraphs discuss these signals in both Master and Slave modes.
Master-In, Slave-Out
The Master-In, Slave-Out (MISO) pin is configured as an input in a Master device and as
an output in a slave device. Data is transferred either most significant bit first or least sig-
nificant bit first as determined by the LSBF bit of the ESPI Mode register. The MISO pin
of a Slave device is placed in a high-impedance state if the slave is not selected. When the
ESPI is not enabled, this signal is in a high-impedance state. The direction of this pin is
controlled by the MMEN bit of the ESPI Control Register.
Master-Out, Slave-In
The Master-Out, Slave-In (MOSI) pin is configured as an output in a Master device and as
an input in a slave device. Data is transferred either most significant bit first or least signif-
icant bit first as determined by the LSBF bit of the ESPI Mode register. When the ESPI is
not enabled, this signal is in a high-impedance state. The direction of this pin is controlled
by the MMEN bit of the ESPI Control Register.
Serial Clock
The Serial Clock (SCK) synchronizes data movement both in and out of the shift register
via the MOSI and MISO pins. In Master mode (MMEN = 1), the ESPI’s Baud Rate Gen-
erator creates the serial clock and drives it out on its SCK pin to the slave devices. In slave
mode, the SCK pin is an input. Slave devices ignore the SCK signal, unless their SS pin is
asserted.
The Master and Slave are each capable of exchanging a character of data during a
sequence of NUMBITS clock cycles (refer to NUMBITS field in the ESPIMODE regis-
ter). In both Master and Slave ESPI devices, data is shifted on one edge of the SCK and is
sampled on the opposite edge where data is stable. SCK phase and polarity is determined
by the PHASE and CLKPOL bits in the ESPI Control register.
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Slave Select
The Slave Select signal is a bidirectional framing signal with several modes of operation
to support SPI and other synchronous serial interface protocols. The Slave Select mode is
selected by the SSMD field of the ESPI Mode register. The direction of the SS signal is
controlled by the SSIO bit of the ESPI Mode register. The SS signal is an input on slave
devices and is an output on the active Master device. Slave devices ignore transactions on
the bus unless their Slave Select input is asserted. In SPI Master mode additional GPIO
pins are required to provide Slave Selects if there is more than one slave device.
ESPI Register Overview
The ESPI Control/Status Registers are summarized in table below.
Table 107. ESPI Registers
Address
XX0
Even Address
Data
Odd Address
Transmit Data Command
Mode
XX2
Control
XX4
Status
State
XX6
Baud Rate High
Baud Rate Low
Comparison with Basic SPI Block
The ESPI module has a number of enhancements compared to the simpler SPI module
found on other Z8 Encore! parts. This section will highlight the differences.
•
•
•
•
Data-buffer register added to support higher performance
Separate transmit and receive interrupts
Error interrupts
Transmit Data Command Register - new register to improve performance. SSV and
TEOF can be set on same cycle that the Data register is written.
•
Control Register
–
–
IRQE changed to DIRQE. Errors did not generate interrupts on the SPI module.
STR bit on the SPI module replaced with ESPIEN1. SPIEN replaced with
ESPIEN0. This enhancement allows uni-directional transfers which minimizes
software overhead.
–
BIRQ replaced with BRGCTL. Added support for Slave mode SCK watch-dog
timer function.
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•
Mode Register
–
Added SSMD field which adds support for loopback mode and new synchronous
Slave Select modes.
–
–
Removed DIAG bit.
Moved SSV bit to the Transmit Data Command register as described above.
Replaced with SSPO (Slave Select Polarity) to support active high and low Slave
Select on SS pin.
•
•
Status Register
–
–
IRQ split into TDRE and RDRF (separate transmit and receive interrupts).
Replace Overrun error with separate Transmit Underrun and Receive Overrun.
State Register.
–
–
Replaced SCKEN bit with SCKI
Replaced TCKEN with SDI
Operation
During a transfer, data is sent and received simultaneously by both the Master and the
Slave devices. Separate signals are required for transmit data, receive data and the serial
clock. When a transfer occurs, a multi-bit (typically 8-bit) character is shifted out one data
pin and an multi-bit character is simultaneously shifted in on a second data pin. An 8-bit
shift register in the Master and an 8-bit shift register in the Slave are connected as a circu-
lar buffer. The ESPI shift register is buffered to support back to back character transfers in
high performance applications. A transaction is initiated when the Data register is written
in the Master device. The value from the Data register is transferred into the shift register
and the I2C transaction begins. At the end of each character transfer, if the next transmit
value has been written to the data register, the data and shift register values are swapped,
which places the new transmit data into the shift register and the shift register contents
(receive data) into the data register. At that point the Receive Data Register Full signal is
asserted (RDRF bit set in the Status Register). Once software reads the receive data from
the Data register, the Transmit Data Register Empty signal is asserted (TDRE bit set in the
Status Register) to request the next transmit byte. To support back to back transfers with-
out an intervening pause the receive and transmit interrupts must both be serviced while
the current character is being transferred.
The Master sources the Serial Clock (SCK) and Slave Select signal (SS) during the trans-
fer.
Internal data movement (by software) to/from the ESPI block is controlled by the Trans-
mit Data Register Empty (TDRE) and Receive Data Register Full (RDRF) signals. These
signals are read only bits in the ESPI Status register. When either the TDRE or RDRF bits
assert, an interrupt is sent to the interrupt controller. In many cases the software applica-
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tion is only moving information in one direction. In this case either the TDRE or RDRF
interrupts may be disabled to minimize software overhead. Unidirectional data transfer is
supported by setting the ESPIEN1,0 bits in the Control Register to 10 or 01.
Throughput
In Master mode the maximum SCK rate supported is one-half the system clock frequency.
This is achieved by programming the value 0001H into the Baud Rate High/Low register
pair. Though each character will be transferred at this rate it is unlikely that software inter-
rupt routines could keep up with this rate. In SPI mode the transfer will automatically
pause between characters until the current receive character is read and the next transmit
data value is written.
In Slave mode, the transfer rate is controlled by the Master. As long as the TDRE and
RDRF interrupt are serviced before the next character transfer completes the Slave will
keep up with the Master. In Slave mode the baud rate must be restricted to a maximum of
one-fourth of the system clock frequency to allow for synchronization of the SCK input to
the internal system clock.
ESPI Clock Phase and Polarity Control
The ESPI supports four combinations of serial clock phase and polarity using two bits in
the ESPI Control register. The clock polarity bit, CLKPOL, selects an active high or active
low clock and has no effect on the transfer format. Table 108 lists the ESPI Clock Phase
and Polarity Operation parameters. The clock phase bit, PHASE, selects one of two funda-
mentally different transfer formats. The data is output a half-cycle before the receive clock
edge which provides a half cycle of setup and hold time.
Table 108. ESPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation
SCK Transmit
Edge
SCK Receive
Edge
SCK Idle
State
PHASE
CLKPOL
0
0
1
1
0
1
0
1
Falling
Rising
Rising
Falling
Rising
Falling
Falling
Rising
Low
High
Low
High
Transfer Format with Phase Equals Zero
Figure 35 illustrates the timing diagram for an SPI type transfer in which PHASE= 0. For
SPI transfers the clock only toggles during the character transfer. The two SCK wave-
forms show polarity with CLKPOL= 0 and with CLKPOL= 1. The diagram may be inter-
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preted as either a Master or Slave timing diagram because the SCK Master-In/Slave-Out
(MISO) and Master-Out/Slave-In (MOSI) pins are directly connected between the Master
and the Slave.
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit7
Bit7
Bit6
Bit6
Bit5
Bit5
Bit4
Bit4
Bit3
Bit3
Bit2
Bit2
Bit1
Bit1
Bit0
Bit0
MISO
Input Sample Time
SS
Figure 35.ESPI Timing When PHASE is 0
Transfer Format with Phase Equals One
Figure 36 illustrates the timing diagram for an SPI type transfer in which PHASEis one.
For SPI transfers the clock only toggles during the character transfer. Two waveforms are
depicted for SCK, one for CLKPOL= 0 and another for CLKPOL= 1.
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SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit7
Bit7
Bit6
Bit6
Bit5
Bit5
Bit4
Bit4
Bit3
Bit3
Bit2
Bit2
Bit1
Bit1
Bit0
Bit0
MISO
Input Sample Time
SS
Figure 36.ESPI Timing When PHASE is 1
Slave Select Modes of Operation
This section describes the different modes of data transfer supported by the ESPI block.
The mode is selected by the Slave Select Mode (SSMD) field of the Mode Register.
SPI Mode
This mode is selected by setting the SSMD field of the Mode Register to 00. In this mode
software controls the assertion of the SS signal directly via the SSV bit of the SPI Trans-
mit Data Command register. Software can be used to control an SPI mode transaction.
Prior to or simultaneously with writing the first transmit data byte, software sets the SSV
bit. Software can set the SSV bit either by performing a byte write to the Transmit Data
Command register prior to writing the first transmit character to the Data register or by
performing a word write to the Data register address which loads the first transmit charac-
ter and simultaneously sets the SSV bit. SS will remain asserted while one or more charac-
ters are transferred. There are two mechanisms for deasserting SS at the end of the
transaction. One method which is used by software, is to set the TEOF bit of the Transmit
Data Command register when the last TDRE interrupt is being serviced (set TEOF before
or simultaneously with writing the last data byte). Once the last bit of the last character is
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transmitted, the hardware will automatically deassert the SSV and TEOF bits. The second
method is for software to directly clear the SSV bit after the transaction completes. If soft-
ware clears the SSV bit directly it is not necessary for software to also set the TEOF bit on
the last transmit byte. After writing the last transmit byte, the end of the transaction can be
detected by waiting for the last RDRF interrupt or monitoring the TFST bit in the ESPI
Status register.
The transmit underrun and receive overrun errors will not occur in an SPI mode Master. If
the RDRF and TDRE requests have not been serviced before the current byte transfer
completes, SCLK will be paused until the data register is read and written. The transmit
underrun and receive overrun errors will occur in a Slave if the Slave’s software does not
keep up with the Master data rate. In this case the shift register in the Slave will be loaded
with all 1’s.
In the SPI mode, the SCK will be active only for the data transfer with one SCK period per
bit transferred. If the SPI bus has multiple Slaves, the Slave Select lines to all or all but
one of the Slaves must be controlled independently by software using GPIO pins.
Figure 38 illustrates multiple character transfer in SPI mode. Note that while character n is
being transferred via the shift register, software responds to the receive request for charac-
ter n-1 and the transmit request for character n+1.
SCK (SSMD = 00,
PHASE = 0,
CLKPOL = 0,
SSPO = 0)
Bit0
Bit7
Bit6
Bit1
Bit0
Bit7
Bit 6
MOSI, MISO
Data Register
empty
Rx n
Tx n
Rx n-1
empty
Tx n+1
Tx/Rx n
Tx/Rx n-1
Tx/Rx n+1
Shift Register
TDRE
RDRF
ESPI Interrupt
Figure 37.SPI mode (SSMD = 00)
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Synchronous Frame Sync Pulse Mode
This mode is selected by setting the SSMD field of the Mode Register to 10. This mode is
typically used for continuous transfer of fixed length frames where the frames are delin-
eated by a pulse of duration one SCK period. The SSV bit in the ESPI Transmit Data
Command register does not control the SS pin directly in this mode. SSV should be set
before or in sync with the first transmit data byte being written. The SS signal will assert 1
SCK cycle before the first data bit and will stop after 1 SCK period. SCK is active from
the initial assertion of SS until the transaction is ended by lack of transmit data.
The transaction is terminated by the Master when it no longer has data to send. If TDRE =
1 at the end of a character, the SS output will remain detached and SCK will stop after the
last bit is transferred. The TUND bit (transmit underrun) will assert in this case. Once the
transaction has completed, hardware will clear the SSV bit.
Figure 38 illustrates a frame with synchronous frame sync pulse mode.
SCK (SSMD = 10,
PHASE = 0,
CLKPOL = 0,
SSPO = 1)
Bit7
Bit6
Bit1
Bit0
Bit7
Bit 6
MOSI, MISO
SS
SSV
Figure 38.Synchronous Frame Sync Pulse mode (SSMD = 10)
Synchronous Framing with SS Mode
This mode is selected by setting the SSMD field of the Mode Register to 11. Figure 39
illustrates synchronous message framing mode with SS alternating between consecutive
frames. A frame consists of a fixed number of data bytes as defined by software. An exam-
ple of this mode is the I2S (Inter-IC Sound) protocol which is used to transfer left/right
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channel audio data. The SSV indicates whether the corresponding bytes are left or right
channel data. The SSV value must be updated when servicing the TDRE interrupt/request
for the first byte in a left or write channel frame. This can be accomplished by performing
a word write when writing the first byte of the audio word, which will update both the
ESPI Data and Transmit Data Command words or by doing a byte write to update SSV
followed by a byte write to the data register. The SS signal will lead the data by one SCK
period.
The transaction is terminated when the Master has no more data to transmit. After the last
bit is transferred, SCLK will stop and SS and SSV will return to their default states. A
transmit underrun error will occur at this point.
SCK (SSMD = 11,
PHASE = 0,
CLKPOL = 0)
SS
Bit0
Bit 7
MOSI, MISO
Bit7
Bit7
Bit0
frame n
frame n + 1
Figure 39.Synchronous Message Framing mode (SSMD = 11), Multiple Frames
SPI Protocol Configuration
This section describes in more detail how to configure the ESPI block for the SPI protocol.
In the SPI protocol the Master sources the SCK and asserts Slave Select signals to one or
more Slaves. The Slave Select signals are typically active low.
SPI Master Operation
The ESPI block is configured for Master mode operation by setting the MMEN bit = 1 in
the ESPICTL register. The SSMD field of the ESPI Mode register is set to 00 for SPI pro-
tocol mode. The PHASE, CLKPOL and WOR bits in the ESPICTL register and the NUM-
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BITS field in the ESPI Mode register must be set to be consistent with the Slave SPI
devices. Typically for an SPI Master, LSBF = 0, SSIO = 1 and SSPO = 0.
The appropriate GPIO pins are configured for the ESPI alternate function on the MOSI,
MISO and SCK pins. Typically the GPIO for the ESPI SS pin is configured in alternate
function mode as well though software can use any GPIO pin(s) to drive one or more
Slave select lines. If the ESPI SS signal is not used to drive a Slave select the SSIO bit
should still be set = 1 in a single Master system. Figure 40 and Figure 41 show the ESPI
block configured as an SPI Master.
ESPI Master
To Slave’s SS Pin
From Slave
SS
8-bit Shift Register
Bit 0 Bit 7
MISO
MOSI
SCK
To Slave
To Slave
Baud Rate
Generator
Figure 40.ESPI Configured as an SPI Master in a Single Master, Single Slave System
ESPI Master
To Slave #2’s SS Pin
To Slave #1’s SS Pin
GPIO
GPIO
8-bit Shift Register
Bit 0 Bit 7
From Slaves
To Slaves
MISO
MOSI
SCK
Baud Rate
Generator
To Slaves
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Figure 41.ESPI Configured as an SPI Master in a Single Master, Multiple Slave System
Multi-Master SPI Operation
In a multi-Master SPI system, all SCK pins are tied together, all MOSI pins are tied
together and all MISO pins are tied together. All SPI pins must be configured in open-
drain mode to prevent bus contention. At any one time, only one SPI device is configured
as the Master and all other devices on the bus are configured as slaves. The Master asserts
the SS pin on the selected slave. Then, the active Master drives the clock and transmit data
on the SCK and MOSI pins to the SCK and MOSI pins on the Slave (including those
Slaves which are not enabled). The enabled slave drives data out its MISO pin to the
MISO Master pin.
When the ESPI is configured as a Master in a multi-Master SPI system, the SS pin must be
configured as an input. The SS input signal on a device configured as a Master should
remain High. If the SS signal on the active Master goes Low (indicating another Master is
accessing this device as a Slave), a Collision error flag is set in the ESPI Status register.
The Slave select outputs on a Master in a multi-Master system must come from GPIO
pins.
SPI Slave Operation
The ESPI block is configured for Slave mode operation by setting the MMEN bit = 0 in
the ESPICTL register and setting the SSIO bit = 0 in the ESPIMODE register. The SSMD
field of the ESPI Mode register is set to 00 for SPI protocol mode. The PHASE, CLKPOL
and WOR bits in the ESPICTL register and the NUMBITS field in the ESPIMODE regis-
ter must be set to be consistent with the other SPI devices. Typically for an SPI Slave,
SSPO = 0.
If the Slave has data to send to the Master, the data must be written to the Data register
before the transaction starts (first edge of SCK when SS is asserted). If the Data register is
not written prior to the Slave transaction, the MISO pin outputs all 1’s.
Due to the delay resulting from synchronization of the SS and SCK input signals to the
internal system clock, the maximum SCK baud rate that can be supported in Slave mode is
the system clock frequency divided by 4. This rate is controlled by the SPI Master.
Figure 42 shows the ESPI configuration in SPI Slave mode.
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SPI Slave
From Master
SS
8-bit Shift Register
MISO
MOSI
To Master
Bit 7
Bit 0
From Master
SCK
From Master
Figure 42.ESPI Configured as an SPI Slave
Error Detection
Error events detected by the ESPI block are described in this section. Error events gener-
ate an ESPI interrupt and set a bit in the ESPI Status register. The error bits of the ESPI
Status register are read/write 1 to clear.
Transmit Underrun
A transmit underrun error occurs for a Master with SSMD = 10 or 11 when a character
transfer completes and TDRE = 1. In these modes when a transmit underrun occurs the
transfer will be aborted (SCK will halt and SSV will be deassertd). For a Master in SPI
mode (SSMD = 00) a transmit underrun is not signaled since SCK will pause and wait for
the data register to be written.
In Slave mode, a transmit underrun error occurs if TDRE = 1 at the start of a transfer.
When a transmit underrun occurs in Slave mode, ESPI will transmit a character of all 1’s.
A transmit underrun sets the TUNDbit in the ESPI Status register to 1. Writing a 1 to
TUNDclears this error flag.
Mode Fault (Multi-Master Collision)
A mode fault indicates when more than one Master is trying to communicate at the same
time (a multi-Master collision) in SPI mode. The mode fault is detected when the enabled
Master’s SS input pin is asserted. For this to happen the Control and Mode registers must
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be configured with MMEN = 1, SSIO = 0 (SS is an input) and SS input = 0. A mode fault
sets the COLbit in the ESPI Status register to 1. Writing a 1 to COLclears this error flag.
Receive Overrun
A receive overrun error occurs when a transfer completes and the RDRF bit is still set
from the previous transfer. A receive overrun sets the ROVRbit in the ESPI Status register
to 1. Writing a 1 to ROVRclears this error flag. The receive data register is not overwritten
and will contain the data from the transfer which initially set the RDRF bit. Subsequent
received data is lost until the RDRF bit is cleared.
In SPI Master mode, a receive overrun will not occur. Instead the SCK will be paused until
software responds to the previous RDRF/TDRE requests.
Slave Mode Abort
In Slave mode of operation if the SS pin deasserts before all bits in a character have been
transferred, the transaction is aborted. When this condition occurs the ABT bit is set in the
ESPI Status register. A Slave abort error resets the Slave control logic to the idle state.
A Slave abort error is also asserted in Slave mode if BRGCTL = 1 and a baud rate genera-
tor time-out occurs. When BRGCTL = 1 in Slave mode, the baud rate generator functions
as a watch dog timer monitoring the SCK signal. The BRG counter is reloaded every time
a transition on SCK occurs while SS is asserted. The Baud Rate Reload registers should be
programmed with a value longer than the expected time between SS assertion and the first
SCK edge, between SCK transitions while SS is asserted and between the last SCK edge
and SS deassertion. A time-out indicates the Master is stalled or disabled.
Writing a 1 to ABT clears this error flag.
ESPI Interrupts
ESPI has a single interrupt output which is asserted when any of the TDRE, TUND, COL,
ABT, ROVR or RDRF bits are set in the ESPI Status register. The interrupt is a pulse
which is generated when any one of the source bits initially sets. The TDRE and RDRF
interrupts may be enabled/disabled via the Data Interrupt Request Enable (DIRQE) bit of
the ESPI Control register.
A transmit interrupt is asserted by the TDRE status bit when the ESPI block is enabled and
the DIRQE bit is set. The TDRE bit in the Status register is cleared automatically when the
Data register is written or the ESPI block is disabled. Once the Data register is loaded into
the shift register to start a new transfer, the TDRE bit will be set again, causing a new
transmit interrupt. In Slave mode, if information is being received but not transmitted the
transmit interrupts may be eliminated by selecting Receive Only mode (ESPIEN1,0 = 01).
A Master cannot operate in Receive Only mode since a write to the ESPI (Transmit) Data
register is still required to initiate the transfer of a character even if information is being
received but not transmitted by the software application.
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A receive interrupt is generated by the RDRF status bit when the ESPI block is enabled,
the DIRQE bit is set and a character transfer completes. At the end of the character trans-
fer, the contents of the shift register are transferred into the data register, causing the
RDRF bit to assert. The RDRF bit is cleared when the Data register is read. If information
is being transmitted but not received by the software application, the receive interrupt can
be eliminated by selecting Transmit Only mode (ESPIEN1,0 = 10) in either Master or
Slave modes. When information is being sent and received under interrupt control, RDRF
and TDRE will both assert simultaneously at the end of a character transfer. Since the new
receive data is in the Data register, the receive interrupt must be serviced before the trans-
mit interrupt.
ESPI error interrupts occur if any of the TUND, COL, ABT and ROVR bits in the ESPI
Status register are set. These bits are cleared by writing a 1.
If the ESPI is disabled (ESPIEN1,0 = 00), an ESPI interrupt can be generated by a Baud
Rate Generator time-out. This timer function must be enabled by setting the BRGCTL bit
in the ESPICTL register. This timer interrupt does not set any of the bits of the ESPI Sta-
tus register.
ESPI Baud Rate Generator
In ESPI Master mode, the Baud Rate Generator creates a lower frequency serial clock
(SCK) for data transmission synchronization between the Master and the external Slave.
The input to the Baud Rate Generator is the system clock. The ESPI Baud Rate High and
Low Byte registers combine to form a 16-bit reload value, BRG[15:0], for the ESPI Baud
Rate Generator. The ESPI baud rate is calculated using the following equation:
System Clock Frequency (Hz)
SPI Baud Rate (bits/s) = ---------------------------------------------------------------------------
2 × BRG[15:0]
Minimum baud rate is obtained by setting BRG[15:0] to 0000H for a clock divisor value
of (2 X 65536 = 131072).
When the ESPI is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt
on time-out, complete the following procedure:
1. Disable the ESPI by clearing the ESPIEN1,0bits in the ESPI Control register.
2. Load the desired 16-bit count value into the ESPI Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BRGCTLbit in the ESPI Control register to 1.
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ESPI Control Register Definitions
ESPI Data Register
The ESPI Data register (Table 109) addresses both the outgoing transmit data register and
the incoming receive data register. Reads from the ESPI Data register return the contents
of the receive data register. The receive data register is updated with the contents of the
shift register at the end of each transfer. Writes to the ESPI Data register load the transmit
data register unless TDRE = 0. Data is shifted out starting with bit 7. The last bit received
resides in bit position 0.
With the ESPI configured as a Master, writing a data byte to this register initiates the data
transmission. With the ESPI configured as a Slave, writing a data byte to this register
loads the shift register in preparation for the next data transfer with the external Master. In
either the Master or Slave modes, if TDRE = 0, writes to this register are ignored.
When the character length is less than 8 bits (as set by the NUMBITSfield in the ESPI
Mode register), the transmit character must be left justified in the ESPI Data register. A
received character of less than 8 bits is right justified (last bit received is in bit position 0).
For example, if the ESPI is configured for 4-bit characters, the transmit characters must be
written to ESPIDATA[7:4] and the received characters are read from ESPIDATA[3:0].
Table 109. ESPI Data Register (ESPIDATA)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DATA
F60H
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ADDR
DATA—Data
Transmit and/or receive data. Writes to the ESPIDATA register load the shift register.
Reads from the ESPIDATA register return the value of the receive data register.
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ESPI Transmit Data Command Register
The ESPI Transmit Data Command register (Table 110) provides control of the SS pin
when it is configured as an output (Master mode). The TEOF and SSV bits can be con-
trolled by a bus write to this register.
Table 110. ESPI Transmit Data Command Register (ESPITDCR)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
TEOF
0
0
SSV
0
0
0
0
0
0
0
R
R
R
R
R
R
R/W
R/W
F61H
ADDR
TEOF—Transmit End of Frame
This bit is used in Master mode to indicate that the data in the transmit data register is the
last byte of the transfer or frame. When the last byte has been sent SS (and SSV) will
change state and TEOF will automatically clear.
0 = The data in the transmit data register is not the last character in the message.
1 = The data in the transmit data register is the last character in the message.
SSV—Slave Select Value
When SSIO = 1, writes to this register will control the value output on the SS pin. Refer to
the SSMD field of the ESPI Mode register for more details.
ESPI Control Register
The ESPI Control register (Table 111) configures the ESPI for transmit and receive opera-
tions.
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Table 111. ESPI Control Register (ESPICTL)
BITS
FIELD
RESET
R/W
7
DIRQE
0
6
5
4
PHASE
0
3
CLKPOL
0
2
WOR
0
1
MMEN
0
0
ESPIEN0
0
ESPIEN1 BRGCTL
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F62H
ADDR
DIRQE—Data Interrupt Request Enable
This bit can be used to disable or enable data (TDRE and RDRF) interrupts. Disabling the
data interrupts is needed when controlling data transfer by polling. Error interrupts are not
disabled. To block all ESPI interrupt sources, clear the ESPI interrupt enable bit in the
Interrupt Controller.
0 = TDRE and RDRF assertions do not cause an interrupt.
Use this setting if controlling data transfer by software polling of TDRE
and RDRF. The TUND, COL, ABT, and ROVR bits will cause an interrupt.
1 = TDRE and RDRF assertions will cause an interrupt.
TUND, COL, ABT, and ROVR will also cause interrupts. Use this setting if
controlling data transfer via interrupt handlers.
ESPIEN1, ESPIEN0—ESPI Enable and Direction Control
00 = ESPI block is disabled.
BRG may be used as a general purpose timer by setting BRGCTL = 1.
01 = Receive Only Mode.
Use this setting in Slave mode if software application is receiving data but not
sending. TDRE will not assert. Transmitted data will be all 1’s.
Not valid in Master mode since Master must source data to drive the transfer.
10 = Transmit Only Mode
Use this setting in Master or Slave mode when the software application is sending
data but not receiving. RDRF will not assert.
11 = Transmit/Receive Mode
Use this setting if the software application is both sending and receiving information.
Both TDRE and RDRF will be active.
BRGCTL—Baud Rate Generator Control
The function of this bit depends upon ESPIEN1,0. When ESPIEN1,0 = 00, this bit allows
enabling the BRG to provide periodic interrupts.
If the ESPI is disabled:
0 = The Baud Rate Generator timer function is disabled.
Reading the Baud Rate High and Low registers returns the BRG Reload value.
1 = The Baud Rate Generator timer function and time-out interrupt are enabled.
Reading the Baud Rate High and Low registers returns the BRG Counter value.
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If the ESPI is enabled:
0 = Reading the Baud Rate High and Low registers returns the BRG Reload value.
If MMEN = 1 the BRG is enabled to generate SCK. If MMEN = 0 the BRG is
disabled.
1 = Reading the Baud Rate High and Low registers returns the BRG Counter value.
If MMEN = 1 the BRG is enabled to generate SCK. If MMEN = 0 the BRG is
enabled to provide a Slave SCK time-out. Refer to the Slave Abort error description.
If reading the counter one byte at a time while the BRG is counting keep in mind that
the values will not be in sync. It is recommended to read the counter using word (2-byte)
reads.
Caution:
PHASE—Phase Select
Sets the phase relationship of the data to the clock. Refer to the ESPI Clock Phase and
Polarity Control section for more information on operation of the PHASEbit.
CLKPOL—Clock Polarity
0 = SCK idles Low (0).
1 = SCK idles High (1).
WOR—Wire-OR (Open-Drain) Mode Enabled
0 = ESPI signal pins not configured for open-drain.
1 = All four ESPI signal pins (SCK, SS, MISO, MOSI) configured for open-drain func-
tion. This setting is typically used for multi-Master and/or multi-Slave configurations.
MMEN—ESPI Master Mode Enable
This bit controls the data i/o pin selection and SCK direction
0 = data out on MISO, data in on MOSI (used in SPI Slave mode), SCK is an input.
1 = data out on MOSI, data in on MISO (used in SPI Master mode), SCK is an output.
ESPIEN—ESPI Enable
0 = ESPI disabled.
1 = ESPI enabled.
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ESPI Mode Register
The ESPI Mode register (Table 112) configures the character bit width and mode of the
ESPI IO pins.
Table 112. ESPI Mode Register (ESPIMODE)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
SSIO
0
0
SSPO
0
SSMD
00
NUMBITS[2:0]
0
0
0
R/W
0
R/W
R
R/W
R/W
R/W
R/W
F63H
ADDR
SSMD—Slave Select Mode
This field selects the behavior of SS as a framing signal. For a detailed description of these
modes refer to the section “Slave Select” on page 193.
00 = SPI mode.
When SSIO = 1, the SS pin is driven directly from the SSV bit in the Transmit Data Com-
mand register. The Master software should set SSV (or a GPIO output if the SS pin is not
connected to the desired Slave) to the asserted state prior to or on the same clock cycle that
the transmit data register is written with the initial byte. At the end of a frame (after the
last RDRF event), SSV will be automatically deasserted by hardware. In this mode SCK is
active only for data transfer (one clock cycle per bit transferred).
01 = Loopback Mode.
When ESPI is configured as Master (MMEN = 1) the outputs are deasserted and data is
looped from shift register out to shift register in. When ESPI is configured as a Slave
(MMEN = 0) and SS in asserts, MISO (Slave output) is tied to MOSI (Slave input) to pro-
vide an asynchronous remote loop back (echo) function.
10 = Synchronous Frame Synch Pulse.
One SCK period before transmitting the first bit of a frame, the Master will output the
value from the SSV bit of the Transmit Data Command register onto the SS pin for one
SCK cycle. In this mode SCK will run continuously, starting with the initial frame sync
pulse. Frames will run back to back as long as software continue to provide data. The
frame sync pulse for the following frame will be asserted in sync with the last bit of the
current frame (TEOF set in Transmit Data Command Register for last byte in frame). The
transaction will continue with back to back frames until a transmit underrun occurs in the
Master (software has no more frames to send). This mode is typically used to send contin-
uous frames of fixed length as in TDM (Time Division Multiplexing) applications. In
Slave mode, the assertion of SS (low to high if SSPO = 1, high to low if SSPO = 0) will
trigger the start of a transaction on the next SCK cycle. The next assertion will mark the
current byte as an End of Frame byte.
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11 = Synchronous Framing with SSV
In this mode, the value from SSV will be output by the Master on the SS pin one SCK
period before the data and will remain in that state until the start of the next frame. Typi-
cally this mode is used to send back to back frames with SS alternating on each frame. A
frame boundary is indicated in the Master when SSV changes. A frame boundary is
detected in the Slave by SS changing state. The SS framing signal will lead the frame by
one SCK period. In this mode SCK will run continuously, starting with the initial SS
assertion. Frames will run back to back as long as software continue to provide data. An
example of this mode is the I2S protocol (Inter IC Sound) which is used to carry left and
right channel audio data with the SS signal indicating which channel is being sent. In
Slave mode, the change in state of SS (low to high or high to low) will trigger the start of a
transaction on the next SCK cycle.
NUMBITS[2:0]—Number of Data Bits Per Character to Transfer
This field contains the number of bits to shift for each character transfer. Refer to the ESPI
Data Register description for information on valid bit positions when the character length
is less than 8-bits.
000 = 8 bits
001 = 1 bit
010 = 2 bits
011 = 3 bits
100 = 4 bits
101 = 5 bits
110 = 6 bits
111 = 7 bits.
SSIO—Slave Select I/O
This bit controls the direction of the SS pin. In single Master mode, SSIO is set to 1 unless
a separate GPIO pin is being used to provide the SS output function. In the SPI Slave or
multi-Master configuration SSIO is set to 0.
0 = SS pin configured as an input (SPI Slave and multi-Master modes).
1 = SS pin configured as an output (SPI single Master mode).
SSPO—Slave Select Polarity
This bit controls the polarity of the SS pin.
0 = SS is active low. (SSV = 1 corresponds to SS = 0)
1 = SS is active high. (SSV = 1 corresponds to SS = 1)
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ESPI Status Register
The ESPI Status register (Table 113) indicates the current state of the ESPI. All bits revert
to their reset state if the ESPI is disabled.
Table 113. ESPI Status Register (ESPISTAT)
BITS
FIELD
RESET
R/W
7
TDRE
1
6
5
COL
0
4
ABT
0
3
2
RDRF
0
1
TFST
0
0
SLAS
1
TUND
0
ROVR
0
R
R/W*
R/W*
R/W*
R/W*
R
R
R
F64H
ADDR
R/W* = Read access. Write a 1 to clear the bit to 0.
TDRE—Transmit Data Register Empty
0 = Transmit data register is full or ESPI is disabled.
1 = Transmit data register is empty. A write to the ESPI (Transmit) Data register clears
this bit.
TUND—Transmit Underrun
0 = A Transmit Underrun error has not occurred.
1 = A Transmit Underrun error has occurred.
COL—Collision
0 = A multi-Master collision (mode fault) has not occurred.
1 = A multi-Master collision (mode fault) has been detected.
ABT—Slave mode transaction abort
This bit is set if the ESPI is configured in Slave mode, a transaction is occurring and SS
deasserts before all bits of a character have been transferred as defined by the NUMBITS
field of the ESPIMODE register. This bit can also be set in Slave mode by an SCK moni-
tor time-out (MMEN = 0, BRGCTL = 1).
0 = A Slave mode transaction abort has not occurred.
1 = A Slave mode transaction abort has been detected.
ROVR—Receive Overrun
0 = A Receive Overrun error has not occurred.
1 = A Receive Overrun error has occurred.
RDRF—Receive Data Register Full
0 = Receive Data register is empty
1 = Receive Data register is full. A read from the ESPI (Receive) Data register clears this
bit.
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TFST—Transfer Status
0 = No data transfer is currently in progress.
1 = Data transfer is currently in progress.
SLAS—Slave Select
Reading this bit returns the current value of the SS pin.
0 = The SS pin input is low
1 = The SS pin input is high
ESPI State Register
The ESPI State register (Table 114) lets you observe the ESPI clock, data and internal
state.
Table 114. ESPI State Register (ESPISTATE)
BITS
FIELD
RESET
R/W
7
SCKI
0
6
SDI
0
5
4
3
2
1
0
ESPISTATE
0
R
R
R
F65H
ADDR
SCKI - Serial Clock Input
This bit reflects the state of the serial clock pin.
0 = The SCK input pin is low
1 = The SCK input pin is high
SDI - Serial Data Input
This bit reflects the state of the serial data input (MOSI or MISO depending on the MMEN
bit).
0 = The serial data input pin is low.
1 = The serial data input pin is high.
ESPISTATE - ESPI State Machine
Indicates the current state of the internal ESPI State Machine. This information is intended
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for manufacturing test. The state values may change in future hardware revs and are not
intended to be used by a software driver. Table 115 defines the valid states.
Table 115. ESPISTATE values
ESPISTATE
Value
Description
00_0000
00_0001
01_0001
10_1110
10_1111
10_1100
10_1101
10_1010
10_1011
10_1000
10_1001
10_0110
10_0111
10_0100
10_0101
10_0010
10_0011
10_0000
10_0001
Idle
Slave Wait For SCK
Master Ready
Bit 7 Receive
Bit 7 Transmit
Bit 6 Receive
Bit 6 Transmit
Bit 5 Receive
Bit 5 Transmit
Bit 4 Receive
Bit 4 Transmit
Bit 3 Receive
Bit 3 Transmit
Bit 2 Receive
Bit 2 Transmit
Bit 1 Receive
Bit 1 Transmit
Bit 0 Receive
Bit 0 Transmit
ESPI Baud Rate High and Low Byte Registers
The ESPI Baud Rate High and Low Byte registers (Tables 116 and 68) combine to form a
16-bit reload value, BRG[15:0], for the ESPI Baud Rate Generator. The ESPI baud rate is
calculated using the following equation:
System Clock Frequency (Hz)
SPI Baud Rate (bits/s) = ---------------------------------------------------------------------------
2 × BRG[15:0]
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Minimum baud rate is obtained by setting BRG[15:0] to 0000Hfor a clock divisor value
of (2 X 65536 = 131072).
Table 116. ESPI Baud Rate High Byte Register (ESPIBRH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
BRH
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F66H
ADDR
BRH = ESPI Baud Rate High Byte
Most significant byte, BRG[15:8], of the ESPI Baud Rate Generator’s reload value.
Table 117. ESPI Baud Rate Low Byte Register (ESPIBRL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
BRL
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/w
F67H
ADDR
BRL = ESPI Baud Rate Low Byte
Least significant byte, BRG[7:0], of the ESPI Baud Rate Generator’s reload value.
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2
I C Master/Slave Controller
The I2C Master/Slave Controller ensures that the Z8 Encore! XP® F1680 Series devices
are bus-compatible with the I2C protocol. The I2C bus consists of the serial data signal
(SDA) and a serial clock signal (SCL) bidirectional lines. Features of the I2C controller
include:
•
•
•
•
•
•
•
Operates in MASTER/SLAVE or SLAVE ONLY modes
Supports arbitration in a multimaster environment (MASTER/SLAVE mode)
Supports data rates up to 400Kbps
7- or 10-bit slave address recognition (interrupt only on address match)
Optional general call address recognition
Optional digital filter on receive SDA, SCL lines
Optional interactive receive mode allows software interpretation of each received ad-
dress and/or data byte before acknowledging
•
•
Unrestricted number of data bytes per transfer
Baud Rate Generator can be used as a general-purpose timer with an interrupt if the I2C
controller is disabled.
Architecture
Figure 43 illustrates the architecture of the I2C controller.
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SDA
SCL
Shift
SHIFT
Load
I2CDATA
Baud Rate Generator
I2CBRH
I2CBRL
Tx/Rx State Machine
I2CISTAT
I2CSTATE
I2CCTL
I2CMODE
I2CSLVAD
I2C Interrupt
Register Bus
2
Figure 43. I C Controller Block Diagram
2
I C Master/Slave Controller Registers
Table 119 summarizes the I2C master/slave controller’s software-accessible registers.
2
Table 119. I C Master/Slave Controller Registers
Name
Abbreviation Description
I2CDATA Transmit/receive data register.
2
I C Data
2
I C Interrupt Status I2CISTAT
Interrupt status register.
2
I C Control
I2CCTL
Control register—basic control functions.
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2
Table 119. I C Master/Slave Controller Registers (Continued)
Name
Abbreviation Description
2
I C Baud Rate High I2CBRH
High byte of baud rate generator initialization
value.
2
I C Baud Rate Low I2CBRL
Low byte of baud rate generator initialization
value.
2
I C State
I2CSTATE
I2CMODE
State register.
2
I C Mode
Selects MASTER or SLAVE modes, 7- or 10-bit
addressing; configure address recognition, define
slave address bits [9:8].
2
I C Slave Address I2CSLVAD
Defines slave address bits [7:0].
2
Comparison with the Master Mode Only I C Controller
Porting code written for the MASTER ONLY I2C controller found on other Z8 Encore!®
parts to the I2C Master/Slave Controller is straightforward. The I2CDATA, I2CCTL,
I2CBRH and I2CBRL Register definitions have not changed. The following bullets high-
light the differences between these two designs.
•
The Status (I2CSTATE) Register from the MASTER ONLY I2C controller is split into
the Interrupt Status (I2CISTAT) Register and the State (I2CSTATE) Register because
more interrupt sources are available. The ACK, 10B, TAS(now called AS), and DSS
(now called DS) bits, formerly part of the Status Register, are now part of the State Reg-
ister.
•
•
The I2CSTATE Register was called the Diagnostic State (I2CDST) Register in the
MASTER mode-only version. The I2CDST Register provided diagnostic information.
The I2CSTATE Register contains status and state information that may be useful to
software in an operational mode.
The I2CMODE Register was called the Diagnostic Control (I2CDIAG) Register in the
MASTER mode-only version. The I2CMODE Register provides control for the
SLAVE modes of operation, as well as the most significant two bits of the 10-bit slave
address.
•
•
•
The I2CSLVAD Register is added to provide programming capabilities for the slave
address.
The ACKV bit in the I2CSTATE Register enables the master to check the Acknowl-
edge from the slave before sending the next byte.
Support for multimaster environments—if arbitration is lost when operating as a mas-
ter, the ARBLST bit in the I2CISTAT Register is set and the mode automatically
switches to SLAVE mode.
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Operation
The I2C Master/Slave Controller operates in MASTER/SLAVE mode, SLAVE ONLY
mode, or with master arbitration. In MASTER/SLAVE mode, it can be used as the only
master on the bus or as one of several masters on the bus, with arbitration. In a multimaster
environment, the controller switches from MASTER to SLAVE mode upon losing arbitra-
tion.
Though slave operation is fully supported in MASTER/SLAVE mode, if a device is
intended to operate only as a slave, then SLAVE ONLY mode can be selected. In SLAVE
ONLY mode, the device will not initiate a transaction, even if the software inadvertently
sets the START bit.
SDA and SCL Signals
The I2C circuit sends all addresses, data, and Acknowledge signals over the SDA line,
most-significant bit first. SCL is the clock for the I2C bus. When the SDA and SCL pin
alternate functions are selected for their respective GPIO ports, the pins are automatically
configured for open-drain operation.
The master is responsible for driving the SCL clock signal. During the Low period of the
clock, a slave can hold the SCL signal Low to suspend the transaction if it is not ready to
proceed. The master releases the clock at the end of the Low period and notices that the
clock remains Low instead of returning to a High level. When the slave releases the clock,
the I2C master continues the transaction. All data is transferred in bytes; there is no limit to
the amount of data transferred in one operation. When transmitting address, data, or an
Acknowledge, the SDA signal changes in the middle of the Low period of SCL. When
receiving address, Data or an Acknowledge, the SDA signal is sampled in the middle of
the High period of SCL.
A low-pass digital filter can be applied to the SDA and SCL receive signals by setting the
Filter Enable (FILTEN) bit in the I2C Control Register. When the filter is enabled, any
glitch that is less than a system clock period in width will be rejected. This filter should be
enabled when running in I2C FAST mode (400kbps), and can also be used at lower data
rates.
2
I C Interrupts
The I2C controller contains multiple interrupt sources that are combined into one interrupt
request signal to the interrupt controller. If the I2C controller is enabled, the source of the
interrupt is determined by which bits are set in the I2CISTAT Register. If the I2C control-
ler is disabled, the BRG controller can be used to generate general-purpose timer inter-
rupts.
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Each interrupt source, other than the baud rate generator interrupt, features an associated
bit in the I2CISTAT Register that clears automatically when software reads the register or
performs another task, such as reading/writing the data register.
Transmit Interrupts
Transmit interrupts (TDREbit = 1 in I2CISTAT) occur under the following conditions, both
of which must be true.
•
•
The transmit data register is empty and the TXIbit = 1 in the I2C Control Register
The I2C controller is enabled, with one of the following:
–
–
The first bit of a 10-bit address is shifted out
The first bit of the final byte of an address is shifted out and the RDbit is deas-
serted
–
The first bit of a data byte is shifted out
Writing to the I2C Data Register always clears the TRDEbit to 0.
Receive Interrupts
Receive interrupts (RDRFbit = 1 in I2CISTAT) occur when a byte of data has been
received by the I2C controller. The RDRFbit is cleared by reading from the I2C Data Reg-
ister. If the RDRF interrupt is not serviced prior to the completion of the next Receive
byte, the I2C controller holds SCL Low during the final data bit of the next byte until
RDRFis cleared, to prevent receive overruns. A receive interrupt does not occur when a
slave receives an address byte or for data bytes following a slave address that did not
match. An exception is if the Interactive Receive Mode (IRM) bit is set in the I2CMODE
Register, in which case Receive interrupts occur for all Receive address and data bytes in
SLAVE mode.
Slave Address Match Interrupts
Slave address match interrupts (SAMbit = 1 in I2CISTAT) occur when the I2C controller is
in SLAVE mode and an address is received that matches the unique slave address. The
General Call Address (0000_0000) and STARTBYTE (0000_0001) are recognized if the
GCEbit = 1 in the I2CMODE Register. The software checks the RDbit in the I2CISTAT
Register to determine if the transaction is a Read or Write transaction. The General Call
Address and STARTBYTE address are also distinguished by the RDbit. The General Call
Address (GCA) bit of the I2CISTAT Register indicates whether the address match occurred
on the unique slave address or the General Call/STARTBYTE address. The SAMbit clears
automatically when the I2CISTAT Register is read.
If configured via the MODE[1:0]field of the I2C Mode Register for 7-bit slave address-
ing, the most significant 7 bits of the first byte of the transaction are compared against the
SLA[6:0]bits of the Slave Address Register. If configured for 10-bit slave addressing,
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the first byte of the transaction is compared against {11110,SLA[9:8],R/W} and the sec-
ond byte is compared against SLA[7:0].
Arbitration Lost Interrupts
Arbitration Lost interrupts (ARBLSTbit = 1 in I2CISTAT) occur when the I2C controller is
in MASTER mode and loses arbitration (outputs a 1 on SDA and receives a 0 on SDA).
The I2C controller switches to SLAVE mode when this instance occurs. This bit clears
automatically when the I2CISTAT Register is read.
Stop/Restart Interrupts
A Stop/Restart event interrupt (SPRSbit = 1 in I2CISTAT) occurs when the I2C controller
is in SLAVE mode and a STOPor RESTARTcondition is received, indicating the end of the
transaction. The RSTRbit in the I2C State Register indicates whether the bit was set due to
a STOPor RESTARTcondition. When a restart occurs, a new transaction by the same mas-
ter is expected to follow. This bit is cleared automatically when the I2CISTAT Register is
read. The STOP/RESTART interrupt only occurs on a selected (address match) slave.
Not Acknowledge Interrupts
Not Acknowledge interrupts (NCKIbit = 1 in I2CISTAT) occur in MASTER mode when a
Not Acknowledge is received or sent by the I2C controller and the STARTor STOPbit is
not set in the I2C Control Register. In MASTER mode, the Not Acknowledge interrupt
clears by setting the STARTor STOPbit. When this interrupt occurs in MASTER mode,
the I2C controller waits until it is cleared before performing any action. In SLAVE mode,
the Not Acknowledge interrupt occurs when a Not Acknowledge is received in response to
data sent. The NCKIbit clears in SLAVE mode when software reads the I2CISTAT Regis-
ter.
General Purpose Timer Interrupt from Baud Rate Generator
If the I2C controller is disabled (IENbit in the I2CCTL Register = 0) and the BIRQbit in
the I2CCTL Register = 1, an interrupt is generated when the baud rate generator (BRG)
counts down to 1. The baud rate generator reloads and continues counting, providing a
periodic interrupt. None of the bits in the I2CISTAT Register are set, allowing the BRG in
the I2C controller to be used as a general-purpose timer when the I2C controller is dis-
abled.
Start and Stop Conditions
The master generates the START and STOP conditions to start or end a transaction. To
start a transaction, the I2C controller generates a STARTcondition by pulling the SDA sig-
nal Low while SCL is High. To complete a transaction, the I2C controller generates a
STOPcondition by creating a Low-to-High transition of the SDA signal while the SCL
signal is High. These START and STOP events occur when the STARTand STOPbits in
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the I2C Control Register are written by software to begin or end a transaction. Any byte
transfer currently under way, including the Acknowledge phase, finishes before the
START or STOPcondition occurs.
2
Software Control of I C Transactions
The I2C controller is configured via the I2C Control and I2C Mode registers. The
MODE[1:0]field of the I2C Mode Register allows the configuration of the I2C controller
for MASTER/SLAVE or SLAVE ONLY mode, and configures the slave for 7- or 10-bit
addressing recognition.
MASTER/SLAVE mode can be used for:
•
•
•
MASTER ONLY operation in a single master/one or more slave I2C system
MASTER/SLAVE in a multimaster/multislave I2C system
SLAVE ONLY operation in an I2C system
In SLAVE ONLY mode, the START bit of the I2C Control Register is ignored (software
cannot initiate a master transaction by accident), and operation to SLAVE ONLY mode is
restricted, thereby preventing accidental operation in MASTER mode.
The software can control I2C transactions by enabling the I2C controller interrupt in the
interrupt controller or by polling the I2C Status Register.
To use interrupts, the I2C interrupt must be enabled in the interrupt controller and followed
by executing an EI instruction. The TXIbit in the I2C Control Register must be set to
enable transmit interrupts. An I2C interrupt service routine then checks the I2C Status
Register to determine the cause of the interrupt.
To control transactions by polling, the TDRE, RDRF, SAM, ARBLST, SPRS, and NCKIinter-
rupt bits in the I2C Status Register should be polled. The TDREbit asserts regardless of the
state of the TXIbit.
Master Transactions
The following sections describe master Read and Write transactions to both 7- and 10-bit
slaves.
Master Arbitration
If a master loses arbitration during the address byte, it releases the SDA line, switches to
SLAVE mode and monitors the address to determine if it is selected as a slave. If a master
loses arbitration during the transmission of a data byte, it releases the SDA line and waits
for the next STOPor STARTcondition.
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The master detects a loss of arbitration when a 1 is transmitted but a 0 is received from the
bus in the same bit-time. This loss occurs if more than one master is simultaneously
accessing the bus. Loss of arbitration can occur during the address phase (two or more
masters accessing different slaves) or during the data phase, when the masters are attempt-
ing to write different data to the same slave.
When a master loses arbitration, the software is informed by means of the Arbitration Lost
interrupt. The software can repeat the same transaction at a later time.
A special case can occur when a slave transaction starts just before the software attempts
to start a new master transaction by setting the STARTbit. In this case, the state machine
enters its slave states before the STARTbit is set, and as a result, the I2C controller will not
arbitrate. If a slave address match occurs and the I2C controller receives/transmits data, the
STARTbit is cleared and an Arbitration Lost interrupt is asserted. The software can mini-
mize the chance of this instance occurring by checking the BUSYbit in the I2CSTATE
Register before initiating a master transaction. If a slave address match does not occur, the
Arbitration Lost interrupt will not occur, and the STARTbit will not be cleared. The I2C
controller will initiate the master transaction after the I2C bus is no longer busy.
Master Address-Only Transactions
It is sometimes preferable to perform an address-only transaction to determine if a particu-
lar slave device is able to respond. This transaction can be performed by monitoring the
ACKVbit in the I2CSTATE Register after the address has been written to the I2CDATA
Register and the STARTbit has been set. After the ACKVbit is set, the ACKbit in the
I2CSTATE Register determines if the slave is able to communicate. The STOPbit must be
set in the I2CCTL Register to terminate the transaction without transferring data. For a 10-
bit slave address, if the first address byte is acknowledged, the second address byte should
also be sent to determine if the preferred slave is responding.
Another approach is to set both the STOPand STARTbits (for sending a 7-bit address).
After both bits have cleared (7-bit address has been sent and transaction is complete), the
ACKbit can be read to determine if the slave has acknowledged. For a 10-bit slave, set the
STOPbit after the second TDRE interrupt (which indicates that the second address byte is
being sent).
Master Transaction Diagrams
In the following transaction diagrams, the shaded regions indicate the data that is trans-
ferred from the master to the slave, and the unshaded regions indicate the data that is trans-
ferred from the slave to the master. The transaction field labels are defined as follows:
S
Start
W
A
Write
Acknowledge
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A
P
Not Acknowledge
Stop
Master Write Transaction with a 7-Bit Address
Figure 44 illustrates the data transfer format from a master to a 7-bit addressed slave
Slave
Address
S
W = 0
A
Data
A
Data
A
Data
A/A
P/S
Figure 44. Data Transfer Format—Master Write Transaction with a 7-Bit Address
The procedure for a master transmit operation to a 7-bit addressed slave is as follows:
1. The software initializes the MODEfield in the I2C Mode Register for MASTER/
SLAVE mode with either a 7- or 10-bit slave address. The MODEfield selects the
address width for this mode when addressed as a slave (but not for the remote slave).
The software asserts the IENbit in the I2C Control Register.
2. The software asserts the TXIbit of the I2C Control Register to enable transmit inter-
rupts.
3. The I2C interrupt asserts, because the I2C Data Register is empty.
4. The software responds to the TDREbit by writing a 7-bit slave address plus the Write
bit (which is cleared to 0) to the I2C Data Register.
5. The software sets the STARTbit of the I2C Control Register.
6. The I2C controller sends a STARTcondition to the I2C slave.
7. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Reg-
ister.
8. After one bit of the address has been shifted out by the SDA signal, the transmit inter-
rupt asserts.
9. The software responds by writing the transmit data into the I2C Data Register.
10. The I2C controller shifts the remainder of the address and the Write bit out via the
SDA signal.
11. The I2C slave sends an Acknowledge (by pulling the SDA signal Low) during the next
high period of SCL. The I2C controller sets the ACKbit in the I2C Status Register.
If the slave does not acknowledge the address byte, the I2C controller sets the NCKI
bit in the I2C Status Register, sets the ACKVbit, and clears the ACKbit in the I2C State
Register. The software responds to the Not Acknowledge interrupt by setting the STOP
bit and clearing the TXIbit. The I2C controller flushes the Transmit Data Register,
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sends a STOPcondition on the bus, and clears the STOPand NCKIbits. The transaction
is complete, and the following steps can be ignored.
12. The I2C controller loads the contents of the I2C Shift Register with the contents of the
I2C Data Register.
13. The I2C controller shifts the data out via the SDA signal. After the first bit is sent, the
transmit interrupt asserts.
14. If more bytes remain to be sent, return to Step 9.
15. When there is no more data to be sent, the software responds by setting the STOPbit of
the I2C Control Register (or the STARTbit to initiate a new transaction).
16. If no additional transaction is queued by the master, the software can clear the TXIbit
of the I2C Control Register.
17. The I2C controller completes transmission of the data on the SDA signal.
18. The I2C controller sends a STOPcondition to the I2C bus.
Note: If the slave terminates the transaction early by responding with a Not Acknowledge during
the transfer, the I2C controller asserts the NCKIinterrupt and halts. The software must ter-
minate the transaction by setting either the STOPbit (end transaction) or the STARTbit
(end this transaction, start a new one). In this case, it is not necessary for software to set
the FLUSHbit of the I2CCTL Register to flush the data that was previously written but not
transmitted. The I2C controller hardware automatically flushes transmit data in this not
acknowledge case.
Master Write Transaction with a 10-Bit Address
Figure 45 illustrates the data transfer format from a master to a 10-bit addressed slave.
Slave Address
1st Byte
Slave Address
2nd Byte
S
W=0
A
A
Data
A
Data
A/A
F/S
Figure 45. Data Transfer Format—Master Write Transaction with a 10-Bit Address
The first 7 bits transmitted in the first byte are 11110XX. The 2 XXbits are the two most
significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
Read/Write control bit (which is cleared to 0). The transmit operation is performed in the
same manner as 7-bit addressing.
The procedure for a master transmit operation to a 10-bit addressed slave is as follows:
1. The software initializes the MODEfield in the I2C Mode Register for MASTER/
SLAVE mode with 7- or 10-bit addressing (the I2C bus protocol allows the mixing of
slave address types). The MODEfield selects the address width for this mode when
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addressed as a slave (but not for the remote slave). The software asserts the IENbit in
the I2C Control Register.
2. The software asserts the TXIbit of the I2C Control Register to enable transmit inter-
rupts.
3. The I2C interrupt asserts because the I2C Data Register is empty.
4. The software responds to the TDREinterrupt by writing the first slave address byte
(11110xx0). The least-significant bit must be 0 for the write operation.
5. The software asserts the STARTbit of the I2C Control Register.
6. The I2C controller sends a STARTcondition to the I2C slave.
7. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Reg-
ister.
8. After one bit of the address is shifted out by the SDA signal, the transmit interrupt
asserts.
9. The software responds by writing the second byte of address into the contents of the
I2C Data Register.
10. The I2C controller shifts the remainder of the first byte of the address and the Write bit
out via the SDA signal.
11. The I2C slave sends an Acknowledge by pulling the SDA signal Low during the next
high period of SCL. The I2C controller sets the ACKbit in the I2C Status Register.
If the slave does not acknowledge the first address byte, the I2C controller sets the
NCKIbit in the I2C Status Register, sets the ACKVbit, and clears the ACKbit in the I2C
State Register. The software responds to the Not Acknowledge interrupt by setting the
STOPbit and clearing the TXIbit. The I2C controller flushes the second address byte
from the data register, sends a STOPcondition on the bus, and clears the STOPand
NCKIbits. The transaction is complete, and the following steps can be ignored.
12. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Reg-
ister (2nd address byte).
13. The I2C controller shifts the second address byte out via the SDA signal. After the
first bit has been sent, the transmit interrupt asserts.
14. The software responds by writing the data to be written out to the I2C Control Regis-
ter.
15. The I2C controller shifts out the remainder of the second byte of the slave address (or
ensuing data bytes, if looping) via the SDA signal.
16. The I2C slave sends an Acknowledge by pulling the SDA signal Low during the next
high period of SCL. The I2C controller sets the ACKbit in the I2C Status Register.
If the slave does not acknowledge, refer to the second paragraph of Step 11.
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17. The I2C controller shifts the data out by the SDA signal. After the first bit is sent, the
transmit interrupt asserts.
18. If more bytes remain to be sent, return to Step 14.
19. The software responds by asserting the STOPbit of the I2C Control Register.
20. The I2C controller completes transmission of the data on the SDA signal.
21. The I2C controller sends a STOPcondition to the I2C bus.
Note: If the slave responds with a Not Acknowledge during the transfer, the I2C controller
asserts the NCKIbit, sets the ACKVbit, clears the ACKbit in the I2C State Register, and
halts. The software terminates the transaction by setting either the STOPbit (end transac-
tion) or the STARTbit (end this transaction, start a new one). The Transmit Data Register
is flushed automatically.
Master Read Transaction with a 7-Bit Address
Figure 46 illustrates the data transfer format for a read operation to a 7-bit addressed slave.
S
Slave Address
R = 1
A
Data
A
Data
A
P/S
Figure 46. Data Transfer Format—Master Read Transaction with a 7-Bit Address
The procedure for a master Read operation to a 7-bit addressed slave is as follows:
1. The software initializes the MODEfield in the I2C Mode Register for MASTER/
SLAVE mode with 7- or 10-bit addressing (the I2C bus protocol allows the mixing of
slave address types). The MODEfield selects the address width for this mode when
addressed as a slave (but not for the remote slave). The software asserts the IENbit in
the I2C Control Register.
2. The software writes the I2C Data Register with a 7-bit slave address, plus the Read bit
(which is set to 1).
3. The software asserts the STARTbit of the I2C Control Register.
4. If this operation is a single-byte transfer, the software asserts the NAKbit of the I2C
Control Register so that after the first byte of data has been read by the I2C controller,
a Not Acknowledge instruction is sent to the I2C slave.
5. The I2C controller sends a STARTcondition.
6. The I2C controller sends the address and Read bit out via the SDA signal.
7. The I2C slave acknowledges the address by pulling the SDA signal Low during the
next high period of SCL.
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If the slave does not acknowledge the address byte, the I2C controller sets the NCKI
bit in the I2C Status Register, sets the ACKVbit, and clears the ACKbit in the I2C State
Register. The software responds to the Not Acknowledge interrupt by setting the STOP
bit and clearing the TXIbit. The I2C controller flushes the Transmit Data Register,
sends a STOPcondition on the bus, and clears the STOPand NCKIbits. The transaction
is complete, and the following steps can be ignored.
8. The I2C controller shifts in the first byte of data from the I2C slave on the SDA signal.
9. The I2C controller asserts the receive interrupt.
10. The software responds by reading the I2C Data Register. If the next data byte is to be
the final byte, the software must set the NAKbit of the I2C Control Register.
11. The I2C controller sends a Not Acknowledge to the I2C slave if the next byte is the
final byte; otherwise, it sends an Acknowledge.
12. If there are more bytes to transfer, the I2C controller returns to Step 7.
13. A NAK interrupt (NCKIbit in I2CISTAT) is generated by the I2C controller.
14. The software responds by setting the STOPbit of the I2C Control Register.
15. A STOPcondition is sent to the I2C slave.
Master Read Transaction with a 10-Bit Address
Figure 47 illustrates the read transaction format for a 10-bit addressed slave.
Slave Address
1st Byte
Slave Address
2nd Byte
Slave Address
1st Byte
S
W=0 A
A S
R=1
A
Data
A
Data A P
Figure 47. Data Transfer Format—Master Read Transaction with a 10-Bit Address
The first 7 bits transmitted in the first byte are 11110XX. The two XXbits are the two
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write control bit.
The data transfer procedure for a Read operation to a 10-bit addressed slave is as follows:
1. The software initializes the MODEfield in the I2C Mode Register for MASTER/
SLAVE mode with 7- or 10-bit addressing (the I2C bus protocol allows the mixing of
slave address types). The MODEfield selects the address width for this mode when
addressed as a slave (but not for the remote slave). The software asserts the IENbit in
the I2C Control Register.
2. The software writes 11110b, followed by the two most-significant address bits and a
0 (write) to the I2C Data Register.
3. The software asserts the STARTbit of the I2C Control Register.
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4. The I2C controller sends a STARTcondition.
5. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Reg-
ister.
6. After the first bit has been shifted out, a transmit interrupt is asserted.
7. The software responds by writing the least significant eight bits of address to the I2C
Data Register.
8. The I2C controller completes shifting of the first address byte.
9. The I2C slave sends an Acknowledge by pulling the SDA signal Low during the next
high period of SCL.
If the slave does not acknowledge the address byte, the I2C controller sets the NCKI
bit in the I2C Status Register, sets the ACKVbit and clears the ACKbit in the I2C State
Register. The software responds to the Not Acknowledge interrupt by setting the STOP
bit and clearing the TXIbit. The I2C controller flushes the Transmit Data Register,
sends the STOPcondition on the bus and clears the STOPand NCKIbits. The transac-
tion is complete, and the following steps can be ignored.
10. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Reg-
ister (the lower byte of the 10-bit address).
11. The I2C controller shifts out the next eight bits of the address. After the first bit shifts,
the I2C controller generates a transmit interrupt.
12. The software responds by setting the STARTbit of the I2C Control Register to generate
a repeated STARTcondition.
13. The software writes 11110b, followed by the 2-bit slave address and a 1 (Read) to the
I2C Data Register.
14. If the user chooses to read only one byte, the software responds by setting the NAKbit
of the I2C Control Register.
15. After the I2C controller shifts out the address bits listed in Step 9 (the second address
transfer), the I2C slave sends an Acknowledge by pulling the SDA signal Low during
the next High period of SCL.
If the slave does not acknowledge the address byte, the I2C controller sets the NCKI
bit in the I2C Status Register, sets the ACKVbit, and clears the ACKbit in the I2C State
Register. The software responds to the Not Acknowledge interrupt by setting the STOP
bit and clearing the TXIbit. The I2C controller flushes the Transmit Data Register,
sends the STOPcondition on the bus, and clears the STOPand NCKIbits. The transac-
tion is complete, and the following steps can be ignored.
16. The I2C controller sends a repeated STARTcondition.
17. The I2C controller loads the I2C Shift Register with the contents of the I2C Data Reg-
ister (the third address transfer).
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18. The I2C controller sends 11110b, followed by the two most-significant bits of the
slave read address and a 1 (Read).
19. The I2C slave sends an Acknowledge by pulling the SDA signal Low during the next
High period of SCL.
20. The I2C controller shifts in a byte of data from the slave.
21. The I2C controller asserts the Receive interrupt.
22. The software responds by reading the I2C Data Register. If the next data byte is to be
the final byte, the software must set the NAKbit of the I2C Control Register.
23. The I2C controller sends an Acknowledge or Not Acknowledge to the I2C slave, based
on the value of the NAKbit.
24. If there are more bytes to transfer, the I2C controller returns to Step 18.
25. The I2C controller generates a NAK interrupt (the NCKIbit in the I2CISTAT Regis-
ter).
26. The software responds by setting the STOPbit of the I2C Control Register.
27. A STOPcondition is sent to the I2C slave.
Slave Transactions
The following sections describe Read and Write transactions to the I2C controller config-
ured for 7- and 10-bit slave modes.
Slave Address Recognition
The following slave address recognition options are supported.
Slave 7-Bit Address Recognition Mode. If IRM= 0 during the address phase and the
controller is configured for MASTER/SLAVE or SLAVE 7-bit address mode, the hard-
ware detects a match to the 7-bit slave address defined in the I2CSLVAD Register and
generates the slave address match interrupt (theSAMbit = 1 in the I2CISTAT Register).
The I2C controller automatically responds during the Acknowledge phase with the value
in the NAKbit of the I2CCTL Register.
Slave 10-Bit Address Recognition Mode. If IRM= 0 during the address phase and the
controller is configured for MASTER/SLAVE or SLAVE 10-bit address mode, the hard-
ware detects a match to the 10-bit slave address defined in the I2CMODE and I2CSLVAD
registers and generates the slave address match interrupt (the SAMbit = 1 in the I2CISTAT
Register). The I2C controller automatically responds during the Acknowledge phase with
the value in the NAKbit of the I2CCTL Register.
General Call and Start Byte Address Recognition. If GCE= 1 and IRM= 0 during the
address phase, and the controller is configured for MASTER/SLAVE or SLAVE in either
7- or 10-bit address modes, the hardware detects a match to the General Call Address or
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the START byte and generates the slave address match interrupt. A General Call Address
is a 7-bit address of all 0’s with the R/W bit = 0. A START byte is a 7-bit address of all 0’s
with the R/W bit = 1. The SAMand GCAbits are set in the I2CISTAT Register. The RDbit in
the I2CISTAT Register distinguishes a General Call Address from a START byte which is
cleared to 0 for a General Call Address). For a General Call Address, the I2C controller
automatically responds during the address acknowledge phase with the value in the NAK
bit of the I2CCTL Register. If the software is set to process the data bytes associated with
the GCAbit, the IRMbit can optionally be set following the SAMinterrupt to allow the soft-
ware to examine each received data byte before deciding to set or clear the NAKbit.
A START byte will not be acknowledged—a requirement of the I2C specification.
Software Address Recognition. To disable hardware address recognition, the IRMbit
must be set to 1 prior to the reception of the address byte(s). When IRM= 1, each received
byte generates a receive interrupt (RDRF= 1 in the I2CISTAT Register). The software must
examine each byte and determine whether to set or clear the NAKbit. The slave holds SCL
Low during the Acknowledge phase until the software responds by writing to the I2CCTL
Register. The value written to the NAKbit is used by the controller to drive the I2C bus,
then releasing the SCL. The SAM and GCAbits are not set when IRM= 1 during the address
phase, but the RDbit is updated based on the first address byte.
Slave Transaction Diagrams
In the following transaction diagrams, the shaded regions indicate data transferred from
the master to the slave, and the unshaded regions indicate the data transferred from the
slave to the master. The transaction field labels are defined as follows:
S
W
A
A
P
Start
Write
Acknowledge
Not Acknowledge
Stop
Slave Receive Transaction with 7-Bit Address
The data transfer format for writing data from a master to a slave in 7-bit address mode is
shown in Figure 48. The procedure that follows describes the I2C Master/Slave Controller
operating as a slave in 7-bit addressing mode and receiving data from the bus master.
S
Slave Address
W=0
A
Data
A
Data
A
Data
A/A
P/S
Figure 48. Data Transfer Format—Slave Receive Transaction with 7-Bit Address
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1. The software configures the controller for operation as a slave in 7-bit addressing
mode, as follows.
a. Initialize the MODEfield in the I2C Mode Register for either SLAVE ONLY mode
or MASTER/SLAVE mode with 7-bit addressing.
b. Optionally set the GCEbit.
c. Initialize the SLA[6:0]bits in the I2C Slave Address Register.
d. Set IEN= 1 in the I2C Control Register. Set NAK= 0 in the I2C Control Register.
2. The bus master initiates a transfer, sending the address byte. In SLAVE mode, the I2C
controller recognizes its own address and detects that the R/W bit = 0 (written from
the master to the slave). The I2C controller acknowledges, indicating it is available to
accept the transaction. The SAMbit in the I2CISTAT Register is set to 1, causing an
interrupt. The RDbit in the I2CISTAT Register is cleared to 0, indicating a Write to the
slave. The I2C controller holds the SCL signal Low, waiting for the software to load
the first data byte.
3. The software responds to the interrupt by reading the I2CISTAT Register (which
clears the SAMbit). After seeing the SAMbit to 1, the software checks the RDbit.
Because RD= 0, no immediate action is required until the first byte of data is received.
If software is only able to accept a single byte it sets the NAKbit in the I2CCTL Regis-
ter at this time.
4. The master detects the Acknowledge and sends the byte of data.
5. The I2C controller receives the data byte and responds with Acknowledge or Not
Acknowledge depending on the state of the NAKbit in the I2CCTL Register. The I2C
controller generates the receive data interrupt by setting the RDRFbit in the I2CISTAT
Register.
6. The software responds by reading the I2CISTAT Register, finding the RDRFbit = 1
and reading the I2CDATA Register clearing the RDRFbit. If software can accept only
one more data byte it sets the NAKbit in the I2CCTL Register.
7. The master and slave loops through steps 4 to 6 until the master detects a Not
Acknowledge instruction or runs out of data to send.
8. The master sends the STOPor RESTARTsignal on the bus. Either of these signals can
cause the I2C controller to assert a STOP interrupt (the STOPbit = 1 in the I2CISTAT
Register). Because the slave received data from the master, the software takes no
action in response to the STOP interrupt other than reading the I2CISTAT Register to
clear the STOPbit in the I2CISTAT Register.
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Slave Receive Transaction with 10-Bit Address
The data transfer format for writing data from a master to a slave with 10-bit addressing is
shown in Figure 49. The procedure that follows describes the I2C Master/Slave Controller
operating as a slave in 10-bit addressing mode and receiving data from the bus master.
s
Slave Address
1st Byte
Slave Address
2nd Byte
S
W=0
A
A
Data
A
Data
A/A
P/S
Figure 49. Data Transfer Format—Slave Receive Transaction with 10-Bit Address
1. The software configures the controller for operation as a slave in 10-bit addressing
mode, as follows.
a. Initialize the MODEfield in the I2CMODE Register for either SLAVE ONLY
mode or MASTER/SLAVE mode with 10-bit addressing.
b. Optionally set the GCEbit.
c. Initialize the SLA[7:0]bits in the I2CSLVAD Register and the SLA[9:8]bits in
the I2CMODE Register.
d. Set IEN= 1 in the I2CCTL Register. Set NAK= 0 in the I2C Control Register.
2. The master initiates a transfer, sending the first address byte. The I2C controller recog-
nizes the start of a 10-bit address with a match to SLA[9:8]and detects the R/W bit =
0 (a Write from the master to the slave). The I2C controller acknowledges, indicating
it is available to accept the transaction.
3. The master sends the second address byte. The SLAVE mode I2C controller detects an
address match between the second address byte and SLA[7:0]. The SAMbit in the
I2CISTAT Register is set to 1, thereby causing an interrupt. The RDbit is cleared to 0,
indicating a Write to the slave. The I2C controller acknowledges, indicating it is avail-
able to accept the data.
4. The software responds to the interrupt by reading the I2CISTAT Register, which clears
the SAMbit. Because RD= 0, no immediate action is taken by the software until the
first byte of data is received. If the software is only able to accept a single byte, it sets
the NAKbit in the I2CCTL Register.
5. The master detects the Acknowledge and sends the first byte of data.
6. The I2C controller receives the first byte and responds with Acknowledge or Not
Acknowledge, depending on the state of the NAKbit in the I2CCTL Register. The I2C
controller generates the receive data interrupt by setting the RDRFbit in the I2CISTAT
Register.
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7. The software responds by reading the I2CISTAT Register, finding the RDRFbit = 1,
and then reading the I2CDATA Register, which clears the RDRFbit. If the software can
accept only one more data byte, it sets the NAKbit in the I2CCTL Register.
8. The master and slave loops through steps 5 to 7 until the master detects a Not
Acknowledge instruction or runs out of data to send.
9. The master sends the STOPor RESTARTsignal on the bus. Either of these signals can
cause the I2C controller to assert the STOP interrupt (the STOPbit = 1 in the
I2CISTAT Register). Because the slave received data from the master, the software
takes no action in response to the STOP interrupt other than reading the I2CISTAT
Register to clear the STOPbit.
Slave Transmit Transaction With 7-bit Address
The data transfer format for a master reading data from a slave in 7-bit address mode is
shown in Figure 50. The procedure that follows describes the I2C Master/Slave Controller
operating as a slave in 7-bit addressing mode and transmitting data to the bus master.
S
Slave Address
R = 1
A
Data
A
Data
A
P/S
Figure 50. Data Transfer Format—Slave Transmit Transaction with 7-bit Address
1. The software configures the controller for operation as a slave in 7-bit addressing
mode, as follows.
a. Initialize the MODEfield in the I2C Mode Register for either SLAVE ONLY mode
or MASTER/SLAVE mode with 7-bit addressing.
b. Optionally set the GCEbit.
c. Initialize the SLA[6:0]bits in the I2C Slave Address Register.
d. Set IEN= 1 in the I2C Control Register. Set NAK= 0 in the I2C Control Register.
2. The master initiates a transfer, sending the address byte. The SLAVE mode I2C con-
troller finds an address match and detects that the R/W bit = 1 (read by the master
from the slave). The I2C controller acknowledges, indicating that it is ready to accept
the transaction. The SAMbit in the I2CISTAT Register is set to 1, causing an interrupt.
The RDbit is set to 1, indicating a Read from the slave.
3. The software responds to the interrupt by reading the I2CISTAT Register, thereby
clearing the SAMbit. Because RD= 1, the software responds by loading the first data
byte into the I2CDATA Register. The software sets the TXIbit in the I2CCTL Register
to enable transmit interrupts. When the master initiates the data transfer, the I2C con-
troller holds SCL Low until the software has written the first data byte to the
I2CDATA Register.
4. SCL is released and the first data byte is shifted out.
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5. After the first bit of the first data byte has been transferred, the I2C controller sets the
TDREbit, which asserts the transmit data interrupt.
6. The software responds to the transmit data interrupt (TDRE= 1) by loading the next
data byte into the I2CDATA Register, which clears TDRE.
7. After the data byte has been received by the master, the master transmits an Acknowl-
edge instruction (or Not Acknowledge instruction if this byte is the final data byte).
8. The bus cycles through steps 5 to 7 until the final byte has been transferred. If the soft-
ware has not yet loaded the next data byte when the master brings SCL Low to trans-
fer the most significant data bit, the slave I2C controller holds SCL Low until the data
register has been written. When a Not Acknowledge instruction is received by the
slave, the I2C controller sets the NCKIbit in the I2CISTAT Register, causing the Not
Acknowledge interrupt to be generated.
9. The software responds to the Not Acknowledge interrupt by clearing the TXIbit in the
I2CCTL Register and by asserting the FLUSHbit of the I2CCTL Register to empty the
data register.
10. When the master has completed the final acknowledge cycle, it asserts a STOPor
RESTARTcondition on the bus.
11. The slave I2C controller asserts the STOP/RESTARTinterrupt (set SPRSbit in
I2CISTAT Register).
12. The software responds to the STOP/RESTARTinterrupt by reading the I2CISTAT Reg-
ister, which clears the SPRSbit.
Slave Transmit Transaction With 10-Bit Address
The data transfer format for a master reading data from a slave with 10-bit addressing is
shown in Figure 51. The following procedure describes the I2C Master/Slave Controller
operating as a slave in 10-bit addressing mode, transmitting data to the bus master.
Slave Address
1st Byte
Slave Address
2nd Byte
Slave Address
1st Byte
S
W = 0 A
A
S
R = 1 A Data
A
Data
A
P
Figure 51. Data Transfer Format—Slave Transmit Transaction with 10-Bit Address
1. The software configures the controller for operation as a slave in 10-bit addressing
mode.
a. Initialize the MODEfield in the I2C Mode Register for either SLAVE ONLY mode
or MASTER/SLAVE mode with 10-bit addressing.
b. Optionally set the GCEbit.
c. Initialize the SLA[7:0]bits in the I2CSLVAD Register and SLA[9:8]in the
I2CMODE Register.
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d. Set IEN= 1, NAK= 0 in the I2C Control Register.
2. The master initiates a transfer, sending the first address byte. The SLAVE mode I2C
controller recognizes the start of a 10-bit address with a match to SLA[9:8]and
detects the R/W bit = 0 (a Write from the master to the slave). The I2C controller
acknowledges, indicating it is available to accept the transaction.
3. The master sends the second address byte. The SLAVE mode I2C controller compares
the second address byte with the value in SLA[7:0]. If there is a match, the SAMbit in
the I2CISTAT Register is set = 1, causing a slave address match interrupt. The RDbit
is set = 0, indicating a write to the slave. If a match occurs, the I2C controller acknowl-
edges on the I2C bus, indicating it is available to accept the data.
4. The software responds to the slave address match interrupt by reading the I2CISTAT
Register, which clears the SAMbit. Because the RDbit = 0, no further action is
required.
5. The master sees the Acknowledge and sends a RESTARTinstruction, followed by the
first address byte with the R/W set to 1. The SLAVE mode I2C controller recognizes
the RESTARTinstruction followed by the first address byte with a match to
SLA[9:8], and detects the R/W = 1 (the master reads from the slave). The slave I2C
controller sets the SAMbit in the I2CISTAT Register, which causes the slave address
match interrupt. The RDbit is set = 1. The SLAVE mode I2C controller acknowledges
on the bus.
6. The software responds to the interrupt by reading the I2CISTAT Register, clearing the
SAMbit. The software loads the initial data byte into the I2CDATA Register and sets
the TXIbit in the I2CCTL Register.
7. The master starts the data transfer by asserting SCL Low. After the I2C controller has
data available to transmit, the SCL is released, and the master proceeds to shift the
first data byte.
8. After the first bit of the first data byte has been transferred, the I2C controller sets the
TDREbit which asserts the transmit data interrupt.
9. The software responds to the transmit data interrupt by loading the next data byte into
the I2CDATA Register.
10. The I2C master shifts in the remainder of the data byte. The master transmits the
Acknowledge (or Not Acknowledge, if this byte is the final data byte).
11. The bus cycles through steps 7 to 10 until the final byte has been transferred. If the
software has not yet loaded the next data byte when the master brings SCL Low to
transfer the most significant data bit, the slave I2C controller holds SCL Low until the
data register is written.
When a Not Acknowledge is received by the slave, the I2C controller sets the NCKIbit
in the I2CISTAT Register, causing the NAK interrupt to be generated.
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12. The software responds to the NAKinterrupt by clearing the TXIbit in the I2CCTL
Register and by asserting the FLUSHbit of the I2CCTL Register.
13. When the master has completed the Acknowledge cycle of the last transfer, it asserts a
STOPor RESTARTcondition on the bus.
14. The slave I2C controller asserts the STOP/RESTARTinterrupt (sets the SPRS bit in the
I2CISTAT Register).
15. The software responds to the STOPinterrupt by reading the I2CISTAT Register and
clearing the SPRSbit.
I2C Control Register Definitions
2
I C Data Register
The I2C Data Register shown in Table 120 contains the data that is to be loaded into the
Shift Register to transmit onto the I2C bus. This register also contains data that is loaded
from the Shift Register after it is received from the I2C bus. The I2C Shift Register is not
accessible in the Register File address space, but is used only to buffer incoming and out-
going data.
Writes by the software to the I2CDATA Register are blocked if a slave Write transaction is
underway (the I2C controller is in SLAVE mode, and data is being received).
2
Table 120. I C Data Register (I2CDATA = F50h)
I
BITS
7
6
5
4
3
2
1
0
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
FIELD
RESET
R/W
0
0
0
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F50H
ADDR
Bit
Position
Value
Description
[7:0] DATA
SPI Data Byte
I2C Interrupt Status Register
The Read-only I2C Interrupt Status Register, shown in Table 121, indicates the cause of
any current I2C interrupt and provides status of the I2C controller. When an interrupt
occurs, one or more of the TDRE, RDRF, SAM, ARBLST, SPRSor NCKIbits is set. The
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GCAand RDbits do not generate an interrupt but rather provide status associated
with the SAMbit interrupt.
Table 121. I2C Interrupt Status Register (I2CSTAT = F51h)
BITS
7
6
5
4
3
2
1
0
TDRE
RDRF
SAM
GCA
RD
ARBLST
SPRS
NCKI
FIELD
RESET
R/W
0
0
0
1
0
1
0
0
R
R
R
R
R
R
R
R
F51H
ADDR
Bit
Position
Value
Description
7
Transmit Data Register Empty
2
2
TDRE
When the I C controller is enabled, this bit is 1 when the I C Data Register is empty. When
2
2
set, this bit causes the I C controller to generate an interrupt, except when the I C
controller is shifting in data during the reception of a byte or when shifting an address and
the RD bit is set. This bit clears by writing to the I2CDATA Register.
6
Receive Data Register Full
This bit is set to 1 when the I C controller is enabled and the I C controller has received a
byte of data. When asserted, this bit causes the I C controller to generate an interrupt. This
2
2
RDRF
2
bit clears by reading the I2CDATA Register.
5
SAM
Slave Address Match
2
This bit is set to 1 if the I C controller is enabled in Slave mode and an address is received
which matches the unique Slave address or General Call Address (if enabled by the GCE
2
bit in the I C Mode Register). In 10-bit addressing mode, this bit is not set until a match is
achieved on both address bytes. When this bit is set, the RD and GCA bits are also valid.
This bit clears by reading the I2CISTAT Register.
4
General Call Address
GCA
This bit is set in Slave mode when the General Call Address or START byte is recognized
(in either 7 or 10 bit Slave mode). The GCE bit in the I C Mode Register must be set to
2
enable recognition of the General Call Address and START byte. This bit clears when IEN
= 0 and is updated following the first address byte of each Slave mode transaction. A
General Call Address is distinguished from a START byte by the value of the RD bit (RD =
0 for General Call Address, 1 for START byte).
3
Read
RD
This bit indicates the direction of transfer of the data. It is set when the Master is reading
data from the Slave. This bit matches the least-significant bit of the address byte after the
START condition occurs (for both MASTER and SLAVE modes). This bit clears when IEN
= 0 and is updated following the first address byte of each transaction.
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Bit
Position
Value
Description
2
Arbitration Lost
2
ARBLST
This bit is set when the I C controller is enabled in MASTER mode and loses arbitration
(outputs a 1 on SDA and receives a 0 on SDA). The ARBLST bit clears when the
I2CISTAT Register is read.
1
Stop/Restart Condition Interrupt
This bit is set when the I C controller is enabled in Slave mode and detects a STOP or
2
SPRS
RESTART condition during a transaction directed to this slave. This bit clears when the
I2CISTAT Register is read. Read the RSTR bit of the I2CSTATE Register to determine
whether the interrupt was caused by a STOP or RESTART condition.
0
Not Acknowledge (NAK) Interrupt
NCKI
In MASTER mode, this bit is set when a Not Acknowledge condition is received or sent and
neither the START nor the STOP bit is active. In MASTER mode, this bit can only be
cleared by setting the START or STOP bits.
In Slave mode, this bit is set when a Not Acknowledge condition is received (master
reading data from slave), indicating the Master is finished reading. A STOP or RESTART
condition follows. In Slave mode this bit clears when the I2CISTAT Register is read.
TDRE—Transmit Data Register Empty
When the I2C controller is enabled, this bit is 1 when the I2C Data Register is empty.
When set, this bit causes the I2C controller to generate an interrupt, except when the I2C
controller is shifting in data during the reception of a byte or when shifting an address and
the RDbit is set. This bit clears by writing to the I2CDATA Register.
RDRF—Receive Data Register Full
This bit is set = 1 when the I2C controller is enabled and the I2C controller has received a
byte of data. When asserted, this bit causes the I2C controller to generate an interrupt. This
bit clears by reading the I2CDATA Register.
SAM—Slave Address Match
This bit is set = 1 if the I2C controller is enabled in SLAVE mode and an address is
received which matches the unique slave address or General Call Address (if enabled by
the GCEbit in the I2C Mode Register). In 10-bit addressing mode, this bit is not set until a
match is achieved on both address bytes. When this bit is set, the RDand GCAbits are also
valid. This bit clears by reading the I2CISTAT Register.
GCA—General Call Address
This bit is set in SLAVE mode when the General Call Address or START byte is recog-
nized (in either 7 or 10 bit SLAVE mode). The GCEbit in the I2C Mode Register must be
set to enable recognition of the General Call Address and START byte. This bit clears
when IEN= 0 and is updated following the first address byte of each SLAVE mode trans-
action. A General Call Address is distinguised from a START byte by the value of the RD
bit (RD = 0 for General Call Address, 1 for START byte).
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RD—Read
This bit indicates the direction of transfer of the data. It is set when the master is reading
data from the slave. This bit matches the least-significant bit of the address byte after the
STARTcondition occurs (for both MASTER and SLAVE modes). This bit clears when
IEN = 0 and is updated following the first address byte of each transaction.
ARBLST—Arbitration Lost
This bit is set when the I2C controller is enabled in MASTER mode and loses arbitration
(outputs a 1 on SDA and receives a 0 on SDA). The ARBLST bit clears when the
I2CISTAT Register is read.
SPRS—Stop/RESTARTcondition Interrupt
This bit is set when the I2C controller is enabled in SLAVE mode and detects a STOPor
RESTARTcondition during a transaction directed to this slave. This bit clears when the
I2CISTAT Register is read. Read the RSTRbit of the I2CSTATE Register to determine
whether the interrupt was caused by a STOPor RESTARTcondition.
NCKI—NAK Interrupt
In MASTER mode, this bit is set when a Not Acknowledge condition is received or sent
and neither the STARTnor the STOPbit is active. In MASTER mode, this bit can only be
cleared by setting the STARTor STOPbits.
In SLAVE mode, this bit is set when a Not Acknowledge condition is received (master
reading data from slave), indicating the master is finished reading. A STOPor RESTART
condition follows. In SLAVE mode this bit clears when the I2CISTAT Register is read.
I2C Control Register
The I2C Control Register, shown in Table 122, enables and configures I2C operation.
2
Table 122. I C Control Register (I2CTL = 52h)
BITS
7
6
5
4
3
2
1
0
IEN
START
STOP
BIRQ
TXI
NAK
FLUSH
FILTEN
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F52H
ADDR
Bit
Position
Value
Description
2
7
I C Enable
IEN
2
0
1
I C controller is disabled.
2
I C controller is enabled.
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242
Bit
Position
Value
Description
6
Send Start Condition
START
0
1
[Requires input.]
2
The I C controller (when configured as the Master) sends a Start condition.
5
Send Stop Condition
STOP
0
1
[Requires input.]
2
The I C controller (when configured as the Master) sends a STOP condition.
4
Baud Rate Generator Interrupt Request
BIRQ
0
1
[Requires input.]
[Requires input.]
3
Enable TDRE Interrupts
TXI
0
1
Interrupts are disabled.
Interrupts are enabled.
2
Send Not Acknowledge
NAK
0
[Requires input.]
1
Sends a Not Acknowledge condition.
1
Flush Data
FLUSH
0
[Requires input.]
2
1
Clears the I C Data Register and sets the TDRE bit to 1.
2
0
I C Signal Filter Enable
FILTEN
0
1
Disables low-pass digital filters on the SDA and SCL input signals.
Enables low-pass digital filters on the SDA and SCL input signals.
2
I C Enable (IEN). This bit enables the I2C controller.
Send Start Condition (START). When set, this bit causes the I2C controller (when con-
figured as the Master) to send the START condition. After asserted, it is cleared by the I2C
controller after it sends the START condition or by removing the IEN bit. If this bit is 1, it
cannot be cleared by writing to the bit. After this bit is set, the START condition is sent if
there is data in the I2CDATA or I2CSHIFT Register. If there is no data in one of these reg-
isters, the I2C controller waits until data is loaded. If this bit is set while the I2C controller
is shifting out data, it generates a RESTART condition after the byte shifts and the
acknowledge phase completes. If the STOP bit is also set, it also waits until the STOP con-
dition is sent before the START condition.
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If START is set while a slave mode transaction is underway to this device, the START bit
will be cleared and ARBLST bit in the Interrupt Status Register will be set.
Send Stop Condition (STOP). When set, this bit causes the I2C controller (when config-
ured as the Master) to send the STOP condition after the byte in the I2C Shift Register has
completed transmission or after a byte has been received in a receive operation. When set,
this bit is reset by the I2C controller after a STOP condition has been sent or by removing
the IEN bit. If this bit is 1, it cannot be cleared to 0 by writing to the register.
If STOP is set while a slave mode transaction is underway, the STOP bit will be cleared by
hardware.
Baud Rate Generator Interrupt Request (BIRQ). This bit is ignored when the I2C con-
troller is enabled. If this bit is set to 1 when the I2C controller is disabled (IEN = 0) the
baud rate generator is used as an additional timer, causing an interrupt to occur every time
the baud rate generator counts down to 1. The baud rate generator runs continuously in
this mode, generating periodic interrupts.
Enable TDRE Interrupts (TXI). This bit enables interrupts when the I2C Data Register is
empty.
Send Not Acknowledge (NAK). Setting this bit sends a Not Acknowledge condition after
the next byte of data has been received. It is automatically deasserted after the Not
Acknowledge is sent or the IEN bit is cleared. If this bit is 1, it cannot be cleared to 0 by
writing to the register.
Flush Data (FLUSH). Setting this bit clears the I2C Data Register and sets the TDRE bit
to 1. This bit allows flushing of the I2C Data Register when an NAK condition is received
after the next data byte has been written to the I2C Data Register. Reading this bit always
returns 0.
2
I C Signal Filter Enable (FILTEN). Setting this bit enables low-pass digital filters on the
SDA and SCL input signals. This function provides the spike suppression filter required in
I2C Fast Mode. These filters reject any input pulse with periods less than a full system
clock cycle. The filters introduce a 3-system clock cycle latency on the inputs.
2
Table 123. I C Control Register (I2CCTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
IEN
START
STOP
BIRQ
TXI
NAK
FLUSH
FILTEN
0
0
0
0
0
0
0
0
R/W
R/W1
R/W1
R/W
R/W
R/W1
W
R/W
F52H
ADDR
The R/W1 bit may be set (written to 1), but not cleared.
Note:
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IEN—I2C Enable
This bit enables the I2C controller.
START—Send STARTcondition
When set, this bit causes the I2C controller (when configured as the master) to send a
STARTcondition. After it is asserted, this bit is cleared by the I2C controller after it sends
the STARTcondition or by deasserting the IENbit. If this bit is 1, it cannot be cleared by
writing to the bit. After this bit is set, a STARTcondition is sent if there is data in the
I2CDATA or I2CSHIFT Register. If there is no data in one of these registers, the I2C con-
troller waits until data is loaded. If this bit is set while the I2C controller is shifting out
data, it generates a RESTARTcondition after the byte shifts and the Acknowledge phase
completes. If the STOPbit is also set, it also waits until the STOPcondition is sent before
the STARTcondition.
If START is set while a slave mode transaction is underway to this device, the START bit
will be cleared and ARBLST bit in the Interrupt Status Register will be set.
STOP—Send STOPcondition
When set, this bit causes the I2C controller (when configured as the master) to send the
STOPcondition after the byte in the I2C Shift Register has completed transmission or after
a byte has been received in a receive operation. When set, this bit is reset by the I2C con-
troller after a STOPcondition has been sent or by deasserting the IENbit. If this bit is 1, it
cannot be cleared to 0 by writing to the register.
If STOP is set while a slave mode transaction is underway, the STOP bit will be cleared by
hardware.
BIRQ—Baud Rate Generator Interrupt Request
This bit is ignored when the I2C controller is enabled. If this bit is set = 1 when the I2C
controller is disabled (IEN= 0) the baud rate generator is used as an additional timer caus-
ing an interrupt to occur every time the baud rate generator counts down to one. The baud
rate generator runs continuously in this mode, generating periodic interrupts.
TXI—Enable TDRE interrupts
This bit enables interrupts when the I2C Data Register is empty.
NAK—Send NAK
Setting this bit sends a Not Acknowledge condition after the next byte of data has been
received. It is automatically deasserted after the Not Acknowledge is sent or the IENbit is
cleared. If this bit is 1, it cannot be cleared to 0 by writing to the register.
FLUSH—Flush Data
Setting this bit clears the I2C Data Register and sets the TDREbit to 1. This bit allows
flushing of the I2C Data Register when an NAK condition is received after the next data
byte has been written to the I2C Data Register. Reading this bit always returns 0.
FILTEN—I2C Signal Filter Enable
Setting this bit enables low-pass digital filters on the SDA and SCL input signals. This
function provides the spike suppression filter required in I2C Fast Mode. These filters
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reject any input pulse with periods less than a full system clock cycle. The filters introduce
a 3-system clock cycle latency on the inputs.
I2C Baud Rate High and Low Byte Registers
The I2C Baud Rate High and Low Byte registers (Table 124 and Table 125) combine to
form a 16-bit reload value, BRG[15:0], for the I2C Baud Rate Generator. The I2C baud rate
is calculated using the following equation.
If BRG= 0000h, use 10000hin the equation):
Note:
System Clock Frequency (Hz)
2
I C Baud Rate (bits/s)
=
4 x BRG[15:0]
2
Table 124. I C Baud Rate High Byte Register (I2CBRH = 53h)
BITS
7
6
5
4
3
2
1
0
BRH
FIELD
RESET
R/W
FFh
R/W
FFh
R/W
FFh
R/W
FFh
R/W
FFh
R/W
FFh
R/W
FFh
R/W
FFh
R/W
F53H
ADDR
Bit
Position
Value
Description
2
[7:0]
BRH
I C Baud Rate High Byte
2
The most significant byte, BRG[15:8], of the I C Baud Rate Generator’s reload value.
If the DIAGbit in the I2C Mode Register is set to 1, a read of the I2CBRH Register returns
Note:
the current value of the I2C Baud Rate Counter[15:8].
2
Table 125. I C Baud Rate Low Byte Register (I2CBRL = F54h)
BITS
7
6
5
4
3
2
1
0
BRL
FIELD
RESET
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
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R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F54H
ADDR
Bit
Position
Value
Description
2
[7:0]
BRL
I C Baud Rate Low Byte
2
The least significant byte, BRG[7:0], of the I C Baud Rate Generator’s reload value.
If the DIAGbit in the I2C Mode Register is set to 1, a read of the I2CBRL Register returns
Note:
the current value of the I2C Baud Rate Counter[7:0].
I2C State Register
The read-only I2C State Register provides information about the state of the I2C bus and
the I2C bus controller.
When the DIAGbit of the I2C Mode Register is cleared, this register provides information
on the internal state of the I2C controller and I2C bus, as shown in Table 126.
When the DIAGbit of the I2C Mode Register is set, this register returns the value of the
I2C controller state machine as shown in Table 126.
Table 126. I2C State Register (I2CSTATE = F55h)—Description when DIAG = 0
BITS
7
6
5
4
3
2
1
0
ACKV
ACK
AS
DS
10B
RSTR
SCLOUT
BUSY
FIELD
RESET
R/W
0
0
0
0
0
0
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F55H
ADDR
Bit
Position
Value
Description
7
ACK Valid
ACKV
0
1
[Requires input.]
[Requires input.]
6
Acknowledge
ACK
0
1
[Requires input.]
[Requires input.]
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Bit
Position
Value
Description
5
Address State
AS
0
[Requires input.]
1
[Requires input.]
4
Data State
DS
0
[Requires input.]
[Requires input.]
1
3
10B
10B
0
[Requires input.]
[Requires input.]
1
2
RESTART
RSTR
0
1
Stop condition.
Restart condition.
1
Serial Clock Output
SCLOUT
0
1
[Requires input.]
[Requires input.]
2
0
I C Bus Busy
BUSY
2
0
1
No activity on the I C Bus.
A transaction is underway on the I C bus.
2
ACK Valid (ACKV). This bit is set if sending data (master or slave) and the ACK bit in this
register is valid for the byte just transmitted. This bit can be monitored if it is appropriate
for software to verify the ACK value before writing the next byte to be sent. To operate in
this mode, the data register must not be written when TDRE asserts; instead, software
waits for ACKV to assert. This bit clears when transmission of the next byte begins or the
transaction is ended by a STOP or RESTART condition.
Acknowledge (ACK). This bit indicates the status of the Acknowledge for the last byte
transmitted or received. This bit is set for an Acknowledge and cleared for a Not
Acknowledge condition.
Address State (AS). This bit is active High while the address is being transferred on the
I2C bus.
Data State (DS). This bit is active High while the data is being transferred on the I2C bus.
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10B. This bit indicates whether a 10 or 7-bit address is being transmitted when operating
as a master. After the START bit is set, if the five most-significant bits of the address are
11110b, this bit is set. When set, it is reset after the address has been sent.
RESTART (RSTR). This bit is updated each time a STOP or RESTART interrupt occurs
(SPRS bit set in I2CISTAT Register).
Serial Clock Output (SCLOUT). Current value of Serial Clock being output onto the bus.
The actual values of the SCL and SDA signals on the I2C bus can be observed via the
GPIO Input Register.
2
I C Bus Busy (BUSY). See the bit description in Table 127.
ACK Valid (ACKV). This bit is set if sending data (master or slave) and the ACK bit in this
register is valid for the byte just transmitted. This bit can be monitored if it is appropriate
for software to verify the ACK value before writing the next byte to be sent. To operate in
this mode, the data register must not be written when TDRE asserts; instead, software
waits for ACKV to assert. This bit clears when transmission of the next byte begins or the
transaction is ended by a STOP or RESTART condition.
Acknowledge (ACK). This bit indicates the status of the Acknowledge for the last byte
transmitted or received. This bit is set for an Acknowledge and cleared for a Not
Acknowledge condition.
Address State (AS). This bit is active High while the address is being transferred on the
I2C bus.
Data State (DS). This bit is active High while the data is being transferred on the I2C bus.
10B. This bit indicates whether a 10 or 7-bit address is being transmitted when operating
as a master. After the START bit is set, if the five most-significant bits of the address are
11110b, this bit is set. When set, it is reset after the address has been sent.
RESTART (RSTR). This bit is updated each time a STOP or RESTART interrupt occurs
(SPRS bit set in I2CISTAT Register).
Serial Clock Output (SCLOUT). Current value of Serial Clock being output onto the bus.
The actual values of the SCL and SDA signals on the I2C bus can be observed via the
GPIO Input Register.
2
I C Bus Busy (BUSY). See the bit description in Table 127.
Table 127. I2C State Register((I2CSTATE = F55h)—Description when DIAG = 1
BITS
7
6
5
4
3
2
1
0
I2CSTATE _H
I2CSTATE _L
FIELD
RESET
0
0
0
0
0
0
0
0
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R
R
R
R
R
R
R
R
R/W
F55H
ADDR
Bit
Position
Value
Description
2
[7:4]
0000
I C State High Byte
2
I2CSTATE_H
This field defines the current state of the I C controller. It is the most
significant nibble of the internal state machine. Table 130 defines the
states for this field.
2
[3:0]
0000
I C State Low Byte
2
I2CSTATE_L
Least significant nibble of the I C state machine. This field defines the
substates for the states defined by I2CSTATE_H. Table 131 defines the
values for this field.
2
Table 128. I C State Register (I2CSTATE)—Description when DIAG = 0
BITS
7
6
5
4
3
2
1
0
ACKV
ACK
AS
DS
10B
RSTR
SCLOUT
BUSY
FIELD
RESET
R/W
0
0
0
0
0
0
X
R
X
R
R
R
R
R
R
R
F55H
ADDR
ACKV—ACK Valid
This bit is set if sending data (master or slave) and the ACKbit in this register is valid for
the byte just transmitted. This bit can be monitored if it is appropriate for software to ver-
ify the ACKvalue before writing the next byte to be sent. To operate in this mode, the data
register must not be written when TDREasserts; instead, the software waits for ACKVto
assert. This bit clears when transmission of the next byte begins or the transaction is ended
by a STOPor RESTARTcondition.
ACK—Acknowledge
This bit indicates the status of the Acknowledge for the last byte transmitted or received.
This bit is set for an Acknowledge and cleared for a Not Acknowledge condition.
AS—Address State
This bit is active High while the address is being transferred on the I2C bus.
DS—Data State
This bit is active high while the data is being transferred on the I2C bus.
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10B—This bit indicates whether a 10 or 7-bit address is being transmitted when operating
as a master. After the STARTbit is set, if the five most-significant bits of the address are
11110B, this bit is set. When set, it is reset once the address has been sent.
RSTR—RESTART
This bit is updated each time a STOPor RESTARTinterrupt occurs (SPRSbit set in
I2CISTAT Register).
0 = STOPcondition
1 = RESTARTcondition
SCLOUT—Serial Clock Output
Current value of Serial Clock being output onto the bus. The actual values of the SCL and
SDA signals on the I2C bus can be observed via the GPIO Input Register.
BUSY—I2C Bus Busy
0 = No activity on the I2C Bus.
1 = A transaction is underway on the I2C bus.
2
Table 129. I C State Register (I2CSTATE)—Description when DIAG = 1
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
I2CSTATE_H
I2CSTATE_L
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
F55H
ADDR
I2CSTATE_H—I2C State
This field defines the current state of the I2C controller. It is the most significant nibble of
the internal state machine. Table 130 defines the states for this field.
I2CSTATE_L—Least significant nibble of the I2C state machine. This field defines the
substates for the states defined by I2CSTATE_H. Table 131 defines the values for this
field.
Table 130. I2CSTATE_H
State
Encoding
State Name
Idle
State Description
2
2
0000
0001
0010
0011
I C bus is idle or I C controller is disabled.
2
Slave Start
Slave Bystander
Slave Wait
I C controller has received a START condition.
Address did not match; ignore remainder of transaction.
Waiting for STOP or RESTART condition after sending a Not
Acknowledge instruction.
0100
Master Stop2
Master completing STOP condition (SCL = 1, SDA = 1).
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Table 130. I2CSTATE_H (Continued)
State
Encoding
State Name
State Description
0101
0110
0111
Master Start/Restart
Master Stop1
Master Wait
MASTER mode sending START condition (SCL = 1, SDA = 0).
Master initiating STOP condition (SCL = 1, SDA = 0).
Master received a Not Acknowledge instruction, waiting for
software to assert STOP or START control bits.
1000
1001
1010
Slave Transmit Data
Slave Receive Data
9 substates, one for each data bit and one for the Acknowledge.
9 substates, one for each data bit and one for the Acknowledge.
Slave Receive Addr1 Slave receiving first address byte (7- and 10-bit addressing)
9 substates, one for each address bit and one for the
Acknowledge.
1011
Slave Receive Addr2 Slave Receiving second address byte (10-bit addressing)
9 substates, one for each address bit and one for the
Acknowledge.
1100
1101
1110
Master Transmit Data 9 substates, one for each data bit and one for the Acknowledge.
Master Receive Data 9 substates, one for each data bit and one for the Acknowledge.
Master Transmit Addr1 Master sending first address byte (7- and 10-bit addressing)
9 substates, one for each address bit and one for the
Acknowledge.
1111
Master Transmit Addr2 Master sending second address byte (10-bit addressing)
9 substates, one for each address bit and one for the
Acknowledge.
Table 131. I2CSTATE_L
Substate
State
I2CSTATE_H I2CSTATE_L Substate Name
State Description
0000–0100
0110–0111
0101
0000
—
There are no substates for these I2CSTATE_H
values.
0000
—
There are no substates for these I2CSTATE_H
values.
0000
0001
Master Start
Initiating a new transaction
Master Restart
Master is ending one transaction and starting a
new one without letting the bus go idle.
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Table 131. I2CSTATE_L (Continued)
State
Substate
I2CSTATE_H I2CSTATE_L Substate Name
State Description
1000–1111
0111
0110
0101
0100
0011
0010
0001
0000
1000
send/receive bit 7
send/receive bit 6
send/receive bit 5
send/receive bit 4
send/receive bit 3
send/receive bit 2
send/receive bit 1
send/receive bit 0
Sending/Receiving most significant bit
Sending/Receiving least significant bit
Sending/Receiving Acknowledge
send/receive
Acknowledge
I2C Mode Register
The I2C Mode Register, Table 132, provides control over master versus slave operating
mode, slave address and diagnostic modes.
2
Table 132. I C Mode Register (I2C Mode = F56h)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
Reserved
MODE[1:0]
IRM
GCE
SLA[9:8]
0
DIAG
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
F56H
ADDR
2
I C Controller Operational Mode Selection (MODE). See the bit description in Table 132.
Interactive Receive Mode (IRM). Valid in Slave mode when software needs to interpret
each received byte before acknowledging. This bit is useful for processing the data bytes
following a General Call Address or if software wants to disable hardware address recog-
nition.
General Call Address Enable (GCE). Enables reception of messages beginning with the
General Call Address or START byte.
Slave Address Bits 9 and 8 (SLA[9:8]). Initialize with the appropriate slave address
value when using 10-bit slave addressing. These bits are ignored when using 7-bit slave
addressing.
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Diagnostic Mode (DIAG). Selects Read value of the Baud Rate Reload and State Registers.
MODE—Selects the I2C controller operational mode
00 = MASTER/SLAVE capable (supports multi-master arbitration) with 7-bit slave
address
01 = MASTER/SLAVE capable (supports multi-master arbitration) with 10-bit slave
address
10 = SLAVE ONLY capable with 7-bit address
11 = SLAVE ONLY capable with 10-bit address
IRM—Interactive Receive Mode
Valid in SLAVE mode when software needs to interpret each received byte before
acknowledging. This bit is useful for processing the data bytes following a General Call
Address or if software wants to disable hardware address recognition.
0 = Acknowledge occurs automatically and is determined by the value of the NAKbit of
the I2CCTL Register.
1 = A receive interrupt is generated for each byte received (address or data). The SCL is
held Low during the Acknowledge cycle until software writes to the I2CCTL Register.
The value written to the NAKbit of the I2CCTL Register is output on SDA. This value
allows software to Acknowledge or Not Acknowledge after interpreting the associated
address/data byte.
GCE—General Call Address Enable
Enables reception of messages beginning with the General Call Address or START byte.
0 = Do not accept a message with the General Call Address or START byte.
1 = Do accept a message with the General Call Address or START byte. When an address
match occurs, the GCA and RD bits in the I2C Status Register indicates whether the
address matched the General Call Address/START byte or not. Following the General Call
Address byte, the software may set the IRMbit that allows software to examine the follow-
ing data byte(s) before acknowledging.
SLA[9:8]— Slave Address Bits 9 and 8.
Initialize with the appropriate slave address value when using 10-bit slave addressing.
These bits are ignored when using 7-bit slave addressing.
DIAG—Diagnostic Mode
Selects read back value of the Baud Rate Reload and State registers.
0 = Reading the Baud Rate registers returns the Baud Rate register values. Reading the
State register returns I2C controller state information
1 = Reading the Baud Rate registers returns the current value of the baud rate counter.
Reading the State register returns additional state information.
2
I C Slave Address Register
The I2C Slave Address Register, shown in Table 133, provides control over the lower
order address bits used in 7 and 10 bit slave address recognition.
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Product Specification
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Table 133. I2C Slave Address Register (I2CSLVAD = 57h)
BITS
7
6
5
4
3
2
1
0
I2C Slave Address
FIELD
RESET
R/W
0
0
0
1
0
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F57H
ADDR
Bit
Position
Value
00h
Description
Slave Address Bits 7:0
[7:0]
SLA[7:0]
Initialize with the appropriate Slave address value. When using 7 bit Slave
addressing, SLA[9:7] are ignored.
2
Table 134. I C Slave Address Register (I2CSLVAD)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
SLA[7:0]
00h
R/W
F57H
ADDR
SLA[7:0]—slave address bits 7–0. Initialize with the appropriate slave address value. When using 7 bit
slave addressing, SLA[9:7] are ignored.
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Comparator
Overview
The Z8 Encore! XP® F1680 Series devices feature two same general purpose comparators
that compares two analog input signals. For each comparator, a GPIO (C0INP/C1INP) pin
provides the positive comparator input, the negative input (C0INN/C1INN) may be taken
from either an external GPIO pin or an internal reference. The output of each comparator
is available as an interrupt source or can be routed to an external pin using the GPIO mul-
tiplex. Features for each comparator include:
•
•
•
•
•
•
2 inputs which can be connected up using the GPIO multiplex (MUX)
1 input can be connected to a programmable internal reference
1 input can be connected to the on-chip temperature sensor
Output can enable/disable Timer operation
Output can be either an interrupt source or an output to an external pin
Operation in Stop Mode
Operation
One of the comparator inputs may be connected to an internal reference which is a user
selectable reference that is user programmable with 200 mV resolution.
The comparator may be powered down to save on supply current or continue to operate in
Stop Mode. See the Power Control Register 0 on page 43 for details. In Stop Mode, the
comparator interrupt (if enabled) automatically initiates a Stop Mode Recovery and gener-
ates an interrupt request. In the Reset Status Register, the Stop bit is set to 1. Also, the
Comparator request bit in Interrupt Request 1 Register is set. Following completion of
the Stop Mode Recovery, if interrupts are enabled, the CPU responds to the interrupt
request by fetching the comparator interrupt vector.
Because of the propagation delay of the comparator, it is not recommended to enable the
comparator without first disabling interrupts and waiting for the comparator output to
settle. Doing so can result in spurious interrupts after comparator enabling. The follow-
ing example shows how to safely enable the comparator:
Caution:
di
ld cmp0
nop
nop
; wait for output to settle
clr irq0 ; clear any spurious interrupts pending
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ei
Comparator Control Register Definitions
Comparator 0 Control Register
The Comparator 0 Control Register (CMP0CTL) Table 134 configures the comparator 0
inputs and sets the value of the internal voltage reference.
Table 134. Comparator 0 Control Register (CMP0CTL)
BITS
7
6
5
4
3
2
1
0
INPSEL
INNSEL
REFLVL
TIMTRG
FIELD
RESET
R/W
0
0
0
1
0
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F90H
ADDR
INPSEL—Signal Select for Positive Input
0 = GPIO pin used as positive comparator 0 input
1 = temperature sensor used as positive comparator 0 input
INNSEL—Signal Select for Negative Input
0 = internal reference disabled, GPIO pin used as negative comparator 0 input
1 = internal reference enabled as negative comparator 0 input
REFLVL—Comparator 0 Internal Reference Voltage Level (note that this reference is
independent of the ADC voltage reference)
0000 = 0.0 V
0001 = 0.2 V
0010 = 0.4 V
0011 = 0.6 V
0100 = 0.8 V
0101 = 1.0 V (Default)
0110 = 1.2 V
0111 = 1.4 V
1000 = 1.6 V
1001 = 1.8 V
1010–1111 = Reserved
TIMTRG—Timer Trigger to Toggle (enable/disable) timer operation
00 = Disable Timer Trigger
01 = Comparator 0 output works as Timer 0 Trigger
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10 = Comparator 0 output works as Timer 1 Trigger
11 = Comparator 0 output works as Timer 2 Trigger
Comparator 1 Control Register
The Comparator 1 Control Register (CMP1CTL) Table 135 configures the comparator 1
inputs and sets the value of the internal voltage reference.
Table 135. Comparator 1 Control Register (CMP1CTL)
BITS
7
6
5
4
3
2
1
0
INPSEL
INNSEL
REFLVL
TIMTRG
FIELD
RESET
R/W
0
0
0
1
0
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F90H
ADDR
INPSEL—Signal Select for Positive Input
0 = GPIO pin used as positive comparator 1 input
1 = temperature sensor used as positive comparator 1 input
INNSEL—Signal Select for Negative Input
0 = internal reference disabled, GPIO pin used as negative comparator 1 input
1 = internal reference enabled as negative comparator 1 input
REFLVL—Comparator 1 Internal Reference Voltage Level (note that this reference is
independent of the ADC voltage reference)
0000 = 0.0 V
0001 = 0.2 V
0010 = 0.4 V
0011 = 0.6 V
0100 = 0.8 V
0101 = 1.0 V (Default)
0110 = 1.2 V
0111 = 1.4 V
1000 = 1.6 V
1001 = 1.8 V
1010–1111 = Reserved
TIMTRG—Timer Trigger to Toggle (enable/disable) timer operation
00 = Disable Timer Trigger
01 = Comparator 1 output works as Timer 0 Trigger
10 = Comparator 1 output works as Timer 1 Trigger
11 = Comparator 1 output works as Timer 2 Trigger
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Temperature Sensor
Overview
The on-chip Temperature Sensor allows the user the ability to measure temperature on the
die to an accuracy of roughly ±7°C over a range of -40 to +105°C. Over a reduced range,
the accuracy is significantly better. This block is a moderately accurate temperature sensor
for low power applications where high accuracy is not required. Uncalibrated accuracy is
significantly worse, therefore the temperature sensor is not recommended for untrimmed
use.
•
•
•
•
On-chip temperature sensor
±7°C full-range accuracy for calibrated version
±1.5°C accuracy over the range of 20°C to 30°C
Flash recalibration capability
Operation
The on-chip temperature sensor is a PTAT (proportional to absolute temperature) topol-
ogy which has provision for zero-point calibration. A pair of Flash option bytes contain
the calibration data. The temperature sensor can be disabled by a bit in the “Power Control
Register 0” on page 43 to reduce power consumption.
The temperature sensor can be directly read by the ADC to determine the absolute value of
its output. The temperature sensor output is also available as an input to the comparator for
threshold type measurement determination. The accuracy of the sensor when used with the
comparator is substantially less than when measured by the ADC.
If the temperature sensor is routed to the ADC, the ADC must be configured in unity-gain
buffered mode. The value read back from the ADC is a signed number, although it is
always positive.
Maximum accuracy can be obtained by customer re-trimming the sensor using an external
reference and using a high-precision external reference in the target application.
During normal operation, the die undergoes heating that will cause a mismatch between
the ambient temperature and that measured by the sensor. For best results, the XP device
should be placed into STOP mode for sufficient time such that the die and ambient tem-
peratures converge (this time will be dependent on the thermal design of the system). The
temperature sensor measurement should then be made immediately after recovery from
STOP mode.
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The following equation defines the transfer function between the temperature sensor out-
put voltage and the die temperature:
T = 100*V - 77 (where T is the temperature in C; V is the sensor output in Volts)
Assuming a compensated ADC measurement, the following equation defines the relation-
ship between the ADC reading and the die temperature:
T = (25/128)*ADC - 77 (where T is the temperature in C; ADC is the 10 bit compensated
ADC value)
Calibration
The temperature sensor undergoes calibration during the manufacturing process and is
maximally accurate only at 30°C. Accuracy decreases as measured temperatures move
further from the calibration point.
Because this sensor is an on-chip sensor it is recommended that the user account for the
difference between ambient and die temperature when inferring ambient temperature con-
ditions.
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Flash Memory
Overview
The products in the Z8 Encore! XP® F1680 Series features either 24KB (24576), 16KB
(16384), 8KB (8192) or 4KB (4096) of non-volatile Flash memory with read/write/erase
capability. The Flash Memory can be programmed and erased in-circuit by either user
code or through the On-Chip Debugger.
The Flash memory array is arranged in pages with 512 bytes per page. The 512-byte page
is the minimum Flash block size that can be erased. Each page is divided into 8 rows of 64
bytes.
For program/data protection, the Flash memory is also divided into sectors. In the Z8
Encore! XP® F1680 Series, the flash memory is divided into 8 sectors which can be pro-
tected from programming and erase operation on a per sector basis.
The first 2 bytes of the Flash Program memory are used as Flash Option Bits. Refer to the
chapter “Flash Option Bits” on page 271 for more information about their operation.
Table 136 describes the Flash memory configuration for each device in the Z8 Encore!
XP® F1680 Series. Figure 52 illustrates the Flash memory arrangement.
®
Table 136. Z8 Encore! XP F1680 Series Flash Memory Configurations
Flash Size
KB (Bytes)
Flash
Pages
Program Memory
Addresses
Flash Sector
Size (bytes)
Number of
Sectors
Pages per
Sector
Part Number
Z8F248x
Z8F168x
Z8F088x
Z8F048x
24 (24576)
16 (16384)
8 (8192)
48
32
16
8
0000A–5FFFH
0000H–3FFFH
0000H–1FFFH
0000H–0FFFH
3072
2048
1024
512
8
8
8
8
6
4
2
1
4 (4096)
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24KB Flash
Program Memory
Addresses
5FFFH
3E00H
3DFFH
3C00H
3BFFH
3A00H
48 Pages
512 Bytes each
05FFH
0400H
03FFH
Sector 1
Sector 0
0200H
01FFH
0000H
Figure 52.Flash Memory Arrangement
Flash Information Area
The Flash information area is separate from program memory and is mapped to the
address range FE00Hto FFFFH. Not all of these addresses are user accessible. Factory trim
values for the analog peripherals are stored here. Factory calibration data for the ADC is
also stored here.
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Operation
The Flash Controller programs and erases flash memory. The Flash Controller provides
the proper flash controls and timing for byte programming, Page Erase, and Mass Erase of
flash memory.
The Flash Controller contains several protection mechanisms to prevent accidental pro-
gramming or erasure. These mechanism operate on the page, sector and full-memory lev-
els.
The Flow Chart in Figure 53 illustrates basic Flash Controller operation. The following
subsections provide details about the various operations (Lock, Unlock, Byte Program-
ming, Page Protect, Page Unprotect, Page Select Page Erase, and Mass Erase) listed in
Figure 53.
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Reset
Lock State 0
Write Page
Select Register
Write FCTL
No
73H
Yes
Lock State 1
Write FCTL
Writes to Page Select
Register in Lock State 1
result in a return to
Lock State 0
No
8CH
Yes
Write Page
Select Register
No
Page Select
values match?
Yes
Yes
Page in
Protected Sector?
Byte Program
Write FCTL
No
Page
Yes
Unlocked
95H
No
Page Erase
Program/Erase
Enabled
Figure 53.Flash Controller Operation Flow Chart
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Flash Operation Timing Using the Flash Frequency Registers
Before performing either a program or erase operation on Flash memory, the user must
first configure the Flash Frequency High and Low Byte registers. The Flash Frequency
registers allow programming and erasing of the flash with system clock frequencies rang-
ing from 32KHz (32768Hz) through 20MHz.
The Flash Frequency High and Low Byte registers combine to form a 16-bit value,
FFREQ, to control timing for flash program and erase operations. The 16-bit binary Flash
Frequency value must contain the system clock frequency (in KHz). This value is calcu-
lated using the following equation:
.
System Clock Frequency (Hz)
FFREQ[15:0] = ---------------------------------------------------------------------------
1000
Flash programming and erasure are not supported for system clock frequencies below
32KHz (32768Hz) or above 20MHz. The Flash Frequency High and Low Byte registers
must be loaded with the correct value to ensure operation of the Z8 Encore! XP® F1680
Series devices.
Caution:
Flash Code Protection Against External Access
The user code contained within the Flash memory can be protected against external access
with the On-Chip Debugger. Programming the FRPFlash Option Bit prevents reading of
the user code with the On-Chip Debugger. Refer to the chapter “Flash Option Bits” on page 271
and the chapter “On-Chip Debugger” on page 280 for more information.
Flash Code Protection Against Accidental Program and Erasure
The Z8 Encore! XP® F1680 Series provides several levels of protection against accidental
program and erasure of the flash memory contents. This protection is provided by a com-
bination of the Flash Option bits, the register locking mechanism, the page select redun-
dancy and the sector level protection control of the Flash Controller.
Flash Code Protection Using the Flash Option Bits
The FHSWPand FWPFlash Option Bits combine to provide three levels of Flash Program
Memory protection as listed in Table 137. Refer to the chapter “Flash Option Bits” on page 271
for more information.
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.
Table 137. Flash Code Protection Using the Flash Option Bits
FHSWP
FWP
Flash Code Protection Description
0
0
Programming and erasing disabled for all of Flash Program
Memory. In user code programming, Page Erase, and Mass Erase
are all disabled. Mass Erase is available through the On-Chip
Debugger.
0 or 1
1
Programming, Page Erase, and Mass Erase are enabled for all of
Flash Program Memory.
Flash Code Protection Using the Flash Controller
At Reset, the Flash Controller locks to prevent accidental program or erasure of the Flash
memory. To program or erase the flash memory, first write the Page Select Register with
the target page. Unlock the Flash Controller by making two consecutive writes to the
Flash Control register with the values 73Hand 8CH, sequentially. The Page Select Register
must be rewritten with the same page previously stored there. If the two Page Select writes
do not match, the controller reverts to a locked state. If the two writes match, the selected
page becomes active. See Figure 53 for details.
After unlocking a specific page, the user can enable either Page Program or Erase. Writing
the value 95Hcauses a Page Erase only if the active page resides in a sector that is not pro-
tected. Any other value written to the Flash Control register locks the Flash Controller.
Mass Erase is not allowed in the user code but only in through the Debug Port.
After unlocking a specific page, the user can also write to any byte on that page. After a
byte is written, the page remains unlocked, allowing for subsequent writes to other bytes
on the same page. Further writes to the Flash Control Register cause the active page to
revert to a locked state.
Sector Based Flash Protection
The final protection mechanism is implemented on a per-sector basis. The Flash memories
of Z8 Encore!® devices are divided into maximum number of 8 sectors. A sector is 1/8 of
the total size of the Flash memory, unless this value is smaller than the page size, in which
case the sector and page sizes are equal. On the Z8 Encore! XP® F1680 Series devices, the
sector size is 3KB, 2KB, 1KB or 512 bytes depending on available on-chip flash size of
24KB, 16KB, 8KB or 4KB.
The Sector Protect Register controls the protection state of each Flash sector. This register
is shared with the Page Select Register. This is accessed by unlocking the Flash controller
and writing the command byte 5EH. The next write to the Page Select Register targets the
Sector Protect Register.
The Sector Protect Register is initialized to 0 on reset, putting each sector into an unpro-
tected state. When a bit in the Sector Protect Register is written to 1, the corresponding
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sector can no longer be written or erased. After a bit of the Sector Protect Register has
been set, it can not be cleared except by powering down the device.
Byte Programming
The Flash Memory is enabled for byte programming after unlocking the Flash Controller
and successfully enabling either Mass Erase or Page Erase. When the Flash Controller is
unlocked and Mass Erase is successfully enabled, all Program Memory locations are
available for byte programming. In contrast, when the Flash Controller is unlocked and
Page Erase is successfully enabled, only the locations of the selected page are available for
byte programming. An erased Flash byte contains all 1’s (FFH). The programming opera-
tion can only be used to change bits from 1 to 0. To change a Flash bit (or multiple bits)
from 0 to 1 requires execution of either the Page Erase or Mass Erase commands.
Byte Programming can be accomplished using the On-Chip Debugger's Write Memory
command or eZ8 CPU execution of the LDC or LDCI instructions. Refer to the eZ8 CPU
User Manual (available for download at www.zilog.com)for a description of the LDC and
LDCI instructions. While the Flash Controller programs the Flash memory, the eZ8 CPU
idles but the system clock and on-chip peripherals continue to operate. To exit program-
ming mode and lock the Flash, write any value to the Flash Control register, except the
Mass Erase or Page Erase commands.
The byte at each address of the Flash memory cannot be programmed (any bits written
to 0) more than twice before an erase cycle occurs.
Caution:
Page Erase
The Flash memory can be erased one page (512 bytes) at a time. Page Erasing the Flash
memory sets all bytes in that page to the value FFH. The Flash Page Select register identi-
fies the page to be erased. Only a page residing in an unprotected sector can be erased.
With the Flash Controller unlocked and the active page set, writing the value 95hto the
Flash Control register initiates the Page Erase operation. While the Flash Controller exe-
cutes the Page Erase operation, the eZ8 CPU idles but the system clock and on-chip
peripherals continue to operate. The eZ8 CPU resumes operation after the Page Erase
operation completes. If the Page Erase operation is performed using the On-Chip Debug-
ger, poll the Flash Status register to determine when the Page Erase operation is complete.
When the Page Erase is complete, the Flash Controller returns to its locked state.
Mass Erase
The Flash memory can also be Mass Erased using the Flash Controller, but only by using
the On-Chip Debugger. Mass Erasing the Flash memory sets all bytes to the value FFH.
With the Flash Controller unlocked and the Mass Erase successfully enabled, writing the
value 63Hto the Flash Control register initiates the Mass Erase operation. While the Flash
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Controller executes the Mass Erase operation, the eZ8 CPU idles but the system clock and
on-chip peripherals continue to operate. Using the On-Chip Debugger, poll the Flash Sta-
tus register to determine when the Mass Erase operation is complete. When the Mass
Erase is complete, the Flash Controller returns to its locked state.
Flash Controller Bypass
The Flash Controller can be bypassed and the control signals for the Flash memory
brought out to the GPIO pins. Bypassing the Flash Controller allows faster Row Program-
ming algorithms by controlling the Flash programming signals directly.
Row programing is recommended for gang programming applications and large volume
customers who do not require in-circuit initial programming of the Flash memory. Mass
Erase and Page Erase operations are also supported when the Flash Controller is bypassed.
Please refer to the document entitled Third-Party Flash Programming Support for Z8
Encore!® for more information about bypassing the Flash Controller. This document is
available for download at www.zilog.com.
Flash Controller Behavior in Debug Mode
The following changes in behavior of the Flash Controller occur when the Flash Control-
ler is accessed using the On-Chip Debugger:
•
•
•
The Flash Write Protect option bit is ignored.
The Flash Sector Protect register is ignored for programming and erase operations.
Programming operations are not limited to the page selected in the Page Select
register.
•
•
Bits in the Flash Sector Protect register can be written to one or zero.
The second write of the Page Select register to unlock the Flash Controller is not
necessary.
•
•
The Page Select register can be written when the Flash Controller is unlocked.
The Mass Erase command is enabled through the Flash Control register.
For security reasons, flash controller allows only a single page to be opened for write/
erase. When writing multiple flash pages, the flash controller must go through the un-
lock sequence again to select another page.
Caution:
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Flash Control Register Definitions
Flash Control Register
The Flash Controller must be unlocked using the Flash Control register before program-
ming or erasing the Flash memory. Writing the sequence 73H8CH, sequentially, to the
Flash Control register unlocks the Flash Controller. When the Flash Controller is
unlocked, the Flash memory can be enabled for Mass Erase or Page Erase by writing the
appropriate enable command to the FCTL. Switching between PRAM Modes (Normal
and Remap) can also be done by writing to the FCTL when the flash controller is
unlocked. Page Erase applies only to the active page selected in Flash Page Select register.
Mass Erase is enabled only through the On-Chip Debugger. Writing an invalid value or an
invalid sequence returns the Flash Controller to its locked state. The Write-only Flash
Control Register shares its Register File address with the read-only Flash Status Register
.
Table 138. Flash Control Register (FCTL)
7
6
5
4
3
2
1
0
BITS
FCMD
FF8H
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
ADDR
FCMD—Flash Command
73H = First unlock command.
8CH = Second unlock command.
95H = Page Erase command (must be third command in sequence to initiate Page Erase).
63H = Mass Erase command (must be third command in sequence to initiate Mass Erase).
5EH = Enable Flash Sector Protect Register Access
Flash Status Register
The Flash Status register indicates the current state of the Flash Controller. This register
can be read at any time. The read-only Flash Status Register shares its Register File
address with the Write-only Flash Control Register.
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Table 139. Flash Status Register (FSTAT)
7
6
5
4
3
2
1
0
BITS
Reserved
FSTAT
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
FF8H
ADDR
Reserved—Must be 0.
FSTAT—Flash Controller Status
000000 = Flash Controller locked.
000001 = First unlock command received (73H written).
000010 = Second unlock command received (8CH written).
000011 = Flash Controller unlocked.
000100 = Sector protect register selected.
001xxx = Program operation in progress.
010xxx = Page erase operation in progress.
100xxx = Mass erase operation in progress
Flash Page Select Register
The Flash Page Select register shares address space with the Flash Sector Protect Register.
Unless the Flash controller is unlocked and written with 5EH, writes to this address target
the Flash Page Select Register.
The register is used to select one of the Flash memory pages to be programmed or erased.
Each Flash Page contains 512 bytes of Flash memory. During a Page Erase operation, all
Flash memory having addresses with the most significant 7-bits given by FPS[6:0] are
chosen for program/erase operation.
Table 140. Flash Page Select Register (FPS)
7
INFO_EN
0
6
5
4
3
PAGE
0
2
1
0
BITS
FIELD
RESET
R/W
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FF9H
ADDR
INFO_EN—Information Area Enable
0 = Information Area us not selected
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1 = Information Area is selected. The Information Area is mapped into the Program Mem-
ory address space at addresses FE00Hthrough FFFFH.
PAGE—Page Select
This 7-bit field identifies the Flash memory page for Page Erase and page unlocking.
Program Memory Address[15:9] = PAGE[6:0]. For the Z8F16xx devices, the upper 2 bits
must always be 0. For the Z8F08xx devices, the upper 3 bits must always to 0. For the
Z8F04xx devices, the upper 4 bits must always to 0.
Flash Sector Protect Register
The Flash Sector Protect register is shared with the Flash Page Select Register. When the
Flash Control Register is written with 73H followed by 5EH, the next write to this address
targets the Flash Sector Protect Register. In all other cases, it targets the Flash Page Select
Register.
This register selects one of the 8 available Flash memory sectors to be protected. The reset
state of each Sector Protect bit is an unprotected state. After a sector is protected by setting
its corresponding register bit, it cannot be unprotected (the register bit cannot be cleared)
without powering down the device.
Table 141. Flash Sector Protect Register (FPROT)
7
6
5
4
3
2
1
0
BITS
SPROT7 SPROT6 SPROT5 SPROT4 SPROT3 SPROT2 SPROT1 SPROT0
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FF9H
ADDR
SPROT7-SPROT0—Sector Protection
Each bit corresponds to a 2KB Flash sector for Z8F16xx devices. For the Z8F08xx
devices each bit correspond to a 1KB Flash Sector. For the Z8F04xx devices each bit cor-
respond to a 512 byte Flash Sector.
Flash Frequency High and Low Byte Registers
The Flash Frequency High and Low Byte registers combine to form a 16-bit value,
FFREQ, to control timing for Flash program and erase operations. The 16-bit binary Flash
Frequency value must contain the system clock frequency (in KHz) and is calculated using
the following equation:.
System Clock Frequency
FFREQ[15:0] = {FFREQH[7:0],FFREQL[7:0]} = ---------------------------------------------------------------
1000
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Flash programming and erasure is not supported for system clock frequencies below
20KHz or above 20MHz. The Flash Frequency High and Low Byte registers must be
loaded with the correct value to ensure proper operation of the device.
Caution:
Table 142. Flash Frequency High Byte Register (FFREQH)
7
6
5
4
3
2
1
0
BITS
FFREQH
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FFAH
ADDR
FFREQH—Flash Frequency High Byte
High byte of the 16-bit Flash Frequency value.
Table 143. Flash Frequency Low Byte Register (FFREQL)
7
6
5
4
3
2
1
0
BITS
FFREQL
0
FIELD
RESET
R/W
R/W
FFBH
ADDR
FFREQL—Flash Frequency Low Byte
Low byte of the 16-bit Flash Frequency value.
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Flash Option Bits
Overview
Programmable Flash Option Bits allow user configuration of certain aspects of Z8 Encore!
XP® F1680 Series operation. The feature configuration data is stored in the Flash Program
Memory and read during Reset. The features available for control through the Flash
Option Bits are:
•
•
•
•
Watch-Dog Timer time-out response selection–interrupt or system reset
Watch-Dog Timer enabled at Reset
The ability to prevent unwanted read access to user code in Program Memory
The ability to prevent accidental programming and erasure of all or a portion of the user
code in Program Memory
•
Voltage Brown-Out configuration-always enabled or disabled during STOP mode to re-
duce STOP mode power consumption
•
•
Voltage Brown-Out voltage threshold selection
Oscillator mode selection-for high, medium, and low power crystal oscillators, or external
RC oscillator
•
Factory trimming information for the Internal Precision Oscillator and Temperature Sen-
sor
Operation
Option Bit Configuration By Reset
Each time the Flash Option Bits are programmed or erased, the device must be Reset for
the change to take effect. During any reset operation (System Reset, system reset, or
STOP Mode Recovery), the Flash Option Bits are automatically read from the Flash Pro-
gram Memory and written to Option Configuration registers. The Option Configuration
registers control operation of the devices within the Z8 Encore! XP® F1680 Series. Option
Bit control is established before the device exits Reset and the eZ8 CPU begins code exe-
cution. The Option Configuration registers are not part of the Register File and are not
accessible for read or write access.
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Option Bit Types
User Option Bits
The user option bits are contained in the first two bytes of program memory. User access
to these bits has been provided because these locations contain application-specific device
configurations. The information contained here is lost when page 0 of the program mem-
ory is erased.
Trim Option Bits
The trim option bits are contained in the information page of the Flash memory. These bits
are factory programmed values required to optimize the operation of onboard analog cir-
cuitry and cannot be permanently altered by the user. Program memory may be erased
without endangering these values. It is possible to alter working values of these bits by
accessing the Trim Bit Address and Data Registers, but these working values are lost after
a power loss.
There are 32 bytes of trim data. To modify one of these values the user code must first
write a value between 00Hand 1FHinto the Trim Bit Address Register. The next write to
the Trim Bit Data register changes the working value of the target trim data byte.
Reading the trim data requires the user code to write a value between 00Hand 1FHinto the
Trim Bit Address Register. The next read from the Trim Bit Data register returns the
working value of the target trim data byte.
The trim address range is from information address 20-3F only. The remainder of the
information page is not accessible through the trim bit address and data registers.
Note:
Calibration Option Bits
The calibration option bits are also contained in the information page. These bits are fac-
tory programmed values intended for use in software correcting the device’s analog per-
formance. To read these values, the user code must employ the LDC instruction to access
the information area of the address space as defined in See “Flash Information Area” on
page 22.
The following code example shows how to read the calibration data from the flash infor-
mation area.
; get value at info address 60 (FE60h)
ldx FPS, #%80 ; enable access to flash info page
ld R0, #%FE
ld R1, #%60
ldc R2, @RR0 ; R2 now contains the calibration value
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Flash Option Bit Control Register Definitions
Trim Bit Address Register
This register contains the target address for an access to the trim option bits.Trim Bit
Address (00h-1Fh) maps to the Information Area address (20hto 3Fh) as shown in
Table 144.
Table 144. Trim Bit Address Register (TRMADR)
BITS
7
6
5
4
3
2
1
0
TRMADR - Trim Bit Address (00H to 1FH)
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FF6H
ADDR
Trim Bit Data Register
This register contains the read or write data for access to the trim option bits.
Table 145. Trim Bit Data Register (TRMDR)
BITS
7
6
5
4
3
2
1
0
TRMDR - Trim Bit Data
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FF7H
ADDR
Table 146. Trim Bit Address Map
Trim Bit
Address
Information
Area Address
00h
01h
02h
03h
:
20h
21h
22h
23h
:
1Fh
3Fh
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Flash Option Bit Address Space
The first two bytes of Flash Program Memory at addresses 0000Hand 0001Hare reserved
for the user-programmable Flash Option Bits.
Flash Program Memory Address 0000H
Table 147. Flash Option Bits at Program Memory Address 0000H
BITS
7
6
5
4
3
2
1
0
WDT_RES WDT_AO
OSC_SEL[1:0]
VBO_AO
FRP
PRAM_M
FWP
FIELD
RESET
R/W
U
U
U
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Program Memory 0000H
ADDR
Note: U = Unchanged by Reset. R/W = Read/Write.
WDT_RES—Watch-Dog Timer Reset
0 = Watch-Dog Timer time-out generates an interrupt request. Interrupts must be globally
enabled for the eZ8 CPU to acknowledge the interrupt request.
1 = Watch-Dog Timer time-out causes a system reset. This setting is the default for unpro-
grammed (erased) Flash.
WDT_AO—Watch-Dog Timer Always On
0 = Watch-Dog Timer is automatically enabled upon application of system power. Watch-
Dog Timer can not be disabled.
1 = Watch-Dog Timer is enabled upon execution of the WDT instruction. Once enabled,
the Watch-Dog Timer can only be disabled by a Reset or STOP Mode Recovery. This set-
ting is the default for unprogrammed (erased) Flash.
OSC_SEL[1:0]—Oscillator Mode Selection
00 = On-chip oscillator configured for use with external RC networks or external clock
input(<4MHz).
01 = Minimum power for use with very low frequency crystals (32KHz).
10 = Medium power for use with medium frequency crystals or ceramic resonators (1MHz
to 8.0MHz).
11 = Maximum power for use with high frequency crystals (8.0MHz to 20.0MHz). This
setting is the default for unprogrammed (erased) Flash.
VBO_AO—Voltage Brown-Out Protection Always On
0 = Voltage Brown-Out Protection is disabled in STOP mode to reduce total power con-
sumption.
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1 = Voltage Brown-Out Protection is always enabled including during STOP mode. This
setting is the default for unprogrammed (erased) Flash.
FRP—Flash Read Protect
0 = User program code is inaccessible. Limited control features are available through the
On-Chip Debugger.
1 = User program code is accessible. All On-Chip Debugger commands are enabled. This
setting is the default for unprogrammed (erased) Flash.
PRAM_M—On-chip Program RAM Mode select.
0 = Program RAM is used as on-chip Register RAM, and it begins at address 800H in the
Register File address space.
1 = Program RAM is used as on-chip Program RAM, and it begins at address E000H in
the Program Memory address space. This setting is the dafault for unprogrammed (erased)
Flash.
FWP—Flash Write Protect
This Option Bit provides Flash Program Memory protection:
0 = Programming and erasure disabled for all of Flash Program Memory. Programming,
Page Erase, and Mass Erase through User Code is disabled. Mass Erase is available using
the On-Chip Debugger.
1 = Programming, Page Erase, and Mass Erase are enabled for all of Flash Program Mem-
ory.
Flash Program Memory Address 0001H
Table 148. Flash Options Bits at Program Memory Address 0001H
BITS
7
6
5
4
3
2
1
0
EXTLTMG
Reserved EXTL_AO
Reserved
X2_Mode X2TL_AO
FIELD
RESET
R/W
U
U
U
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Program Memory 0001H
ADDR
Note: U = Unchanged by Reset. R/W = Read/Write.
EXTLTMG—External Crystal Reset Timing
00 = 3,000 Internal Precision Oscillator Cycles
01 = 5,000 Internal Precision Oscillator Cycles
10 = 10,000 Internal Precision Oscillator Cycles
11 = 20,000 Internal Precision Oscillator Cycles
Reserved—Must be 1.
EXTL_AO—External Crystal Always On.
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This bit determines the state of the external crystal oscillator at Reset. Its selection as sys-
tem clock must be done in the OScillator Control Register (OSCCTL0).
0 = Crystal oscillator is enabled during reset, resulting in longer reset timing
1 = Crystal oscillator is disabled during reset, resulting in shorter reset timing
Note:
X2_Mode—Secondary Crystal Mode Select
0 = External RC Network or external clock input(<4MHz)
1 = External 32KHz watch crystal
X2TL_AO—Secondary Crystal Always On
This bit determines state of the Secondary Crystal Oscillator at Reset. Its selection as
peripheral clock must be done in the Peripheral Control (for example, Timer Control2)
register.
Note:
0 = Secondary Crystal Oscillator is enabled during reset.
1 = Secondary Crystal Oscillator is disabled during reset.
Trim Bit Address Space
All available Trim bit address and their function is listed in Table 149.
Table 149. Trim Bit Address Description
Address
Function
Temprature Sensor Trim0
Temprature Sensor Trim1
Internal Precision Oscillator
VBO and LVD
00H
01H
02H
03H
04H
05H
06H
07H
08H
ADC and Comparator 0/1
ADC Reference Voltage
20M Oscillator and 32K Oscillator
20M Clock Filter
32K Clock Filter
Trim Bit Address 0000H
Table 150. Trim Options Bits at Address 0000H (TTEMP0)
BITS
7
6
5
4
3
2
1
0
TS_FINE
Reserved
TS_ULTRAFINE
FIELD
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Table 150. Trim Options Bits at Address 0000H (TTEMP0)
U
U
U
U
U
U
U
U
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Information Page Memory 0020H
ADDR
Note: U = Unchanged by Reset. R/W = Read/Write.
TS_FINE—Temperature Sensor Fine Control Trim Bits
Contains fine control offset trimming bits for Temperature Sensor.
Reserved—Must be 1.
TS_ULTRAFINE—Temperature Sensor Ultra Fine Control Trim Bits
Contains ultra fine control offset trimming bits for Temperature Sensor.
Trim Bit Address 0001H
Table 151. Trim Option Bits at 0001H (TTEMP1)
BITS
7
6
5
4
3
2
1
0
Reserved
TS_COARSE
FIELD
RESET
R/W
U
U
U
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Information Page Memory 0021H
ADDR
Note: U = Unchanged by Reset. R/W = Read/Write.
Reserved—Must be 1.
TS_COARSE—Temperature Sensor Coarse Control Trim Bits
Contains coarse control offset trimming bits for Temperature Sensor.
Trim Bit Address 0002H
Table 152. Trim Option Bits at 0002H (TIPO)
BITS
7
6
5
4
3
2
1
0
IPO_TRIM
FIELD
RESET
R/W
U
R/W
Information Page Memory 0022H
ADDR
Note: U = Unchanged by Reset. R/W = Read/Write.
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IPO_TRIM—Internal Precision Oscillator Trim Byte
Contains trimming bits for Internal Precision Oscillator.
Trim Bit Address 0003H
Table 153. Trim Option Bits at Address 0003H (TLVD_VBO)
BITS
7
6
5
4
3
2
1
0
VBO_TRIM
LVD_TRIM
FIELD
RESET
R/W
U
U
U
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Information Page Memory 0023H
ADDR
Note: U = Unchanged by Reset. R/W = Read/Write.
VBO_TRIM—Voltage Brown Out Trim
This trimming affects the low voltage detection threshold. Each LSB represents a
50mV change in the threshold level. Alternatively, the low voltage threshold may
be computed from the options bit value by the following equation:
LVD_TRIM—Low Voltage Detect Trim
This trimming affects the low voltage detection threshold. Each LSB represents a
50mV change in the threshold level. Alternatively, the low voltage threshold may
be computed from the options bit value by the following equation:
LVD_LVL = 3.2V - LVD_TRIM * 0.05V
LVD Threshold (V)
Description
Minimum Typical Maximum
LVD_TRIM
00000
00001
00010
00011
TBD
TBD
TBD
TBD
3.20
3.15
3.10
3.05
TBD
TBD
TBD
TBD
Maximum LVD threshold
00100
to
01010
3.00
to
2.79
Default on Reset and to be programmed into Flash
before customer delivery to ensure 2.7V operation.
TBD
TBD
TBD
TBD
01010
to
2.70
to
Minimum LVD threshold
11111
1.65
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Trim Bit Address
Trim Bit Address 0004H - 0008H - Reserved
ZiLOG Calibration Bits
Watchdog Timer Calibration Bits
Table 154. Watchdog Calibration High Byte at 007EH (WDTCALH)
BITS
7
6
5
4
3
2
1
0
WDTCALH
FIELD
RESET
R/W
U
U
U
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Information Page Memory 007EH
ADDR
Note: U = Unchanged by Reset. R/W = Read/Write.
WDTCALH—Watchdog Timer Calibration High Byte
The WDTCALH and WDTCALL bytes, when loaded into the watchdog timer reload reg-
isters result in a one second timeout at room temperature and 3.3V supply voltage. To use
the Watch-Dog Timer calibration, user code must load WDTU with 0x00, WDTH with
WDTCALH and WDTL with WDTCALL.
Table 155. Watchdog Calibration Low Byte at 007FH (WDTCALL)
BITS
7
6
5
4
3
2
1
0
WDTCALL
FIELD
RESET
R/W
U
U
U
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Information Page Memory 007FH
ADDR
Note: U = Unchanged by Reset. R/W = Read/Write.
WDTCALL—Watchdog Timer Calibration Low Byte
The WDTCALH and WDTCALL bytes, when loaded into the watchdog timer reload reg-
isters result in a one second timeout at room temperature and 3.3V supply voltage. To use
the watchdog timer calibration, user code must load WDTU with 0x00, WDTH with
WDTCALH and WDTL with WDTCALL.
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On-Chip Debugger
Overview
The Z8 Encore XP® devices contain an integrated On-Chip Debugger (OCD) that pro-
vides advanced debugging features including:
•
•
•
•
Reading and writing of the Register File
Reading and writing of Program and Data Memory
Setting of Breakpoints and Watchpoints
Executing eZ8 CPU instructions
Architecture
The On-Chip Debugger consists of four primary functional blocks: transmitter, receiver,
auto-baud detector/generator, and debug controller. Figure 54 illustrates the architecture of
the On-Chip Debugger
System Clock
Auto-Baud
Detector/Generator
Transmitter
Receiver
Debug Controller
DBG Pin
Figure 54.On-Chip Debugger Block Diagram
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Operation
OCD Interface
The On-Chip Debugger uses the DBG pin for communication with an external host. This
one-pin interface is a bi-directional open-drain interface that transmits and receives data.
Data transmission is half-duplex, in that transmit and receive cannot occur simultaneously.
The serial data on the DBG pin is sent using the standard asynchronous data format
defined in RS-232. This pin creates an interface from the Z8 Encore! XP® F1680 Series
products to the serial port of a host PC using minimal external hardware.Two different
methods for connecting the DBG pin to an RS-232 interface are depicted in Figures 55
and 56 . The recommended method is the buffered implementation depicted in Figure 56 .
The DBG pin must always be connected to VDD through an external pull-up resistor.
Caution:
For operation of the On-Chip Debugger, all power pins (VDD and AVDD)
must be supplied with power, and all ground pins (VSS and AVSS) must be
properly grounded.
The DBGpin is open-drain and must always be connected to VDD through
an external pull-up resistor to insure proper operation.
VDD
RS-232
Transceiver
10KOhm
DBG Pin
Schottky
Diode
RS-232 TX
RS-232 RX
Figure 55.Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (1)
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VDD
RS-232
Transceiver
10KOhm
DBG Pin
Open-Drain
Buffer
RS-232 TX
RS-232 RX
Figure 56.Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2)
DEBUG Mode
The operating characteristics of the devices in DEBUG mode are:
•
The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to execute
specific instructions
•
•
•
•
The system clock operates unless in STOP mode
All enabled on-chip peripherals operate unless in STOP mode
Automatically exits HALT mode
Constantly refreshes the Watch-Dog Timer, if enabled
Entering DEBUG Mode
•
•
The device enters DEBUG mode after the eZ8 CPU executes a BRK (Breakpoint) instruc-
tion.
If the DBG pin is held Low during the most recent clock cycle of system reset, the part
enters DEBUG mode upon exiting system reset.
Exiting DEBUG Mode
The device exits DEBUG mode following any of these operations:
•
•
•
•
Clearing the DBGMODE bit in the OCD Control Register to 0.
Power-on reset
Voltage Brown-Out reset
Watch-Dog Timer reset
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•
•
Asserting the RESET pin Low to initiate a Reset.
Driving the DBG pin Low while the device is in STOP mode initiates a System Reset.
OCD Data Format
The OCD interface uses the asynchronous data format defined for RS-232. Each character
is transmitted as 1 Start bit, 8 data bits (least-significant bit first), and 1.5 Stop bits
(Figure 57)
START
D0
D1
D2
D3
D4
D5
D6
D7
STOP
Figure 57.OCD Data Format
OCD Auto-Baud Detector/Generator
To run over a range of baud rates (data bits per second) with various system clock frequen-
cies, the On-Chip Debugger contains an Auto-Baud Detector/Generator. After a reset, the
OCD is idle until it receives data. The OCD requires that the first character sent from the
host is the character 80H. The character 80Hhas eight continuous bits Low (one Start bit
plus 7 data bits), framed between High bits. The Auto-Baud Detector measures this period
and sets the OCD Baud Rate Generator accordingly.
The Auto-Baud Detector/Generator is clocked by the system clock. The minimum baud
rate is the system clock frequency divided by 512. For optimal operation with asynchro-
nous data streams, the maximum recommended baud rate is the system clock frequency
divided by 8. The maximum possible baud rate for asynchronous data streams is the sys-
tem clock frequency divided by 4, but this theoretical maximum is possible only for low
noise designs with clean signals. Table 156 lists minimum and recommended maximum
baud rates for sample crystal frequencies.
Table 156. OCD Baud-Rate Limits
Recommended
Recommended
System Clock Frequency Maximum Baud Standard PC Baud Minimum Baud
(MHz)
20.0
Rate (Kbps)
2500.0
125.0
Rate (bps)
1,843,200
115,200
2400
Rate (Kbps)
39
1.0
1.95
0.032768 (32KHz)
4.096
0.064
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If the OCD receives a Serial Break (nine or more continuous bits Low) the Auto-Baud
Detector/Generator resets. Reconfigure the Auto-Baud Detector/Generator by sending
80H.
OCD Serial Errors
The On-Chip Debugger can detect any of the following error conditions on the DBG pin:
•
•
•
Serial Break (a minimum of nine continuous bits Low)
Framing Error (received Stopbit is Low)
Transmit Collision (OCD and host simultaneous transmission detected by the OCD)
When the OCD detects one of these errors, it aborts any command currently in progress,
transmits a four character long Serial Break back to the host, and resets the Auto-Baud
Detector/Generator. A Framing Error or Transmit Collision may be caused by the host
sending a Serial Break to the OCD. Because of the open-drain nature of the interface,
returning a Serial Break break back to the host only extends the length of the Serial Break
if the host releases the Serial Break early.
The host transmits a Serial Break on the DBGpin when first connecting to the Z8 Encore!
XP® F1680 Series devices or when recovering from an error. A Serial Break from the host
resets the Auto-Baud Generator/Detector but does not reset the OCD Control register. A
Serial Break leaves the device in DEBUG mode if that is the current mode. The OCD is
held in Reset until the end of the Serial Break when the DBG pin returns High. Because of
the open-drain nature of the DBG pin, the host can send a Serial Break to the OCD even if
the OCD is transmitting a character.
Breakpoints
Execution Breakpoints are generated using the BRK instruction (opcode 00H). When the
eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If Breakpoints are
enabled, the OCD enters DEBUG mode and idles the eZ8 CPU. If Breakpoints are not
enabled, the OCD ignores the BRK signal and the BRKinstruction operates as an NOP
instruction.
Breakpoints in Flash Memory
The BRKinstruction is opcode 00H, which corresponds to the fully programmed state of a
byte in Flash memory. To implement a Breakpoint, write 00Hto the required break
address, overwriting the current instruction. To remove a Breakpoint, the corresponding
page of Flash memory must be erased and reprogrammed with the original data.
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Runtime Counter
The On-Chip Debugger contains a 16-bit Runtime Counter. It counts system clock cycles
between Breakpoints. The counter starts counting when the On-Chip Debugger leaves
DEBUG mode and stops counting when it enters DEBUG mode again or when it reaches
the maximum count of FFFFH.
On-Chip Debugger Commands
The host communicates to the On-Chip Debugger by sending OCD commands using the
DBG interface. During normal operation, only a subset of the OCD commands are avail-
able. In DEBUG mode, all OCD commands become available unless the user code and
control registers are protected by programming the Flash Read Protect Option bit (FRP).
The Flash Read Protect Option bit prevents the code in memory from being read out of the
Z8 Encore! XP® F1680 Series products. When this option is enabled, several of the OCD
commands are disabled. Table 157 is a summary of the On-Chip Debugger commands.
Each OCD command is described in further detail in the bulleted list following this table.
Table 157 also indicates those commands that operate when the device is not in DEBUG
mode (normal operation) and those commands that are disabled by programming the Flash
Read Protect Option bit.
Table 157. On-Chip Debugger Commands
Command Enabled when NOT
Disabled by
Debug Command
Byte
00H
01H
02H
03H
04H
05H
06H
07H
08H
in DEBUG mode?
Flash Read Protect Option Bit
Read OCD Revision
Reserved
Yes
–
–
–
Read OCD Status Register
Read Runtime Counter
Write OCD Control Register
Read OCD Control Register
Write Program Counter
Read Program Counter
Write Register
Yes
–
–
–
Yes
Yes
–
Cannot clear DBGMODE bit
–
Disabled
Disabled
–
–
Only writes of the Flash Memory Control
registers are allowed. Additionally, only
the Mass Erase command is allowed to
be written to the Flash Control register.
Read Register
09H
0AH
–
–
Disabled
Disabled
Write Program Memory
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Table 157. On-Chip Debugger Commands
Command Enabled when NOT
Disabled by
Debug Command
Read Program Memory
Write Data Memory
Read Data Memory
Read Program Memory CRC
Reserved
Byte
in DEBUG mode?
Flash Read Protect Option Bit
0BH
–
–
–
–
–
–
–
–
–
Disabled
0CH
Yes
0DH
–
0EH
–
0FH
–
Step Instruction
10H
Disabled
Disabled
Disabled
–
Stuff Instruction
11H
Execute Instruction
Reserved
12H
13H–FFH
In the following bulleted list of OCD Commands, data and commands sent from the host
to the On-Chip Debugger are identified by ’DBG← Command/Data’. Data sent from the
On-Chip Debugger back to the host is identified by ’DBG→ Data’
•
Read OCD Revision (00H)—The Read OCD Revision command determines the ver-
sion of the On-Chip Debugger. If OCD commands are added, removed, or changed, this
revision number changes.
DBG ← 00H
DBG → OCDRev[15:8] (Major revision number)
DBG → OCDRev[7:0] (Minor revision number)
•
•
Read OCD Status Register (02H)—The Read OCD Status Register command reads the
OCDSTAT register.
DBG ← 02H
DBG → OCDSTAT[7:0]
Read Runtime Counter (03H)—The Runtime Counter counts system clock cycles in
between Breakpoints. The 16-bit Runtime Counter counts up from 0000Hand stops at the
maximum count of FFFFH. The Runtime Counter is overwritten during the Write Memo-
ry, Read Memory, Write Register, Read Register, Read Memory CRC, Step Instruction,
Stuff Instruction, and Execute Instruction commands.
DBG ← 03H
DBG → RuntimeCounter[15:8]
DBG → RuntimeCounter[7:0]
•
Write OCD Control Register (04H)—The Write OCD Control Register command
writes the data that follows to the OCDCTL register. When the Flash Read Protect Option
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Bit is enabled, the DBGMODE bit (OCDCTL[7]) can only be set to 1, it cannot be cleared
to 0 and the only method of returning the device to normal operating mode is to reset the
device.
DBG ← 04H
DBG ← OCDCTL[7:0]
•
•
Read OCD Control Register (05H)—The Read OCD Control Register command reads
the value of the OCDCTL register.
DBG ← 05H
DBG → OCDCTL[7:0]
Write Program Counter (06H)—The Write Program Counter command writes the data
that follows to the eZ8 CPU’s Program Counter (PC). If the device is not in DEBUG mode
or if the Flash Read Protect Option bit is enabled, the Program Counter (PC) values are
discarded.
DBG ← 06H
DBG ← ProgramCounter[15:8]
DBG ← ProgramCounter[7:0]
•
•
Read Program Counter (07H)—The Read Program Counter command reads the value
in the eZ8 CPU’s Program Counter (PC). If the device is not in DEBUG mode or if the
Flash Read Protect Option bit is enabled, this command returns FFFFH.
DBG ← 07H
DBG → ProgramCounter[15:8]
DBG → ProgramCounter[7:0]
Write Register (08H)—The Write Register command writes data to the Register File.
Data can be written 1–256 bytes at a time (256 bytes can be written by setting size to 0). If
the device is not in DEBUG mode, the address and data values are discarded. If the Flash
Read Protect Option bit is enabled, only writes to the Flash Control Registers are allowed
and all other register write data values are discarded.
DBG ← 08H
DBG ← {4’h0,Register Address[11:8]}
DBG ← Register Address[7:0]
DBG ← Size[7:0]
DBG ← 1-256 data bytes
•
Read Register (09H)—The Read Register command reads data from the Register File.
Data can be read 1–256 bytes at a time (256 bytes can be read by setting size to 0). If the
device is not in DEBUG mode or if the Flash Read Protect Option bit is enabled, this com-
mand returns FFHfor all the data values.
DBG ← 09H
DBG ← {4’h0,Register Address[11:8]
DBG ← Register Address[7:0]
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DBG ← Size[7:0]
DBG → 1-256 data bytes
•
Write Program Memory (0AH)—The Write Program Memory command writes data
to Program Memory. This command is equivalent to the LDC and LDCI instructions. Data
can be written 1–65536 bytes at a time (65536 bytes can be written by setting size to 0).
The on-chip Flash Controller must be written to and unlocked for the programming oper-
ation to occur. If the Flash Controller is not unlocked, the data is discarded. If the device
is not in DEBUG mode or if the Flash Read Protect Option bit is enabled, the data is dis-
carded.
DBG ← 0AH
DBG ← Program Memory Address[15:8]
DBG ← Program Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG ← 1-65536 data bytes
•
•
•
Read Program Memory (0BH)—The Read Program Memory command reads data
from Program Memory. This command is equivalent to the LDC and LDCI instructions.
Data can be read 1–65536 bytes at a time (65536 bytes can be read by setting size to 0). If
the device is not in DEBUG mode or if the Flash Read Protect Option Bit is enabled, this
command returns FFHfor the data.
DBG ← 0BH
DBG ← Program Memory Address[15:8]
DBG ← Program Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG → 1-65536 data bytes
Write Data Memory (0CH)—The Write Data Memory command writes data to Data
Memory. This command is equivalent to the LDE and LDEI instructions. Data can be writ-
ten 1–65536 bytes at a time (65536 bytes can be written by setting size to 0). If the device
is not in DEBUG mode or if the Flash Read Protect Option Bit is enabled, the data is dis-
carded.
DBG ← 0CH
DBG ← Data Memory Address[15:8]
DBG ← Data Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG ← 1-65536 data bytes
Read Data Memory (0DH)—The Read Data Memory command reads from Data Mem-
ory. This command is equivalent to the LDE and LDEI instructions. Data can be read 1 to
65536 bytes at a time (65536 bytes can be read by setting size to 0). If the device is not in
DEBUG mode, this command returns FFHfor the data.
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DBG ← 0DH
DBG ← Data Memory Address[15:8]
DBG ← Data Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG → 1-65536 data bytes
•
Read Program Memory CRC (0EH)—The Read Program Memory CRC command
computes and returns the Cyclic Redundancy Check (CRC) of Program Memory using the
16-bit CRC-CCITT polynomial. If the device is not in DEBUG mode, this command re-
turns FFFFHfor the CRC value. Unlike most other OCD Read commands, there is a delay
from issuing of the command until the OCD returns the data. The OCD reads the Program
Memory, calculates the CRC value, and returns the result. The delay is a function of the
Program Memory size and is approximately equal to the system clock period multiplied
by the number of bytes in the Program Memory.
DBG ← 0EH
DBG → CRC[15:8]
DBG → CRC[7:0]
•
•
Step Instruction (10H)—The Step Instruction command steps one assembly instruction
at the current Program Counter (PC) location. If the device is not in DEBUG mode or the
Flash Read Protect Option bit is enabled, the OCD ignores this command.
DBG ← 10H
Stuff Instruction (11H)—The Stuff Instruction command steps one assembly instruction
and allows specification of the first byte of the instruction. The remaining 0-4 bytes of the
instruction are read from Program Memory. This command is useful for stepping over in-
structions where the first byte of the instruction has been overwritten by a Breakpoint. If
the device is not in DEBUG mode or the Flash Read Protect Option bit is enabled, the
OCD ignores this command.
DBG ← 11H
DBG ← opcode[7:0]
•
Execute Instruction (12H)—The Execute Instruction command allows sending an en-
tire instruction to be executed to the eZ8 CPU. This command can also step over Break-
points. The number of bytes to send for the instruction depends on the opcode. If the device
is not in DEBUG mode or the Flash Read Protect Option bit is enabled, this command
reads and discards one byte.
DBG ← 12H
DBG ← 1-5 byte opcode
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On-Chip Debugger Control Register Definitions
OCD Control Register
The OCD Control register controls the state of the On-Chip Debugger. This register is
used to enter or exit DEBUG mode and to enable the BRKinstruction. It can also reset the
Z8 Encore! XP® F1680 Series device.
A reset and stop function can be achieved by writing 81Hto this register. A reset and go
function can be achieved by writing 41Hto this register. If the device is in DEBUG mode,
a run function can be implemented by writing 40H to this register.
.
Table 158. OCD Control Register (OCDCTL)
BITS
7
6
5
4
3
2
1
0
DBGMODE BRKEN DBGACK
Reserved
RST
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R
R
R
R
R/W
DBGMODE—Debug Mode
The device enters DEBUG mode when this bit is 1. When in DEBUG mode, the eZ8 CPU
stops fetching new instructions. Clearing this bit causes the eZ8 CPU to restart. This bit is
automatically set when a BRK instruction is decoded and Breakpoints are enabled. If the
Flash Read Protect Option Bit is enabled, this bit can only be cleared by resetting the
device. It cannot be written to 0.
0 = The Z8 Encore! XP® F1680 Series Series device is operating in NORMAL mode.
1 = The Z8 Encore! XP® F1680 Series device is in DEBUG mode.
BRKEN—Breakpoint Enable
This bit controls the behavior of the BRKinstruction (opcode 00H). By default, Break-
points are disabled and the BRKinstruction behaves similar to an NOP instruction. If this
bit is 1, when a BRKinstruction is decoded, the DBGMODEbit of the OCDCTL register is
automatically set to 1.
0 = Breakpoints are disabled.
1 = Breakpoints are enabled.
DBGACK—Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, the OCD sends a
Debug Acknowledge character (FFH) to the host when a Breakpoint occurs.
0 = Debug Acknowledge is disabled.
1 = Debug Acknowledge is enabled.
Reserved—Must be 0.
RST—Reset
Setting this bit to 1 resets the device. The device goes through a normal Power-On Reset
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sequence with the exception that the On-Chip Debugger is not reset. This bit is automati-
cally cleared to 0 at the end of reset.
0 = No effect.
1 = Reset the Flash Read Protect Option Bit device.
OCD Status Register
The OCD Status register reports status information about the current state of the debugger
and the system.
Table 159. OCD Status Register (OCDSTAT)
BITS
7
6
5
4
3
2
1
0
DBG
HALT
FRPENB
Reserved
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
DBG—Debug Status
0 = NORMAL mode
1 = DEBUG mode
HALT—HALT Mode
0 = Not in HALT mode
1 = In HALT mode
FRPENB—Flash Read Protect Option Bit Enable
0 = FRP bit enabled, that allows disabling of many OCD commands
1 = FRP bit has no effect
Reserved—Must be 0.
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Non-Volatile Data Storage
Overview
The Z8 Encore! XP® F1680 Series devices contain a Non-Volatile Data Storage (NVDS)
element of up to 256 bytes. This memory can perform over 100,000 write cycles.
Operation
The NVDS is implemented by special purpose ZiLOG software stored in areas of program
memory not accessible to the user. These special-purpose routines use the Flash memory
to store the data. The routines incorporate a dynamic addressing scheme to maximize the
write/erase endurance of the Flash.
Different members of the Z8 Encore! XP® F1680 Series feature multiple NVDS array
sizes. See “Z8 Encore! XP® F1680 Series Family Part Selection Guide” on page 2. for
details.
Note:
NVDS Code Interface
Two routines are required to access the NVDS: a write routine and a read routine. Both of
these routines are accessed with a CALL instruction to a pre-defined address outside of the
user-accessible program memory. Both the NVDS address and data are single-byte values.
Because these routines disturb the working register set, user code must ensure that any
required working register values are preserved by pushing them onto the stack or by
changing the working register pointer just prior to NVDS execution.
During both read and write accesses to the NVDS, interrupt service is NOT disabled. Any
interrupts that occur during the NVDS execution must take care not to disturb the working
register and existing stack contents or else the array may become corrupted. Disabling
interrupts before executing NVDS operations is recommended.
Use of the NVDS requires 15 bytes of available stack space. Also, the contents of the
working register set are overwritten.
For correct NVDS operation, the Flash Frequency Registers must be programmed based
on the system clock frequency. See “Flash Operation Timing Using the Flash Frequency
Registers” on page 263.
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Byte Write
To write a byte to the NVDS array, the user code must first push the address, then the data
byte onto the stack. The user code issues a CALLinstruction to the address of the byte-
write routine (0x10B3). At the return from the sub-routine, the write status byte resides in
working register R0. The bit fields of this status byte are defined in Table 160. The con-
tents of the status byte are undefined for write operations to illegal addresses. Also, user
code should pop the address and data bytes off the stack.
The write routine uses 13 bytes of stack space in addition to the two bytes of address and
data pushed by the user. Sufficient memory must be available for this stack usage.
Because of the flash-memory architecture, NVDS writes exhibit a non-uniform execution
time. In general, a write takes 251μs (assuming a 20MHz system clock). Every 400 to 500
writes, however, a maintenance operation is necessary. In this rare occurrence, the write
takes up to 61ms to complete. Slower system clock speeds result in proportionally higher
execution times.
NVDS byte writes to invalid addresses (those exceeding the NVDS array size) have no
effect. Illegal write operations have a 2μs execution time.
Table 160. Write Status Byte
BITS
7
6
5
4
3
2
1
0
Reserved
RCPY
PF
AWE
DWE
FIELD
0
0
0
0
0
0
0
0
DEFAULT
VALUE
Reserved—Must be 0.
RCPY—Recopy Subroutine Executed
A recopy subroutine was executed. These operations take significantly longer than a
normal write operation.
PF—Power Failure Indicator
A power failure or system reset occurred during the most recent attempted write to the
NVDS array.
AW—Address Write Error
An address byte failure occurred during the most recent attempted write to the NVDS
array.
DWE—Data Write Error
A data byte failure occurred during the most recent attempted write to the NVDS
array.
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Byte Read
To read a byte from the NVDS array, user code must first push the address onto the stack.
User code issues a CALLinstruction to the address of the byte-read routine (0x1000). At
the return from the sub-routine, the read byte resides in working register R0, and the read
status byte resides in working register R1. The contents of the status byte are undefined for
read operations to illegal addresses. Also, the user code should pop the address byte off the
stack.
The read routine uses 9 bytes of stack space in addition to the 1 byte of address pushed by
the user. Sufficient memory must be available for this stack usage.
Because of the flash-memory architecture, NVDS reads exhibit a non-uniform execution
time. A read operation takes between 44μs and 489μs (assuming a 20MHz system clock).
Slower system clock speeds result in proportionally higher execution times.
NVDS byte reads from invalid addresses (those exceeding the NVDS array size) return
0xff. Illegal read operations have a 2μs execution time.
The status byte returned by the NVDS read routine is zero for successful read, as deter-
mined by a CRC check. If the status byte is non-zero, there was a corrupted value in the
NVDS array at the location being read. In this case, the value returned in R0 is the byte
most recently written to the array that does not have a CRC error.
Power Failure Protection
The NVDS routines employ error checking mechanisms to ensure a power failure endan-
gers only the most recently written byte. Bytes previously written to the array are not per-
turbed. For this protection to function, the VBO must be enabled (“Low-Power Modes” on
page 42) and configured for a threshold voltage of 2.4V or greater (“Trim Bit Address
Space” on page 276).
A system reset (such as a pin reset or watchdog timer reset) that occurs during a write
operation also perturbs the byte currently being written. All other bytes in the array are
unperturbed.
Optimizing NVDS Memory Usage for Execution Speed
As Table 161 shows, the NVDS read time varies drastically, this discrepancy being a
trade-off for minimizing the frequency of writes that require post-write page erases. The
NVDS read time of address N is a function of the number of writes to addresses other than
N since the most recent write to address N, as well as the number of writes since the most
recent page erase. Neglecting effects caused by page erases and results caused by the ini-
tial condition in which the NVDS is blank, a rule of thumb is that every write since the
most recent page erase causes read times of unwritten addresses to increase by 1 μs, up to
a maximum of (511-NVDS_SIZE) μs.
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Table 161. NVDS Read Time
Minimum
Latency
Maximum
Latency
Operation
Read (16 byte array)
Read (64 byte array)
Read (128 byte array)
Write (16 byte array)
Write (64 byte array)
Write (128 byte array)
Illegal Read
875
9961
876
883
4973
4971
4984
43
8952
7609
5009
5013
5023
43
Illegal Write
31
31
If NVDS read performance is critical to your software architecture, there are some things
you can do to optimize your code for speed, listed in order from most helpful to least help-
ful:
•
Periodically refresh all addresses that are used. The optimal use of NVDS in terms of speed
is to rotate the writes evenly among all addresses planned to use, bringing all reads closer
to the minimum read time. Because the minimum read time is much less than the write
time, however, actual speed benefits are not always realized.
•
Use as few unique addresses as possible: this helps to optimize the impact of refreshing as
well as minimize the requirement for it.
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Oscillator Control
Overview
The Z8 Encore! XP® F1680 Series devices uses five possible clocking schemes, each
user-selectable:
•
•
•
•
•
On-chip precision trimmed RC oscillator
On-chip oscillator using off-chip crystal or resonator
On-chip oscillator using external RC network
External clock drive
On-chip low precision Watch-Dog Timer oscillator
In addition, Z8 Encore! XP® F1680 Series devices contain:
•
•
A clock failure detection and recovery circuitry, allowing continued operation despite a
failure of the primary oscillator
A peripheral clock that allows timers to be clocked directly from an external 32KHz watch
crystal
Operation
This chapter discusses the logic used to select the system clock and handle primary oscil-
lator failures. A description of the specific operation of each oscillator is outlined else-
where in this document. The detailed description of the Watch-Dog Timer Oscillator starts
on page 134, the Internal Precision Oscillator description begins on page 307, and the
chapter outlining the Crystal Oscillator begins on page 302 of this document.
System Clock Selection
The oscillator control block selects from the available clocks. Table 162 details each clock
source and its usage.
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Table 162. Oscillator Configuration and Selection
Clock Source
Characteristics
Required Setup
Internal Precision
RC Oscillator
• Selectable frequency 0.0432MHz,
0.0864MHz, 0.3456MHz, 0.6912MHz,
1.3842MHz, 2.7648MHz, 5.5296MHz,
11.0592MHz
• Unlock and write Oscillator Control
Register (OSCCTL0) to enable and
select oscillator frequency
• ± 4% accuracy when trimmed
• No external components required
External Crystal/
Resonator
• 32KHz to 20MHz
• Configure Flash option bits for correct
external oscillator mode
• Very high accuracy (dependent on
crystal or resonator used)
• Requires external components
• Unlock and write OSCCTL0 to enable
crystal oscillator, wait for it to stabilize
and select as system clock (if the
EXTL_AO option bit has been de-
asserted, no waiting is required)
External RC
Oscillator
• 32KHz to 4MHz
• Accuracy dependent on external
components
• Configure Flash option bits for correct
external oscillator mode
• Unlock and write OSCCTL0 to enable
crystal oscillator and select as system
clock
External Clock
Drive
• 0 to 20MHz
• Accuracy dependent on external clock
source
• Write GPIO registers to configure PB3
pin for external clock function
• Unlock and write OSCCTL0 to select
external system clock
• Apply external clock signal to GPIO
Internal Watchdog
Timer Oscillator
• 10KHz nominal
• ± 40% accuracy; no external
components required
• Enable WDT if not enabled and wait
until WDT Oscillator is operating.
• Unlock and write Oscillator Control
Register (OSCCTL0) to enable and
select oscillator
• Low power consumption
Unintentional accesses to the oscillator control register can actually stop the chip by
switching to a non-functioning oscillator. To prevent this condition, the oscillator con-
trol block employs a register unlocking/locking scheme.
Caution:
OSC Control Register Unlocking/Locking
To write the oscillator control register (OSCCTL0 and OSCCTL1), unlock it by making
two writes to the OSCCTLx register with the values E7Hfollowed by 18H. A third write to
the OSCCTLx register changes the value of the actual register and returns the register to a
locked state. Any other sequence of oscillator control register writes has no effect. The
values written to unlock the register must be ordered correctly, but are not necessarily con-
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secutive. It is possible to write to or read from other registers within the unlocking/locking
operation.
When selecting a new clock source, the primary oscillator failure detection circuitry and
the Watch-Dog Timer oscillator failure circuitry must be disabled. If POFEN and
WOFEN are not disabled prior to a clock switch-over, it is possible to generate an inter-
rupt for a failure of either oscillator. The Failure detection circuitry can be enabled any-
time after a successful write of SCKSEL in the oscillator control register.
The internal precision oscillator is enabled by default. If the user code changes to a differ-
ent oscillator, it may be appropriate to disable the IPO for power savings. Disabling the
IPO does not occur automatically.
Clock Failure Detection and Recovery
Primary Oscillator Failure
The Z8 Encore! XP® F1680 Series devices can generate non-maskable interrupt-like
events when the primary oscillator fails. To maintain system function in this situation, the
clock failure recovery circuitry automatically forces the Watch-Dog Timer oscillator to
drive the system clock. The Watch-Dog Timer oscillator must be enabled to allow the
recovery. Although this oscillator runs at a much slower speed than the original system
clock, the CPU continues to operate, allowing execution of a clock failure vector and soft-
ware routines that either remedy the oscillator failure or issue a failure alert. This auto-
matic switch-over is not available if the Watch-Dog Timer is the primary oscillator. It is
also unavailable if the Watch-Dog Timer oscillator is disabled, though it is not necessary
to enable the Watch-Dog Timer reset function outlined in the Watch-Dog Timer chapter of
this document on page 134.
The primary oscillator failure detection circuitry asserts if the system clock frequency
drops below 1KHz ±50%. If an external signal is selected as the system oscillator, it is
possible that a very slow but non-failing clock can generate a failure condition. Under
these conditions, do not enable the clock failure circuitry (POFEN must be removed from
the OSCCTL0 register).
Watch-Dog Timer Failure
In the event of a Watch-Dog Timer oscillator failure, a similar non-maskable interrupt-like
event is issued. This event does not trigger an attendant clock switch-over, but alerts the
CPU of the failure. After a Watch-Dog Timer failure, it is no longer possible to detect a
primary oscillator failure. The failure detection circuitry does not function if the Watch-
Dog Timer is used as the primary oscillator or if the Watch-Dog Timer oscillator has been
disabled. For either of these cases, it is necessary to disable the detection circuitry by
removing the WDFEN bit of the OSCCTL0 register.
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The Watch-Dog Timer oscillator failure-detection circuit counts system clocks while
looking for a Watch-Dog Timer clock. The logic counts 8004 system clock cycles before
determining that a failure has occurred. The system clock rate determines the speed at
which the Watch-Dog Timer failure can be detected. A very slow system clock results in
very slow detection times.
It is possible to disable the clock failure detection circuitry as well as all functioning
clock sources. In this case, the Z8 Encore! XP® F1680 Series device ceases functioning
and can only be recovered by Power-On-Reset.
Caution:
Peripheral Clock
The peripheral clock is based on a low-frequency/low-power 32KHz secondary oscillator
that can be used with an external watch crystal. The peripheral clock is only available for
driving Timer and associated noise filter operation. It is not supported for other peripher-
als. The dedicated peripheral clock source allows Timer operation when the device is in
Stop Mode.
Table 111 summarizes peripheral clock source features and usage.
Table 163. Peripheral Clock Source and Usage
Peripheral Clock Source
Characteristics
Required Set-Up
Secondary Oscillator
- Optimized for use with a
32 KHz Watch Crystal
- Very high Accuracy
- Dedicated XTAL pins
-No external components
-Unlock and write OSCCTL1 to enable
secondary oscillator
-Select peripheral clock at Timer clock
source in TxCTL2 register
Oscillator Control Register Definitions
Oscillator Control0 Register
The Oscillator Control Register (OSCCTL0) enables/disables the various oscillator cir-
cuits, enables/disables the failure detection/recovery circuitry and selects the primary
oscillator, which becomes the system clock.
The Oscillator Control 0 Register must be unlocked before writing. Writing the two step
sequence E7Hfollowed by 18Hto the Oscillator Control 0 Register unlocks it. The register
is locked at successful completion of a register write to the OSCCTL0.
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Table 164. Oscillator Control0 Register (OSCCTL0)
BITS
7
6
5
4
3
2
1
0
INTEN
XTLEN
WDTEN
POFEN
WDFEN
SCKSEL
FIELD
RESET
R/W
1
0
1
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F86H
ADDR
INTEN—Internal Precision Oscillator Enable
1 = Internal precision oscillator is enabled
0 = Internal precision oscillator is disabled
XTLEN—Crystal Oscillator Enable; this setting overrides the GPIO register control for
PA0 and PA1
1 = Crystal oscillator is enabled
0 = Crystal oscillator is disabled
WDTEN—Watchdog Timer Oscillator Enable
1 = Watch-Dog Timer oscillator is enabled
0 = Watch-Dog Timer oscillator is disabled
POFEN—Primary Oscillator Failure Detection Enable
1 = Failure detection and recovery of primary oscillator is enabled
0 = Failure detection and recovery of primary oscillator is disabled
WDFEN—Watchdog Timer Oscillator Failure Detection Enable
1 = Failure detection of Watch-Dog Timer oscillator is enabled
0 = Failure detection of Watch-Dog Timer oscillator is disabled
SCKSEL—System Clock Oscillator Select
000 = Internal precision oscillator functions as system clock
001 = Reserved
010 = Crystal oscillator or external RC oscillator functions as system clock
011 = Watch-Dog Timer oscillator functions as system
100 = External clock signal on PB3 functions as system clock
101 = Reserved
110 = Reserved
111 = Reserved
Oscillator Control1 Register
The Oscillator Control1 Register (OSCCTL1) enables/disables the secondary oscillator
circuits which becomes the peripheral clock. The Oscillator Control1 Register is also used
to select the internal precision-oscillator frequency.
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The Oscillator Control 1 Register must be unlocked before writing. Writing the two step
sequence E7Hfollowed by 18Hto the Oscillator Control 1 Register unlocks it. The register
is locked at successful completion of a register write to the OSCCTL1.
Table 165. Oscillator Control1 Register (OSCCTL1)
BITS
7
6
5
4
3
2
1
0
SECEN
SECRDY
Reserved
INTSEL
FIELD
RESET
R/W
0
0
1
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F87H
ADDR
SECEN—Secondary Oscillator Enable
1 = 32KHz Secondary Oscillator is enabled
0 = 32KHz Secondary Oscillator is disabled
SECRDY—Secondary Oscillator Ready Flag
1 = 32KHz Secondary Oscillator is stable and running
0 = 32KHz Secondary Oscillator is not running
Reserved - must be 0
INTSEL—Internal Precision Oscillator Frequency Select
000 = Internal Precision Oscillator Frequency is 11.0592MHz
001 = Internal Precision Oscillator Frequency is 5.5296MHz
010 = Internal Precision Oscillator Frequency is 2.7648MHz
011 = Internal Precision Oscillator Frequency is 1.3824MHz
100 = Internal Precision Oscillator Frequency is 0.6912MHz
101 = Internal Precision Oscillator Frequency is 0.3456MHz
110 = Internal Precision Oscillator Frequency is 0.0864MHz
111 = Internal Precision Oscillator Frequency is 0.0432MHz1
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Crystal Oscillator
Overview
The products in the Z8 Encore! XP® F1680 Series contain a main on-chip crystal oscilla-
tor for use with external crystals with 32KHz to 20MHz frequencies, and a secondary 32K
crystal oscillator. In addition, these two oscillators support external RC networks with
oscillation frequencies up to 4MHz. The on-chip crystal oscillator can be used to generate
the primary system clock for the internal eZ8 CPU and the majority of the on-chip periph-
erals. And the secondary 32K crystal oscillator can only be used to generate clock for
three timers.
Alternatively, the XIN and X2IN input pin can also accept a CMOS-level clock input signal
(for XIN, 32KHz–20MHz; for X2IN, below 4MHz). If an external clock generator is used,
the XOUT or X2OUT pin must be left unconnected. The Z8 Encore! XP® F1680 Series
products do not contain an internal clock divider. The frequency of the signal on the XIN
input pin determines the frequency of the system clock, and the frequency of the signal on
the X2IN determines the frequency of timers.
Although the XIN pin can be used as an main system clock input for an external clock gen-
erator, the CLKIN pin is better suited for such use (See “System Clock Selection” on
page 296)
Note:
Operating Modes
The main on-chip crystal oscillator support four oscillator modes:
•
•
Minimum power for use with very low frequency crystals (32KHz)
Medium power for use with medium frequency crystals or ceramic resonators
(1MHz to 8MHz)
•
•
Maximum power for use with high frequency crystals (8MHz to 20MHz)
On-chip oscillator configured for use with external RC networks (<4MHz)
The main on-chip crystal oscillator mode is selected using user-programmable Flash
Option Bits. Please refer to the chapter “Flash Option Bits” on page 271 for information.
The secondary 32K crystal oscillator support two oscillator modes:
•
•
Normal mode for use with 32K crystals (32KHz)
On-chip oscillator configured for use with external RC networks (<4MHz)
The secondary 32K crystal oscillator mode is selected using user-programmable Flash
Option Bits. Please refer to the chapter “Flash Option Bits” on page 271 for information.
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Main Crystal Oscillator Operation
The Flash Option bit XTLDIS controls whether the crystal oscillator is enabled during
reset. The crystal may later be disabled after reset if a new oscillator has been selected as
the system clock. If the crystal is manually enabled after reset through the OSCCTL regis-
ter, the user code must wait at least 1000 crystal oscillator cycles for the crystal to stabi-
lize. After this, the crystal oscillator may be selected as the system clock.
Figure 58 illustrates a recommended configuration for connection with an external funda-
mental-mode, parallel-resonant crystal operating at 20MHz. Recommended 20MHz crys-
tal specifications are provided in Table 166. Resistor R1 is optional and limits total power
dissipation by the crystal. Printed circuit board layout must add no more than 4pF of stray
capacitance to either the XIN or XOUT pins. If oscillation does not occur, reduce the values
of capacitors C1 and C2 to decrease loading.
On-Chip Oscillator
XIN
XOUT
R1 = 220Ω
Crystal
C1 = 39pF
C2 = 39pF
Figure 58.Recommended 20 MHz Crystal Oscillator Configuration
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Table 166. Recommended Crystal Oscillator Specifications
Value
Units
Comments
Parameter
Frequency
Resonance
Mode
20
MHz
Parallel
Fundamental
Series Resistance (R )
60
30
7
W
pF
Maximum
Maximum
Maximum
Maximum
S
Load Capacitance (C )
L
Shunt Capacitance (C )
pF
0
Drive Level
1
mW
Main Oscillator Operation with an External RC Network
Figure 59 illustrates a recommended configuration for connection with an external resis-
tor-capacitor (RC) network.
VDD
R
XIN
C
Figure 59.Connecting the On-Chip Oscillator to an External RC Network
An external resistance value of 45KΩ is recommended for oscillator operation with an
external RC network. The minimum resistance value to ensure operation is 40KΩ. The
typical oscillator frequency can be estimated from the values of the resistor (R in KΩ) and
capacitor (C in pF) elements using the following equation:
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1×106
Oscillator Frequency (kHz) = ---------------------------------------------------------
(0.4 × R × C) + (4 × C)
Figure 60 illustrates the typical (3.3V and 250C) oscillator frequency as a function of the
capacitor (C in pF) employed in the RC network assuming a 45KΩ external resistor. For
very small values of C, the parasitic capacitance of the oscillator XIN pin and the printed
circuit board should be included in the estimation of the oscillator frequency.
It is possible to operate the RC oscillator using only the parasitic capacitance of the pack-
age and printed circuit board. To minimize sensitivity to external parasitics, external
capacitance values in excess of 20pF are recommended.
4000
3750
3500
3250
3000
2750
2500
2250
2000
1750
1500
1250
1000
750
500
250
0
0
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500
C (pF)
Figure 60.Typical RC Oscillator Frequency as a Function of the External Capacitance with a
45KOhm Resistor
Caution: When using the external RC oscillator mode, the oscillator can stop
oscillating if the power supply drops below 2.7V, but before the power supply drops to
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the voltage brown-out threshold. The oscillator resumes oscillation when the supply
voltage exceeds 2.7V.
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Internal Precision Oscillator
Overview
The Internal Precision Oscillator (IPO) is designed for use without external components.
The user can either manually trim the oscillator for a non-standard frequency or use the
automatic factory-trimmed version to achieve a 0.0432 - 11.0592MHz frequency. IPO fea-
tures include:
•
•
On-chip RC oscillator that does not require external components
Selectable output frequency: 11.0592MHz, 5.5296MHz, 2.7648MHz, 1.3824MHz,
0.6912MHz, 0.3456MHz, 0.0864MHz, 0.0432MHz
•
•
Trimming possible through flash-option bits with user override
Elimination of crystals or ceramic resonators in applications where high timing accuracy
is not required.
•
Accuracy: ± 2.5% over extended temperature and voltage
± 1.0% over standard temperature (0-70C) and voltage
Operation
The internal oscillator is an RC relaxation oscillator that has had its sensitivity to power
supply variation minimized. By using ratio tracking thresholds, the effect of power supply
voltage is cancelled out. The dominant source of oscillator error is the absolute variance of
chip level fabricated components, such as capacitors. An 8-bit trimming register, incorpo-
rated into the design, compensates for absolute variation of oscillator frequency. Once
trimmed the oscillator frequency is stable and does not require subsequent calibration.
Trimming is performed during manufacturing and is not necessary for the user to repeat
unless a frequency other than one of the selectable frequencies is required.
Power down this block for minimum system power.
By default, the oscillator is configured through the Flash Option bits. However, the user
code can override these trim values as described in “Trim Bit Address Space” on
page 276.
Select one of the frequencies for the oscillator using the INTSEL bits in the “Oscillator
Control1 Register” on page 300.
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eZ8 CPU Instruction Set
Assembly Language Programming Introduction
The eZ8 CPU assembly language provides a means for writing an application program
without concern for actual memory addresses or machine instruction formats. A program
written in assembly language is called a source program. Assembly language allows the
use of symbolic addresses to identify memory locations. It also allows mnemonic codes
(opcodes and operands) to represent the instructions themselves. The opcodes identify the
instruction while the operands represent memory locations, registers, or immediate data
values.
Each assembly language program consists of a series of symbolic commands called state-
ments. Each statement can contain labels, operations, operands and comments.
Labels can be assigned to a particular instruction step in a source program. The label iden-
tifies that step in the program as an entry point for use by other instructions.
The assembly language also includes assembler directives that supplement the machine
instruction. The assembler directives, or pseudo-ops, are not translated into a machine
instruction. Rather, the pseudo-ops are interpreted as directives that control or assist the
assembly process.
The source program is processed (assembled) by the assembler to obtain a machine lan-
guage program called the object code. The object code is executed by the eZ8 CPU. An
example segment of an assembly language program is detailed in the following example.
Assembly Language Source Program Example
JP START
START:
; Everything after the semicolon is a comment.
; A label called “START”. The first instruction (JP START) in this
; example causes program execution to jump to the point within the
; program where the STARTlabel occurs.
LD R4, R7
; A Load (LD) instruction with two operands. The first operand,
; Working Register R4, is the destination. The second operand,
; Working Register R7, is the source. The contents of R7 is
; written into R4.
LD 234H, #%01 ; Another Load (LD) instruction with two operands.
; The first operand, Extended Mode Register Address 234H,
; identifies the destination. The second operand, Immediate Data
; value 01H, is the source. The value 01His written into the
; Register at address 234H.
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Assembly Language Syntax
For proper instruction execution, eZ8 CPU assembly language syntax requires that the
operands be written as destination, source. After assembly, the object code usually has the
operands in the order source, destination, but ordering is opcode-dependent. The follow-
ing instruction examples illustrate the format of some basic assembly instructions and the
resulting object code produced by the assembler. This binary format must be followed by
users that prefer manual program coding or intend to implement their own assembler.
Example 1: If the contents of Registers 43H and 08H are added and the result is stored in
43H, the assembly syntax and resulting object code is:
Table 167. Assembly Language Syntax Example 1
ADD
04
43H,
08
08H
43
(ADD dst, src)
(OPC src, dst)
Assembly Language Code
Object Code
Example 2: In general, when an instruction format requires an 8-bit register address, that
address can specify any register location in the range 0–255 or, using Escaped Mode
Addressing, a Working Register R0–R15. If the contents of Register 43H and Working
Register R8 are added and the result is stored in 43H, the assembly syntax and resulting
object code is:
Table 168. Assembly Language Syntax Example 2
ADD
04
43H,
E8
R8
43
(ADD dst, src)
(OPC src, dst)
Assembly Language Code
Object Code
See the device-specific Product Specification to determine the exact register file range
available. The register file size varies, depending on the device type.
eZ8 CPU Instruction Notation
In the eZ8 CPU Instruction Summary and Description sections, the operands, condition
codes, status flags, and address modes are represented by a notational shorthand that is
described in Table 169
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.
Table 169. Notational Shorthand
Notation Description
Operand Range
b
Bit
b
b represents a value from 0 to 7 (000B to 111B).
cc
Condition Code
—
See Condition Codes overview in the eZ8 CPU
User Manual.
DA
ER
Direct Address
Addrs
Reg
Addrs. represents a number in the range of
0000H to FFFFH
Extended Addressing Register
Reg. represents a number in the range of 000H to
FFFH
IM
Ir
Immediate Data
#Data
@Rn
Data is a number between 00H to FFH
n = 0 –15
Indirect Working Register
Indirect Register
IR
@Reg
Reg. represents a number in the range of 00H to
FFH
Irr
Indirect Working Register Pair
Indirect Register Pair
@RRp
@Reg
p = 0, 2, 4, 6, 8, 10, 12, or 14
IRR
Reg. represents an even number in the range
00H to FEH
p
Polarity
p
Polarity is a single bit binary value of either 0B or
1B.
r
Working Register
Register
Rn
n = 0 – 15
R
Reg
Reg. represents a number in the range of 00H to
FFH
RA
Relative Address
X
X represents an index in the range of +127 to –
128 which is an offset relative to the address of
the next instruction
rr
Working Register Pair
Register Pair
RRp
Reg
p = 0, 2, 4, 6, 8, 10, 12, or 14
RR
Reg. represents an even number in the range of
00H to FEH
Vector
X
Vector Address
Indexed
Vector
#Index
Vector represents a number in the range of 00H
to FFH
The register or register pair to be indexed is offset
by the signed Index value (#Index) in a +127 to
-128 range.
Table 170 contains additional symbols that are used throughout the Instruction Summary
and Instruction Set Description sections.
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Table 170. Additional Symbols
Symbol
Definition
dst
src
@
Destination Operand
Source Operand
Indirect Address Prefix
Stack Pointer
SP
PC
FLAGS
RP
#
Program Counter
Flags Register
Register Pointer
Immediate Operand Prefix
Binary Number Suffix
B
%
Hexadecimal Number
Prefix
H
Hexadecimal Number
Suffix
Assignment of a value is indicated by an arrow. For example,
dst ← dst + src
indicates the source data is added to the destination data and the result is stored in the des-
tination location.
eZ8 CPU Instruction Classes
eZ8 CPU instructions can be divided functionally into the following groups:
•
•
•
•
•
•
•
•
Arithmetic
Bit Manipulation
Block Transfer
CPU Control
Load
Logical
Program Control
Rotate and Shift
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Tables 171 through 178 contain the instructions belonging to each group and the number
of operands required for each instruction. Some instructions appear in more than one table
as these instruction can be considered as a subset of more than one category. Within these
tables, the source operand is identified as ’src’, the destination operand is ’dst’ and a con-
dition code is ’cc’.
Table 171. Arithmetic Instructions
Mnemonic
ADC
Operands
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst
Instruction
Add with Carry
ADCX
ADD
Add with Carry using Extended Addressing
Add
ADDX
CP
Add using Extended Addressing
Compare
CPC
Compare with Carry
CPCX
CPX
Compare with Carry using Extended Addressing
Compare using Extended Addressing
Decimal Adjust
DA
DEC
dst
Decrement
DECW
INC
dst
Decrement Word
dst
Increment
INCW
MULT
SBC
dst
Increment Word
dst
Multiply
dst, src
dst, src
dst, src
dst, src
Subtract with Carry
SBCX
SUB
Subtract with Carry using Extended Addressing
Subtract
SUBX
Subtract using Extended Addressing
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Table 172. Bit Manipulation Instructions
Mnemonic
BCLR
BIT
Operands
bit, dst
p, bit, dst
bit, dst
dst
Instruction
Bit Clear
Bit Set or Clear
BSET
BSWAP
CCF
Bit Set
Bit Swap
—
Complement Carry Flag
RCF
—
Reset Carry Flag
SCF
—
Set Carry Flag
TCM
dst, src
dst, src
dst, src
dst, src
Test Complement Under Mask
Test Complement Under Mask using Extended Addressing
Test Under Mask
TCMX
TM
TMX
Test Under Mask using Extended Addressing
Table 173. Block Transfer Instructions
Instruction
Mnemonic Operands
LDCI
LDEI
dst, src
dst, src
Load Constant to/from Program Memory and Auto-Increment Addresses
Load External Data to/from Data Memory and Auto-Increment Addresses
Table 174. CPU Control Instructions
Mnemonic
ATM
CCF
DI
Operands
Instruction
—
—
—
—
—
—
—
—
src
Atomic Execution
Complement Carry Flag
Disable Interrupts
Enable Interrupts
Halt Mode
EI
HALT
NOP
RCF
SCF
SRP
No Operation
Reset Carry Flag
Set Carry Flag
Set Register Pointer
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Table 174. CPU Control Instructions
Mnemonic
STOP
Operands
Instruction
—
—
STOP Mode
WDT
Watch-Dog Timer Refresh
Table 175. Load Instructions
Mnemonic Operands Instruction
CLR
LD
dst
Clear
dst, src
dst, src
dst, src
Load
LDC
LDCI
Load Constant to/from Program Memory
Load Constant to/from Program Memory and Auto-Increment
Addresses
LDE
dst, src
dst, src
Load External Data to/from Data Memory
LDEI
Load External Data to/from Data Memory and Auto-Increment
Addresses
LDWX
LDX
dst, src
dst, src
Load Word using Extended Addressing
Load using Extended Addressing
LEA
dst, X(src) Load Effective Address
POP
dst
dst
src
src
Pop
POPX
PUSH
PUSHX
Pop using Extended Addressing
Push
Push using Extended Addressing
Table 176. Logical Instructions
Mnemonic Operands Instruction
AND
ANDX
COM
OR
dst, src
dst, src
dst
Logical AND
Logical AND using Extended Addressing
Complement
dst, src
dst, src
Logical OR
ORX
Logical OR using Extended Addressing
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Table 176. Logical Instructions
Mnemonic Operands Instruction
XOR
dst, src
dst, src
Logical Exclusive OR
Logical Exclusive OR using Extended Addressing
XORX
Table 177. Program Control Instructions
Mnemonic
Operands
Instruction
BRK
BTJ
—
On-Chip Debugger Break
p, bit, src, DA Bit Test and Jump
BTJNZ
BTJZ
CALL
DJNZ
IRET
JP
bit, src, DA
bit, src, DA
dst
Bit Test and Jump if Non-Zero
Bit Test and Jump if Zero
Call Procedure
dst, src, RA Decrement and Jump Non-Zero
—
Interrupt Return
Jump
dst
dst
DA
DA
—
JP cc
JR
Jump Conditional
Jump Relative
Jump Relative Conditional
Return
JR cc
RET
TRAP
vector
Software Trap
Table 178. Rotate and Shift Instructions
Mnemonic
Operands
dst
Instruction
BSWAP
RL
Bit Swap
dst
Rotate Left
RLC
RR
dst
Rotate Left through Carry
Rotate Right
dst
RRC
SRA
dst
Rotate Right through Carry
Shift Right Arithmetic
dst
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Table 178. Rotate and Shift Instructions
Mnemonic
SRL
Operands
dst
Instruction
Shift Right Logical
Swap Nibbles
SWAP
dst
eZ8 CPU Instruction Summary
Table 179 summarizes the eZ8 CPU instructions. The table identifies the addressing
modes employed by the instruction, the effect upon the Flags register, the number of CPU
clock cycles required for the instruction fetch, and the number of CPU clock cycles
required for the instruction execution.
.
Table 179. eZ8 CPU Instruction Summary
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
r
src
r
C
Z
S
V
D
ADC dst, src
dst ← dst + src + C
12
13
14
15
16
17
18
19
02
03
04
05
06
07
08
09
*
*
*
*
0
*
2
2
3
3
3
3
4
4
2
2
3
3
3
3
4
4
3
4
3
4
3
4
3
3
3
4
3
4
3
4
3
3
r
Ir
R
R
R
IR
IM
IM
ER
IM
r
R
IR
ER
ER
r
ADCX dst, src
ADD dst, src
dst ← dst + src + C
dst ← dst + src
*
*
*
*
*
*
*
*
0
0
*
*
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
ADDX dst, src
Flags Notation:
dst ← dst + src
*
*
*
*
0
*
* = Value is a function of the result of the operation.
– = Unaffected
0 = Reset to 0
1 = Set to 1
X = Undefined
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Table 179. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
r
src
r
C
Z
S
V
D
AND dst, src
dst ← dst AND src
52
53
54
55
56
57
58
59
2F
–
*
*
0
–
–
2
2
3
3
3
3
4
4
1
3
4
3
4
3
4
3
3
2
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
ANDX dst, src
ATM
dst ← dst AND src
–
–
*
*
0
–
–
–
–
–
Block all interrupt and
DMA requests during
execution of the next 3
instructions
–
–
BCLR bit, dst
BIT p, bit, dst
BRK
dst[bit] ← 0
r
r
E2
E2
00
E2
D5
F6
F7
F6
F7
F6
F7
D4
D6
–
–
–
–
X
–
*
*
*
*
0
0
–
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
2
2
1
2
2
3
3
3
3
3
3
2
3
2
2
1
2
2
3
4
3
4
3
4
6
3
dst[bit] ← p
Debugger Break
dst[bit] ← 1
–
*
–
*
BSET bit, dst
BSWAP dst
r
dst[7:0] ← dst[0:7]
R
*
*
BTJ p, bit, src, dst if src[bit] = p
PC ← PC + X
r
Ir
r
–
–
BTJNZ bit, src, dst if src[bit] = 1
PC ← PC + X
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Ir
r
BTJZ bit, src, dst if src[bit] = 0
PC ← PC + X
Ir
CALL dst
SP ← SP -2
@SP ← PC
PC ← dst
IRR
DA
CCF
C ← ~C
EF
B0
B1
*
–
–
–
–
–
–
–
–
–-
–
1
2
2
2
2
3
CLR dst
dst ← 00H
R
–
IR
Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS025001-1105
P R E L I M I N A R Y
eZ8 CPU Instruction Set
Z8 Encore! XP® F1680 Series
Advance Product Specification
318
Table 179. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
R
src
C
Z
S
V
D
COM dst
dst ← ~dst
60
61
–
*
*
0
–
–
2
2
2
2
3
3
3
3
3
3
4
4
4
4
5
5
4
4
2
2
2
2
2
2
1
2
2
3
3
4
3
4
3
4
3
4
3
4
3
4
3
3
3
3
2
3
2
3
5
6
2
3
IR
r
CP dst, src
dst - src
r
A2
*
*
*
*
–
–
r
Ir
A3
R
R
A4
R
IR
IM
IM
r
A5
R
A6
IR
r
A7
CPC dst, src
dst - src - C
1F A2
1F A3
1F A4
1F A5
1F A6
1F A7
1F A8
1F A9
A8
*
*
*
*
–
–
r
Ir
R
R
R
IR
IM
IM
ER
IM
ER
IM
R
IR
ER
ER
ER
ER
R
CPCX dst, src
CPX dst, src
DA dst
dst - src - C
dst - src
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
A9
dst ← DA(dst)
dst ← dst - 1
dst ← dst - 1
IRQCTL[7] ← 0
40
*
X
*
IR
R
41
DEC dst
30
–
–
IR
RR
IRR
31
DECW dst
80
*
81
DI
8F
–
–
–
–
–
–
–
–
–
–
–
–
DJNZ dst, RA
dst ← dst – 1
if dst ≠ 0
r
0A-FA
PC ← PC + X
EI
IRQCTL[7] ← 1
9F
–
–
–
–
–
–
1
2
Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS025001-1105
P R E L I M I N A R Y
eZ8 CPU Instruction Set
Z8 Encore! XP® F1680 Series
Advance Product Specification
319
Table 179. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
Halt Mode
dst
src
C
–
–
Z
–
*
S
–
*
V
–
–
D
–
–
HALT
7F
20
–
–
1
2
2
1
2
2
1
2
2
3
2
5
6
5
INC dst
dst ← dst + 1
R
IR
21
r
0E-FE
A0
INCW dst
IRET
dst ← dst + 1
RR
IRR
–
*
*
*
*
*
*
*
–
*
–
*
A1
FLAGS ← @SP
SP ← SP + 1
PC ← @SP
BF
SP ← SP + 2
IRQCTL[7] ← 1
JP dst
PC ← dst
DA
IRR
DA
8D
C4
–
–
–
–
–
–
–
–
–
–
–
–
3
2
3
2
3
2
JP cc, dst
if cc is true
0D-FD
PC ← dst
JR dst
PC ← PC + X
DA
DA
8B
–
–
–
–
–
–
–
–
–
–
–
–
2
2
2
2
JR cc, dst
if cc is true
0B-FB
PC ← PC + X
LD dst, rc
dst ← src
r
r
IM
X(r)
r
0C-FC
C7
D7
E3
–
–
–
–
–
–
2
3
3
2
3
3
3
3
2
3
2
3
4
3
2
4
2
3
3
3
X(r)
r
Ir
R
R
E4
R
IR
IM
IM
r
E5
R
E6
IR
Ir
E7
F3
IR
R
F5
Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS025001-1105
P R E L I M I N A R Y
eZ8 CPU Instruction Set
Z8 Encore! XP® F1680 Series
Advance Product Specification
320
Table 179. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
r
src
Irr
Irr
r
C
Z
S
V
D
LDC dst, src
dst ← src
C2
C5
D2
C3
D3
–
–
–
–
–
–
2
2
2
2
2
5
9
5
9
9
Ir
Irr
Ir
LDCI dst, src
dst ← src
r ← r + 1
rr ← rr + 1
Irr
Ir
–
–
–
–
–
–
Irr
LDE dst, src
LDEI dst, src
dst ← src
r
Irr
r
82
92
83
93
–
–
–
–
–
–
–
–
–
–
–
–
2
2
2
2
5
5
9
9
Irr
Ir
dst ← src
r ← r + 1
rr ← rr + 1
Irr
Ir
Irr
LDWX dst, src
LDX dst, src
dst ← src
dst ← src
ER
r
ER
ER
ER
IRR
IRR
X(rr)
r
1FE8
84
85
86
87
88
89
94
95
96
97
E8
E9
98
99
F4
–
–
–
–
–
–
–
–
–
–
–
–
5
3
3
3
3
3
3
3
3
3
3
4
4
3
3
2
4
2
3
4
5
4
4
2
3
4
5
2
2
3
5
8
Ir
R
IR
r
X(rr)
ER
ER
IRR
IRR
ER
ER
r
r
Ir
R
IR
ER
IM
LEA dst, X(src)
MULT dst
dst ← src + X
X(r)
X(rr)
–
–
–
–
–
–
rr
dst[15:0] ←
dst[15:8] * dst[7:0]
RR
–
–
–
–
–
–
–
–
–
–
–
–
NOP
No operation
0F
1
2
Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS025001-1105
P R E L I M I N A R Y
eZ8 CPU Instruction Set
Z8 Encore! XP® F1680 Series
Advance Product Specification
321
Table 179. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
r
src
r
C
Z
S
V
D
OR dst, src
dst ← dst OR src
42
43
44
45
46
47
48
49
50
51
D8
–
*
*
0
–
–
2
2
3
3
3
3
4
4
2
2
3
3
4
3
4
3
4
3
3
2
3
2
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
R
ORX dst, src
POP dst
dst ← dst OR src
–
–
*
*
0
–
–
–
–
–
dst ← @SP
SP ← SP + 1
–
–
IR
ER
POPX dst
PUSH src
dst ← @SP
SP ← SP + 1
–
–
–
–
–
–
–
–
–
–
–
–
SP ← SP – 1
@SP ← src
R
70
71
2
2
3
2
3
2
IR
IM
IF70
PUSHX src
SP ← SP – 1
@SP ← src
ER
C8
–
–
–
–
–
–
3
2
RCF
RET
C ← 0
CF
AF
0
–
–
–
–
–
–
–
–
–
–
–
1
1
2
4
PC ← @SP
SP ← SP + 2
RL dst
R
90
91
*
*
*
*
–
–
2
2
2
3
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
IR
RLC dst
R
10
11
*
*
*
*
–
–
2
2
2
3
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
IR
Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS025001-1105
P R E L I M I N A R Y
eZ8 CPU Instruction Set
Z8 Encore! XP® F1680 Series
Advance Product Specification
322
Table 179. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
R
src
C
Z
S
V
D
RR dst
E0
E1
*
*
*
*
–
–
2
2
2
3
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
IR
RRC dst
R
C0
C1
*
*
*
*
*
*
*
*
–
1
–
*
2
2
2
3
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
IR
SBC dst, src
dst ← dst – src - C
r
r
r
32
33
34
35
36
37
38
39
DF
D0
D1
2
2
3
3
3
3
4
4
1
2
2
3
4
3
4
3
4
3
3
2
2
3
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
SBCX dst, src
dst ← dst – src - C
C ← 1
*
*
*
*
1
*
SCF
1
*
–
*
–
*
–
0
–
–
–
–
SRA dst
R
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
C
IR
SRL dst
R
1F C0
1F C1
*
*
0
*
–
–
3
3
2
3
0
D7 D6 D5 D4 D3 D2 D1 D0
dst
IR
SRP src
STOP
RP ← src
IM
01
6F
22
23
24
25
26
27
–
–
*
–
–
*
–
–
*
–
–
*
–
–
1
–
–
*
2
1
2
2
3
3
3
3
2
2
3
4
3
4
3
4
STOP Mode
dst ← dst – src
SUB dst, src
r
r
r
Ir
R
R
R
IR
R
IR
IM
IM
Flags Notation:
PS025001-1105
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
P R E L I M I N A R Y
eZ8 CPU Instruction Set
Z8 Encore! XP® F1680 Series
Advance Product Specification
323
Table 179. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
ER
ER
R
src
ER
IM
C
Z
S
V
D
SUBX dst, src
dst ← dst – src
28
29
F0
F1
62
63
64
65
66
67
68
69
72
73
74
75
76
77
78
79
F2
*
*
*
*
1
*
4
4
2
2
2
2
3
3
3
3
4
4
2
2
3
3
3
3
4
4
2
3
3
2
3
3
4
3
4
3
4
3
3
3
4
3
4
3
4
3
3
6
SWAP dst
dst[7:4] ↔ dst[3:0]
X
–
*
*
*
*
X
0
–
–
–
–
IR
r
TCM dst, src
(NOT dst) AND src
r
Ir
r
R
R
R
IR
R
IM
IM
ER
IM
r
IR
ER
ER
r
–
–
*
*
*
*
0
0
–
–
–
–
TCMX dst, src
(NOT dst) AND src
TM dst, src
dst AND src
r
Ir
R
R
R
IR
R
IM
IM
ER
IM
Vector
IR
ER
ER
TMX dst, src
TRAP Vector
dst AND src
–
–
*
*
0
–
–
–
–
–
SP ← SP – 2
@SP ← PC
–
–
SP ← SP – 1
@SP ← FLAGS
PC ← @Vector
WDT
5F
–
–
–
–
–
–
1
2
Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected
X = Undefined
0 = Reset to 0
1 = Set to 1
PS025001-1105
P R E L I M I N A R Y
eZ8 CPU Instruction Set
Z8 Encore! XP® F1680 Series
Advance Product Specification
324
Table 179. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
r
src
r
C
Z
S
V
D
XOR dst, src
dst ← dst XOR src
B2
B3
B4
B5
B6
B7
B8
B9
–
*
*
0
–
–
2
2
3
3
3
3
4
4
3
4
3
4
3
4
3
3
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
XORX dst, src
Flags Notation:
dst ← dst XOR src
–
*
*
0
–
–
* = Value is a function of the result of the operation.
– = Unaffected
0 = Reset to 0
1 = Set to 1
X = Undefined
PS025001-1105
P R E L I M I N A R Y
eZ8 CPU Instruction Set
Z8 Encore! XP® F1680 Series
Advance Product Specification
325
Opcode Maps
A description of the opcode map data and the abbreviations are provided in Figure 61.
Figures 62 and 32 provide information about each of the eZ8 CPU instructions. Table 180
lists Opcode Map abbreviations.
Opcode
Lower Nibble
Fetch Cycles
Instruction Cycles
4
3.3
CP
Opcode
Upper Nibble
A
R2,R1
First Operand
After Assembly
Second Operand
After Assembly
Figure 61.Opcode Map Cell Description
PS025001-1105
P R E L I M I N A R Y
Opcode Maps
Z8 Encore! XP® F1680 Series
Advance Product Specification
326
Table 180. Opcode Map Abbreviations
Abbreviation
Description
Abbreviation
Description
b
Bit position
IRR
Indirect Register Pair
Polarity (0 or 1)
cc
X
Condition code
p
r
8-bit signed index or
displacement
4-bit Working Register
DA
ER
Destination address
R
8-bit register
Extended Addressing register r1, R1, Ir1, Irr1, IR1,
rr1, RR1, IRR1, ER1
Destination address
IM
Immediate data value
r2, R2, Ir2, Irr2, IR2,
rr2, RR2, IRR2, ER2
Source address
Ir
Indirect Working Register
Indirect register
RA
rr
Relative
IR
Irr
Working Register Pair
Register Pair
Indirect Working Register Pair RR
PS025001-1105
P R E L I M I N A R Y
Opcode Maps
Z8 Encore! XP® F1680 Series
Advance Product Specification
327
Lower Nibble (Hex)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
1.1
2.2
2.3
2.4
3.3
3.4
3.3
3.4
4.3
4.3
2.3
2.2
JR
cc,X
2.2
LD
r1,IM
3.2
JP
cc,DA
1.2
INC
r1
1.2
NOP
BRK SRP ADD ADD ADD ADD ADD ADD ADDX ADDX DJNZ
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
IM
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
r1,X
2.2
RLC
R1
2.3
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
See 2nd
Opcode
Map
RLC ADC ADC ADC ADC ADC ADC ADCX ADCX
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
INC
R1
2.3
INC
IR1
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
1, 2
SUB SUB SUB SUB SUB SUB SUBX SUBX
r1,r2
ATM
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
DEC DEC SBC SBC SBC SBC SBC SBC SBCX SBCX
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
DA
R1
2.3
DA
IR1
2.3
OR
r1,r2
2.4
OR
r1,Ir2
3.3
OR
R2,R1
3.4
OR
IR2,R1
3.3
OR
R1,IM
3.4
4.3
4.3
OR
ORX ORX
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
1.2
WDT
POP POP AND AND AND AND AND AND ANDX ANDX
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
1.2
STOP
COM COM TCM TCM TCM TCM TCM TCM TCMX TCMX
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.3
2.4
TM
r1,Ir2
3.3
TM
R2,R1
3.4
TM
IR2,R1
3.3
TM
R1,IM
3.4
4.3
4.3
1.2
HALT
PUSH PUSH TM
R2
TM
TMX TMX
IR2
r1,r2
IR1,IM ER2,ER1 IM,ER1
2.5
2.6
2.5
2.9
3.2
3.3
LDX
3.4
LDX
3.5
3.4
3.4
1.2
DI
DECW DECW LDE LDEI LDX
RR1
LDX
LDX
LDX
IRR1
r1,Irr2
Ir1,Irr2 r1,ER2 Ir1,ER2 IRR2,R1 IRR2,IR1 r1,rr2,X rr1,r2,X
2.2
RL
R1
2.3
RL
IR1
2.5
2.9
3.2
3.3
LDX
3.4
LDX
3.5
3.3
3.5
1.2
EI
LDE LDEI LDX
r2,Irr1
LDX
LEA
LEA
Ir2,Irr1 r2,ER1 Ir2,ER1 R2,IRR1 IR2,IRR1 r1,r2,X rr1,rr2,X
2.5
2.6
2.3
CP
r1,r2
2.4
CP
r1,Ir2
3.3
CP
R2,R1
3.4
CP
IR2,R1
3.3
CP
R1,IM
3.4
4.3
4.3
1.4
RET
INCW INCW
RR1
CP
CPX
CPX
IRR1
IR1,IM ER2,ER1 IM,ER1
2.2
CLR
R1
2.3
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
1.5
IRET
CLR XOR XOR XOR XOR XOR XOR XORX XORX
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
3.4 3.2
LD PUSHX
2.2
2.3
2.5
2.9
2.3
JP
IRR1
2.9
LDC
Ir1,Irr2
1.2
RCF
RRC RRC LDC LDCI
R1
IR1
r1,Irr2
Ir1,Irr2
r1,r2,X
ER2
2.2
2.3
2.5
2.9
2.6
2.2
3.3
3.4
LD
r2,r1,X
3.2
POPX
ER1
1.2
SCF
SRA SRA
R1
LDC LDCI CALL BSWAP CALL
r2,Irr1
IR1
Ir2,Irr1
IRR1
R1
DA
2.2
RR
R1
2.3
RR
IR1
2.2
BIT
p,b,r1
2.3
LD
r1,Ir2
3.2
LD
R2,R1
3.3
LD
IR2,R1
3.2
LD
R1,IM
3.3
4.2
4.2
1.2
CCF
LD
LDX
LDX
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.6
2.3
LD
Ir1,r2
2.8
MULT
RR1
3.3
LD
3.3
BTJ
3.4
BTJ
SWAP SWAP TRAP
R1
IR1
Vector
R2,IR1 p,b,r1,X p,b,Ir1,X
Figure 62.First Opcode Map
PS025001-1105
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Advance Product Specification
328
Lower Nibble (Hex)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
3, 2
PUSH
IM
3.3
3.4
4.3
4.4
4.3
4.4
5.3
5.3
CPC CPC CPC CPC CPC CPC CPCX CPCX
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
3.2
SRL
R1
3.3
SRL
IR1
5, 4
LDWX
ER2,ER1
Figure 63.Second Opcode Map after 1FH
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329
Electrical Characteristics
The data in this chapter is pre-qualification and pre-characterization and is subject to
change. Additional electrical characteristics may be found in the individual chapters.
Absolute Maximum Ratings
Stresses greater than those listed in Table 181 may cause permanent damage to the device.
These ratings are stress ratings only. Operation of the device at any condition outside those
indicated in the operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
For improved reliability, tie unused inputs to one of the supply voltages (VDD or VSS).
Table 181. Absolute Maximum Ratings
Parameter
Minimum Maximum
Units
°C
°C
V
Notes
Ambient temperature under bias
Storage temperature
0
+105
+150
+5.5
+3.6
+5
-65
-0.3
-0.3
-5
Voltage on any pin with respect to V
1
SS
Voltage on V pin with respect to V
V
DD
SS
Maximum current on input and/or inactive output pin
Maximum output current from active output pin
µA
mA
-25
+25
20-pin Packages Maximum Ratings at 0°C to 70°C
Total power dissipation
430
120
mW
mA
Maximum current into V or out of V
DD
SS
28-pin Packages Maximum Ratings at 0°C to 70°C
Total power dissipation
450
125
mW
mA
Maximum current into V or out of V
DD
SS
40-pin PDIP Maximum Ratings at -40°C to 70°C
Total power dissipation
1000
275
mW
mA
Maximum current into V or out of V
DD
SS
40-pin PDIP Maximum Ratings at 700C to 1050C
Operating temperature is specified in DC Characteristics
1. This voltage applies to all pins except the following: V , AV
.
DD
DD
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Table 181. Absolute Maximum Ratings
Minimum Maximum
Parameter
Units
mW
Notes
Total power dissipation
540
150
Maximum current into V or out of V
mA
DD
SS
44-Pin PLCC Maximum Ratings at -40°C to 70°C
Total power dissipation
750
200
mW
mA
Maximum current into V or out of V
DD
SS
44-Pin PLCC Maximum Ratings at 700C to 1050C
Total power dissipation
295
83
mW
mA
Maximum current into V or out of V
DD
SS
44-pin LQFP Maximum Ratings at -40°C to 70°C
Total power dissipation
750
200
mW
mA
Maximum current into V or out of V
DD
SS
44-pin LQFP Maximum Ratings at 700C to 1050C
Total power dissipation
410
114
mW
mA
Maximum current into V or out of V
DD
SS
Operating temperature is specified in DC Characteristics
1. This voltage applies to all pins except the following: V , AV
.
DD
DD
DC Characteristics
Table 182 lists the DC characteristics of the Z8 Encore! XP® F1680 Series products. All
voltages are referenced to VSS, the primary system ground.
Table 182. DC Characteristics
TA = -40°C to +105°C
Symbol Parameter
Minimum Typical
Maximum Units Conditions
V
V
Supply Voltage
1.8
–
–
3.6
V
V
DD
IL1
Low Level Input Voltage
-0.3
0.3*V
For all input pins except RESET,
DBG, XIN
DD
V
V
Low Level Input Voltage
-0.3
–
–
0.2*V
5.5
V
V
For RESET, DBG, XIN
IL2
DD
High Level Input Voltage 0.7*V
Port A, B. C. D, and E pins
(Digital inputs)
IH1
DD
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Table 182. DC Characteristics (Continued)
TA = -40°C to +105°C
Minimum Typical Maximum Units Conditions
High Level Input Voltage 0.7*V
Symbol Parameter
V
V
V
V
V
–
V +0.3
DD
V
V
Ports B and C (Analog)
I = 2mA; V = 3.0V
OL
IH2
DD
Low Level Output
Voltage
–
–
–
–
–
7
0.4
OL1
OH1
OL2
OH2
DD
High Output Drive disabled.
I = -2mA; V = 3.0V
OH
High Level Output
Voltage
V
V
- 0.5
–
0.6
–
V
DD
DD
DD
High Output Drive disabled.
Low Level Output
Voltage
–
V
I
OL
= 20mA; V = 3.3V
DD
High Output Drive enabled.
I = -20mA; V = 3.3V
OH
High Level Output
Voltage
- 0.5
V
DD
High Output Drive enabled.
I
Input Leakage Current
–
–
nA
V
V
= 3.6V;
DD
IL
1
= V or VSS
IN
DD
I
I
Tristate Leakage Current
Controlled Current Drive
–
0.4
3
–
4.5
10.5
19.5
30
µA V = 3.6V
DD
TL
1.8
2.8
7.8
12
–
mA {AFS2,AFS1} = {0,0}
mA {AFS2,AFS1} = {0,1}
mA {AFS2,AFS1} = {1,0}
mA {AFS2,AFS1} = {1,1}
pF TBD
LED
7
13
20
2
C
GPIO Port Pad
Capacitance
8.0
–
PAD
2
2
C
C
XIN Pad Capacitance
XOUT Pad Capacitance
Weak Pull-up Current
–
–
8.0
9.5
–
–
pF TBD
pF TBD
XIN
XOUT
I
30
100
4
350
5
µA V = 3.0 - 3.6V
DD
PU
mA
ICCA
Supply Current in Active
Mode
V
= 3.3V
DD
Fsysclk = 11 MHz
V = 3.3V
DD
mA
ICCADT Supply Current in Active
Mode with ADC, Timers
and TIAMP
8
Fsysclk = 11 MHz
ADC, Timers, T1AMP enabled
0.3
mA
ICCH
Supply Current in Halt
Mode
V
= 3.3V
DD
Fsysclk = 11 MHz
nA All peripherals including WDT
disabled, V = 3.3V
500
ICCS1 Supply Current in STOP
Mode
DD
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Table 182. DC Characteristics (Continued)
TA = -40°C to +105°C
Minimum Typical Maximum Units Conditions
Symbol Parameter
2
ICCS2 Supply Current in STOP
Mode
µA With watchdog timer running
10
ICCS3 Supply Current in STOP
Mode
–
µA WDT, 2 timers running @32 KHz
1
This condition excludes all pins that have on-chip pull-ups, when driven Low.
These values are provided for design guidance only and are not tested in production.
2
Figure 64 illustrates the typical current consumption while operating at 25ºC, 3.3V, versus
the system clock frequency.
Figure 64. ICC Versus System Clock Frequency
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AC Characteristics
The section provides information about the AC characteristics and timing. All AC timing
information assumes a standard load of 50pF on all outputs.
Table 183. AC Characteristics
VDD = 1.8 to 3.6V
TA = -40°C to +105°C
Symbol
Parameter
Minimum Maximum Units Conditions
F
System Clock Frequency
–
20.0
20.0
MHz Read-only from Flash memory
SYSCLK
0.032768
MHz Program or erasure of the
Flash memory
F
Crystal Oscillator Frequency
1.0
20.0
MHz System clock frequencies
below the crystal oscillator
minimum require an external
clock driver.
XTAL
F
F
Secondary Oscillator
Frequency
32.768
32.768
MHz Optimized for use with watch
crystal
XTAL2
Internal Precision Oscillator
Frequency
0.0432 11.0592
MHz Oscillator is not adjustable over
the entire range. See Table
128.
IPO
F
F
Internal Precision Oscillator
Accuracy
-2.5
-1.0
+2.5
+1.0
%
With trimming, over
temparature and voltage
ACC1
Internal Precision Oscillator
Accuracy
%
With trimming over 0-70C and
voltage
ACC2
T
T
T
T
T
System Clock Period
50
20
20
–
–
30
30
3
ns
ns
ns
ns
ns
T
T
T
T
T
= 1/F
sysclk
XIN
CLK
CLK
CLK
CLK
CLK
System Clock High Time
System Clock Low Time
System Clock Rise Time
System Clock Fall Time
= 50ns
= 50ns
= 50ns
= 50ns
XINH
XINL
XINR
XINF
–
3
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On-Chip Peripheral AC and DC Electrical Characteristics
Table 184. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing
Temperature = -40°C to +105°C
VDD = 1.3 - 3.6 V
Symbol
Minimum Typical Maximum
Units
Description
DC
V
1.36
1.6
1.84
V
Trigger point of POR:
1.6V±15%
POR
T
–
–
50
–
–
3
μs
μA
μΑ
ms
μs
POR reset analog delay
POR on action
ANA
VDD
I
–
–
0
After POR action
AC
DC
T
T
NA
–
–
100
–
Core V ramp time
RAMP
pulse
DD
10
Pulse width can be
removed at PORB
V
V
T
1.36
1.6
80
10
1.84
mV
mV
Trigger point of POR:
1.6V±15%
VBO
hys
–
–
Hysteresis of V
80mV
:
VBO
μs
μA
μA
ms
Pulse width rejection
VBO on action
–
–
–
5
VBO
VDD
I
–
–
–
0
After VBO action
–
AC
T
0.10
20
Core V ramp time
DD
RAMP
Table 185. Flash Memory Electrical Characteristics and Timing
VDD = 1.8 to 3.6V
TA = -40°C to +105°C
Parameter
Minimum Typical
Maximum
Units Notes
Flash Byte Read Time
Flash Byte Program Time
Flash Page Erase Time
Flash Mass Erase Time
100
20
–
–
–
–
–
–
40
–
ns
μs
10
ms
ms
200
–
–
Writes to Single Address
Before Next Erase
2
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Table 185. Flash Memory Electrical Characteristics and Timing (Continued)
VDD = 1.8 to 3.6V
TA = -40°C to +105°C
Parameter
Minimum Typical
Maximum
Units Notes
ms Cumulative program time for
Flash Row Program Time
–
–
8
single row cannot exceed limit
before next erase. This
parameter is only an issue
when bypassing the Flash
Controller.
Data Retention
Endurance
100
–
–
–
–
years 25°C
20,000
cycles Program / erase cycles
Table 186. Watch-Dog Timer Electrical Characteristics and Timing
Temperature = -40°C to +105°C
VDD = 1.3 - 3.6 V
Symbol
Minimum Typical
Maximum
Unit Description
DC
AC
T
I
–
–
–
–
10
5
ms
μA
μA
After pd disable only
startup
Enable
Disable
VDD
–
–
0
Freq.
5
10
–
15
55
KHz Output frequency
Duty cycle of output
Duty cycle
45
%
Table 187. Non Volatile Data Storage
VDD = 1.8 - 3.6V
TA = -40°C to +105°C
Parameter
Minimum Typical
Maximum
Units Notes
μs With system clock at 20MHz
NVDS Byte Read Time
NVDS Byte Program Time
Data Retention
34
0.171
100
–
–
–
–
519
39.7
–
ms With system clock at 20MHz
years 25°C
Endurance
160,000
–
cycles Cumulative write cycles for
entire memory
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Table 188. Analog-to-Digital Converter Electrical Characteristics and Timing
Symbol
Temp
Unit Description
-40°C to +105°C
1.8 - 2.7
°C
V
DC
AVDD
2.7 - 3.6
Symbol
Resolution
INL
Min
–
Typ
10
–
Max
Min
Typ
10
–
Max
–
–
–
Bit
LSB
LSB
LSB
LSB
dB
-1.2
-0.5
-1.0
-1.0
–
+1.2 -4.0
4.0
1.0
4.0
4.0
–
DNL
–
0.5
1.0
1.0
–
-1.0
-4.0
-4.0
–
–
Gain error
Offset error
–
–
–
–
60
–
50
–
SNR
Active current
–
5
–
4
mA
μA
Power down current
Reference voltage
1
1
–
–
–
–
–
1.6
–
–
1.6
–
V
Fixed internal reference
–
AVDD
–
–
AVDD
–
V
Use AVDD for internal
reference
1.6
0
–
–
–
AVDD 1.6
–
–
–
AVDD
1.6
V
V
V
External reference
Analog input range
Analog input load
1.6
0
–
Internal reference = 1.6V
0
90%
90%
AVDD
External reference or use
AVDD as internal reference
AVDD
–
1.0
0.5
–
–
–
5
–
–
–
–
–
2.0
1.0
–
–
–
5
–
–
–
–
–
pF
μS
AC Sample time
Holding time
–
–
μS
Conversion time
Input bandwidth
Wake-up time
13
450
–
13
100
clock
KHz
–
–
–
10
–
10
0.02
mS External reference
Internal reference
0.01
Maximumfrequency
of adc_clk
–
–
20
–
5
10
55
MHz
Duty of adc_clk
45
50
55
45
50
%
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Table 189. Comparator Electrical Characteristics
Temperature = -40°C to +105°C
VDD = 2.7 - 3.6 V VDD = 1.8 - 2.7 V
Symbol
Min
–
Typ
5
Max
–
Min
–
Typ
5
Max
–
Units
mV
V
Description
DC
V
V
Input DC offset
OS
0
–
1.8
0
–
1.8
Programmable
internal reference
voltage range
CREF
V
I
0.92
1.0
1.08
0.9
1.0
1.1
V
Programmable
internal reference
voltage range
CREF
–
–
–
–
–
–
400
0.1
–
–
–
–
–
–
–
400
0.1
–
μA
μA
mV
ns
Enable
AVDD
Disable
V
8
8
Input Hysteresis
Propagation delay
HYS
AC
T
100
–
100
–
PROP
Table 190. Temperature Sensor Electrical Characteristics
Temperature = -40°C to +105°C
VDD = 2.7 - 3.6 V
VDD = 1.8 - 2.7 V
Symbol
Min
Typ
Max
Min
Typ
Max
Units Description
DC
T
–7
–
+7
-10
–
+10
°C
-40°C to +105°C
(as measured by
ADC)
AERR
T
T
–1.5
-10
–
–
+1.5
10
-3
–
–
+3
15
°C
°C
+20°C to +30°C (as
measured by ADC
AERR
AERR
-15
-40°C to +105°C (as
measured by
comparator)
I
–
–
–
–
–
100
0.1
–
–
–
–
–
100
0.1
μA
μA
μs
Enable
VDD
Disable/Stop
Time for wake up
AC
T
80
100
80
100
WAKE
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Table 191. Low Power Operational Amplifier Characteristics
Temperature = -40°C to +105°C
VDD = 2.7 - 3.6 V
Symbol Min Typ Max
VDD = 1.8 - 2.7 V
Min Typ Max
60
Units Description
DC AV
PM
–
–
80
53
0.3
–
–
–
–
–
–
dB
DC Gain
45
0.3
–
–
–
deg
Phase margin (13 pf loading)
GBW
–
–
–
MHz Gain/Bandwidth product
mV Input offset
μV/c Input offset drift with temperature
V
V
I
-4
–
4
-4
–
4
OS
1
10
50
1
10
50
OSTA
–
–
–
–
μA
Output current (Drive ability of
OpAmp)
outTA
I
–
–
10
–
–
–
–
10
–
–
μA
Stop mode current with
transimpedance active (static
current of OpAmp)
CC
V
1.4
0.7
V
Maximum common input voltage
value
com
R
Ω
Mux resistance
MUX
AC
Table 192. IPO Electrical Characteristics
VDD = 1.8 - 3.6 V
Temp. = -40°C to +105°C Temp. = 0°C to +70°C
Symbol
Min
–
Typ
–
Max
15
Min
–
Typ
–
Max
15
Units Description
DC T
I
μs
Setup time for output frequency
setup
–
–
300
0
–
–
300
0
μA Enable
μA Disable
VDD
–
–
–
–
AC Freq.
10.78 11.0 11.33
10.9
486
11.0
592
11.1 MHz Output frequency:
27
592
36
698
-40°C to 105°C: 11.0592 MHz ±2%
0°C to 70°C: 11.0592 MHz ±1%
Duty
45
–
55
45
–
55
%
Duty cycle of output
Cycle
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Table 193. Low Voltage Detect Electrical Characteristics
Temperature = -40°C to +105°C
VDD = 1.3 - 3.6 V
Symbol
Minimum
Typical
Maximum
Units
°C
Description
DC
T
-40
1.6
–
–
–
–
+105
3.6
Operation temperature
Operation voltage range
OP
V
I
V
CHIP_VDD
50
μA
Operation current when
circuit is enabled
OP
V
V
- 0.05
V
V + 0.05
TP
V
Detected source voltage,
TH
TP
TP
V
is preset threshold
TP
voltage to be detected.
V
2.65
50
2.7
2.75
–
V
Detected source voltage
for flash protection
TH_PRO
DELAY
AC
T
1000
ns
The delay from source
voltage jumping lower
than V to I
TP
VD_OUT
output logic high
Table 194. Crystal Oscillator Characteristics
Temperature = -40°C to +105°C Units Description
Supply Voltage
Symbol
VDD
2.7 - 3.6
1.8 - 3.6
V
Min
Typ
–
Max
500
50
Min
Typ
–
Max
300
30
DC ICC
–
–
–
–
μA Supply current in crystal running
nA Supply current in crystal disable
Clk_out state in crystal disable
ICCQ
–
–
Sclk
1
1
1
1
1
1
AC Fxtal
0.032
20
20
0.032
20
20
MHz External crystal oscillator
frequency
Fclk_out 0.032
20
20
0.032
20
20
MHz System clock frequency
Tset
Duty
Jitter
–
40
–
10,000 30,000
–
40
–
10,000 30,000 Cycle Startup time after enable
50
1
60
–
50
1
60
–
%
%
Clk_out duty cycle
Clk_out Jitter
PS025001-1105
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Z8 Encore! XP® F1680 Series
Advance Product Specification
340
Table 195. Low Power 32 KHz Characteristics
Temperature = -40°C to +105°C Units Description
Supply Voltage
Symbol
VDD
2.7 - 3.6
1.8 - 3.6
V
Min
–
Typ
–
Max
20
50
1
Min
–
Typ
–
Max
10
30
1
DC ICC
μA Supply current in crystal running
nA Supply current in crystal disable
Clk_out state in crystal disable
ICCQ
Sclk
–
–
–
–
1
1
1
1
AC Fxtal
32
32
32
32
32
32
KHz External crystal oscillator
frequency
Fclk_out 32
32
400
50
1
32
1000
60
32
–
32
400
50
1
32
KHz System clock frequency
Tset
Duty
Jitter
–
40
–
1000 mS Startup time after enable
40
–
60
–
%
%
Clk_out duty cycle
Clk_out Jitter
–
General Purpose I/O Port Input Data Sample Timing
Figure 65 illustrates timing of the GPIO Port input sampling. The input value on a GPIO
Port pin is sampled on the rising edge of the system clock. The Port value is available to
the eZ8 CPU on the second rising clock edge following the change of the Port value.
PS025001-1105
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Electrical Characteristics
Z8 Encore! XP® F1680 Series
Advance Product Specification
341
TCLK
System
Clock
Port Value
Changes to 0
Port Pin
Input Value
Port Input Data
Register Latch
0 Latched
Into Port Input
Data Register
Port Input Data Register
Value 0 Read
by eZ8
Port Input Data
Read on Data Bus
Figure 65. Port Input Sample Timing
Table 196. GPIO Port Input Timing
Delay (ns)
Parameter Abbreviation
Minimum Maximum
T
T
T
Port Input Transition to XIN Rise Setup Time
(Not pictured)
5
–
S_PORT
H_PORT
SMR
XIN Rise to Port Input Transition Hold Time
(Not pictured)
0
–
GPIO Port Pin Pulse Width to ensure STOP Mode
Recovery
1μs
(for GPIO Port Pins enabled as SMR sources)
PS025001-1105
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Z8 Encore! XP® F1680 Series
Advance Product Specification
342
General Purpose I/O Port Output Timing
Figure 66 and Table 197 provide timing information for GPIO Port pins.
TCLK
XIN
T1
T2
Port Output
Figure 66. GPIO Port Output Timing
Table 197. GPIO Port Output Timing
Delay (ns)
Parameter
Abbreviation
Minimum Maximum
GPIO Port pins
T
T
XIN Rise to Port Output Valid Delay
XIN Rise to Port Output Hold Time
–
2
15
–
1
2
PS025001-1105
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Electrical Characteristics
Z8 Encore! XP® F1680 Series
Advance Product Specification
343
On-Chip Debugger Timing
Figure 67 and Table 198 provide timing information for the DBG pin. The DBG pin tim-
ing specifications assume a 4ns maximum rise and fall time.
TCLK
XIN
T1
T2
T4
DBG
(Output)
Output Data
T3
DBG
(Input)
Input Data
Figure 67. On-Chip Debugger Timing
Table 198. On-Chip Debugger Timing
Delay (ns)
Parameter
DBG
Abbreviation
Minimum
Maximum
T
T
T
T
XIN Rise to DBG Valid Delay
–
2
5
5
15
–
1
2
3
4
XIN Rise to DBG Output Hold Time
DBG to XIN Rise Input Setup Time
DBG to XIN Rise Input Hold Time
–
–
UART Timing
Figure 68 and Table 199 provide timing information for UART pins for the case where
CTS is used for flow control. The CTS to DE assertion delay (T1) assumes the transmit
data register has been loaded with data prior to CTS assertion.
PS025001-1105
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Z8 Encore! XP® F1680 Series
Advance Product Specification
344
CTS
(Input)
T3
DE
(Output)
T1
TXD
bit 7 parity
stop
start
bit 0
bit 1
(Output)
T2
end of
stop bit(s)
Figure 68. UART Timing With CTS
Table 199. UART Timing With CTS
Delay (ns)
Parameter
UART
Abbreviation
Minimum
Maximum
T
CTS Fall to DE output delay
2 * XIN
period
2 * XIN period
+ 1 bit time
1
T
T
DE assertion to TXD falling edge (start bit) delay ± 5
End of Stop Bit(s) to DE deassertion delay ± 5
2
3
PS025001-1105
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Z8 Encore! XP® F1680 Series
Advance Product Specification
345
Figure 69 and Table 200 provide timing information for UART pins for the case where
CTS is not used for flow control. DE asserts after the transmit data register has been writ-
ten. DE remains asserted for multiple characters as long as the transmit data register is
written with the next character before the current character has completed.
T2
DE
(Output)
TXD
(Output)
start
bit0
bit 1
bit 7 parity
stop
T1
end of
stop bit(s)
Figure 69. UART Timing Without CTS
Table 200. UART Timing Without CTS
Delay (ns)
Parameter
UART
Abbreviation
Minimum
Maximum
T
DE assertion to TXD falling edge (start bit) delay 1 * XIN
period
1 bit time
1
T
End of Stop Bit(s) to DE deassertion delay (Tx
data register is empty)
± 5
2
PS025001-1105
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Z8 Encore! XP® F1680 Series
Advance Product Specification
346
Packaging
Figure 70 illustrates the 20-pin Plastic Dual Inline Package (PDIP) available for the Z8
Encore! XP® F1680 Series devices.
Figure 70.20-Pin Plastic Dual Inline Package (PDIP)
PS025001-1105
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Packaging
Z8 Encore! XP® F1680 Series
Advance Product Specification
347
Figure 71 illustrates the 20-pin Small Outline Integrated Circuit Package (SOIC) available
for the Z8 Encore! XP® F1680 Series devices.
Figure 71.20-Pin Small Outline Integrated Circuit Package (SOIC)
Figure 72 illustrates the 20-pin Small Shrink Outline Package (SSOP) available for the Z8
Encore! XP® F1680 Series devices.
PS025001-1105
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Packaging
Z8 Encore! XP® F1680 Series
Advance Product Specification
348
Figure 72.20-Pin Small Shrink Outline Package (SSOP)
Figure 73 illustrates the 28-pin Plastic Dual Inline Package (PDIP) available for the Z8
Encore! XP® F1680 Series devices.
PS025001-1105
P R E L I M I N A R Y
Packaging
Z8 Encore! XP® F1680 Series
Advance Product Specification
349
Figure 73.28-Pin Plastic Dual Inline Package (PDIP)
PS025001-1105
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Packaging
Z8 Encore! XP® F1680 Series
Advance Product Specification
350
Figure 74 illustrates the 28-pin Small Outline Integrated Circuit package (SOIC) available
in the Z8 Encore! XP® F1680 Series devices.
Figure 74.28-Pin Small Outline Integrated Circuit Package (SOIC)
Figure 75 illustrates the 28-pin Small Shrink Outline Package (SSOP) available for the Z8
Encore! XP® F1680 Series devices.
PS025001-1105
P R E L I M I N A R Y
Packaging
Z8 Encore! XP® F1680 Series
Advance Product Specification
351
C
28
15
MILLIMETER
NOM
INCH
NOM
0.073
0.005
0.068
SYMBOL
MIN
1.73
0.05
1.68
0.25
0.09
MAX
1.99
0.21
1.78
0.38
0.20
MIN
MAX
0.078
0.008
0.070
0.015
0.008
A
1.86
0.068
0.002
0.066
0.010
0.004
A1
A2
B
0.13
H
E
1.73
C
0.006
1
14
D
E
e
10.07
5.20
10.20
5.30
10.33
5.38
0.397
0.205
0.402
0.407
0.212
DETAIL A
0.209
0.65 TYP
0.0256 TYP
H
L
7.65
0.63
7.80
0.75
7.90
0.95
0.301
0.025
0.307
0.030
0.311
0.037
A2
A
B
e
SEATING PLANE
CONTROLLING DIMENSIONS: MM
LEADS ARE COPLANAR WITHIN .004 INCHES.
L
0 - 8
DETAIL 'A'
Figure 75.28-Pin Small Shrink Outline Package (SSOP)
Figure 76 illustrates the 40-pin PDIP (plastic dual-inline package) available for the Z8
Encore! XP® F1680 Series devices.
Figure 76.40-Lead Plastic Dual-Inline Package (PDIP)
PS025001-1105
P R E L I M I N A R Y
Packaging
Z8 Encore! XP® F1680 Series
Advance Product Specification
352
Figure 77 illustrates the 40-pin PDIP (plastic dual-inline package) available for the
Z8F1621, Z8F2421, Z8F3221, Z8F4821, and Z8F6421 devices.
Figure 77.40-Lead Plastic Dual-Inline Package (PDIP)
Figure 78 illustrates the 44-pin LQFP (low profile quad flat package) available for the Z8
Encore! XP® F1680 Series devices
A
HD
D
A2
A1
E HE
DETAIL A
LE
c
b
e
L
0-7°
Figure 78.44-Lead Low-Profile Quad Flat Package (LQFP)
PS025001-1105
P R E L I M I N A R Y
Packaging
Z8 Encore! XP® F1680 Series
Advance Product Specification
353
Figure 79 illustrates the 44-pin PLCC (plastic lead chip carrier) package available for the
Z8 Encore! XP® F1680 Series devices
A
D
D1
A1
0.71/0.51
.028/.020
45°
6
1
40
MILLIMETER
INCH
MIN MAX MIN MAX
4.27 4.57 0.168 0.180
SYMBOL
A
7
39
e
0.51/0.36
0.020/0.014
A1 2.41 2.92 0.095 0.115
D/E 17.40 17.65 0.685 0.695
D1/E1 16.51 16.66 0.650 0.656
D2 15.24 16.00 0.600 0.630
M
E1E
0.81/0.66
0.032/0.026
17
29
e
1.27BSC
0.050BSC
18
28
R1.14/0.64
0.045/0.025
NOTES:
1.CONTROLLINGDIMENSION:INCH
2.LEADSARECOPLANARWITHIN0.004".
3.DIMENSION:MM
INCH
Figure 79.44-Lead Plastic Lead Chip Carrier Package (PLCC)
PS025001-1105
P R E L I M I N A R Y
Packaging
Z8 Encore! XP® F1680 Series
Advance Product Specification
354
Ordering Information
Order the Z8 Encore! XP F1680 Series from ZiLOG, referencing the following part numbers. For more
information regarding ordering, please consult your local ZiLOG sales office. The ZiLOG web site at
www.zilog.com lists all regional offices and provides additional Z8 Encore! product information.
Z8 Encore! XP F1680 Series with 24 KB Flash, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0 to 70 °C
Z8F2480SH020SC 24 KB 2 KB 1 KB
Z8F2480HH020SC 24 KB 2 KB 1 KB
Z8F2480PH020SC 24 KB 2 KB 1 KB
Z8F2480SJ020SC 24 KB 2 KB 1 KB
Z8F2480HJ020SC 24 KB 2 KB 1 KB
Z8F2480PJ020SC 24 KB 2 KB 1 KB
Z8F2480PM020SC 24 KB 2 KB 1 KB
Z8F2480AN020SC 24 KB 2 KB 1 KB
Z8F2480VN020SC 24 KB 2 KB 1 KB
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0 17 19 3
0 17 19 3
0 17 19 3
1 23 19 3
1 23 19 3
1 23 19 3
1 33 20 3
1 37 20 3
1 37 20 3
7
7
7
8
8
8
8
8
8
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
PDIP 40-pin package
LQFP 44-pin package
PLCC 44-pin package
Extended Temperature: –40 to 105 °C
Z8F2480SH020EC 24 KB 2 KB 1 KB
Z8F2480HH020EC 24 KB 2 KB 1 KB
Z8F2480PH020EC 24 KB 2 KB 1 KB
Z8F2480SJ020EC 24 KB 2 KB 1 KB
Z8F2480HJ020EC 24 KB 2 KB 1 KB
Z8F2480PJ020EC 24 KB 2 KB 1 KB
Z8F2480PM020EC 24 KB 2 KB 1 KB
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0 17 19 3
0 17 19 3
0 17 19 3
1 23 19 3
1 23 19 3
1 23 19 3
1 33 20 3
7
7
7
8
8
8
8
1
1
1
1
1
1
2
1
1
1
1
1
1
2
1
1
1
1
1
1
1
0
0
0
0
0
0
0
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
PDIP 40-pin package
Note: Replace C with G for lead-free packaging.
PS025001-1105
P R E L I M I N A R Y
Ordering Information
Z8 Encore! XP® F1680 Series
Advance Product Specification
355
Z8F2480AN020EC 24 KB 2 KB 1 KB
Z8F2480VN020EC 24 KB 2 KB 1 KB
0
0
1
1
1 37 20 3
1 37 20 3
8
8
2
2
2
2
1
1
1
1
LQFP 44-pin package
PLCC 44-pin package
Note: Replace C with G for lead-free packaging.
PS025001-1105
P R E L I M I N A R Y
Ordering Information
Z8 Encore! XP® F1680 Series
Advance Product Specification
356
Z8 Encore! XP F1680 Series with 24 KB Flash
Standard Temperature: 0 to 70 °C
Z8F2481SH020SC 24 KB 2 KB 512B 256B
Z8F2481HH020SC 24 KB 2 KB 512B 256B
Z8F2481PH020SC 24 KB 2 KB 512B 256B
Z8F2481SJ020SC 24 KB 2 KB 512B 256B
Z8F2481HJ020SC 24 KB 2 KB 512B 256B
Z8F2481PJ020SC 24 KB 2 KB 512B 256B
Z8F2481PM020SC 24 KB 2 KB 512B 256B
Z8F2481AN020SC 24 KB 2 KB 512B 256B
Z8F2481VN020SC 24 KB 2 KB 512B 256B
1
1
1
1
1
1
1
1
1
0 17 18 3
0 17 18 3
0 17 18 3
1 25 18 3
1 25 18 3
1 25 18 3
1 35 20 3
1 39 20 3
1 39 20 3
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
2
2
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
PDIP 40-pin package
LQFP 44-pin package
PLCC 44-pin package
Extended Temperature: –40 to 105 °C
Z8F2481SH020EC 24 KB 2 KB 512B 256B
Z8F2481HH020EC 24 KB 2 KB 512B 256B
Z8F2481PH020EC 24 KB 2 KB 512B 256B
Z8F2481SJ020EC 24 KB 2 KB 512B 256B
Z8F2481HJ020EC 24 KB 2 KB 512B 256B
Z8F2481PJ020EC 24 KB 2 KB 512B 256B
Z8F2481PM020EC 24 KB 2 KB 512B 256B
Z8F2481AN020EC 24 KB 2 KB 512B 256B
Z8F2481VN020EC 24 KB 2 KB 512B 256B
1
1
1
1
1
1
1
1
1
0 17 18 3
0 17 18 3
0 17 18 3
1 25 18 3
1 25 18 3
1 25 18 3
1 35 20 3
1 39 20 3
1 39 20 3
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
2
2
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
PDIP 40-pin package
LQFP 44-pin package
PLCC 44-pin package
Note: Replace C with G for lead-free packaging.
PS025001-1105
P R E L I M I N A R Y
Ordering Information
Z8 Encore! XP® F1680 Series
Advance Product Specification
357
Z8 Encore! XP F1680 Series with 16 KB Flash, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0 to 70 °C
Z8F1680SH020SC 16 KB 2 KB 1 KB 256B
Z8F1680HH020SC 16 KB 2 KB 1 KB 256B
Z8F1680PH020SC 16 KB 2 KB 1 KB 256B
Z8F1680SJ020SC 16 KB 2 KB 1 KB 256B
Z8F1680HJ020SC 16 KB 2 KB 1 KB 256B
Z8F1680PJ020SC 16 KB 2 KB 1 KB 256B
Z8F1680PM020SC 16 KB 2 KB 1 KB 256B
Z8F1680AN020SC 16 KB 2 KB 1 KB 256B
Z8F1680VN020SC 16 KB 2 KB 1 KB 256B
Extended Temperature: –40 to 105 °C
1
1
1
1
1
1
1
1
1
0 17 19 3
0 17 19 3
0 17 19 3
1 23 19 3
1 23 19 3
1 23 19 3
1 33 20 3
1 37 20 3
1 37 20 3
7
7
7
8
8
8
8
8
8
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
PDIP 40-pin package
LQFP 44-pin package
PLCC 44-pin package
Z8F1680SH020EC 16 KB 2 KB 1 KB 256B
Z8F1680HH020EC 16 KB 2 KB 1 KB 256B
Z8F1680PH020EC 16 KB 2 KB 1 KB 256B
Z8F1680SJ020EC 16 KB 2 KB 1 KB 256B
Z8F1680HJ020EC 16 KB 2 KB 1 KB 256B
Z8F1680PJ020EC 16 KB 2 KB 1 KB 256B
Z8F1680PM020EC 16 KB 2 KB 1 KB 256B
Z8F1680AN020EC 16 KB 2 KB 1 KB 256B
Z8F1680VN020EC 16 KB 2 KB 1 KB 256B
Note: Replace C with G for lead-free packaging.
1
1
1
1
1
1
1
1
1
0 17 19 3
0 17 19 3
0 17 19 3
1 23 19 3
1 23 19 3
1 23 19 3
1 33 20 3
1 37 20 3
1 37 20 3
7
7
7
8
8
8
8
8
8
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
PDIP 40-pin package
LQFP 44-pin package
PLCC 44-pin package
PS025001-1105
P R E L I M I N A R Y
Ordering Information
Z8 Encore! XP® F1680 Series
Advance Product Specification
358
Z8 Encore! XP F1680 Series with 16 KB Flash
Standard Temperature: 0 to 70 °C
Z8F1681SH020SC 16 KB 2 KB 512B 256B 1 0 17 18 3
Z8F1681HH020SC 16 KB 2 KB 512B 256B 1 0 17 18 3
Z8F1681PH020SC 16 KB 2 KB 512B 256B 1 0 17 18 3
Z8F1681SJ020SC 16 KB 2 KB 512B 256B 1 1 25 18 3
Z8F1681HJ020SC 16 KB 2 KB 512B 256B 1 1 25 18 3
Z8F1681PJ020SC 16 KB 2 KB 512B 256B 1 1 25 18 3
Z8F1681PM020SC 16 KB 2 KB 512B 256B 1 1 35 20 3
Z8F1681AN020SC 16 KB 2 KB 512B 256B 1 1 39 20 3
Z8F1681VN020SC 16 KB 2 KB 512B 256B 1 1 39 20 3
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
2
2
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
PDIP 40-pin package
LQFP 44-pin package
PLCC 44-pin package
Extended Temperature: –40 to 105 °C
Z8F1681SH020EC 16 KB 2 KB 512B 256B
Z8F1681HH020EC 16 KB 2 KB 512B 256B
Z8F1681PH020EC 16 KB 2 KB 512B 256B
Z8F1681SJ020EC 16 KB 2 KB 512B 256B
Z8F1681HJ020EC 16 KB 2 KB 512B 256B
Z8F1681PJ020EC 16 KB 2 KB 512B 256B
Z8F1681PM020EC 16 KB 2 KB 512B 256B
Z8F1681AN020EC 16 KB 2 KB 512B 256B
Z8F1681VN020EC 16 KB 2 KB 512B 256B
Note: Replace C with G for lead-free packaging.
1
1
1
1
1
1
1
1
1
0 17 18 3
0 17 18 3
0 17 18 3
1 25 18 3
1 25 18 3
1 25 18 3
1 35 20 3
1 39 20 3
1 39 20 3
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
2
2
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
PDIP 40-pin package
LQFP 44-pin package
PLCC 44-pin package
PS025001-1105
P R E L I M I N A R Y
Ordering Information
Z8 Encore! XP® F1680 Series
Advance Product Specification
359
Z8 Encore! XP F1680 Series with 8 KB Flash, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0 to 70 °C
Z8F0880SH020SC 8 KB 1 KB 1 KB 128B
Z8F0880HH020SC 8 KB 1 KB 1 KB 128B
Z8F0880PH020SC 8 KB 1 KB 1 KB 128B
Z8F0880SJ020SC 8 KB 1 KB 1 KB 128B
Z8F0880HJ020SC 8 KB 1 KB 1 KB 128B
Z8F0880PJ020SC 8 KB 1 KB 1 KB 128B
Z8F0880PM020SC 8 KB 1 KB 1 KB 128B
Z8F0880AN020SC 8 KB 1K B 1 KB 128B
Z8F0880VN020SC 8 KB 1 KB 1 KB 128B
1
1
1
1
1
1
1
1
1
0 17 19 3
0 17 19 3
0 17 19 3
1 23 19 3
1 23 19 3
1 23 19 3
1 33 20 3
1 37 20 3
1 37 20 3
7
7
7
8
8
8
8
8
8
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
PDIP 40-pin package
LQFP 44-pin package
PLCC 44-pin package
Extended Temperature: –40 to 105 °C
Z8F0880SH020EC 8 KB 1 KB 1 KB 128B
Z8F0880HH020EC 8 KB 1 KB 1 KB 128B
Z8F0880PH020EC 8 KB 1 KB 1 KB 128B
Z8F0880SJ020EC 8 KB 1 KB 1 KB 128B
Z8F0880HJ020EC 8 KB 1 KB 1 KB 128B
Z8F0880PJ020EC 8 KB 1 KB 1 KB 128B
Z8F0880PM020EC 8 KB 1 KB 1 KB 128B
Z8F0880AN020EC 8 KB 1 KB 1 KB 128B
Z8F0880VN020EC 8 KB 1 KB 1 KB 128B
Note: Replace C with G for lead-free packaging.
1
1
1
1
1
1
1
1
1
0 17 18 3
0 17 18 3
0 17 18 3
1 23 18 3
1 23 18 3
1 23 18 3
1 33 20 3
1 37 20 3
1 37 20 3
7
7
7
8
8
8
8
8
8
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
PDIP 40-pin package
LQFP 44-pin package
PLCC 44-pin package
PS025001-1105
P R E L I M I N A R Y
Ordering Information
Z8 Encore! XP® F1680 Series
Advance Product Specification
360
Z8 Encore! XP F1680 Series with 8 KB Flash
Standard Temperature: 0 to 70 °C
Z8F0881SH020SC 8 KB 1 KB 512B 128B
Z8F0881HH020SC 8 KB 1 KB 512B 128B
Z8F0881PH020SC 8 KB 1 KB 512B 128B
Z8F0881SJ020SC 8 KB 1 KB 512B 128B
Z8F0881HJ020SC 8 KB 1 KB 512B 128B
Z8F0881PJ020SC 8 KB 1 KB 512B 128B
Z8F0881PM020SC 8 KB 1 KB 512B 128B
Z8F0881AM020SC 8 KB 1 KB 512B 128B
Z8F0881VN020SC 8 KB 1 KB 512B 128B
1
1
1
1
1
1
1
1
1
0 17 17 3
0 17 17 3
0 17 17 3
1 25 17 3
1 25 17 3
1 25 17 3
1 35 20 3
1 39 20 3
1 39 20 3
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
2
2
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
PDIP 40-pin package
LQFP 44-pin package
PLCC 44-pin package
Extended Temperature: –40 to 105°C
Z8F0881SH020EC 8 KB 1 KB 512B 128B
Z8F0881HH020EC 8 KB 1 KB 512B 128B
Z8F0881PH020EC 8 KB 1 KB 512B 128B
Z8F0881SJ020EC 8 KB 1 KB 512B 128B
Z8F0881HJ020EC 8 KB 1 KB 512B 128B
Z8F0881PJ020EC 8 KB 1 KB 512B 128B
Z8F0881PM020EC 8 KB 1 KB 512B 128B
Z8F0881AN020EC 8 KB 1 KB 512B 128B
Z8F0881VN020EC 8 KB 1 KB 512B 128B
Note: Replace C with G for lead-free packaging.
1
1
1
1
1
1
1
1
1
0 17 17 3
0 17 17 3
0 17 17 3
1 25 17 3
1 25 17 3
1 25 17 3
1 35 20 3
1 39 20 3
1 39 20 3
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
2
2
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
PDIP 40-pin package
LQFP 44-pin package
PLCC 44-pin package
PS025001-1105
P R E L I M I N A R Y
Ordering Information
Z8 Encore! XP® F1680 Series
Advance Product Specification
361
Z8 Encore! XP F1680 Series with 4 KB Flash, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0 to 70 °C
Z8F0480SH020SC 4 KB 1 KB 1 KB 128B
Z8F0480HH020SC 4 KB 1 KB 1 KB 128B
Z8F0480PH020SC 4 KB 1 KB 1 KB 128B
Z8F0480SJ020SC 4 KB 1 KB 1 KB 128B
Z8F0480HJ020SC 4 KB 1 KB 1 KB 128B
Z8F0480PJ020SC 4 KB 1 KB 1 KB 128B
Z8F0480PM020SC 4 KB 1 KB 1 KB 128B
Z8F0480AM020SC 4 KB 1 KB 1 KB 128B
Z8F0480VN020SC 4 KB 1 KB 1 KB 128B
1
1
1
1
1
1
1
1
1
0 17 19 3
0 17 19 3
0 17 19 3
1 23 19 3
1 23 19 3
1 23 19 3
1 33 20 3
1 37 20 3
1 37 20 3
7
7
7
8
8
8
8
8
8
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
PDIP 40-pin package
LQFP 44-pin package
PLCC 44-pin package
Extended Temperature: –40 to 105 °C
Z8F0480SH020EC 4 KB 1 KB 1 KB 128B
Z8F0480HH020EC 4 KB 1 KB 1 KB 128B
Z8F0480PH020EC 4 KB 1 KB 1 KB 128B
Z8F0480SJ020EC 4 KB 1 KB 1 KB 128B
Z8F0480HJ020EC 4 KB 1 KB 1 KB 128B
Z8F0480PJ020EC 4 KB 1 KB 1 KB 128B
Z8F0480PM020EC 4 KB 1 KB 1 KB 128B
Z8F0480AN020EC 4 KB 1 KB 1 KB 128B
Z8F0480VN020EC 4 KB 1 KB 1 KB 128B
Note: Replace C with G for lead-free packaging.
1
1
1
1
1
1
1
1
1
0 17 19 3
0 17 19 3
0 17 19 3
1 23 19 3
1 23 19 3
1 23 19 3
1 33 20 3
1 37 20 3
1 37 20 3
7
7
7
8
8
8
8
8
8
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
PDIP 40-pin package
LQFP 44-pin package
PLCC 44-pin package
PS025001-1105
P R E L I M I N A R Y
Ordering Information
Z8 Encore! XP® F1680 Series
Advance Product Specification
362
Z8 Encore! XP F1680 Series with 4 KB Flash
Standard Temperature: 0 to 70 °C
Z8F0481SH020SC 4 KB 1 KB 512B 128B
Z8F0481HH020SC 4 KB 1 KB 512B 128B
Z8F0481PH020SC 4 KB 1 KB 512B 128B
Z8F0481SJ020SC 4 KB 1 KB 512B 128B
Z8F0481HJ020SC 4 KB 1 KB 512B 128B
Z8F0481PJ020SC 4 KB 1 KB 512B 128B
Z8F0481PM020SC 4 KB 1 KB 512B 128B
Z8F0481AN020SC 4 KB 1 KB 512B 128B
Z8F0481VN020SC 4 KB 1 KB 512B 128B
1
1
1
1
1
1
1
1
1
0 17 18 3
0 17 18 3
0 17 18 3
1 25 18 3
1 25 18 3
1 25 18 3
1 35 20 3
1 39 20 3
1 39 20 3
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
2
2
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
PDIP 40-pin package
LQFP 44-pin package
PLCC 44-pin package
Extended Temperature: –40 to 105 °C
Z8F0481SH020EC 4 KB 1 KB 512B 128B
Z8F0481HH020EC 4 KB 1 KB 512B 128B
Z8F0481PH020EC 4 KB 1 KB 512B 128B
Z8F0481SJ020EC 4 KB 1 KB 512B 128B
Z8F0481HJ020EC 4 KB 1 KB 512B 128B
Z8F0481PJ020EC 4 KB 1 KB 512B 128B
Z8F0481PM020EC 4 KB 1 KB 512B 128B
Z8F0481AN020EC 4 KB 1 KB 512B 128B
Z8F0481VN020EC 4 KB 1 KB 512B 128B
Note: Replace C with G for lead-free packaging.
1
1
1
1
1
1
1
1
1
0 17 18 3
0 17 18 3
0 17 18 3
1 25 18 3
1 25 18 3
1 25 18 3
1 35 20 3
1 39 20 3
1 39 20 3
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
2
2
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
PDIP 40-pin package
LQFP 44-pin package
PLCC 44-pin package
PS025001-1105
P R E L I M I N A R Y
Ordering Information
Z8 Encore! XP® F1680 Series
Advance Product Specification
363
Part Number Suffix Designations
Z8
F
16 2B S H 020 S
C
Environmental Flow:
C = Plastic Standard
Temperature Range (°C):
S = Standard, 0 to 70
E = Extended, -40 to +105
Speed:
020 = 20MHz
Pin Count:
H = 20
J = 28
M=40
N=44
Package:
H = SSOP
P = PDIP
S = SOIC
A = LQFP
V = PLCC
Device Type
Memory Size:
24 = 24KB Flash, 2KB RAM, 0B NVDS
16 = 16KB Flash, 2KB RAM, 256B NVDS
08 = 8KB Flash, 1KB RAM, 128B NVDS
04 = 4KB Flash, 1KB RAM, 128B NVDS
Memory Type:
F = Flash
Device Family
PS025001-1105
P R E L I M I N A R Y
Ordering Information
Z8 Encore! XP® F1680 Series
Advance Product Specification
364
Precharacterization Product
The product represented by this document is newly introduced and ZiLOG has not com-
pleted the full characterization of the product. The document states what ZiLOG knows
about this product at this time, but additional features or nonconformance with some
aspects of the document might be found, either by ZiLOG or its customers in the course of
further application and characterization work. In addition, ZiLOG cautions that delivery
might be uncertain at times, because of start-up yield issues.
ZiLOG, Inc.
532 Race Street
San Jose, CA 95126
Telephone (408) 558-8500
FAX 408 558-8300
Internet: www.zilog.com
Customer Support
For valuable information about downloading other relevant documents or for hardware
and software development tools, visit the ZiLOG web site at www.zilog.com.
PS025001-1105
P R E L I M I N A R Y
Ordering Information
Z8 Encore! XP® F1680 Series
Advance Product Specification
365
Customer Feedback Form
Z8 Encore! XP® F1680 Series High Performance 8-Bit Microcontrollers Product
Specification
If you experience any problems while operating this product, or if you note any inaccuracies while reading
this document, please copy and complete this form and mail it to the address below or go to
www.zilog.com (see Return Information, below). We also welcome your suggestions!
Customer Information
Name
Country
Phone
Fax
Company
Address
City/State/Zip
Email
Product Information
Serial # or Board Fab #/Rev. #
Software Version
Document Number
Host Computer Description/Type
Return Information
ZiLOG
System Test/Customer Support
532 Race Street
San Jose, CA 95126-3432
www.zilog.com
PS025001-1105
P R E L I M I N A R Y
Customer Feedback Form
Z8 Encore! XP® F1680 Series
Advance Product Specification
366
Problem Description or Suggestion
Provide a complete description of the problem or your suggestion. If you are reporting a specific problem,
include all steps leading up to the occurrence of the problem. Attach additional pages as necessary.
PS025001-1105
P R E L I M I N A R Y
Customer Feedback Form
Z8 Encore! XP®F1680 Series
Advance Product Specification
1
Symbols
# 311
% 311
@ 311
Numerics
10-bit ADC 5
40-lead plastic dual-inline package 350, 351, 352
44-lead low-profile quad flat package 352
44-lead plastic lead chip carrier package 353
A
absolute maximum ratings 329
AC characteristics 333
ADC 312
block diagram 180
electrical characteristics and timing 336
overview 179
ADC Channel Register 1 (ADCCTL) 182
ADC Data High Byte Register (ADCDH) 184
ADC Data Low Bit Register (ADCDL) 185, 186, 187, 188
ADCX 312
ADD 312
add - extended addressing 312
add with carry 312
add with carry - extended addressing 312
additional symbols 311
address space 19
ADDX 312
analog block/PWM signal synchronization 181
analog block/PWM signal zynchronization 181
analog signals 15
analog-to-digital converter
overview 179
AND 314
ANDX 314
architecture
voltage measurements 179
arithmetic instructions 312
assembly language programming 308
assembly language syntax 309
PS025001-1105
P R E L I M I N A R Y
Z8 Encore! XP®F1680 Series
Advance Product Specification
2
B
B 311
b 310
baud rate generator, UART 154
BCLR 313
binary number suffix 311
BIT 313
bit 310
clear 313
manipulation instructions 313
set 313
set or clear 313
swap 313
test and jump 315
test and jump if non-zero 315
test and jump if zero 315
bit jump and test if non-zero 315
bit swap 315
block diagram 3
block transfer instructions 313
BRK 315
BSET 313
BSWAP 313, 315
BTJ 315
BTJNZ 315
BTJZ 315
C
calibration and compensation, motor control measurements 182
CALL procedure 315
capture mode 109
capture/compare mode 109
cc 310
CCF 313
characteristics, electrical 329
clear 314
clock phase (SPI) 195
CLR 314
COM 314
compare 109
compare - extended addressing 312
compare mode 109
compare with carry 312
PS025001-1105
P R E L I M I N A R Y
Z8 Encore! XP®F1680 Series
Advance Product Specification
3
compare with carry - extended addressing 312
complement 314
complement carry flag 313
condition code 310
continuous mode 108
control register definition, UART 156
control register, I2C 240
Control Registers 19
counter modes 108
CP 312
CPC 312
CPCX 312
CPU and peripheral overview 5
CPU control instructions 313
CPX 312
current measurement
architecture 179
operation 180
Customer Feedback Form 365
Customer Information 365
D
DA 310, 312
data memory 22
data register, I2C 237
DC characteristics 330
debugger, on-chip 280
DEC 312
decimal adjust 312
decrement 312
decrement and jump non-zero 315
decrement word 312
DECW 312
destination operand 311
device, port availability 45
DI 313
direct address 310
disable interrupts 313
DJNZ 315
dst 311
PS025001-1105
P R E L I M I N A R Y
Z8 Encore! XP®F1680 Series
Advance Product Specification
4
E
EI 313
electrical characteristics 329
ADC 336
flash memory and timing 334
GPIO input data sample timing 340
watch-dog timer 335, 337
electrical noise 179
enable interrupt 313
ER 310
extended addressing register 310
external pin reset 37
eZ8 CPU features 5
eZ8 CPU instruction classes 311
eZ8 CPU instruction notation 309
eZ8 CPU instruction set 308
eZ8 CPU instruction summary 316
F
FCTL register 267, 273
features, Z8 Encore! 1
first opcode map 327
FLAGS 311
flags register 311
flash
controller 5
option bit address space 274
option bit configuration - reset 271
program memory address 0000H 274
program memory address 0001H 275
flash memory 259
arrrangement 260
byte programming 265
code protection 263
configurations 259
control register definitions 267, 273
controller bypass 266
electrical characteristics and timing 334
flash control register 267, 273
flash option bits 264
flash status register 267
flow chart 262
frequency high and low byte registers 269
PS025001-1105
P R E L I M I N A R Y
Z8 Encore! XP®F1680 Series
Advance Product Specification
5
mass erase 265
operation 261
operation timing 263
page erase 265
page select register 268, 269
FPS register 268, 269
FSTAT register 267
G
gated mode 109
general-purpose I/O 45
GPIO 5, 45
alternate functions 47
architecture 46
control register definitions 59
input data sample timing 340
interrupts 58
port A-C pull-up enable sub-registers 63, 64
port A-H address registers 59
port A-H alternate function sub-registers 61
port A-H control registers 60
port A-H data direction sub-registers 61
port A-H high drive enable sub-registers 62
port A-H input data registers 65
port A-H output control sub-registers 62
port A-H output data registers 66
port A-H stop mode recovery sub-registers 63
port availability by device 45
port input timing 341
port output timing 342
H
H 311
HALT 313
halt mode 43, 313
hexadecimal number prefix/suffix 311
I
I2C 5
10-bit address read transaction 228
10-bit address transaction 225
PS025001-1105
P R E L I M I N A R Y
Z8 Encore! XP®F1680 Series
Advance Product Specification
6
10-bit addressed slave data transfer format 225, 233
7-bit address transaction 222, 230
7-bit address, reading a transaction 227
7-bit addressed slave data transfer format 224, 231
7-bit receive data transfer format 228, 234, 235
baud high and low byte registers 244, 245, 252
C status register 245, 248
control register definitions 237
controller 216
controller signals 14
interrupts 219
operation 219
SDA and SCL signals 219
stop and start conditions 221
I2CBRH register 249, 253
I2CCTL register 242
I2CSTAT register 248
IM 310
immediate data 310
immediate operand prefix 311
INC 312
increment 312
increment word 312
INCW 312
indexed 310
indirect address prefix 311
indirect register 310
indirect register pair 310
indirect working register 310
indirect working register pair 310
infrared encoder/decoder (IrDA) 175
Instruction Set 308
instruction set, ez8 CPU 308
instructions
ADC 312
ADCX 312
ADD 312
ADDX 312
AND 314
ANDX 314
arithmetic 312
BCLR 313
BIT 313
bit manipulation 313
PS025001-1105
P R E L I M I N A R Y
Z8 Encore! XP®F1680 Series
Advance Product Specification
7
block transfer 313
BRK 315
BSET 313
BSWAP 313, 315
BTJ 315
BTJNZ 315
BTJZ 315
CALL 315
CCF 313
CLR 314
COM 314
CP 312
CPC 312
CPCX 312
CPU control 313
CPX 312
DA 312
DEC 312
DECW 312
DI 313
DJNZ 315
EI 313
HALT 313
INC 312
INCW 312
IRET 315
JP 315
LD 314
LDC 314
LDCI 313, 314
LDE 314
LDEI 313
LDX 314
LEA 314
load 314
logical 314
MULT 312
NOP 313
OR 314
ORX 314
POP 314
POPX 314
program control 315
PUSH 314
PS025001-1105
P R E L I M I N A R Y
Z8 Encore! XP®F1680 Series
Advance Product Specification
8
PUSHX 314
RCF 313
RET 315
RL 315
RLC 315
rotate and shift 315
RR 315
RRC 315
SBC 312
SCF 313
SRA 315
SRL 316
SRP 313
STOP 314
SUB 312
SUBX 312
SWAP 316
TCM 313
TCMX 313
TM 313
TMX 313
TRAP 315
watch-dog timer refresh 314
XOR 315
XORX 315
instructions, eZ8 classes of 311
interrupt control register 80
interrupt controller 68
architecture 68
interrupt assertion types 71
interrupt vectors and priority 71
operation 70
register definitions 72
software interrupt assertion 72
interrupt edge select register 79
interrupt request 0 register 72
interrupt request 1 register 73
interrupt request 2 register 74
interrupt return 315
interrupt vector listing 68
interrupts
SPI 204
UART 151
IR 310
PS025001-1105
P R E L I M I N A R Y
Z8 Encore! XP®F1680 Series
Advance Product Specification
9
Ir 310
IrDA
architecture 101, 155, 175
block diagram 101, 155, 175
control register definitions 178
operation 101, 155, 175
receiving data 177
transmitting data 176
IRET 315
IRQ0 enable high and low bit registers 75
IRQ1 enable high and low bit registers 76
IRQ2 enable high and low bit registers 78
IRR 310
Irr 310
J
JP 315
jump, conditional, relative, and relative conditional 315
L
LD 314
LDC 314
LDCI 313, 314
LDE 314
LDEI 313, 314
LDX 314
LEA 314
load 314
load constant 313
load constant to/from program memory 314
load constant with auto-increment addresses 314
load effective address 314
load external data 314
load external data to/from data memory and auto-increment addresses 313
load external to/from data memory and auto-increment addresses 314
load instructions 314
load using extended addressing 314
logical AND 314
logical AND/extended addressing 314
logical exclusive OR 315
logical exclusive OR/extended addressing 315
logical instructions 314
PS025001-1105
P R E L I M I N A R Y
Z8 Encore! XP®F1680 Series
Advance Product Specification
10
logical OR 314
logical OR/extended addressing 314
low power modes 42
LQFP
44 lead 352
M
master interrupt enable 70
master-in, slave-out and-in 192
memory
data 22
program 20
MISO 192
mode
capture 109
capture/compare 109
continuous 108
counter 108
gated 109
one-shot 108
PWM 108, 109
modes 109
MOSI 192
motor control measurements
ADC Control register definitions 182
calibration and compensation 182
interrupts 182
overview 179
MULT 312
multiply 312
multiprocessor mode, UART 145
N
noise, electrical 179
NOP (no operation) 313
notation
b 310
cc 310
DA 310
ER 310
IM 310
IR 310
PS025001-1105
P R E L I M I N A R Y
Z8 Encore! XP®F1680 Series
Advance Product Specification
11
Ir 310
IRR 310
Irr 310
p 310
R 310
r 310
RA 310
RR 310
rr 310
vector 310
X 310
notational shorthand 310
O
OCD
architecture 280
auto-baud detector/generator 283
baud rate limits 283
block diagram 280
breakpoints 284
commands 285
control register 290
data format 283
DBG pin to RS-232 Interface 281
debug mode 282
debugger break 315
interface 281
serial errors 284
status register 291
timing 343
OCD commands
execute instruction (12H) 289
read data memory (0DH) 288
read OCD control register (05H) 287
read OCD revision (00H) 286
read OCD status register (02H) 286
read program counter (07H) 287
read program memory (0BH) 288
read program memory CRC (0EH) 289
read register (09H) 287
read runtime counter (03H) 286
step instruction (10H) 289
stuff instruction (11H) 289
PS025001-1105
P R E L I M I N A R Y
Z8 Encore! XP®F1680 Series
Advance Product Specification
12
write data memory (0CH) 288
write OCD control register (04H) 286
write program counter (06H) 287
write program memory (0AH) 288
write register (08H) 287
on-chip debugger (OCD) 280
on-chip debugger signals 16
on-chip oscillator 302
one-shot mode 108
opcode map
abbreviations 326
cell description 325
first 327
second after 1FH 328
operation 181
current measurement 180
voltage measurement timing diagram 181
Operational Description 30, 42, 45, 68, 81, 114, 134, 138, 175, 179, 189, 254, 257, 259, 271, 280,
292, 296, 302, 307
OR 314
ordering information 354
ORX 314
oscillator signals 16
P
p 310
packaging
20-pin PDIP 346, 347
20-pin SSOP 347, 350, 351
28-pin PDIP 348
28-pin SOIC 350
LQFP
44 lead 352
PDIP 350, 351, 352
PLCC
44 lead 353
part selection guide 2
PC 311
PDIP 350, 351, 352
peripheral AC and DC electrical characteristics 334
PHASE=0 timing (SPI) 196
PHASE=1 timing (SPI) 197
pin characteristics 17
PS025001-1105
P R E L I M I N A R Y
Z8 Encore! XP®F1680 Series
Advance Product Specification
13
Pin Descriptions 9
PLCC
44 lead 353
polarity 310
POP 314
pop using extended addressing 314
POPX 314
port availability, device 45
port input timing (GPIO) 341
port output timing, GPIO 342
power supply signals 16
power-on and voltage brown-out electrical characteristics and timing 334
power-on reset (POR) 32
Problem Description or Suggestion 366
Product Information 365
program control instructions 315
program counter 311
program memory 20
PUSH 314
push using extended addressing 314
PUSHX 314
PWM mode 108, 109
PxADDR register 59
PxCTL register 60
R
R 310
r 310
RA
register address 310
RCF 313
receive
7-bit data transfer format (I2C) 228, 234, 235
IrDA data 177
receiving UART data-interrupt-driven method 143
receiving UART data-polled method 142
register 210, 310
baud low and high byte (I2C) 244, 245, 252
baud rate high and low byte (SPI) 214
control (SPI) 207
control, I2C 240
data, SPI 206, 207
flash control (FCTL) 267, 273
PS025001-1105
P R E L I M I N A R Y
Z8 Encore! XP®F1680 Series
Advance Product Specification
14
flash high and low byte (FFREQH and FREEQL) 269
flash page select (FPS) 268, 269
flash status (FSTAT) 267
GPIO port A-H address (PxADDR) 59
GPIO port A-H alternate function sub-registers 62
GPIO port A-H control address (PxCTL) 60
GPIO port A-H data direction sub-registers 61
I2C baud rate high (I2CBRH) 249, 253
I2C control (I2CCTL) 242
I2C status 245, 248
I2C status (I2CSTAT) 248
mode, SPI 210
OCD control 290
OCD status 291
SPI baud rate high byte (SPIBRH) 215
SPI baud rate low byte (SPIBRL) 215
SPI control (SPICTL) 208
SPI data (SPIDATA) 206, 207
SPI status (SPISTAT) 212
status, SPI 212
UARTx baud rate high byte (UxBRH) 170
UARTx baud rate low byte (UxBRL) 171
UARTx Control 0 (UxCTL0) 163, 170
UARTx control 1 (UxCTL1) 113, 165, 167, 168
UARTx receive data (UxRXD) 157
UARTx status 0 (UxSTAT0) 158, 159
UARTx status 1 (UxSTAT1) 161
UARTx transmit data (UxTXD) 157
watch-dog timer control (WDTCTL) 40, 255, 256, 300, 301
watch-dog timer reload high byte (WDTH) 137
register file 19
register pair 310
register pointer 311
registers
ADC channel 1 182
ADC data high byte 184
ADC data low bit 185, 186, 187, 188
reset
and stop mode characteristics 31
and stop mode recovery 30
carry flag 313
sources 32
RET 315
return 315
PS025001-1105
P R E L I M I N A R Y
Z8 Encore! XP®F1680 Series
Advance Product Specification
15
Return Information 365
RL 315
RLC 315
rotate and shift instuctions 315
rotate left 315
rotate left through carry 315
rotate right 315
rotate right through carry 315
RP 311
RR 310, 315
rr 310
RRC 315
S
SBC 312
SCF 313
SCK 192
SDA and SCL (IrDA) signals 219
second opcode map after 1FH 328
serial clock 192
serial peripheral interface (SPI) 190
set carry flag 313
set register pointer 313
shift right arithmatic 315
shift right logical 316
signal descriptions 13
slave data transfer formats (I2C) 225, 233
slave select 193
software trap 315
source operand 311
SP 311
SPI
architecture 190
baud rate generator 205
baud rate high and low byte register 214
clock phase 195
configured as slave 203
control register 207
control register definitions 206
data register 206, 207
error detection 203
interrupts 204
mode fault error 203
PS025001-1105
P R E L I M I N A R Y
Z8 Encore! XP®F1680 Series
Advance Product Specification
16
mode register 210
multi-master operation 200
operation 192
overrun error 203, 204
signals 192
single master, multiple slave system 202
single master,single slave system 201
status register 212
timing, PHASE = 0 196
timing, PHASE=1 197
SPI controller signals 14
SPI mode (SPIMODE) 210
SPIBRH register 215
SPIBRL register 215
SPICTL register 208
SPIDATA register 206, 207
SPIMODE register 210
SPISTAT register 212
SRA 315
src 311
SRL 316
SRP 313
SS, SPI signal 192
stack pointer 311
STOP 314
stop mode 42, 314
stop mode recovery
sources 38, 40
using a GPIO port pin transition 39
using watch-dog timer time-out 38
SUB 312
subtract 312
subtract - extended addressing 312
subtract with carry 312
subtract with carry - extended addressing 312
SUBX 312
SWAP 316
swap nibbles 316
symbols, additional 311
T
TCM 313
TCMX 313
PS025001-1105
P R E L I M I N A R Y
Z8 Encore! XP®F1680 Series
Advance Product Specification
17
test complement under mask 313
test complement under mask - extended addressing 313
test under mask 313
test under mask - extended addressing 313
tiing diagram, voltage measurement 181
timer signals 15
timers 81
architecture 81, 114
block diagram 82, 115
capture mode 92, 93, 109
capture/compare mode 96, 109
compare mode 94, 109
continuous mode 86, 108
counter mode 87, 88
counter modes 108
gated mode 95, 109
one-shot mode 83, 108
operating mode 83
PWM mode 89, 90, 108, 109
reading the timer count values 100
reload high and low byte registers 103, 124, 125
timer control register definitions 103
timer output signal operation 100
triggered one-shot mode 84
timers 0-3
control registers 106, 108, 111, 112
high and low byte registers 103, 104, 106, 124
TM 313
TMX 313
tools, hardware and software 364
transmit
IrDA data 176
transmitting UART data-polled method 140
transmitting UART dat-interrupt-driven method 141
TRAP 315
U
UART 5
architecture 138
asynchronous data format without/with parity 140
baud rate generator 154
baud rates table 172, 173, 174
control register definitions 156
PS025001-1105
P R E L I M I N A R Y
Z8 Encore! XP®F1680 Series
Advance Product Specification
18
controller signals 14
data format 139
interrupts 151
multiprocessor mode 145
receiving data using interrupt-driven method 143
receiving data using the polled method 142
transmitting data usin the interrupt-driven method 141
transmitting data using the polled method 140
x baud rate high and low registers 170
x control 0 and control 1 registers 163, 164
x status 0 and status 1 registers 157, 161
UxBRH register 170
UxBRL register 171
UxCTL0 register 163, 170
UxCTL1 register 113, 165, 167, 168
UxRXD register 157
UxSTAT0 register 158, 159
UxSTAT1 register 161
UxTXD register 157
V
vector 310
voltage brown-out reset (VBR) 35
voltage measurement timing diagram 181
W
watch-dog timer
approximate time-out delay 135
approximate time-out delays 134, 254, 257, 292, 296, 307
CNTL 35, 36
control register 255, 256, 299, 300
electrical characteristics and timing 335, 337
interrupt in noromal operation 135
interrupt in STOP mode 135
operation 134, 254, 257, 292, 296, 307
refresh 135, 314
reload unlock sequence 136
reload upper, high and low registers 137
reset 37
reset in normal operation 136
reset in STOP mode 136
time-out response 135
PS025001-1105
P R E L I M I N A R Y
Z8 Encore! XP®F1680 Series
Advance Product Specification
19
WDTCTL register 40, 255, 256, 300, 301
WDTH register 137
working register 310
working register pair 310
X
X 310
XOR 315
XORX 315
Z
Z8 Encore!
block diagram 3
features 1
part selection guide 2
PS025001-1105
P R E L I M I N A R Y
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