Z8R3221VN020SG [IXYS]
Microcontroller, 8-Bit, MROM, 20MHz, CMOS, PQCC44, PLASTIC, LCC-44;
| 型号： | Z8R3221VN020SG |
| 厂家： | 
IXYS CORPORATION |
| 描述： | Microcontroller, 8-Bit, MROM, 20MHz, CMOS, PQCC44, PLASTIC, LCC-44 微控制器 |
| 文件： | 总309页 (文件大小：2157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Performance 8-Bit Microcontrollers
®
Z8 Encore! 64K Series
Product Specification
PS019913-0305
Preliminary
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Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com
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532 Race Street
San Jose, CA 95126
Telephone: 408.558.8500
Fax: 408.558.8300
www.ZiLOG.com
Document Disclaimer
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products and/or service names mentioned herein may be trademarks of the companies with which
they are associated.
©2005 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded.
ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF
ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS
DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered
by warranty and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of
Sale. ZiLOG, Inc. makes no warranty of merchantability or fitness for any purpose Except with the
express written approval of ZiLOG, use of information, devices, or technology as critical components
of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this
document under any intellectual property rights.
PS019913-0305
P r e l i m i n a r y
Z8 Encore!® 64K Series
Product Specification
iii
Revision History
Each instance in Table 1 reflects a change to this document from its previous revi-
sion. To see more detail, click the appropriate link in the table.
Table 1. Revision History of this Document
Revision
Date
Level
Section
Description
Page #
January
2005
12
Added Die Form Sales information to Table 1.
2
March
2005
13
Provided timing equation when the Baud Rate Generator for a peripheral 109, 115,
is used as a simple timer. Closes CR#5618.
131, 137,
155
PS019913-0305
P r e l i m i n a r y
Z8 Encore!® 64K Series
Product Specification
iv
Table of Contents
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Manual Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xix
Manual Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
Safeguards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxi
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
CPU and Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
eZ8 CPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Purpose I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
10-Bit Analog-to-Digital Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Signal and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Available Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Address Space 17
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Register File Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PS019913-0305
P r e l i m i n a r y
Table of Contents
Z8 Encore!® 64K Series
Product Specification
v
Control Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Reset and STOP Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Watch-Dog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
On-Chip Debugger Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
STOP Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
STOP Mode Recovery Using Watch-Dog Timer Time-Out . . . . . . . . . . . . . . . . . . . 48
STOP Mode Recovery Using a GPIO Port Pin Transition HALT . . . . . . . . . . . . . . 48
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
General-Purpose I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
GPIO Port Availability By Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
GPIO Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
GPIO Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Port A-H Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Port A-H Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Port A-H Input Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Port A–H Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Interrupt Vector Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Master Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Interrupt Vectors and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Software Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Interrupt Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Interrupt Request 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Interrupt Request 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Interrupt Request 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
PS019913-0305
P r e l i m i n a r y
Table of Contents
Z8 Encore!® 64K Series
Product Specification
vi
IRQ0 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
IRQ1 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
IRQ2 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Interrupt Edge Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Interrupt Port Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Timers 75
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Timer Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Reading the Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Timer Output Signal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Timer 0-3 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Timer Reload High and Low Byte Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Timer 0-3 PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Timer 0-3 Control 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Timer 0-3 Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Watch-Dog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Watch-Dog Timer Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Watch-Dog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Watch-Dog Timer Reload Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Watch-Dog Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Watch-Dog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Watch-Dog Timer Reload Upper, High and Low Byte Registers . . . . . . . . . . . . . . 95
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Transmitting Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Transmitting Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . . 101
Receiving Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Receiving Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . . . . 103
Clear To Send (CTS) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
MULTIPROCESSOR (9-bit) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
External Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
PS019913-0305
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Table of Contents
Z8 Encore!® 64K Series
Product Specification
vii
UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
UART Control Register Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
UART Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
UART Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
UART Status 0 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
UART Status 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
UART Control 0 and Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
UART Address Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
UART Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Transmitting IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Receiving IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Infrared Encoder/Decoder Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . 123
Serial Peripheral Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
SPI Clock Phase and Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Multi-Master Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Slave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
SPI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SPI Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SPI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
SPI Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
SPI Diagnostic State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
SPI Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
I2C Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
SDA and SCL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
I2C Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Software Control of I2C Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
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Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Master Write and Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Address Only Transaction with a 7-bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Write Transaction with a 7-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Address Only Transaction with a 10-bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Write Transaction with a 10-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Read Transaction with a 7-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Read Transaction with a 10-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
I2C Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
I2C Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
I2C Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
I2C Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
I2C Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
I2C Diagnostic State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
I2C Diagnostic Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
DMA0 and DMA1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Configuring DMA0 and DMA1 for Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . 161
DMA_ADC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Configuring DMA_ADC for Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
DMA Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
DMAx Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
DMAx I/O Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
DMAx Address High Nibble Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
DMAx Start/Current Address Low Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . 165
DMAx End Address Low Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
DMA_ADC Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
DMA_ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
DMA Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Automatic Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Single-Shot Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
DMA Control of the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
ADC Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
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ADC Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
ADC Data Low Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Timing Using the Flash Frequency Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Flash Read Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Flash Write/Erase Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Byte Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Flash Controller Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Flash Controller Behavior in Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Flash Control Register Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Page Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Flash Sector Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Flash Frequency High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Read-Only Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
ROM Code Protection Against External Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
ROM Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Page Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Option Bit Configuration By Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Option Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Program Memory Address 0000H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Program Memory Address 0001H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
OCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
OCD Auto-Baud Detector/Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
OCD Serial Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
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Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
On-Chip Debugger Control Register Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
OCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
OCD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Oscillator Operation with an External RC Network . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
On-Chip Peripheral AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 222
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
General Purpose I/O Port Input Data Sample Timing . . . . . . . . . . . . . . . . . . . . . . 228
General Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
SPI Master Mode Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
eZ8 CPU Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Assembly Language Programming Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
eZ8 CPU Instruction Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
eZ8 CPU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Opcode Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Part Number Suffix Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Document Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
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Table of Contents
Z8 Encore!® 64K Series
Product Specification
xii
List of Figures
Figure 1.
Z8 Encore!® 64K Series Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. 64K Series in 40-Pin Dual Inline Package (PDIP) . . . . . . . . . . . . . . . . . . . . 7
Figure 3. 64K Series in 44-Pin Plastic Leaded Chip Carrier (PLCC) . . . . . . . . . . . . . . 8
Figure 4. 64K Series in 44-Pin Low-Profile Quad Flat Package (LQFP) . . . . . . . . . . . 9
Figure 5. 64K Series in 64-Pin Low-Profile Quad Flat Package (LQFP) . . . . . . . . . . 10
Figure 6. 64K Series in 68-Pin Plastic Leaded Chip Carrier (PLCC) . . . . . . . . . . . . . 11
Figure 7. 64K Series in 80-Pin Quad Flat Package (QFP) . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Power-On Reset Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 9. Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 10. GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 11. Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 12. Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 13. UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 14. UART Asynchronous Data Format without Parity . . . . . . . . . . . . . . . . . . 100
Figure 15. UART Asynchronous Data Format with Parity . . . . . . . . . . . . . . . . . . . . . 100
Figure 16. UART Asynchronous MULTIPROCESSOR Mode Data Format . . . . . . 104
Figure 17. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity) 106
Figure 18. UART Receiver Interrupt Service Routine Flow . . . . . . . . . . . . . . . . . . . 108
Figure 19. Infrared Data Communication System Block Diagram . . . . . . . . . . . . . . . 119
Figure 20. Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 21. Infrared Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 22. SPI Configured as a Master in a Single Master, Single Slave System. . . . 124
Figure 23. SPI Configured as a Master in a Single Master, Multiple Slave System . . 125
Figure 24. SPI Configured as a Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 25. SPI Timing When PHASE is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 26. SPI Timing When PHASE is 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 27. I2C Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 28. 7-Bit Address Only Transaction Format . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 29. 7-Bit Addressed Slave Data Transfer Format. . . . . . . . . . . . . . . . . . . . . . . 144
Figure 30. 10-Bit Address Only Transaction Format . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 31. 10-Bit Addressed Slave Data Transfer Format . . . . . . . . . . . . . . . . . . . . . 146
Figure 32. Receive Data Transfer Format for a 7-Bit Addressed Slave . . . . . . . . . . . 148
Figure 33. Receive Data Format for a 10-Bit Addressed Slave . . . . . . . . . . . . . . . . . 149
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xiii
Figure 34. Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 35. Flash Memory Arrangement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 36. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 37. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232
Interface (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 38. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232
Interface (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 39. OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 40. Recommended 20MHz Crystal Oscillator Configuration . . . . . . . . . . . . . 208
Figure 41. Connecting the On-Chip Oscillator to an External RC Network . . . . . . . . 209
Figure 42. Typical RC Oscillator Frequency as a Function of the External Capacitance
with a 45kW Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 43. Typical Active Mode Idd Versus System Clock Frequency . . . . . . . . . . . 216
Figure 44. Maximum Active Mode Idd Versus System Clock Frequency . . . . . . . . . 217
Figure 45. Typical HALT Mode Idd Versus System Clock Frequency . . . . . . . . . . . 218
Figure 46. Maximum HALT Mode Icc Versus System Clock Frequency. . . . . . . . . . 219
Figure 47. Maximum STOP Mode Idd with VBO enabled versus Power Supply
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 48. Maximum STOP Mode Idd with VBO Disabled versus Power Supply
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 49. Analog-to-Digital Converter Frequency Response . . . . . . . . . . . . . . . . . . 226
Figure 50. Port Input Sample Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 51. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 52. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 53. SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 54. SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 55. I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 56. UART Timing with CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 57. UART Timing without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 58. Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 59. Opcode Map Cell Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Figure 60. First Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 61. Second Opcode Map after 1FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Figure 62. 40-Lead Plastic Dual-Inline Package (PDIP) . . . . . . . . . . . . . . . . . . . . . . 260
Figure 63. 44-Lead Low-Profile Quad Flat Package (LQFP) . . . . . . . . . . . . . . . . . . . 261
Figure 64. 44-Lead Plastic Lead Chip Carrier Package (PLCC) . . . . . . . . . . . . . . . . 262
Figure 65. 64-Lead Low-Profile Quad Flat Package (LQFP) . . . . . . . . . . . . . . . . . . . 262
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Product Specification
xiv
Figure 66. 68-Lead Plastic Lead Chip Carrier Package (PLCC) . . . . . . . . . . . . . . . . 263
Figure 67. 80-Lead Quad-Flat Package (QFP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
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Z8 Encore!® 64K Series
Product Specification
xv
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Revision History of this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Z8 Encore!® 64K Series Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . 2
Z8 Encore!® 64K Series Package Options. . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Characteristics of the 64K Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Z8 Encore® 64K Series Program Memory Maps . . . . . . . . . . . . . . . . . . . . 18
Z8 Encore!® 64K Series Information Area Map . . . . . . . . . . . . . . . . . . . . . 20
64K Series Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reset and STOP Mode Recovery Characteristics and Latency . . . . . . . . . . 43
Table 10. Reset Sources and Resulting Reset Type . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 11. STOP Mode Recovery Sources and Resulting Action . . . . . . . . . . . . . . . . 47
Table 12. Port Availability by Device and Package Type . . . . . . . . . . . . . . . . . . . . . . 51
Table 13. Port Alternate Function Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 14. Port A-H GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . . . . 55
Table 15. GPIO Port Registers and Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 16. Port A–H Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 17. Port A-H Data Direction Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 18. Port A-H Alternate Function Sub-Registers. . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 19. Port A-H Output Control Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 20. Port A–H High Drive Enable Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 21. Port A–H Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 22. Port A-H STOP Mode Recovery Source Enable Sub-Registers . . . . . . . . . 60
Table 23. Port A-H Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 24. Interrupt Vectors in Order of Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 25. Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 26. Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 27. Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 28. IRQ0 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 29. IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . . . . 69
Table 30. IRQ0 Enable Low Bit Register (IRQ0ENL) . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 31. IRQ1 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 32. IRQ1 Enable Low Bit Register (IRQ1ENL) . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 33. IRQ2 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
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xvi
Table 34. IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . . . . 71
Table 35. IRQ2 Enable Low Bit Register (IRQ2ENL) . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 36. IRQ2 Enable High Bit Register (IRQ2ENH) . . . . . . . . . . . . . . . . . . . . . . . 72
Table 37. Interrupt Edge Select Register (IRQES) . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 38. Interrupt Port Select Register (IRQPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 39. Interrupt Control Register (IRQCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 40. Timer 0-3 High Byte Register (TxH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 41. Timer 0-3 Low Byte Register (TxL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 42. Timer 0-3 Reload High Byte Register (TxRH) . . . . . . . . . . . . . . . . . . . . . . 86
Table 43. Timer 0-3 Reload Low Byte Register (TxRL) . . . . . . . . . . . . . . . . . . . . . . . 86
Table 44. Timer 0-3 PWM High Byte Register (TxPWMH) . . . . . . . . . . . . . . . . . . . 87
Table 45. Timer 0-3 PWM Low Byte Register (TxPWML) . . . . . . . . . . . . . . . . . . . . 87
Table 46. Timer 0-3 Control 0 Register (TxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 47. Timer 0-3 Control 1 Register (TxCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 48. Watch-Dog Timer Approximate Time-Out Delays . . . . . . . . . . . . . . . . . . . 92
Table 49. Watch-Dog Timer Control Register (WDTCTL) . . . . . . . . . . . . . . . . . . . . 94
Table 50. Watch-Dog Timer Reload Upper Byte Register (WDTU) . . . . . . . . . . . . . 96
Table 51. Watch-Dog Timer Reload High Byte Register (WDTH) . . . . . . . . . . . . . . 96
Table 52. Watch-Dog Timer Reload Low Byte Register (WDTL) . . . . . . . . . . . . . . . 97
Table 53. UART Transmit Data Register (UxTXD) . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 54. UART Receive Data Register (UxRXD) . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 55. UART Status 0 Register (UxSTAT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 56. UART Status 1 Register (UxSTAT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 57. UART Control 0 Register (UxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 58. UART Control 1 Register (UxCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 59. UART Address Compare Register (UxADDR) . . . . . . . . . . . . . . . . . . . . . 115
Table 60. UART Baud Rate High Byte Register (UxBRH) . . . . . . . . . . . . . . . . . . . 115
Table 61. UART Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 62. UART Baud Rate Low Byte Register (UxBRL) . . . . . . . . . . . . . . . . . . . . 116
Table 63. SPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation . . . 127
Table 64. SPI Data Register (SPIDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 65. SPI Control Register (SPICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 66. SPI Status Register (SPISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 67. SPI Mode Register (SPIMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 68. SPI Diagnostic State Register (SPIDST) . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 69. SPI Baud Rate High Byte Register (SPIBRH) . . . . . . . . . . . . . . . . . . . . . 137
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Table 70. SPI Baud Rate Low Byte Register (SPIBRL) . . . . . . . . . . . . . . . . . . . . . . 137
Table 71. I2C Data Register (I2CDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 72. I2C Status Register (I2CSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 73. I2C Control Register (I2CCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 74. I2C Baud Rate High Byte Register (I2CBRH) . . . . . . . . . . . . . . . . . . . . . 155
Table 75. I2C Baud Rate Low Byte Register (I2CBRL) . . . . . . . . . . . . . . . . . . . . . . 156
Table 76. I2C Diagnostic State Register (I2CDST) . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 77. I2C Diagnostic Control Register (I2CDIAG) . . . . . . . . . . . . . . . . . . . . . . 159
Table 78. DMAx Control Register (DMAxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 79. DMAx I/O Address Register (DMAxIO) . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 80. DMAx Address High Nibble Register (DMAxH) . . . . . . . . . . . . . . . . . . . 164
Table 81. DMAx Start/Current Address Low Byte Register (DMAxSTART) . . . . . 165
Table 82. DMAx End Address Low Byte Register (DMAxEND) . . . . . . . . . . . . . . 166
Table 83. DMA_ADC Register File Address Example . . . . . . . . . . . . . . . . . . . . . . . 166
Table 84. DMA_ADC Address Register (DMAA_ADDR) . . . . . . . . . . . . . . . . . . . 167
Table 85. DMA_ADC Control Register (DMAACTL) . . . . . . . . . . . . . . . . . . . . . . . 168
Table 86. DMA_ADC Status Register (DMAA_STAT) . . . . . . . . . . . . . . . . . . . . . . 169
Table 87. ADC Control Register (ADCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 88. ADC Data High Byte Register (ADCD_H) . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 89. ADC Data Low Bits Register (ADCD_L) . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 90. Flash Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 91. Flash Memory Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 92. 64K Series Information Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 93. Flash Control Register (FCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 94. Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 95. Page Select Register (FPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 96. Flash Sector Protect Register (FPROT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 97. Flash Frequency High Byte Register (FFREQH) . . . . . . . . . . . . . . . . . . . 188
Table 98. Flash Frequency Low Byte Register (FFREQL) . . . . . . . . . . . . . . . . . . . . 188
Table 99. Z8 Encore!® 64K Series Memory Configurations . . . . . . . . . . . . . . . . . . 189
Table 100. Z8 Encore!® 64K Series ROM Information Area Map . . . . . . . . . . . . . . 189
Table 101. Page Select Register (RPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 102. Flash Option Bits At Program Memory Address 0000H . . . . . . . . . . . . . . 192
Table 103. ROM Option Bits At Program Memory Address 0000H . . . . . . . . . . . . . 192
Table 104. Options Bits at Program Memory Address 0001H . . . . . . . . . . . . . . . . . . 194
Table 105. OCD Baud-Rate Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
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xviii
Table 106. On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 107. OCD Control Register (OCDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 108. OCD Status Register (OCDSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 109. Recommended Crystal Oscillator Specifications (20MHz Operation) . . . 208
Table 110. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 111. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 112. Power-On Reset and Voltage Brown-Out Electrical Characteristics and
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 113. Reset and STOP Mode Recovery Pin Timing . . . . . . . . . . . . . . . . . . . . . . 223
Table 114. External RC Oscillator Electrical Characteristics and Timing . . . . . . . . . 223
Table 115. Flash Memory Electrical Characteristics and Timing . . . . . . . . . . . . . . . . 224
Table 116. Watch-Dog Timer Electrical Characteristics and Timing . . . . . . . . . . . . . 224
Table 117. Analog-to-Digital Converter Electrical Characteristics and Timing . . . . . 225
Table 118. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 119. GPIO Port Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 120. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Table 121. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 122. SPI Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 123. SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 124. I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 125. UART Timing with CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 126. UART Timing without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 127. Notational Shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 128. Additional Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Table 129. Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Table 130. Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 131. Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 132. Block Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 133. CPU Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 134. Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 135. Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 136. Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 137. Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 138. eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 139. Opcode Map Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
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Z8 Encore!® 64K Series
Product Specification
xix
Manual Objectives
This Product Specification provides detailed operating information for the Flash and ROM
devices within the Z8 Encore!® 64K Series Microcontroller (MCU) products. Within this
document, the Z8F642x, Z8F482x, Z8F322x, Z8F242x, Z8F162x, Z8R642x, Z8R482x,
Z8R322x, Z8R242x, and Z8R162x devices are referred to collectively as the Z8 Encore!®
64K Series unless specifically stated otherwise.
About This Manual
ZiLOG recommends that the user read and understand everything in this manual before
setting up and using the product. However, we recognize that there are different styles of
learning. Therefore, we have designed this Product Specification to be used either as a
how to procedural manual or a reference guide to important data.
Intended Audience
This document is written for ZiLOG customers who are experienced at working with
microcontrollers, integrated circuits, or printed circuit assemblies.
Manual Conventions
The following assumptions and conventions are adopted to provide clarity and ease of use:
Courier Typeface
Commands, code lines and fragments, bits, equations, hexadecimal addresses, and various
executable items are distinguished from general text by the use of the Couriertypeface.
Where the use of the font is not indicated, as in the Index, the name of the entity is pre-
sented in upper case.
•
Example: FLAGS[1] is smrf.
Hexadecimal Values
Hexadecimal values are designated by uppercase H suffix and appear in the Courier
typeface.
•
Example: R1 is set to F8H.
Brackets
The square brackets, [ ], indicate a register or bus.
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Z8 Encore!® 64K Series
Product Specification
xx
•
Example: for the register R1[7:0], R1 is an 8-bit register, R1[7] is the most significant
bit, and R1[0] is the least significant bit.
Braces
The curly braces, { }, indicate a single register or bus created by concatenating some com-
bination of smaller registers, buses, or individual bits.
•
Example: the 12-bit register address {0H, RP[7:4], R1[3:0]} is composed of a 4-bit
hexadecimal value (0H) and two 4-bit register values taken from the Register Pointer
(RP) and Working Register R1. 0His the most significant nibble (4-bit value) of the
12-bit register, and R1[3:0] is the least significant nibble of the 12-bit register.
Parentheses
The parentheses, ( ), indicate an indirect register address lookup.
•
Example: (R1) is the memory location referenced by the address contained in the
Working Register R1.
Parentheses/Bracket Combinations
The parentheses, ( ), indicate an indirect register address lookup and the square brackets,
[ ], indicate a register or bus.
•
Example: assume PC[15:0] contains the value 1234h. (PC[15:0]) then refers to the
contents of the memory location at address 1234h.
Use of the Words Set, Reset and Clear
The word set implies that a register bit or a condition contains a logical 1. The words reset
or clear imply that a register bit or a condition contains a logical 0. When either of these
terms is followed by a number, the word logical may not be included; however, it is
implied.
Notation for Bits and Similar Registers
A field of bits within a register is designated as: Register[n:n].
•
Example: ADDR[15:0] refers to bits 15 through bit 0 of the Address.
Use of the Terms LSB, MSB, lsb, and msb
In this document, the terms LSB and MSB, when appearing in upper case, mean least sig-
nificant byte and most significant byte, respectively. The lowercase forms, lsb and msb,
mean least significant bit and most significant bit, respectively.
Use of Initial Uppercase Letters
Initial uppercase letters designate settings and conditions in general text.
•
Example 1: The receiver forces the SCL line to Low.
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Z8 Encore!® 64K Series
Product Specification
xxi
•
Example 2: The Master can generate a Stop condition to abort the transfer.
Use of All Uppercase Letters
The use of all uppercase letters designates the names of states, modes, and commands.
•
•
•
Example 1: The bus is considered BUSY after the Start condition.
Example 2: A START command triggers the processing of the initialization sequence.
Example 3: STOP mode
Bit Numbering
Bits are numbered from 0 to n–1 where n indicates the total number of bits. For example,
the 8 bits of a register are numbered from 0 to 7.
Safeguards
It is important that all users understand the following safety terms, which are defined here.
Caution:
Indicates a procedure or file may become corrupted if the user does not fol-
low directions.
Trademarks
ZiLOG®, eZ8, Z8 Encore!®, and Z8® are trademarks of ZiLOG, Inc. in the U.S.A. and
other countries. All other trademarks are the property of their respective corporations.
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Manual Objectives
Z8 Encore!® 64K Series
Product Specification
1
Introduction
The Z8 Encore!® MCU family of products are a line of ZiLOG microcontroller products
based upon the 8-bit eZ8 CPU. The Z8 Encore!® 64K Series, hereafter referred to collec-
tively as the Z8 Encore!® or the 64K Series adds Flash memory to ZiLOG’s extensive line
of 8-bit microcontrollers. The Flash in-circuit programming capability allows for faster
development time and program changes in the field. The Z8 Encore!® 64K Series also
includes ROM devices that are pin- and function-compatible with the Flash products. The
ROM devices provide a low-cost alternative for customers who do not require the repro-
grammability of the Flash devices. The new eZ8 CPU is upward compatible with existing
Z8® instructions. The rich peripheral set of the Z8 Encore!® makes it suitable for a variety
of applications including motor control, security systems, home appliances, personal elec-
tronic devices, and sensors.
Features
•
•
20MHz eZ8 CPU
Up to 64KB Flash (or optional ROM) with in-circuit programming capability (Flash
only)
•
•
•
•
•
•
•
•
•
•
•
•
Up to 4KB register RAM
12-channel, 10-bit analog-to-digital converter (ADC)
Two full-duplex 9-bit UARTs with bus transceiver Driver Enable control
I2C
Serial Peripheral Interface
Two Infrared Data Association (IrDA)-compliant infrared encoder/decoders
Up to four 16-bit timers with capture, compare, and PWM capability
Watch-Dog Timer (WDT) with internal RC oscillator
3-channel DMA
Up to 60 I/O pins
24 interrupts with configurable priority
On-Chip Debugger
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Introduction
Z8 Encore!® 64K Series
Product Specification
2
•
•
•
•
Voltage Brown-out Protection (VBO)
Power-On Reset (POR)
3.0-3.6V operating voltage with 5V-tolerant inputs
0° to +70°C and -40° to +105°C operating temperature ranges
Part Selection Guide
Table 1 identifies the basic features and package styles available for each device within the
Z8 Encore!® Z8 Encore!® product line.
®
Table 1. Z8 Encore! 64K Series Part Selection Guide
Flash/
Part
Number
ROM RAM
16-bit Timers ADC UARTs
40/44-pin 64/68-pin 80-pin
2
(KB) (KB) I/O with PWM Inputs with IrDA I C SPI packages packages package
Z8X1621
Z8X1622
Z8X2421
Z8X2422
Z8X3221
Z8X3222
Z8X4821
Z8X4822
Z8X4823
Z8X6421
Z8X6422
Z8X6423
16
16
24
24
32
32
48
48
48
64
64
64
2
2
2
2
2
2
4
4
4
4
4
4
31
46
31
46
31
46
31
46
60
31
46
60
3
4
3
4
3
4
3
4
4
3
4
4
8
12
8
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
12
8
12
8
12
12
8
X
X
X
12
12
X
Die Form
Sales
Please
contact
ZiLOG
Flash: X=F, ROM: X=R
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Introduction
Z8 Encore!® 64K Series
Product Specification
3
Block Diagram
Figure 1 illustrates the block diagram of the architecture of the Z8 Encore!® 64K Series.
XTAL / RC
Oscillator
On-Chip
Debugger
POR/VBO
& Reset
Controller
eZ8
CPU
Interrupt
Controller
WDT with
RC Oscillator
System
Clock
Memory Busses
Register Bus
2
Flash/ROM
Controller
RAM
Controller
Timers
UARTs
I C
SPI
ADC
DMA
IrDA
Flash/ROM
Memory
RAM
GPIO
Figure 1. Z8 Encore!® 64K Series Block Diagram
CPU and Peripheral Overview
eZ8 CPU Features
The eZ8, ZiLOG’s latest 8-bit Central Processing Unit (CPU), meets the continuing
demand for faster and more code-efficient microcontrollers. The eZ8 CPU executes a
superset of the original Z8 instruction set. The eZ8 CPU features include:
•
Direct register-to-register architecture allows each register to function as an
accumulator, improving execution time and decreasing the required program memory
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Introduction
Z8 Encore!® 64K Series
Product Specification
4
•
Software stack allows much greater depth in subroutine calls and interrupts than
hardware stacks
•
•
•
Compatible with existing Z8® code
Expanded internal Register File allows access of up to 4KB
New instructions improve execution efficiency for code developed using higher-level
programming languages, including C
•
•
Pipelined instruction fetch and execution
New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC,
LDCI, LEA, MULT, and SRL
•
•
•
•
New instructions support 12-bit linear addressing of the Register File
Up to 10 MIPS operation
C-Compiler friendly
2-9 clock cycles per instruction
For more information regarding the eZ8 CPU, refer to the eZ8 CPU User Manual avail-
able for download at www.zilog.com.
General Purpose I/O
The 64K Series features seven 8-bit ports (Ports A-G) and one 4-bit port (Port H) for gen-
eral purpose I/O (GPIO). Each pin is individually programmable. All ports (except B and
H) support 5V-tolerant inputs.
Flash Controller
The Flash Controller programs and erases the Flash memory.
10-Bit Analog-to-Digital Converter
The Analog-to-Digital Converter (ADC) converts an analog input signal to a 10-bit binary
number. The ADC accepts inputs from up to 12 different analog input sources.
UARTs
Each UART is full-duplex and capable of handling asynchronous data transfers. The
UARTs support 8- and 9-bit data modes, selectable parity, and an efficient bus transceiver
Driver Enable signal for controlling a multi-transceiver bus, such as RS-485.
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Introduction
Z8 Encore!® 64K Series
Product Specification
5
I2C
The inter-integrated circuit (I2C®) controller makes the Z8 Encore!® compatible with the
I2C protocol. The I2C controller consists of two bidirectional bus lines, a serial data (SDA)
line and a serial clock (SCL) line.
Serial Peripheral Interface
The serial peripheral interface (SPI) allows the Z8 Encore!® to exchange data between
other peripheral devices such as EEPROMs, A/D converters and ISDN devices. The SPI is
a full-duplex, synchronous, character-oriented channel that supports a four-wire interface.
Timers
Up to four 16-bit reloadable timers can be used for timing/counting events or for motor
control operations. These timers provide a 16-bit programmable reload counter and oper-
ate in One-Shot, Continuous, Gated, Capture, Compare, Capture and Compare, and PWM
modes. Only 3 timers (Timers 0-2) are available in the 44-pin packages.
Interrupt Controller
The 64K Series products support up to 24 interrupts. These interrupts consist of 12 inter-
nal and 12 general-purpose I/O pins. The interrupts have 3 levels of programmable inter-
rupt priority.
Reset Controller
The Z8 Encore!® can be reset using the RESET pin, power-on reset, Watch-Dog Timer
(WDT), STOP mode exit, or Voltage Brown-Out (VBO) warning signal.
On-Chip Debugger
The Z8 Encore!® features an integrated On-Chip Debugger (OCD). The OCD provides a
rich set of debugging capabilities, such as reading and writing registers, programming the
Flash, setting breakpoints and executing code. A single-pin interface provides communi-
cation to the OCD.
DMA Controller
The 64K Series features three channels of DMA. Two of the channels are for register
RAM to and from I/O operations. The third channel automatically controls the transfer of
data from the ADC to the memory.
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Introduction
Z8 Encore!® 64K Series
Product Specification
6
Signal and Pin Descriptions
Overview
®
The Z8 Encore! 64K Series products are available in a variety of packages styles and pin
configurations. This chapter describes the signals and available pin configurations for
each of the package styles. For information regarding the physical package specifications,
please refer to the chapter Packaging on page 260.
Available Packages
Table 2 identifies the package styles that are available for each device within the Z8
®
Encore! 64K Series product line.
®
Table 2. Z8 Encore! 64K Series Package Options
40-Pin
PDIP
44-pin
LQFP
44-pin
PLCC
64-pin
LQFP
68-pin
PLCC
80-pin
QFP
Part Number
Z8X1621
X
X
X
X
X
X
X
X
X
X
X
X
Z8X1622
X
X
X
X
X
X
X
X
Z8X2421
Z8X2422
Z8X3221
Z8X3222
Z8X4821
Z8X4822
Z8X4823
X
X
Z8X6421
X
X
X
Z8X6422
X
X
Z8X6423
Flash: X=F, ROM X=R
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P r e l i m i n a r y
Signal and Pin Descriptions
Z8 Encore!® 64K Series
Product Specification
7
Pin Configurations
Figures 2 through 7 illustrate the pin configurations for all of the packages available in the
64K Series. Refer to Table 3 for a description of the signals. Timer 3 is not available in the
40-pin and 44-pin packages.
PD4/RXD1
PD3 / DE1
PC5 / MISO
PA3 / CTS0
PA2/DE0
PA1 /T0OUT
PA0 / T0IN
PC2 / SS
RESET
1
5
40
PD5 / TXD1
PC4 / MOSI
PA4 / RXD0
PA5 / TXD0
PA6 / SCL
35
PA7 / SDA
PD6 / CTS1
PC3 / SCK
VSS
10
15
20
VDD
VDD
30
PC6 / T2IN *
DBG
VSS
PD1
PD0
PC1 / T1OUT
PC0 / T1IN
AVSS
XOUT
XIN
25
21
AVDD
VREF
PB2 / ANA2
PB3 / ANA3
PB7 / ANA7
PB6 / ANA6
PB0 / ANA0
PB1 / ANA1
PB4 / ANA4
PB5 / ANA5
* T2OUT is not supported.
Note: Timer 3 is not supported.
Figure 2. 64K Series in 40-Pin Dual Inline Package (PDIP)
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Signal and Pin Descriptions
Z8 Encore!® 64K Series
Product Specification
8
6
1
40
39
PA7 / SDA
PA0 / T0IN
PD2
7
PD6 / CTS1
PC3 / SCK
VSS
PC2 / SS
RESET
VDD
VDD
34
12
PC7 / T2OUT
PC6 / T2IN
DBG
VSS
PD1
PD0
XOUT
XIN
PC1 / T1OUT
PC0 / T1IN
VSS
29
28
VDD
17
18
23
Figure 3. 64K Series in 44-Pin Plastic Leaded Chip Carrier (PLCC)
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P r e l i m i n a r y
Signal and Pin Descriptions
Z8 Encore!® 64K Series
Product Specification
9
33
34
23
22
28
PA7 / SDA
PA0 / T0IN
PD2
PD6 / CTS1
PC3 / SCK
VSS
PC2 / SS
RESET
VDD
VDD
39
44
17
PC7 / T2OUT
PC6 / T2IN
DBG
VSS
PD1
PD0
XOUT
XIN
PC1 / T1OUT
PC0 / T1IN
VSS
12
11
VDD
1
6
Figure 4. 64K Series in 44-Pin Low-Profile Quad Flat Package (LQFP)
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P r e l i m i n a r y
Signal and Pin Descriptions
Z8 Encore!® 64K Series
Product Specification
10
40
48
49
33
32
PA7 / SDA
PA0 / T0IN
PD2
PD6 / CTS1
PC3 / SCK
PC2 / SS
RESET
VDD
PD7 / RCOUT
VSS
PE5
PE4
PE6
PE3
25
PE7
VSS
56
VDD
PE2
PE1
PG3
VDD
PE0
PC7 / T2OUT
PC6 / T2IN
DBG
VSS
PD1 / T3OUT
PD0 / T3IN
XOUT
XIN
PC1 / T1OUT
PC0 / T1IN
64
17
16
1
8
Figure 5. 64K Series in 64-Pin Low-Profile Quad Flat Package (LQFP)
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P r e l i m i n a r y
Signal and Pin Descriptions
Z8 Encore!® 64K Series
Product Specification
11
9
1
61
60
PA7 / SDA
PA0 / T0IN
PD2
10
PD6 / CTS1
PC3 / SCK
PC2 / SS
RESET
VDD
PD7 / RCOUT
VSS
PE5
PE4
PE6
PE3
PE7
VSS
52
18
VDD
PE2
PE1
PG3
VDD
PE0
PC7 / T2OUT
PC6 / T2IN
DBG
VSS
VDD
PD1 / T3OUT
PD0 / T3IN
XOUT
XIN
PC1 / T1OUT
PC0 / T1IN
VSS
26
44
43
27
35
Figure 6. 64K Series in 68-Pin Plastic Leaded Chip Carrier (PLCC)
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P r e l i m i n a r y
Signal and Pin Descriptions
Z8 Encore!® 64K Series
Product Specification
12
80
65
64
75
70
PA7 / SDA
PA0 / T0IN
PD2
1
5
PD6 / CTS1
PC3 / SCK
PD7 / RCOUT
PC2 / SS
PF6
60
RESET
VDD
PG0
VSS
PG1
PF5
PG2
PF4
PE5
PF3
10
15
55
50
45
PE4
PE6
PE7
PE3
VDD
VSS
PG3
PE2
PG4
PE1
PE0
PG5
PG6
VSS
VDD
PF2
PG7
PF1
PC7 / T2OUT
PC6 / T2IN
DBG
PF0
20
24
VDD
PD1 / T3OUT
PD0 / T3IN
XOUT
XIN
PC1 / T1OUT
PC0 / T1IN
41 VSS
40
25
30
35
Figure 7. 64K Series in 80-Pin Quad Flat Package (QFP)
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P r e l i m i n a r y
Signal and Pin Descriptions
Z8 Encore!® 64K Series
Product Specification
13
Signal Descriptions
Table 3 describes the Z8 Encore! signals. Refer to the section Pin Configurations on
page 7 to determine the signals available for the specific package styles.
Table 3. Signal Descriptions
Signal
Mnemonic
I/O
Description
General-Purpose I/O Ports A-H
PA[7:0]
I/O
Port A[7:0]. These pins are used for general-purpose I/O and support 5V-tolerant
inputs.
PB[7:0]
PC[7:0]
I/O
I/O
Port B[7:0]. These pins are used for general-purpose I/O.
Port C[7:0]. These pins are used for general-purpose I/O. These pins are used for
general-purpose I/O and support 5V-tolerant inputs
PD[7:0]
PE[7:0]
PF[7:0]
PG[7:0]
PH[3:0]
I/O
I/O
I/O
I/O
I/O
Port D[7:0]. These pins are used for general-purpose I/O. These pins are used for
general-purpose I/O and support 5V-tolerant inputs
Port E[7:0]. These pins are used for general-purpose I/O. These pins are used for
general-purpose I/O and support 5V-tolerant inputs.
Port F[7:0]. These pins are used for general-purpose I/O. These pins are used for
general-purpose I/O and support 5V-tolerant inputs.
Port G[7:0]. These pins are used for general-purpose I/O. These pins are used for
general-purpose I/O and support 5V-tolerant inputs.
Port H[3:0]. These pins are used for general-purpose I/O.
2
I C Controller
2
SCL
SDA
O
Serial Clock. This is the output clock for the I C. This pin is multiplexed with a
general-purpose I/O pin. When the general-purpose I/O pin is configured for
alternate function to enable the SCL function, this pin is open-drain.
2
I/O
Serial Data. This open-drain pin transfers data between the I C and a slave. This pin
is multiplexed with a general-purpose I/O pin. When the general-purpose I/O pin is
configured for alternate function to enable the SDA function, this pin is open-drain.
SPI Controller
®
I/O
I/O
Slave Select. This signal can be an output or an input. If the Z8 Encore! 64K Series
SS
is the SPI master, this pin may be configured as the Slave Select output. If the Z8
Encore! 64K Series is the SPI slave, this pin is the input slave select. It is
®
multiplexed with a general-purpose I/O pin.
®
SCK
SPI Serial Clock. The SPI master supplies this pin. If the Z8 Encore! 64K Series is
the SPI master, this pin is an output. If the Z8 Encore! 64K Series is the SPI slave,
®
this pin is an input. It is multiplexed with a general-purpose I/O pin.
PS019913-0305
P r e l i m i n a r y
Signal and Pin Descriptions
Z8 Encore!® 64K Series
Product Specification
14
Table 3. Signal Descriptions (Continued)
Signal
Mnemonic
I/O
Description
MOSI
I/O
Master Out Slave In. This signal is the data output from the SPI master device and
the data input to the SPI slave device. It is multiplexed with a general-purpose I/O
pin.
MISO
I/O
Master In Slave Out. This pin is the data input to the SPI master device and the data
output from the SPI slave device. It is multiplexed with a general-purpose I/O pin.
UART Controllers
TXD0 / TXD1
O
I
Transmit Data. These signals are the transmit outputs from the UARTs. The TXD
signals are multiplexed with general-purpose I/O pins.
RXD0 / RXD1
CTS0 / CTS1
DE0 / DE1
Receive Data. These signals are the receiver inputs for the UARTs and IrDAs. The
RXD signals are multiplexed with general-purpose I/O pins.
I
Clear To Send. These signals are control inputs for the UARTs. The CTS signals are
multiplexed with general-purpose I/O pins.
O
Driver Enable. This signal allows automatic control of external RS-485 drivers. This
signal is approximately the inverse of the TXE (Transmit Empty) bit in the UART
Status 0 register. The DE signal may be used to ensure an external RS-485 driver is
enabled when data is transmitted by the UART.
Timers
T0OUT / T1OUT/
T2OUT / T3OUT
O
I
Timer Output 0-3. These signals are output pins from the timers. The Timer Output
signals are multiplexed with general-purpose I/O pins. T3OUT is not available in 44-
pin package devices.
T0IN / T1IN/
T2IN / T3IN
Timer Input 0-3. These signals are used as the capture, gating and counter inputs.
The Timer Input signals are multiplexed with general-purpose I/O pins. T3IN is not
available in 44-pin package devices.
Analog
ANA[11:0]
I
I
Analog Input. These signals are inputs to the analog-to-digital converter (ADC). The
ADC analog inputs are multiplexed with general-purpose I/O pins.
VREF
Analog-to-digital converter reference voltage input. The VREF pin must be left
unconnected (or capacitively coupled to analog ground) if the internal voltage
reference is selected as the ADC reference voltage.
Oscillators
XIN
I
External Crystal Input. This is the input pin to the crystal oscillator. A crystal can be
connected between it and the XOUT pin to form the oscillator. This signal is usable
with external RC networks and an external clock driver.
PS019913-0305
P r e l i m i n a r y
Signal and Pin Descriptions
Z8 Encore!® 64K Series
Product Specification
15
Table 3. Signal Descriptions (Continued)
Signal
Mnemonic
I/O
Description
XOUT
O
External Crystal Output. This pin is the output of the crystal oscillator. A crystal can
be connected between it and the XIN pin to form the oscillator. When the system
clock is referred to in this manual, it refers to the frequency of the signal at this pin.
This pin must be left unconnected when not using a crystal.
RCOUT
O
RC Oscillator Output. This signal is the output of the RC oscillator. It is multiplexed
with a general-purpose I/O pin. This signal must be left unconnected when not using
a crystal.
On-Chip Debugger
DBG
I/O
Debug. This pin is the control and data input and output to and from the On-Chip
Debugger. This pin is open-drain.
For operation of the On-Chip Debugger, all power pins (V and AV ) must be
Caution:
DD
DD
supplied with power and all ground pins (V and AV ) must be properly grounded.
SS
SS
The DBG pin is open-drain and must have an external pull-up resistor to ensure
proper operation.
Reset
I
RESET. Generates a Reset when asserted (driven Low).
RESET
Power Supply
VDD
I
I
I
I
Power Supply.
Analog Power Supply.
Ground.
AVDD
VSS
AVSS
Analog Ground.
PS019913-0305
P r e l i m i n a r y
Signal and Pin Descriptions
Z8 Encore!® 64K Series
Product Specification
16
Pin Characteristics
Table 4 provides detailed information on the characteristics for each pin available on the
64K Series products. Data in Table 4 is sorted alphabetically by the pin symbol mne-
monic.
Table 4. Pin Characteristics of the 64K Series
Active Low
or
Direction Direction Active High
Internal
Tri-State Pull-up or
Output Pull-down
Schmitt
Trigger
Input
Symbol
Mnemonic
Reset
Open Drain
Output
AVSS
N/A
N/A
I/O
N/A
N/A
I
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Yes
No
No
No
No
No
No
No
Yes
No
Yes
N/A
N/A
Yes
AVDD
DBG
VSS
N/A
I/O
N/A
I
N/A
Yes
N/A
PA[7:0]
Yes,
Programmable
PB[7:0]
PC[7:0]
PD[7:0]
PE7:0]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes,
Programmable
Yes,
Programmable
Yes,
Programmable
Yes,
Programmable
PF[7:0]
PG[7:0]
PH[3:0]
Yes,
Programmable
Yes,
Programmable
Yes,
Programmable
RESET
VDD
I
N/A
I
I
N/A
I
Low
N/A
N/A
N/A
N/A
N/A
N/A
Pull-up
No
Yes
No
No
No
N/A
N/A
N/A
No
XIN
No
XOUT
O
O
Yes, in
STOP
mode
No
x represents integer 0, 1,... to indicate multiple pins with symbol mnemonics that differ only by the integer
PS019913-0305
P r e l i m i n a r y
Signal and Pin Descriptions
Z8 Encore!® 64K Series
Product Specification
17
Address Space
Overview
The eZ8 CPU can access three distinct address spaces:
•
•
•
The Register File contains addresses for the general-purpose registers and the eZ8
CPU, peripheral, and general-purpose I/O port control registers.
The Program Memory contains addresses for all memory locations having executable
code and/or data.
The Data Memory contains addresses for all memory locations that hold data only.
These three address spaces are covered briefly in the following subsections. For more
detailed information regarding the eZ8 CPU and its address space, refer to the eZ8 CPU
User Manual available for download at www.zilog.com.
Register File
The Register File address space in the 64K Series is 4KB (4096 bytes). The Register File
is composed of two sections—control registers and general-purpose registers. When
instructions are executed, registers are read from when defined as sources and written to
when defined as destinations. The architecture of the eZ8 CPU allows all general-purpose
registers to function as accumulators, address pointers, index registers, stack areas, or
scratch pad memory.
The upper 256 bytes of the 4KB Register File address space are reserved for control of the
eZ8 CPU, the on-chip peripherals, and the I/O ports. These registers are located at
addresses from F00Hto FFFH. Some of the addresses within the 256-byte control register
section are reserved (unavailable). Reading from an reserved Register File addresses
returns an undefined value. Writing to reserved Register File addresses is not recom-
mended and can produce unpredictable results.
The on-chip RAM always begins at address 000H in the Register File address space. The
64K Series provide 2KB to 4KB of on-chip RAM depending upon the device. Reading
from Register File addresses outside the available RAM addresses (and not within the con-
trol register address space) returns an undefined value. Writing to these Register File
addresses produces no effect. Refer to the Part Selection Guide on page 2 to determine
the amount of RAM available for the specific 64K Series device.
PS019913-0305
P r e l i m i n a r y
Address Space
Z8 Encore!® 64K Series
Product Specification
18
Program Memory
The eZ8 CPU supports 64KB of Program Memory address space. The Z8 Encore!® 64K
Series contains 16KB to 64KB of on-chip Flash /Read-Only memory (ROM) in the Pro-
gram Memory address space, depending upon the device. Reading from Program Memory
addresses outside the available Flash/ROM memory addresses returns FFH. Writing to
these unimplemented Program Memory addresses produces no effect. Table 5 describes
the Program Memory Maps for the 64K Series products.
®
Table 5. Z8 Encore 64K Series Program Memory Maps
Program Memory Address (Hex) Function
Z8X162x Products
0000-0001
0002-0003
0004-0005
0006-0007
0008-0037
0038-3FFF
Option Bits
Reset Vector
WDT Interrupt Vector
Illegal Instruction Trap
Interrupt Vectors*
Program Memory
Z8X242x Products
0000-0001
0002-0003
0004-0005
0006-0007
0008-0037
0038-5FFF
Option Bits
Reset Vector
WDT Interrupt Vector
Illegal Instruction Trap
Interrupt Vectors*
Program Memory
Z8X322x Products
0000-0001
0002-0003
0004-0005
0006-0007
0008-0037
0038-7FFF
Option Bits
Reset Vector
WDT Interrupt Vector
Illegal Instruction Trap
Interrupt Vectors*
Program Memory
* See Table 23 on page 63 for a list of the interrupt vectors.
Flash: X=F, ROM X=R
PS019913-0305
P r e l i m i n a r y
Address Space
Z8 Encore!® 64K Series
Product Specification
19
®
Table 5. Z8 Encore 64K Series Program Memory Maps (Continued)
Program Memory Address (Hex) Function
Z8X482x Products
0000-0001
0002-0003
0004-0005
0006-0007
0008-0037
0038-BFFF
Option Bits
Reset Vector
WDT Interrupt Vector
Illegal Instruction Trap
Interrupt Vectors*
Program Memory
Z8X642x Products
0000-0001
0002-0003
0004-0005
0006-0007
0008-0037
0038-FFFF
Option Bits
Reset Vector
WDT Interrupt Vector
Illegal Instruction Trap
Interrupt Vectors*
Program Memory
* See Table 23 on page 63 for a list of the interrupt vectors.
Flash: X=F, ROM X=R
Data Memory
The Z8 Encore!® 64K Series does not use the eZ8 CPU’s 64KB Data Memory address
space.
Information Area
Table 6 describes the Z8 Encore!® 64K Series Information Area. This 512 byte Informa-
tion Area is accessed by setting bit 7 of the Page Select Register to 1. When access is
enabled, the Information Area is mapped into the Program Memory and overlays the 512
bytes at addresses FE00Hto FFFFH. When the Information Area access is enabled, execu-
tion of LDC and LDCI instruction from these Program Memory addresses return the Infor-
mation Area data rather than the Program Memory data. Reads of these addresses through
the On-Chip Debugger also returns the Information Area data. Execution of code from
these addresses continues to correctly use the Program Memory. Access to the Information
Area is read-only.
PS019913-0305
P r e l i m i n a r y
Address Space
Z8 Encore!® 64K Series
Product Specification
20
®
Table 6. Z8 Encore! 64K Series Information Area Map
Program Memory Address (Hex) Function
FE00H-FE3FH
FE40H-FE53H
Reserved
Part Number
20-character ASCII alphanumeric code
Left justified and filled with zeros
(ASCII Null character).
FE54H-FFFFH
Reserved
PS019913-0305
P r e l i m i n a r y
Address Space
Z8 Encore!® 64K Series
Product Specification
21
Register File Address Map
Table 7 provides the address map for the Register File of the 64K Series products. Not all
devices and package styles in the 64K Series support Timer 3 and all of the GPIO Ports.
Consider registers for unimplemented peripherals as Reserved.
Table 7. 64K Series Register File Address Map
Address (Hex) Register Description
General Purpose RAM
Mnemonic
Reset (Hex)
Page #
000-EFF
General-Purpose Register File RAM
—
XX
Timer 0
F00
F01
F02
F03
F04
F05
F06
F07
Timer 0 High Byte
Timer 0 Low Byte
T0H
T0L
T0RH
T0RL
T0PWMH
T0PWML
T0CTL0
T0CTL1
00
01
FF
FF
00
00
00
00
84
84
85
85
87
87
88
88
Timer 0 Reload High Byte
Timer 0 Reload Low Byte
Timer 0 PWM High Byte
Timer 0 PWM Low Byte
Timer 0 Control 0
Timer 0 Control 1
Timer 1
F08
F09
F0A
F0B
F0C
F0D
F0E
Timer 1 High Byte
Timer 1 Low Byte
T1H
T1L
T1RH
T1RL
T1PWMH
T1PWML
T1CTL0
T1CTL1
00
01
FF
FF
00
00
00
00
84
84
85
85
87
87
88
88
Timer 1 Reload High Byte
Timer 1 Reload Low Byte
Timer 1 PWM High Byte
Timer 1 PWM Low Byte
Timer 1 Control 0
F0F
Timer 1 Control 1
Timer 2
F10
F11
F12
F13
F14
F15
F16
F17
Timer 2 High Byte
Timer 2 Low Byte
T2H
T2L
T2RH
T2RL
T2PWMH
T2PWML
T2CTL0
T2CTL1
00
01
FF
FF
00
00
00
00
84
84
85
85
87
87
88
88
Timer 2 Reload High Byte
Timer 2 Reload Low Byte
Timer 2 PWM High Byte
Timer 2 PWM Low Byte
Timer 2 Control 0
Timer 2 Control 1
XX=Undefined
PS019913-0305
P r e l i m i n a r y
Register File Address Map
Z8 Encore!® 64K Series
Product Specification
22
Table 7. 64K Series Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic
Reset (Hex)
Page #
Timer 3 (unavailable in the 44-pin packages)
F18
F19
Timer 3 High Byte
Timer 3 Low Byte
T3H
T3L
T3RH
T3RL
T3PWMH
T3PWML
T3CTL0
T3CTL1
—
00
01
FF
FF
00
00
00
00
XX
84
84
85
85
87
87
88
88
F1A
F1B
F1C
F1D
F1E
F1F
20-3F
Timer 3 Reload High Byte
Timer 3 Reload Low Byte
Timer 3 PWM High Byte
Timer 3 PWM Low Byte
Timer 3 Control 0
Timer 3 Control 1
Reserved
UART 0
F40
UART0 Transmit Data
UART0 Receive Data
UART0 Status 0
UART0 Control 0
UART0 Control 1
U0TXD
U0RXD
U0STAT0
U0CTL0
U0CTL1
U0STAT1
U0ADDR
U0BRH
U0BRL
XX
XX
0000011Xb
00
00
00
00
FF
FF
109
110
110
112
112
110
115
115
115
F41
F42
F43
F44
F45
F46
F47
UART0 Status 1
UART0 Address Compare Register
UART0 Baud Rate High Byte
UART0 Baud Rate Low Byte
UART 1
F48
UART1 Transmit Data
UART1 Receive Data
UART1 Status 0
UART1 Control 0
UART1 Control 1
U1TXD
XX
XX
0000011Xb
00
00
00
00
FF
FF
109
110
110
112
112
110
115
115
115
U1RXD
U1STAT0
U1CTL0
U1CTL1
U1STAT1
U1ADDR
U1BRH
U1BRL
F49
F4A
F4B
F4C
F4D
F4E
F4F
UART1 Status 1
UART1 Address Compare Register
UART1 Baud Rate High Byte
UART1 Baud Rate Low Byte
2
I C
F50
F51
F52
F53
F54
F55
F56
2
I C Data
I2CDATA
I2CSTAT
I2CCTL
I2CBRH
I2CBRL
I2CDST
I2CDIAG
—
00
80
00
FF
FF
C0
00
151
152
154
155
155
157
159
2
I C Status
2
I C Control
2
I C Baud Rate High Byte
2
I C Baud Rate Low Byte
2
I C Diagnostic State
2
I C Diagnostic Control
F57-F5F
Reserved
XX
XX=Undefined
PS019913-0305
P r e l i m i n a r y
Register File Address Map
Z8 Encore!® 64K Series
Product Specification
23
Table 7. 64K Series Register File Address Map (Continued)
Address (Hex) Register Description
Serial Peripheral Interface (SPI)
Mnemonic
Reset (Hex)
Page #
F60
F61
F62
F63
F64
F65
F66
F67
SPI Data
SPI Control
SPI Status
SPI Mode
SPI Diagnostic State
Reserved
SPI Baud Rate High Byte
SPI Baud Rate Low Byte
Reserved
SPIDATA
SPICTL
SPISTAT
SPIMODE
SPIDST
—
SPIBRH
SPIBRL
—
XX
00
01
00
00
XX
FF
FF
XX
132
132
134
135
136
137
137
F68-F6F
Analog-to-Digital Converter (ADC)
F70
F71
F72
F73
ADC Control
Reserved
ADC Data High Byte
ADC Data Low Bits
Reserved
ADCCTL
—
ADCD_H
ADCD_L
—
20
174
XX
XX
XX
XX
175
175
F74-FAF
DMA 0
FB0
FB1
FB2
FB3
DMA0 Control
DMA0 I/O Address
DMA0 End/Start Address High Nibble
DMA0 Start Address Low Byte
DMA0 End Address Low Byte
DMA0CTL
DMA0IO
DMA0H
DMA0START XX
DMA0END
00
XX
XX
163
164
164
165
166
FB4
XX
DMA 1
FB8
FB9
FBA
FBB
FBC
DMA1 Control
DMA1 I/O Address
DMA1 End/Start Address High Nibble
DMA1 Start Address Low Byte
DMA1 End Address Low Byte
DMA1CTL
DMA1IO
DMA1H
DMA1START XX
DMA1END XX
00
XX
XX
163
164
164
165
166
DMA ADC
FBD
FBE
DMA_ADC Address
DMA_ADC Control
DMA_ADC Status
DMAA_ADDR XX
DMAACTL 00
DMAASTAT 00
167
168
169
FBF
Interrupt Controller
FC0
FC1
FC2
FC3
FC4
FC5
FC6
Interrupt Request 0
IRQ0
00
00
00
00
00
00
00
66
69
69
67
70
70
68
IRQ0 Enable High Bit
IRQ0 Enable Low Bit
Interrupt Request 1
IRQ1 Enable High Bit
IRQ1 Enable Low Bit
Interrupt Request 2
IRQ0ENH
IRQ0ENL
IRQ1
IRQ1ENH
IRQ1ENL
IRQ2
XX=Undefined
PS019913-0305
P r e l i m i n a r y
Register File Address Map
Z8 Encore!® 64K Series
Product Specification
24
Table 7. 64K Series Register File Address Map (Continued)
Address (Hex) Register Description
Mnemonic
IRQ2ENH
IRQ2ENL
—
IRQES
IRQPS
Reset (Hex)
Page #
71
71
FC7
FC8
FC9-FCC
FCD
IRQ2 Enable High Bit
IRQ2 Enable Low Bit
Reserved
Interrupt Edge Select
Interrupt Port Select
Interrupt Control
00
00
XX
00
00
00
72
73
74
FCE
FCF
IRQCTL
GPIO Port A
FD0
FD1
FD2
FD3
Port A Address
Port A Control
Port A Input Data
Port A Output Data
PAADDR
PACTL
PAIN
00
00
XX
00
55
56
60
61
PAOUT
GPIO Port B
FD4
FD5
FD6
FD7
Port B Address
Port B Control
Port B Input Data
Port B Output Data
PBADDR
PBCTL
PBIN
00
00
XX
00
55
56
60
61
PBOUT
GPIO Port C
FD8
FD9
FDA
FDB
Port C Address
Port C Control
Port C Input Data
Port C Output Data
PCADDR
PCCTL
PCIN
00
00
XX
00
55
56
60
61
PCOUT
GPIO Port D
FDC
FDD
FDE
FDF
Port D Address
Port D Control
Port D Input Data
Port D Output Data
PDADDR
PDCTL
PDIN
00
00
XX
00
55
56
60
61
PDOUT
GPIO Port E
FE0
FE1
FE2
FE3
Port E Address
Port E Control
Port E Input Data
Port E Output Data
PEADDR
PECTL
PEIN
00
00
XX
00
55
56
60
61
PEOUT
GPIO Port F
FE4
FE5
FE6
FE7
Port F Address
Port F Control
Port F Input Data
Port F Output Data
PFADDR
PFCTL
PFIN
00
00
XX
00
55
56
60
61
PFOUT
GPIO Port G
FE8
FE9
FEA
FEB
Port G Address
Port G Control
Port G Input Data
Port G Output Data
PGADDR
PGCTL
PGIN
00
00
XX
00
55
56
60
61
PGOUT
XX=Undefined
PS019913-0305
P r e l i m i n a r y
Register File Address Map
Z8 Encore!® 64K Series
Product Specification
25
Table 7. 64K Series Register File Address Map (Continued)
Address (Hex) Register Description
GPIO Port H
Mnemonic
Reset (Hex)
Page #
FEC
FED
FEE
FEF
Port H Address
Port H Control
Port H Input Data
Port H Output Data
PHADDR
PHCTL
PHIN
00
00
XX
00
55
56
60
61
PHOUT
Watch-Dog Timer (WDT)
FF0
FF1
FF2
FF3
Watch-Dog Timer Control
WDTCTL
WDTU
WDTH
WDTL
—
XXX00000b
94
95
95
95
Watch-Dog Timer Reload Upper Byte
Watch-Dog Timer Reload High Byte
Watch-Dog Timer Reload Low Byte
Reserved
FF
FF
FF
XX
FF4--FF7
Flash Memory Controller
FF8
FF8
FF9
Flash Control
Flash Status
Page Select
FCTL
FSTAT
FPS
FPROT
FFREQH
FFREQL
—
00
00
00
00
00
00
XX
184
185
186
187
188
188
FF9 (if enabled) Flash Sector Protect
FFA
FFB
FF4-FF8
Flash Programming Frequency High Byte
Flash Programming Frequency Low Byte
Reserved
Read-Only Memory Controller
FF9
FFA-FFB
Page Select
Reserved
RPS
—
00
XX
eZ8 CPU
FFC
FFD
FFE
FFF
Flags
—
RP
SPH
SPL
XX
XX
XX
XX
Refer to the eZ8
CPU User
Manual
Register Pointer
Stack Pointer High Byte
Stack Pointer Low Byte
XX=Undefined
PS019913-0305
P r e l i m i n a r y
Register File Address Map
Z8 Encore!® 64K Series
Z8 Encore!
26
Control Register Summary
Timer 0 Control 1
T0CTL1 (F07H - Read/Write)
Timer 0 High Byte
T0H (F00H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Timer Mode
000 = One-Shot mode
001 = CONTINUOUS mode
010 = COUNTER mode
011 = PWM mode
Timer 0 current count value [15:8]
100 = CAPTURE mode
101 = COMPARE mode
110 = GATED mode
Timer 0 Low Byte
T0L (F01H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
111 = Capture/COMPARE mode
Prescale Value
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
Timer 0 current count value [7:0]
Timer 0 Reload High Byte
T0RH (F02H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer Input/Output Polarity
Operation of this bit is a function of
the current operating mode of the timer
Timer 0 reload value [15:8]
Timer Enable
0 = Timer is disabled
1 = Timer is enabled
Timer 0 Reload Low Byte
T0RL (HF03 - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 0 reload value [7:0]
Timer 1 High Byte
T1H (F08H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 0 PWM High Byte
T0PWMH (F04H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 current count value [15:8]
Timer 0 PWM value [15:8]
Timer 1 Low Byte
T1L (F09H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 0 Control 0
T0CTL0 (F06H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 current count value [7:0]
Reserved
Timer 1 Reload High Byte
T1RH (F0AH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Cascade Timer
0 = Timer 0 Input signal is GPIO pin
1 = Timer 0 Input signal is Timer 3 out
Reserved
Timer 1 reload value [15:8]
Timer 1 Reload Low Byte
T1RL (F0BH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 reload value [7:0]
PS019913-0305
P r e l i m i n a r y
Control Register Summary
Z8 Encore!® 64K Series
Z8 Encore!
27
Timer 1 PWM High Byte
T1PWMH (F0CH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 2 High Byte
T2H (F10H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 PWM value [15:8]
Timer 2 current count value [15:8]
Timer 1 PWM Low Byte
T1PWML (F0DH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 2 Low Byte
T2L (F11H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 1 PWM value [7:0]
Timer 2 current count value [7:0]
Timer 1 Control 0
T1CTL0 (F0EH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 2 Reload High Byte
T2RH (F12H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Timer 2 reload value [15:8]
Cascade Timer
0 = Timer 1 Input signal is GPIO pin
1 = Timer 1 Input signal is Timer 0 out
Timer 2 Reload Low Byte
T2RL (F13H- Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Timer 2 reload value [7:0]
Timer 1 Control 1
T1CTL1 (F0FH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 2 PWM High Byte
T2PWMH (F14H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer Mode
000 = One-Shot mode
001 = CONTINUOUS mode
010 = COUNTER mode
011 = PWM mode
Timer 2 PWM value [15:8]
100 = CAPTURE mode
101 = COMPARE mode
110 = GATED mode
Timer 2 PWM Low Byte
T2PWML (F15H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
111 = Capture/COMPARE mode
Prescale Value
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
Timer 2 PWM value [7:0]
Timer 2 Control 0
T2CTL0 (F16H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer Input/Output Polarity
Operation of this bit is a function of
the current operating mode of the timer
Reserved
Cascade Timer
0 = Timer 2 Input signal is GPIO pin
1 = Timer 2 Input signal is Timer 1 out
Timer Enable
0 = Timer is disabled
1 = Timer is enabled
Reserved
PS019913-0305
P r e l i m i n a r y
Control Register Summary
Z8 Encore!® 64K Series
Z8 Encore!
28
Timer 2 Control 1
T2CTL1 (F17H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 3 PWM High Byte
T3PWMH (F1CH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer Mode
000 = One-Shot mode
Timer 3 PWM value [15:8]
001 = CONTINUOUS mode
010 = COUNTER mode
011 = PWM mode
Timer 3 PWM Low Byte
T3PWML (F1DH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
100 = CAPTURE mode
101 = COMPARE mode
110 = GATED mode
111 = CAPTURE/COMPARE mode
Timer 3 PWM value [7:0]
Prescale Value
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
Timer 3 Control 0
T3CTL0 (F1EH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Cascade Timer
0 = Timer 3 Input signal is GPIO pin
1 = Timer 3 Input signal is Timer 2 out
Timer Input/Output Polarity
Operation of this bit is a function of
the current operating mode of the timer
Reserved
Timer Enable
0 = Timer is disabled
1 = Timer is enabled
Timer 3 Control 1
T3CTL1 (F1FH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 3 High Byte
T3H (F18H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer Mode
000 = One-Shot mode
001 = CONTINUOUS mode
010 = COUNTER mode
011 = PWM mode
Timer 3 current count value [15:8]
100 = CAPTURE mode
101 = COMPARE mode
110 = GATED mode
Timer 3 Low Byte
T3L (F19H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
111 = Capture/COMPARE mode
Prescale Value
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
Timer 3 current count value [7:0]
Timer 3 Reload High Byte
T3RH (F1AH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer Input/Output Polarity
Operation of this bit is a function of
the current operating mode of the timer
Timer 3 reload value [15:8]
Timer Enable
0 = Timer is disabled
1 = Timer is enabled
Timer 3 Reload Low Byte
T3RL (F1BH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Timer 3 reload value [7:0]
PS019913-0305
P r e l i m i n a r y
Control Register Summary
Z8 Encore!® 64K Series
Z8 Encore!
29
UART0 Transmit Data
U0TXD (F40H - Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
UART0 Control 0
U0CTL0 (F42H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
UART0 transmitter data byte [7:0]
Loop Back Enable
0 = Normal operation
1 = Transmit data is looped back to
the receiver
UART0 Receive Data
U0RXD (F40H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Stop Bit Select
0 = Transmitter sends 1 Stop bit
1 = Transmitter sends 2 Stop bits
UART0 receiver data byte [7:0]
Send Break
0 = No break is sent
1 = Output of the transmitter is zero
UART0 Status 0
U0STAT0 (F41H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Parity Select
0 = Even parity
1 = Odd parity
Parity Enable
0 = Parity is disabled
1 = Parity is enabled
CTS signal
Returns the level of the CTS signal
Transmitter Empty
0 = Data is currently transmitting
1 = Transmission is complete
CTS Enable
0 = CTS signal has no effect on the
transmitter
1 = UART recognizes CTS signal as a
transmit enable control signal
Transmitter Data Register Empty
0 = Transmit Data Register is full
1 = Transmit Data register is empty
Receive Enable
0 = Receiver disabled
1 = Receiver enabled
Break Detect
0 = No break occurred
1 = A break occurred
Transmit Enable
0 = Transmitter disabled
1 = Transmitter enabled
Framing Error
0 = No framing error occurred
1 = A framing occurred
Overrun Error
0 = No overrun error occurred
1 = An overrun error occurred
Parity Error
0 = No parity error occurred
1 = A parity error occurred
Receive Data Available
0 = Receive Data Register is empty
1 = A byte is available in the Receive
Data Register
PS019913-0305
P r e l i m i n a r y
Control Register Summary
Z8 Encore!® 64K Series
Z8 Encore!
30
UART0 Control 1
U0CTL1 (F43H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
UART0 Baud Rate Generator High Byte
U0BRH (F46H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Infrared Encoder/Decoder Enable
UART0 Baud Rate divisor [15:8]
0 = Infrared endec is disabled
1 = Infrared endec is enabled
Received Data Interrupt Enable
0 = Received data and errors generate
interrupt requests
1 = Only errors generate interrupt
requests. Received data does not.
UART0 Baud Rate Generator Low Byte
U0BRL (F47H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
UART0 Baud Rate divisor [7:0]
Baud Rate Registers Control
Refer to UART chapter for operation
UART1 Transmit Data
U1TXD (F48H - Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Driver Enable Polarity
0 = DE signal is active High
1 = DE signal is active Low
Multiprocessor Bit Transmit
0 = Send a 0 as the multiprocessor bit
1 = Send a 1 as the multiprocessor bit
UART1 transmitter data byte[7:0]
Multiprocessor Mode [0]
UART1 Receive Data
See Multiprocessor Mode [1] below
U1RXD (F48H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Multiprocessor (9-bit) Enable
0 = Multiprocessor mode is disabled
1 = Multiprocessor mode is enabled
UART receiver data byte [7:0]
Multiprocessor Mode [1]
with Multiprocess Mode bit 0:
00 = Interrupt on all received bytes
01 = Interrupt only on address bytes
10 = Interrupt on address match and
following data
11 = Interrupt on data following an
address match
UART0 Status 1
U0STAT1 (F44H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Mulitprocessor Receive
Returns value of last multiprocessor bit
New Frame
0 = Current byte is not start of frame
1 = Current byte is start of new frame
Reserved
UART0 Address Compare
U0ADDR (F45H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
UART0 Address Compare [7:0]
PS019913-0305
P r e l i m i n a r y
Control Register Summary
Z8 Encore!® 64K Series
Z8 Encore!
31
UART1 Status 0
U1STAT0 (F49H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
UART1 Control 0
U1CTL0 (F4AH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
CTS signal
Loop Back Enable
Returns the level of the CTS signal
0 = Normal operation
1 = Transmit data is looped back to
the receiver
Transmitter Empty
0 = Data is currently transmitting
1 = Transmission is complete
Stop Bit Select
0 = Transmitter sends 1 Stop bit
1 = Transmitter sends 2 Stop bits
Transmitter Data Register Empty
0 = Transmit Data Register is full
1 = Transmit Data register is empty
Send Break
0 = No break is sent
1 = Output of the transmitter is zero
Break Detect
0 = No break occurred
1 = A break occurred
Parity Select
0 = Even parity
1 = Odd parity
Framing Error
0 = No framing error occurred
1 = A framing occurred
Parity Enable
0 = Parity is disabled
1 = Parity is enabled
Overrun Error
0 = No overrun error occurred
1 = An overrun error occurred
CTS Enable
0 = CTS signal has no effect on the
transmitter
1 = UART recognizes CTS signal as a
transmit enable control signal
Parity Error
0 = No parity error occurred
1 = A parity error occurred
Receive Enable
Receive Data Available
0 = Receiver disabled
1 = Receiver enabled
0 = Receive Data Register is empty
1 = A byte is available in the Receive
Data Register
Transmit Enable
0 = Transmitter disabled
1 = Transmitter enabled
PS019913-0305
P r e l i m i n a r y
Control Register Summary
Z8 Encore!® 64K Series
Z8 Encore!
32
UART1 Control 1
U0CTL1 (F4BH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
UART1 Baud Rate Generator High Byte
U0BRH (F4EH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Infrared Encoder/Decoder Enable
UART1 Baud Rate divisor [15:8]
0 = Infrared endec is disabled
1 = Infrared endec is enabled
Received Data Interrupt Enable
0 = Received data and errors generate
interrupt requests
1 = Only errors generate interrupt
requests. Received data does not.
UART1 Baud Rate Generator Low Byte
U1BRL (F4FH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
UART1 Baud Rate divisor [7:0]
Baud Rate Registers Control
Refer to UART chapter for operation
I2C Data
I2CDATA (F50H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Driver Enable Polarity
0 = DE signal is active High
1 = DE signal is active Low
Multiprocessor Bit Transmit
0 = Send a 0 as the multiprocessor bit
1 = Send a 1 as the multiprocessor bit
I2C data [7:0]
Multiprocessor Mode [0]
See Multiprocessor Mode [1] below
I2C Status
I2CSTAT (F51H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Multiprocessor (9-bit) Enable
0 = Multiprocessor mode is disabled
1 = Multiprocessor mode is enabled
NACK Interrupt
0 = No action required to service NAK
Multiprocessor Mode [1]
1 = START/STOP not set after NAK
with Multiprocess Mode bit 0:
00 = Interrupt on all received bytes
01 = Interrupt only on address bytes
10 = Interrupt on address match and
following data
Data Shift State
0 = Data is not being transferred
1 = Data is being transferred
11 = Interrupt on data following an
address match
Transmit Address State
0 = Address is not being transferred
1 = Address is being transferred
Read
0 = Write operation
1 = Read operation
UART1 Status 1
U0STAT1 (F4CH - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
10-Bit Address
0 = 7-bit address being transmitted
1 = 10-bit address being transmitted
Mulitprocessor Receive
Returns value of last multiprocessor bit
Acknowledge
0 = Acknowledge not
transmitted/received
1 = For last byte, Acknowledge was
transmitted/received
New Frame
0 = Current byte is not start of frame
1 = Current byte is start of new frame
Reserved
Receive Data Register Full
0 = I2C has not received data
1 = Data register contains received data
UART1 Address Compare
U0ADDR (F4DH - Read/Write)
Transmit Data Register Empty
0 = Data register is full
1 = Data register is empty
D7 D6 D5 D4 D3 D2 D1 D0
UART1 Address Compare [7:0]
PS019913-0305
P r e l i m i n a r y
Control Register Summary
Z8 Encore!® 64K Series
Z8 Encore!
33
I2C Control
I2CCTL (F52H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
SPI Data
SPIDATA (F60H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
I2C Signal Filter Enable
SPI Data [7:0]
0 = Digital filtering disabled
1 = Low-pass digital filters enabled
on SDA and SCL input signals
SPI Control
SPICTL (F61H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Flush Data
0 = No effect
1 = Clears I2C Data register
SPI Enable
0 = SPI disabled
1 = SPI enabled
Send NAK
0 = Do not send NAK
1 = Send NAK after next byte received
from slave
Master Mode Enabled
0 = SPI configured in Slave mode
1 = SPI configured in Master mode
Enable TDRE Interrupts
0 = Do not generate an interrupt when
the I2C Data register is empty
1 = Generate an interrupt when the I2C
Transmit Data register is empty
Wire-OR (open-drain) Mode Enabled
0 = SPI signals not configured for
open-drain
1 = SPI signals (SCK, SS, MISO, and
MOSI) configured for open-drain
Baud Rate Generator Interrupt Request
0 = Interrupts behave as set by I2C
control
1 = BRG generates an interrupt when
it counts down to zero
Clock Polarity
0 = SCK idles Low
1 = SPI idles High
Send Stop Condition
Phase Select
Sets the phase relationship of the data
to the clock.
0 = Do not issue Stop condition after
data transmission is complete
1 = Issue Stop condition after data
transmission is complete
BRG Timer Interrupt Request
0 = BRG timer function is disabled
1 = BRG time-out interrupt is enabled
Send Start Condition
0 = Do not send Start Condition
1 = Send Start Condition
Start an SPI Interrupt Request
0 = No effect
1 = Generate an SPI interrupt request
I2C Enable
0 = I2C is disabled
1 = I2C is enabled
Interrupt Request Enable
0 = SPI interrupt requests are disabled
1 = SPI interrupt requests are enabled
I2C Baud Rate Generator High Byte
I2CBRH (F53H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
I2C Baud Rate divisor [15:8]
I2C Baud Rate Generator Low Byte
I2CBRL (F54H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
I2C Baud Rate divisor [7:0]
PS019913-0305
P r e l i m i n a r y
Control Register Summary
Z8 Encore!® 64K Series
Z8 Encore!
34
SPI Status
SPISTAT (F62H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
SPI Diagnostic State
SPIDST (F64H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Slave Select
SPI State
0 = If Slave, SS pin is asserted
1 = If Slave, SS pin is not asserted
Transmit Clock Enable
0 = Internal transmit clock enable
signal is deasserted
Transmit Status
0 = No data transmission in progress
1 = Data transmission now in progress
1 = Internal transmit clock enable
signal is asserted
Reserved
Shift Clock Enable
0 = Internal shift clock enable signal
is deasserted
Slave Mode Transaction Abort
0 = No slave mode transaction abort
detected
1 = Internal shift clock enable signal
is asserted
1 = Slave mode transaction abort was
detected
Collision
SPI Baud Rate Generator High Byte
0 = No multi-master collision detected
1 = Multi-master collision was detected
SPIBRH (F66H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Overrun
0 = No overrun error detected
1 = Overrun error was detected
SPI Baud Rate divisor [15:8]
Interrupt Request
0 = No SPI interrupt request pending
1 = SPI interrupt request is pending
SPI Baud Rate Generator Low Byte
SPIBRL (F67H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
SPI Baud Rate divisor [7:0]
SPI Mode
SPIMODE (F63H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
ADC Control
Slave Select Value
ADCCTL (F70H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
If Master and SPIMODE[1] = 1:
0 = SS pin driven Low
1 = SS pin driven High
Analog Input Select
0000 = ANA0
0010 = ANA2
0100 = ANA4
0110 = ANA6
1000 = ANA8
0001 = ANA1
0011 = ANA3
0101 = ANA5
0111 = ANA7
1001 = ANA9
Slave Select I/O
0 = SS pin configured as an input
1 = SS pin configured as an output
(Master mode only)
1010 = ANA10 1011 = ANA11
11xx = Reserved
Number of Data Bits Per Character
000 = 8 bits
001 = 1 bit
Continuous Mode Select
0 = Single-shot conversion
1 = Continuous conversion
010 = 2 bits
011 = 3 bits
100 = 4 bits
101 = 5 bit
External VREF select
0 = Internal voltage reference selected
1 = External voltage reference selected
110 = 6 bits
111 = 7 bits
Diagnostic Mode Control
Reserved
0 = Reading from SPIBRH, SPIBRL
returns reload values
Conversion Enable
0 = Conversion is complete
1 = Begin conversion
1 = Reading from SPIBRH, SPIBRL
returns current BRG count value
Reserved
PS019913-0305
P r e l i m i n a r y
Control Register Summary
Z8 Encore!® 64K Series
Z8 Encore!
35
ADC Data High Byte
ADCD_H (F72H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
DMA0 Address High Nibble
DMA0H (FB2H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
ADC Data [9:2]
DMA0 Start Address [11:8]
DMA0 End Address [11:8]
ADC Data Low Bits
ADCD_L (F73H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
DMA0 Start/Current Address Low Byte
DMA0START (FB3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
ADC Data [1:0]
DMA0 Start Address [7:0]
DMA0 Control
DMA0CTL (FB0H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA0 End Address Low Byte
DMA0END (FB4H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Request Trigger Source Select
DMA0 End Address [7:0]
000 = Timer 0
001 = Timer 1
010 = Timer 2
011 = Timer 3
DMA1 Control
100 = UART0 Received Data register
contains valid data
DMA1CTL (FB8H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
101 = UART1 Received Data register
contains valid data
Request Trigger Source Select
000 = Timer 0
110 = I2C receiver contains valid data
111 = Reserved
001 = Timer 1
010 = Timer 2
Word Select
0 = DMA transfers 1 byte per request
1 = DMA transfers 2 bytes per request
011 = Timer 3
100 = UART0 Transmit Data register
is empty
101 = UART1 Transmit Data register
is empty
DMA0 Interrupt Enable
0 = DMA0 does not generate interrupts
1 = DMA0 generates an interrupt when
End Address data is transferred
110 = I2C Transmit Data register
is empty
111 = Reserved
DMA0 Data Transfer Direction
0 = Register File to peripheral registers
1 = Peripheral registers to Register File
Word Select
0 = DMA transfers 1 byte per request
1 = DMA transfers 2 bytes per request
DMA0 Loop Enable
DMA1 Interrupt Enable
0 = DMA disables after End Address
1 = DMA reloads Start Address after
End Address and continues to run
0 = DMA1 does not generate interrupts
1 = DMA1 generates an interrupt when
End Address data is transferred
DMA0 Enable
0 = DMA0 is disabled
1 = DMA0 is enabled
DMA1 Data Transfer Direction
0 = Register File to peripheral registers
1 = Peripheral registers to Register File
DMA1 Loop Enable
0 = DMA disables after End Address
1 = DMA reloads Start Address after
End Address and continues to run
DMA0 I/O Address
DMA0IO (FB1H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA1 Enable
0 = DMA1 is disabled
1 = DMA1 is enabled
DMA0 Peripheral Register Address
Low byte of on-chip peripheral control
registers on Register File page FH
PS019913-0305
P r e l i m i n a r y
Control Register Summary
Z8 Encore!® 64K Series
Z8 Encore!
36
DMA1 I/O Address
DMA1IO (FB9H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA_ADC Control
DMAACTL (FBEH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA1 Peripheral Register Address
Low byte of on-chip peripheral control
registers on Register File page FH
ADC Analog Input Number
0000 = Analog input 0 updated
0001 = Analog input 0-1 updated
0010 = Analog input 0-2 updated
0011 = Analog input 0-3 updated
0100 = Analog input 0-4 updated
0101 = Analog input 0-5 updated
0100 = Analog input 0-6 updated
0101 = Analog input 0-7 updated
1000 = Analog input 0-8 updated
1001 = Analog input 0-9 updated
1010 = Analog input 0-10 updated
1011 = Analog inputs 0-11 updated
11xx = Reserved
DMA1 Address High Nibble
DMA1H (FBAH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA1 Start Address [11:8]
DMA1 End Address [11:8]
Reserved
Interrupt request enable
0 = DMA_ADC does not generate
interrupt requests
1 = DMA_ADC generates interrupt
requests after last analog input
DMA1 Start/Current Address Low Byte
DMA1START (FBBH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA1 Start Address [7:0]
DMA_ADC Enable
0 = DMA_ADC is disabled
1 = DMA_ADC is enabled
DMA1 End Address Low Byte
DMA1END (FBCH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA Status
DMAA_STAT (FBFH - Read Only)
DMA1 End Address [7:0]
D7 D6 D5 D4 D3 D2 D1 D0
DMA0 Interrupt Request Indicator
0 = DMA0 is not the source of the IRQ
1 = DMA0 is the source of the IRQ
DMA_ADC Address
DMAA_ADDR (FBDH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
DMA1 Interrupt Request Indicator
0 = DMA1 is not the source of the IRQ
1 = DMA1 is the source of the IRQ
Reserved
DMA_ADC Address
DMA_ADC Interrupt Request Indicator
0 = DMA_ADC is not the source of the
IRQ
1 = DMA_ADC is the source of the
IRQ
Reserved
Current ADC analog input
Identifies the analog input the ADC is
currently converting
PS019913-0305
P r e l i m i n a r y
Control Register Summary
Z8 Encore!® 64K Series
Z8 Encore!
37
Interrupt Request 0
IRQ0 (FC0H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
IRQ0 Enable Low Bit
IRQ0ENL (FC2H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
ADC Interrupt Request
ADC IRQ Enable Hit Bit
SPI Interrupt Request
SPI IRQ Enable Low Bit
I2C Interrupt Request
I2C IRQ Enable Low Bit
UART 0 Transmitter IRQ Enable Low
UART 0 Receiver IRQ Enable Low Bit
Timer 0 IRQ Enable Low Bit
Timer 1 IRQ Enable Low Bit
Timer 2 IRQ Enable Low Bit
UART 0 Transmitter Interrupt Request
UART 0 Receiver Interrupt Request
Timer 0 Interrupt Request
Timer 1 Interrupt Request
Timer 2 Interrupt Request
For all of the above peripherals:
0 = Peripheral IRQ is not pending
1 = Peripheral IRQ is awaiting service
Interrupt Request 1
IRQ1 (FC3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
IRQ0 Enable High Bit
Port A or D Pin Interrupt Request
IRQ0ENH (FC1H - Read/Write)
0 = IRQ from corresponding pin [7:0]
is not pending
D7 D6 D5 D4 D3 D2 D1 D0
1 = IRQ from corresponding pin [7:0]
is awaiting service
ADC IRQ Enable Hit Bit
SPI IRQ Enable High Bit
I2C IRQ Enable High Bit
IRQ1 Enable High Bit
IRQ1ENH (FC4H - Read/Write)
UART 0 Transmitter IRQ Enable High
UART 0 Receiver IRQ Enable High Bit
Timer 0 IRQ Enable High Bit
Timer 1 IRQ Enable High Bit
Timer 2 IRQ Enable High Bit
D7 D6 D5 D4 D3 D2 D1 D0
Port A or D Pin IRQ Enable High Bit
IRQ1 Enable Low Bit
IRQ1ENL (FC5H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A or D Pin IRQ Enable Low Bit
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Control Register Summary
Z8 Encore!® 64K Series
Z8 Encore!
38
Interrupt Request 2
IRQ2 (FC6H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Port Select
IRQPS (FCEH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Pin Interrupt Request
Port A or D Port Pin Select [7:0]
0 = Port A pin is the interrupt source
1 = Port D pin is the interrupt source
0 = IRQ from corresponding pin [3:0]
is not pending
1 = IRQ from corresponding pin [3:0]
is awaiting service
DMA Interrupt Request
Interrupt Control
IRQCTL (FCFH - Read/Write)
UART 1 Transmitter Interrupt Request
UART 1 Receiver Interrupt Request
Timer 3 Interrupt Request
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Interrupt Request Enable
0 = Interrupts are disabled
1 = Interrupts are enabled
For all of the above peripherals:
0 = Peripheral IRQ is not pending
1 = Peripheral IRQ is awaiting service
Port A Address
PAADDR (FD0H - Read/Write)
IRQ2 Enable High Bit
D7 D6 D5 D4 D3 D2 D1 D0
IRQ2ENH (FC7H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A Address[7:0]
Selects Port Sub-Registers:
00H = No function
Port C Pin IRQ Enable High Bit
01H = Data direction
DMA IRQ Enable High Bit
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = STOP mode recovery enable
06H-FFH = No function
UART 1 Transmitter IRQ Enable High
UART 1 Receiver IRQ Enable High Bit
Timer 3 IRQ Enable High Bit
Port A Control
PACTL (FD1H - Read/Write)
IRQ2 Enable Low Bit
D7 D6 D5 D4 D3 D2 D1 D0
IRQ2ENL (FC8H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A Control[7:0]
Provides Access to Port Sub-Registers
Port C Pin IRQ Enable Low Bit
DMA IRQ Enable Low Bit
Port A Input Data
UART 1 Transmitter IRQ Enable Low
UART 1 Receiver IRQ Enable Low Bit
Timer 3 IRQ Enable Low Bit
PAIN (FD2H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port A Input Data [7:0]
Port A Output Data
PAOUT (FD3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Edge Select
IRQES (FCDH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port A Output Data [7:0]
Port A or D Interrupt Edge Select [7:0]
0 = Falling edge
1 = Rising edge
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Control Register Summary
Z8 Encore!® 64K Series
Z8 Encore!
39
Port B Address
PBADDR (FD4H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Input Data
PCIN (FDAH - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Input Data [7:0]
Port B Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = STOP mode recovery enable
06H-FFH = No function
Port C Output Data
PCOUT (FDBH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Output Data [7:0]
Port B Control
Port D Address
PDADDR (FDCH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
PBCTL (FD5H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port B Control[7:0]
Provides Access to Port Sub-Registers
Port D Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = STOP mode recovery enable
06H-FFH = No function
Port B Input Data
PBIN (FD6H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port B Input Data [7:0]
Port D Control
Port B Output Data
PBOUT (FD7H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
PDCTL (FDDH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port D Control[7:0]
Provides Access to Port Sub-Registers
Port B Output Data [7:0]
Port C Address
PCADDR (FD8H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port D Input Data
PDIN (FDE H- Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port D Input Data [7:0]
Port C Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = STOP mode recovery enable
06H-FFH = No function
Port D Output Data
PDOUT (FDFH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port D Output Data [7:0]
Port C Control
PCCTL (FD9H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port C Control[7:0]
Provides Access to Port Sub-Registers
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Control Register Summary
Z8 Encore!® 64K Series
Z8 Encore!
40
Port E Address
PEADDR (FE0H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port F Input Data
PFIN (FE6H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port F Input Data [7:0]
Port E Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = STOP mode recovery enable
06H-FFH = No function
Port F Output Data
PFOUT (FE7H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port F Output Data [7:0]
Port E Control
Port G Address
PGADDR (FE8H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
PECTL (FE1H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port E Control[7:0]
Provides Access to Port Sub-Registers
Port G Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = STOP mode recovery enable
06H-FFH = No function
Port E Input Data
PEIN (FE2H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port E Input Data [7:0]
Port G Control
Port E Output Data
PEOUT (FE3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
PGCTL (FE9H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port G Control[7:0]
Provides Access to Port Sub-Registers
Port E Output Data [7:0]
Port F Address
PFADDR (FE4H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port G Input Data
PGIN (FEAH - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port G Input Data [7:0]
Port F Address[7:0]
Selects Port Sub-Registers:
00H = No function
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = STOP mode recovery enable
06H-FFH = No function
Port G Output Data
PGOUT (FEBH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port G Output Data [7:0]
Port F Control
PFCTL (FE5H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port F Control[7:0]
Provides Access to Port Sub-Registers
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Control Register Summary
Z8 Encore!® 64K Series
Z8 Encore!
41
Port H Address
PHADDR (FECH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Watch-Dog Timer Control
WDTCTL (FF0H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
SM Configuration Indicator
Port H Address[7:0]
Reserved
Selects Port Sub-Registers:
00H = No function
EXT
0 = Reset not generated by RESET pin
1 = Reset generated by RESET pin
01H = Data direction
02H = Alternate function
03H = Output control (open-drain)
04H = High drive enable
05H = STOP mode recovery enable
06H-FFH = No function
WDT
0 = WDT timeout has not occurred
1 = WDT timeout occurred
STOP
0 = SMR has not occurred
1 = SMR has occurred
Port H Control
PHCTL (FEDH - Read/Write)
POR
D7 D6 D5 D4 D3 D2 D1 D0
0 = POR has not occurred
1 = POR has occurred
Port H Control [3:0]
Provides Access to Port Sub-Registers
Reserved
Watch-Dog Timer Reload Upper Byte
WDTU (FF1H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port H Input Data
WDT reload value [23:16]
PHIN (FEEH - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port H Input Data [3:0]
Reserved
Watch-Dog Timer Reload Middle Byte
WDTH (FF2 H- Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
WDT reload value [15:8]
Port H Output Data
PHOUT (FEFH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Watch-Dog Timer Reload Low Byte
WDTL (FF3H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Port H Output Data [3:0]
Reserved
WDT reload value [7:0]
Flash Control
FCTL (FF8H - Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Flash Command
73H = First unlock command
8CH = Second unlock command
95H = Page erase command
63H = Mass erase command
5EH = Flash Sector Protect reg select
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Control Register Summary
Z8 Encore!® 64K Series
Z8 Encore!
42
Flash Status
FSTAT (FF8H - Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Flags
FLAGS (FFC - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Flash Controller Status
F1 - User Flag 1
00_0000 = Flash controller locked
00_0001 = First unlock received
00_0010 = Second unlock received
00_0011 = Flash controller unlocked
00_0100 = Flash Sector Protect register
selected
00_1xxx = Programming in progress
01_0xxx = Page erase in progress
10_0xxx = Mass erase in progress
F2 - User Flag 2
H - Half Carry
D - Decimal Adjust
V - Overflow Flag
S - Sign Flag
Reserved
Z - Zero Flag
C - Carry Flag
Page Select
FPS (FF9H - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Register Pointer
Page Select [6:0]
Identifies the Flash memory page for
Page Erase operation.
RP (FFDH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Working Register Page Address [11:8]
Working Register Group Address [7:4]
Information Area Enable
0 = Information Area access is disabled
1 = Information Area access is enabled
Stack Pointer High Byte
Flash Sector Protect
SPH (FFEH - Read/Write)
FPROT (FF9H - Read/Write to 1’s)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer [15:8]
Flash Sector Protect [7:0]
0 = Sector can be programmed or
erased from user code
1 = Sector is protected and cannot be
programmed or erased from user
code
Stack Pointer Low Byte
SPL (FFFH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer [7:0]
Flash Frequency High Byte
FFREQH (FFAH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Flash Frequency value [15:8]
Flash Frequency Low Byte
FFREQL (FFBH - Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Flash Frequency value [7:0]
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Control Register Summary
Z8 Encore!® 64K Series
Product Specification
43
Reset and STOP Mode Recovery
Overview
The Reset Controller within the Z8 Encore!® 64K Series controls Reset and STOP Mode
Recovery operation. In typical operation, the following events cause a Reset to occur:
•
•
•
Power-On Reset (POR)
Voltage Brown-Out (VBO)
Watch-Dog Timer time-out (when configured via the WDT_RES Option Bit to initiate
a Reset)
•
•
External RESET pin assertion
On-Chip Debugger initiated Reset (OCDCTL[0] set to 1)
When the 64K Series devices are in STOP mode, a STOP Mode Recovery is initiated by
either of the following:
•
•
•
Watch-Dog Timer time-out
GPIO Port input pin transition on an enabled STOP Mode Recovery source
DBG pin driven Low
Reset Types
The 64K Series provides two different types of reset operation (System Reset and STOP
Mode Recovery). The type of Reset is a function of both the current operating mode of the
64K Series devices and the source of the Reset. Table 8 lists the types of Reset and their
operating characteristics.
Table 8. Reset and STOP Mode Recovery Characteristics and Latency
Reset Characteristics and Latency
Reset Type
Control Registers
eZ8 CPU Reset Latency (Delay)
System Reset
Reset (as applicable)
Reset
Reset
66 WDT Oscillator cycles + 16 System Clock cycles
66 WDT Oscillator cycles + 16 System Clock cycles
STOP Mode
Recovery
Unaffected, except
WDT_CTL register
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Reset and STOP Mode Recovery
Z8 Encore!® 64K Series
Product Specification
44
System Reset
During a System Reset, the 64K Series devices are held in Reset for 66 cycles of the
Watch-Dog Timer oscillator followed by 16 cycles of the system clock. At the beginning
of Reset, all GPIO pins are configured as inputs.
During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watch-Dog Timer oscillator continue to run. The system clock begins oper-
ating following the Watch-Dog Timer oscillator cycle count. The eZ8 CPU and on-chip
peripherals remain idle through the 16 cycles of the system clock.
Upon Reset, control registers within the Register File that have a defined Reset value are
loaded with their reset values. Other control registers (including the Stack Pointer, Regis-
ter Pointer, and Flags) and general-purpose RAM are undefined following Reset. The eZ8
CPU fetches the Reset vector at Program Memory addresses 0002Hand 0003Hand loads
that value into the Program Counter. Program execution begins at the Reset vector
address.
Reset Sources
Table 9 lists the reset sources as a function of the operating mode. The text following pro-
vides more detailed information on the individual Reset sources. A Power-On Reset/Volt-
age Brown-Out event always takes priority over all other possible reset sources to ensure a
full system reset occurs.
Table 9. Reset Sources and Resulting Reset Type
Operating Mode
Reset Source
Reset Type
Normal or HALT
modes
Power-On Reset / Voltage Brown-Out System Reset
Watch-Dog Timer time-out
when configured for Reset
System Reset
System Reset
RESET pin assertion
On-Chip Debugger initiated Reset
(OCDCTL[0] set to 1)
System Reset except the On-Chip Debugger is
unaffected by the reset
STOP mode
Power-On Reset / Voltage Brown-Out System Reset
RESET pin assertion
DBG pin driven Low
System Reset
System Reset
Power-On Reset
Each device in the 64K Series contains an internal Power-On Reset (POR) circuit. The
POR circuit monitors the supply voltage and holds the device in the Reset state until the
supply voltage reaches a safe operating level. After the supply voltage exceeds the POR
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Product Specification
45
voltage threshold (VPOR), the POR Counter is enabled and counts 66 cycles of the Watch-
Dog Timer oscillator. After the POR counter times out, the XTAL Counter is enabled to
count a total of 16 system clock pulses. The devices are held in the Reset state until both
the POR Counter and XTAL counter have timed out. After the 64K Series devices exit the
Power-On Reset state, the eZ8 CPU fetches the Reset vector. Following Power-On Reset,
the PORstatus bit in the Watch-Dog Timer Control (WDTCTL) register is set to 1.
Figure 8 illustrates Power-On Reset operation. Refer to the Electrical Characteristics
chapter for the POR threshold voltage (VPOR).
VCC = 3.3V
V
POR
V
VBO
Program
Execution
VCC = 0.0V
WDT Clock
Primary
Oscillator
Oscillator
Start-up
Internal RESET
signal
POR
XTAL
counter delay
counter delay
Not to Scale
Figure 8. Power-On Reset Operation)
Voltage Brown-Out Reset
The devices in the 64K Series provide low Voltage Brown-Out (VBO) protection. The
VBO circuit senses when the supply voltage drops to an unsafe level (below the VBO
threshold voltage) and forces the device into the Reset state. While the supply voltage
remains below the Power-On Reset voltage threshold (VPOR), the VBO block holds the
device in the Reset state.
After the supply voltage again exceeds the Power-On Reset voltage threshold, the devices
progress through a full System Reset sequence, as described in the Power-On Reset sec-
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Product Specification
46
tion. Following Power-On Reset, the PORstatus bit in the Watch-Dog Timer Control
(WDTCTL) register is set to 1. Figure 9 illustrates Voltage Brown-Out operation. Refer to
the Electrical Characteristics chapter for the VBO and POR threshold voltages (VVBO
and VPOR).
The Voltage Brown-Out circuit can be either enabled or disabled during STOP mode.
Operation during STOP mode is set by the VBO_AOOption Bit. Refer to the Option Bits
chapter for information on configuring VBO_AO.
VCC = 3.3V
VCC = 3.3V
V
POR
V
VBO
Program
Voltage
Program
Execution
Brownout
Execution
WDT Clock
Primary
Oscillator
Internal RESET
Signal
POR
XTAL
Counter Delay Counter Delay
Figure 9. Voltage Brown-Out Reset Operation
Watch-Dog Timer Reset
If the device is in normal or HALT mode, the Watch-Dog Timer can initiate a System
Reset at time-out if the WDT_RESOption Bit is set to 1. This capability is the default
(unprogrammed) setting of the WDT_RESOption Bit. The WDTstatus bit in the WDT Con-
trol register is set to signify that the reset was initiated by the Watch-Dog Timer.
External Pin Reset
The RESET pin has a Schmitt-triggered input, an internal pull-up, an analog filter and a
digital filter to reject noise. Once the RESET pin is asserted for at least 4 system clock
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Product Specification
47
cycles, the devices progress through the System Reset sequence. While the RESET input
pin is asserted Low, the 64K Series devices continue to be held in the Reset state. If the
RESET pin is held Low beyond the System Reset time-out, the devices exit the Reset state
immediately following RESET pin deassertion. Following a System Reset initiated by the
external RESET pin, the EXTstatus bit in the Watch-Dog Timer Control (WDTCTL) reg-
ister is set to 1.
On-Chip Debugger Initiated Reset
A Power-On Reset can be initiated using the On-Chip Debugger by setting the RSTbit in
the OCD Control register. The On-Chip Debugger block is not reset but the rest of the chip
goes through a normal system reset. The RSTbit automatically clears during the system
reset. Following the system reset the PORbit in the WDT Control register is set.
STOP Mode Recovery
STOP mode is entered by the eZ8 executing a STOPinstruction. Refer to the Section
Low-Power Modes on page 49 for detailed STOP mode information. During STOP Mode
Recovery, the devices are held in reset for 66 cycles of the Watch-Dog Timer oscillator
followed by 16 cycles of the system clock. STOP Mode Recovery only affects the contents
of the Watch-Dog Timer Control register. STOP Mode Recovery does not affect any other
values in the Register File, including the Stack Pointer, Register Pointer, Flags, peripheral
control registers, and general-purpose RAM.
The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002Hand 0003H
and loads that value into the Program Counter. Program execution begins at the Reset vec-
tor address. Following STOP Mode Recovery, the STOPbit in the Watch-Dog Timer Con-
trol Register is set to 1. Table 10 lists the STOP Mode Recovery sources and resulting
actions. The text following provides more detailed information on each of the STOP Mode
Recovery sources.
Table 10. STOP Mode Recovery Sources and Resulting Action
Operating Mode
STOP Mode Recovery Source
Action
STOP mode
Watch-Dog Timer time-out
when configured for Reset
STOP Mode Recovery
Watch-Dog Timer time-out
when configured for interrupt
STOP Mode Recovery followed by interrupt (if
interrupts are enabled)
Data transition on any GPIO Port pin
enabled as a STOP Mode Recovery
source
STOP Mode Recovery
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Product Specification
48
STOP Mode Recovery Using Watch-Dog Timer Time-Out
If the Watch-Dog Timer times out during STOP mode, the device undergoes a STOP
Mode Recovery sequence. In the Watch-Dog Timer Control register, the WDTand STOP
bits are set to 1. If the Watch-Dog Timer is configured to generate an interrupt upon time-
out and the 64K Series devices are configured to respond to interrupts, the eZ8 CPU ser-
vices the Watch-Dog Timer interrupt request following the normal STOP Mode Recovery
sequence.
STOP Mode Recovery Using a GPIO Port Pin Transition HALT
Each of the GPIO Port pins may be configured as a STOP Mode Recovery input source.
On any GPIO pin enabled as a STOP Mode Recovery source, a change in the input pin
value (from High to Low or from Low to High) initiates STOP Mode Recovery. The GPIO
STOP Mode Recovery signals are filtered to reject pulses less than 10ns (typical) in dura-
tion. In the Watch-Dog Timer Control register, the STOPbit is set to 1.
Caution:
In STOP mode, the GPIO Port Input Data registers (PxIN) are disabled.
The Port Input Data registers record the Port transition only if the signal
stays on the Port pin through the end of the STOP Mode Recovery delay.
Thus, short pulses on the Port pin can initiate STOP Mode Recovery with-
out being written to the Port Input Data register or without initiating an in-
terrupt (if enabled for that pin).
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Product Specification
49
Low-Power Modes
Overview
The 64K Series products contain power-saving features. The highest level of power reduc-
tion is provided by STOP mode. The next level of power reduction is provided by the
HALT mode.
STOP Mode
Execution of the eZ8 CPU’s STOP instruction places the device into STOP mode. In
STOP mode, the operating characteristics are:
•
Primary crystal oscillator is stopped; the XIN pin is driven High and the XOUT pin is
driven Low.
•
•
•
•
System clock is stopped
eZ8 CPU is stopped
Program counter (PC) stops incrementing
The Watch-Dog Timer and its internal RC oscillator continue to operate, if enabled for
operation during STOP mode.
•
•
The Voltage Brown-Out protection circuit continues to operate, if enabled for
operation in STOP mode using the associated Option Bit.
All other on-chip peripherals are idle.
To minimize current in STOP mode, all GPIO pins that are configured as digital inputs
must be driven to one of the supply rails (VCC or GND), the Voltage Brown-Out protection
must be disabled, and the Watch-Dog Timer must be disabled. The devices can be brought
out of STOP mode using STOP Mode Recovery. For more information on STOP Mode
Recovery refer to the Reset and STOP Mode Recovery chapter beginning on page 43.
STOP Mode must not be used when driving the 64K Series devices with
an external clock driver source.
Caution:
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Product Specification
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HALT Mode
Execution of the eZ8 CPU’s HALT instruction places the device into HALT mode. In
HALT mode, the operating characteristics are:
•
•
•
•
•
•
•
Primary crystal oscillator is enabled and continues to operate
System clock is enabled and continues to operate
eZ8 CPU is stopped
Program counter (PC) stops incrementing
Watch-Dog Timer’s internal RC oscillator continues to operate
The Watch-Dog Timer continues to operate, if enabled
All other on-chip peripherals continue to operate
The eZ8 CPU can be brought out of HALT mode by any of the following operations:
•
•
•
•
•
Interrupt
Watch-Dog Timer time-out (interrupt or reset)
Power-on reset
Voltage-brown out reset
External RESET pin assertion
To minimize current in HALT mode, all GPIO pins which are configured as inputs must be
driven to one of the supply rails (VCC or GND).
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Z8 Encore!® 64K Series
Product Specification
51
General-Purpose I/O
Overview
The 64K Series products support a maximum of seven 8-bit ports (Ports A–G) and one 4-
bit port (Port H) for general-purpose input/output (I/O) operations. Each port contains
control and data registers. The GPIO control registers are used to determine data direction,
open-drain, output drive current and alternate pin functions. Each port pin is individually
programmable. All ports (except B and H) support 5V-tolerant inputs.
GPIO Port Availability By Device
Table 11 lists the port pins available with each device and package type.
Table 11. Port Availability by Device and Package Type
Device
Packages
40-pin
Port A Port B Port C Port D Port E Port F Port G Port H
Z8X1621
Z8X1621
Z8X1622
Z8X2421
Z8X2421
Z8X2422
Z8X3221
Z8X3221
Z8X3222
Z8X4821
Z8X4821
Z8X4822
Z8X4823
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[6:0] [6:3, 1:0]
-
-
-
-
44-pin
[7:0]
[7:0]
[6:0]
[7:0]
-
-
[7]
-
-
[3]
-
-
64- and 68-pin
40-pin
[7:0]
[3:0]
[6:0] [6:3, 1:0]
-
-
44-pin
[7:0]
[7:0]
[6:0]
[7:0]
-
-
-
-
64- and 68-pin
40-pin
[7:0]
[7]
-
[3]
-
[3:0]
[6:0] [6:3, 1:0]
-
-
44-pin
[7:0]
[7:0]
[6:0]
[7:0]
-
[7:0]
-
-
-
-
[3:0]
-
64- and 68-pin
40-pin
[7]
-
[3]
-
[6:0] [6:3, 1:0]
44-pin
[7:0]
[7:0]
[7:0]
[6:0]
[7:0]
[7:0]
-
-
-
-
64- and 68-pin
80-pin
[7:0]
[7:0]
[7]
[7:0]
[3]
[7:0]
[3:0]
[3:0]
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Table 11. Port Availability by Device and Package Type (Continued)
Device
Packages
40-pin
Port A Port B Port C Port D Port E Port F Port G Port H
Z8X6421
Z8X6421
Z8X6422
Z8X6423
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[6:0] [6:3, 1:0]
-
-
-
-
-
-
44-pin
[7:0]
[7:0]
[7:0]
[6:0]
[7:0]
[7:0]
-
-
64- and 68-pin
80-pin
[7:0]
[7:0]
[7]
[7:0]
[3]
[7:0]
[3:0]
[3:0]
Architecture
Figure 10 illustrates a simplified block diagram of a GPIO port pin. In this figure, the abil-
ity to accommodate alternate functions and variable port current drive strength are not
illustrated.
Port Input
Data Register
Schmitt Trigger
Q
D
System
Clock
VDD
Port Output Control
Port Output
Data Register
DATA
Bus
D
Q
Port
Pin
System
Clock
Port Data Direction
GND
Figure 10. GPIO Port Pin Block Diagram
GPIO Alternate Functions
Many of the GPIO port pins can be used as both general-purpose I/O and to provide access
to on-chip peripheral functions such as the timers and serial communication devices. The
Port A–H Alternate Function sub-registers configure these pins for either general-purpose
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I/O or alternate function operation. When a pin is configured for alternate function, control
of the port pin direction (input/output) is passed from the Port A–H Data Direction regis-
ters to the alternate function assigned to this pin. Table 12 lists the alternate functions
associated with each port pin.
Table 12. Port Alternate Function Mapping
Port
Pin
Mnemonic
T0IN
Alternate Function Description
Timer 0 Input
Port A
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
T0OUT
DE0
Timer 0 Output
UART 0 Driver Enable
UART 0 Clear to Send
CTS0
RXD0 / IRRX0 UART 0 / IrDA 0 Receive Data
TXD0 / IRTX0 UART 0 / IrDA 0 Transmit Data
2
SCL
I C Clock (automatically open-drain)
2
SDA
I C Data (automatically open-drain)
Port B
ANA0
ANA1
ANA2
ANA3
ANA4
ANA5
ANA6
ANA7
T1IN
ADC Analog Input 0
ADC Analog Input 1
ADC Analog Input 2
ADC Analog Input 3
ADC Analog Input 4
ADC Analog Input 5
ADC Analog Input 6
ADC Analog Input 7
Timer 1 Input
Port C
T1OUT
SS
Timer 1 Output
SPI Slave Select
SCK
SPI Serial Clock
MOSI
MISO
T2IN
SPI Master Out Slave In
SPI Master In Slave Out
Timer 2 In
T2OUT
Timer 2 Out
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Table 12. Port Alternate Function Mapping (Continued)
Port
Pin
Mnemonic
T3IN
Alternate Function Description
Port D
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
Timer 3 In (unavailable in 44-pin packages)
Timer 3 Out (unavailable in 44-pin packages)
No alternate function
T3OUT
N/A
DE1
UART 1 Driver Enable
RXD1 / IRRX1 UART 1 / IrDA 1 Receive Data
TXD1 / IRTX1 UART 1 / IrDA 1 Transmit Data
CTS1
UART 1 Clear to Send
Watch-Dog Timer RC Oscillator Output
No alternate functions
No alternate functions
No alternate functions
ADC Analog Input 8
RCOUT
Port E
Port F
Port G
Port H
PE[7:0] N/A
PF[7:0] N/A
PG[7:0] N/A
PH0
PH1
PH2
PH3
ANA8
ANA9
ADC Analog Input 9
ANA10
ANA11
ADC Analog Input 10
ADC Analog Input 11
GPIO Interrupts
Many of the GPIO port pins can be used as interrupt sources. Some port pins may be con-
figured to generate an interrupt request on either the rising edge or falling edge of the pin
input signal. Other port pin interrupts generate an interrupt when any edge occurs (both
rising and falling). Refer to the Interrupt Controller chapter for more information on
interrupts using the GPIO pins.
GPIO Control Register Definitions
Four registers for each Port provide access to GPIO control, input data, and output data.
Table 13 lists these Port registers. Use the Port A–H Address and Control registers
together to provide access to sub-registers for Port configuration and control.
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Table 13. GPIO Port Registers and Sub-Registers
Port Register Mnemonic
Port Register Name
PxADDR
Port A-H Address Register
(Selects sub-registers)
PxCTL
Port A-H Control Register
(Provides access to sub-registers)
Port A-H Input Data Register
Port A-H Output Data Register
PxIN
PxOUT
Port Sub-Register Mnemonic Port Register Name
PxDD
PxAF
Data Direction
Alternate Function
PxOC
Output Control (Open-Drain)
High Drive Enable
PxDD
PxSMRE
STOP Mode Recovery Source Enable
Port A-H Address Registers
The Port A–H Address registers select the GPIO Port functionality accessible through the
Port A–H Control registers. The Port A–H Address and Control registers combine to pro-
vide access to all GPIO Port control (Table 14).
Table 14. Port A-H GPIO Address Registers (PxADDR)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PADDR[7:0]
00H
R/W
FD0H, FD4H, FD8H, FDCH, FE0H, FE4H, FE8H, FECH
ADDR
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PADDR[7:0]—Port Address
The Port Address selects one of the sub-registers accessible through the Port Control reg-
ister.
PADDR[7:0] Port Control sub-register accessible using the Port A-H Control Registers
00H
01H
No function. Provides some protection against accidental Port reconfiguration.
Data Direction
02H
Alternate Function
03H
Output Control (Open-Drain)
High Drive Enable
04H
05H
STOP Mode Recovery Source Enable.
No function.
06H-FFH
Port A-H Control Registers
The Port A–H Control registers set the GPIO port operation. The value in the correspond-
ing Port A–H Address register determines the control sub-registers accessible using the
Port A–H Control register (Table 15).
Table 15. Port A–H Control Registers (PxCTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PCTL
00H
R/W
FD1H, FD5H, FD9H, FDDH, FE1H, FE5H, FE9H, FEDH
ADDR
PCTL[7:0]—Port Control
The Port Control register provides access to all sub-registers that configure the GPIO Port
operation.
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Port A-H Data Direction Sub-Registers
The Port A–H Data Direction sub-register is accessed through the Port A–H Control regis-
ter by writing 01H to the Port A–H Address register (Table 16).
Table 16. Port A-H Data Direction Sub-Registers
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
1
R/W
If 01H in Port A-H Address Register, accessible through Port A-H Control Register
ADDR
DD[7:0]—Data Direction
These bits control the direction of the associated port pin. Port Alternate Function opera-
tion overrides the Data Direction register setting.
0 = Output. Data in the Port A–H Output Data register is driven onto the port pin.
1 = Input. The port pin is sampled and the value written into the Port A-H Input Data Reg-
ister. The output driver is tri-stated.
Port A–H Alternate Function Sub-Registers
The Port A–H Alternate Function sub-register (Table 17) is accessed through the Port A–
H Control register by writing 02Hto the Port A–H Address register. The Port A–H Alter-
nate Function sub-registers select the alternate functions for the selected pins. Refer to the
GPIO Alternate Functions section to determine the alternate function associated with
each port pin.
Caution:
Do not enable alternate function for GPIO port pins which do not have an
associated alternate function. Failure to follow this guideline may result in
unpredictable operation.
Table 17. Port A-H Alternate Function Sub-Registers
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
AF7
AF6
AF5
AF4
AF3
AF2
AF1
AF0
0
R/W
If 02H in Port A-H Address Register, accessible through Port A-H Control Register
ADDR
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AF[7:0]—Port Alternate Function enabled
0 = The port pin is in normal mode and the DDxbit in the Port A–H Data Direction sub-
register determines the direction of the pin.
1 = The alternate function is selected. Port pin operation is controlled by the alternate
function.
Port A-H Output Control Sub-Registers
The Port A-H Output Control sub-register (Table 18) is accessed through the Port A–H
Control register by writing 03Hto the Port A–H Address register. Setting the bits in the
Port A–H Output Control sub-registers to 1 configures the specified port pins for open-
drain operation. These sub-registers affect the pins directly and, as a result, alternate func-
tions are also affected.
Table 18. Port A-H Output Control Sub-Registers
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
POC7
POC6
POC5
POC4
POC3
POC2
POC1
POC0
0
R/W
If 03H in Port A-H Address Register, accessible through Port A-H Control Register
ADDR
POC[7:0]—Port Output Control
These bits function independently of the alternate function bit and disables the drains if set
to 1.
0 = The drains are enabled for any output mode.
1 = The drain of the associated pin is disabled (open-drain mode).
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Port A-H High Drive Enable Sub-Registers
The Port A–H High Drive Enable sub-register (Table 19) is accessed through the Port A–
H Control register by writing 04Hto the Port A-H Address register. Setting the bits in the
Port A–H High Drive Enable sub-registers to 1 configures the specified port pins for high
current output drive operation. The Port A–H High Drive Enable sub-register affects the
pins directly and, as a result, alternate functions are also affected.
Table 19. Port A–H High Drive Enable Sub-Registers
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PHDE7
PHDE6
PHDE5
PHDE4
PHDE3
PHDE2
PHDE1
PHDE0
0
R/W
If 04H in Port A-H Address Register, accessible through Port A-H Control Register
ADDR
PHDE[7:0]—Port High Drive Enabled
0 = The Port pin is configured for standard output current drive.
1 = The Port pin is configured for high output current drive.
Port A-H STOP Mode Recovery Source Enable Sub-Registers
The Port A–H STOP Mode Recovery Source Enable sub-register (Table 20) is accessed
through the Port A–H Control register by writing 05Hto the Port A–H Address register.
Setting the bits in the Port A–H STOP Mode Recovery Source Enable sub-registers to 1
configures the specified Port pins as a STOP Mode Recovery source. During STOP Mode,
any logic transition on a Port pin enabled as a STOP Mode Recovery source initiates
STOP Mode Recovery.
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Table 20. Port A-H STOP Mode Recovery Source Enable Sub-Registers
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PSMRE7
PSMRE6
PSMRE5
PSMRE4
PSMRE3
PSMRE2
PSMRE1
PSMRE0
0
R/W
If 05H in Port A–H Address Register, accessible through Port A-H Control Register
ADDR
PSMRE[7:0]—Port STOP Mode Recovery Source Enabled
0 = The Port pin is not configured as a STOP Mode Recovery source. Transitions on this
pin during STOP mode do not initiate STOP Mode Recovery.
1 = The Port pin is configured as a STOP Mode Recovery source. Any logic transition on
this pin during STOP mode initiates STOP Mode Recovery.
Port A-H Input Data Registers
Reading from the Port A–H Input Data registers (Table 21) returns the sampled values
from the corresponding port pins. The Port A–H Input Data registers are Read-only.
Table 21. Port A–H Input Data Registers (PxIN)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PIN7
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
PIN0
X
R
FD2H, FD6H, FDAH, FDEH, FE2H, FE6H, FEAH, FEEH
ADDR
PIN[7:0]—Port Input Data
Sampled data from the corresponding port pin input.
0 = Input data is logical 0 (Low).
1 = Input data is logical 1 (High).
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Port A–H Output Data Register
The Port A–H Output Data register (Table 22) writes output data to the pins.
Table 22. Port A-H Output Data Register (PxOUT)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
POUT7
POUT6
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
0
R/W
FD3H, FD7H, FDBH, FDFH, FE3H, FE7H, FEBH, FEFH
ADDR
POUT[7:0]—Port Output Data
These bits contain the data to be driven out from the port pins. The values are only driven
if the corresponding pin is configured as an output and the pin is not configured for alter-
nate function operation.
0 = Drive a logical 0 (Low).
1= Drive a logical 1 (High). High value is not driven if the drain has been disabled by set-
ting the corresponding Port Output Control register bit to 1.
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Interrupt Controller
Overview
The interrupt controller on the 64K Series products prioritizes the interrupt requests from
the on-chip peripherals and the GPIO port pins. The features of the interrupt controller
include the following:
•
24 unique interrupt vectors:
–
–
12 GPIO port pin interrupt sources
12 on-chip peripheral interrupt sources
•
Flexible GPIO interrupts
–
–
8 selectable rising and falling edge GPIO interrupts
4 dual-edge interrupts
•
•
3 levels of individually programmable interrupt priority
Watch-Dog Timer can be configured to generate an interrupt
Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly
manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt
service routine is involved with the exchange of data, status information, or control infor-
mation between the CPU and the interrupting peripheral. When the service routine is com-
pleted, the CPU returns to the operation from which it was interrupted.
The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,
the interrupt control has no effect on operation. Refer to the eZ8 CPU User Manual for
more information regarding interrupt servicing by the eZ8 CPU. The eZ8 CPU User Man-
ual is available for download at www.zilog.com.
Interrupt Vector Listing
Table 23 lists all of the interrupts available in order of priority. The interrupt vector is
stored with the most significant byte (MSB) at the even Program Memory address and the
least significant byte (LSB) at the following odd Program Memory address.
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Table 23. Interrupt Vectors in Order of Priority
Program Memory
Priority Vector Address
Highest 0002H
0004H
Interrupt Source
Reset (not an interrupt)
Watch-Dog Timer (see Watch-Dog Timer chapter)
0006H
Illegal Instruction Trap (not an interrupt)
0008H
Timer 2
000AH
Timer 1
000CH
Timer 0
000EH
UART 0 receiver
UART 0 transmitter
0010H
2
0012H
I C
0014H
SPI
0016H
ADC
0018H
Port A7 or Port D7, rising or falling input edge
Port A6 or Port D6, rising or falling input edge
Port A5 or Port D5, rising or falling input edge
Port A4 or Port D4, rising or falling input edge
Port A3 or Port D3, rising or falling input edge
Port A2 or Port D2, rising or falling input edge
Port A1 or Port D1, rising or falling input edge
Port A0 or Port D0, rising or falling input edge
Timer 3 (not available in 44-pin packages)
UART 1 receiver
001AH
001CH
001EH
0020H
0022H
0024H
0026H
0028H
002AH
002CH
UART 1 transmitter
002EH
DMA
0030H
Port C3, both input edges
0032H
Port C2, both input edges
0034H
Port C1, both input edges
Lowest 0036H
Port C0, both input edges
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Architecture
Figure 11 illustrates a block diagram of the interrupt controller.
High
Priority
Port Interrupts
Vector
Priority
Mux
IRQ Request
Medium
Priority
Internal Interrupts
Low
Priority
Figure 11. Interrupt Controller Block Diagram
Operation
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
•
•
•
Executing an EI (Enable Interrupt) instruction
Executing an IRET (Return from Interrupt) instruction
Writing a 1 to the IRQEbit in the Interrupt Control register
Interrupts are globally disabled by any of the following actions:
•
•
Execution of a DI (Disable Interrupt) instruction
eZ8 CPU acknowledgement of an interrupt service request from the interrupt
controller
•
•
Writing a 0 to the IRQEbit in the Interrupt Control register
Reset
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•
•
Executing a Trap instruction
Illegal Instruction trap
Interrupt Vectors and Priority
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest
priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all of
the interrupts were enabled with identical interrupt priority (all as Level 2 interrupts, for
example), then interrupt priority would be assigned from highest to lowest as specified in
Table 23. Level 3 interrupts always have higher priority than Level 2 interrupts which, in
turn, always have higher priority than Level 1 interrupts. Within each interrupt priority
level (Level 1, Level 2, or Level 3), priority is assigned as specified in Table 23. Reset,
Watch-Dog Timer interrupt (if enabled), and Illegal Instruction Trap always have highest
priority.
Interrupt Assertion
Interrupt sources assert their interrupt requests for only a single system clock period (sin-
gle pulse). When the interrupt request is acknowledged by the eZ8 CPU, the correspond-
ing bit in the Interrupt Request register is cleared until the next interrupt occurs. Writing a
0 to the corresponding bit in the Interrupt Request register likewise clears the interrupt
request.
Caution:
The following style of coding to clear bits in the Interrupt Request registers
is NOT recommended. All incoming interrupts that are received between
execution of the first LDX command and the last LDX command are lost.
Poor coding style that can result in lost interrupt requests:
LDX r0, IRQ0
AND r0, MASK
LDX IRQ0, r0
To avoid missing interrupts, the following style of coding to clear bits in
the Interrupt Request 0 register is recommended:
Good coding style that avoids lost interrupt requests:
ANDX IRQ0, MASK
Software Interrupt Assertion
Program code can generate interrupts directly. Writing a 1 to the desired bit in the Interrupt
Request register triggers an interrupt (assuming that interrupt is enabled). When the inter-
rupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request register is
automatically cleared to 0.
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Caution:
The following style of coding to generate software interrupts by setting
bits in the Interrupt Request registers is NOT recommended. All incoming
interrupts that are received between execution of the first LDX command
and the last LDX command are lost.
Poor coding style that can result in lost interrupt requests:
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
To avoid missing interrupts, the following style of coding to set bits in the
Interrupt Request registers is recommended:
Good coding style that avoids lost interrupt requests:
ORX IRQ0, MASK
Interrupt Control Register Definitions
For all interrupts other than the Watch-Dog Timer interrupt, the interrupt control registers
enable individual interrupts, set interrupt priorities, and indicate interrupt requests.
Interrupt Request 0 Register
The Interrupt Request 0 (IRQ0) register (Table 24) stores the interrupt requests for both
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ0 register becomes 1. If interrupts are globally enabled (vec-
tored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 0 register to determine if any interrupt requests are pending
Table 24. Interrupt Request 0 Register (IRQ0)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
T2I
T1I
T0I
U0RXI
U0TXI
I2CI
SPII
ADCI
0
R/W
FC0H
ADDR
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T2I—Timer 2 Interrupt Request
0 = No interrupt request is pending for Timer 2.
1 = An interrupt request from Timer 2 is awaiting service.
T1I—Timer 1 Interrupt Request
0 = No interrupt request is pending for Timer 1.
1 = An interrupt request from Timer 1 is awaiting service.
T0I—Timer 0 Interrupt Request
0 = No interrupt request is pending for Timer 0.
1 = An interrupt request from Timer 0 is awaiting service.
U0RXI—UART 0 Receiver Interrupt Request
0 = No interrupt request is pending for the UART 0 receiver.
1 = An interrupt request from the UART 0 receiver is awaiting service.
U0TXI—UART 0 Transmitter Interrupt Request
0 = No interrupt request is pending for the UART 0 transmitter.
1 = An interrupt request from the UART 0 transmitter is awaiting service.
I2CI— I2C Interrupt Request
0 = No interrupt request is pending for the I2C.
1 = An interrupt request from the I2C is awaiting service.
SPII—SPI Interrupt Request
0 = No interrupt request is pending for the SPI.
1 = An interrupt request from the SPI is awaiting service.
ADCI—ADC Interrupt Request
0 = No interrupt request is pending for the Analog-to-Digital Converter.
1 = An interrupt request from the Analog-to-Digital Converter is awaiting service.
Interrupt Request 1 Register
The Interrupt Request 1 (IRQ1) register (Table 25) stores interrupt requests for both vec-
tored and polled interrupts. When a request is presented to the interrupt controller, the cor-
responding bit in the IRQ1 register becomes 1. If interrupts are globally enabled (vectored
interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts
are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 1
register to determine if any interrupt requests are pending.
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Table 25. Interrupt Request 1 Register (IRQ1)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PAD7I
PAD6I
PAD5I
PAD4I
PAD3I
PAD2I
PAD1I
PAD0I
0
R/W
FC3H
ADDR
PADxI—Port A or Port D Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port A or Port D pin x.
1 = An interrupt request from GPIO Port A or Port D pin x is awaiting service.
where x indicates the specific GPIO Port pin number (0 through 7). For each pin, only 1 of
either Port A or Port D can be enabled for interrupts at any one time. Port selection (A or
D) is determined by the values in the Interrupt Port Select Register.
Interrupt Request 2 Register
The Interrupt Request 2 (IRQ2) register (Table 26) stores interrupt requests for both vec-
tored and polled interrupts. When a request is presented to the interrupt controller, the cor-
responding bit in the IRQ2 register becomes 1. If interrupts are globally enabled (vectored
interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If interrupts
are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt Request 1
register to determine if any interrupt requests are pending.
Table 26. Interrupt Request 2 Register (IRQ2)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
T3I
U1RXI
U1TXI
DMAI
PC3I
PC2I
PC1I
PC0I
0
R/W
FC6H
ADDR
T3I—Timer 3 Interrupt Request
0 = No interrupt request is pending for Timer 3.
1 = An interrupt request from Timer 3 is awaiting service.
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U1RXI—UART 1 Receive Interrupt Request
0 = No interrupt request is pending for the UART1 receiver.
1 = An interrupt request from UART1 receiver is awaiting service.
U1TXI—UART 1 Transmit Interrupt Request
0 = No interrupt request is pending for the UART 1 transmitter.
1 = An interrupt request from the UART 1 transmitter is awaiting service.
DMAI—DMA Interrupt Request
0 = No interrupt request is pending for the DMA.
1 = An interrupt request from the DMA is awaiting service.
PCxI—Port C Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port C pin x.
1 = An interrupt request from GPIO Port C pin x is awaiting service.
where x indicates the specific GPIO Port C pin number (0 through 3).
IRQ0 Enable High and Low Bit Registers
The IRQ0 Enable High and Low Bit registers (Tables 28 and 29) form a priority encoded
enabling for interrupts in the Interrupt Request 0 register. Priority is generated by setting
bits in each register. Table 27 describes the priority control for IRQ0.
Table 27. IRQ0 Enable and Priority Encoding
IRQ0ENH[x] IRQ0ENL[x] Priority
Description
Disabled
Low
0
0
1
1
0
1
0
1
Disabled
Level 1
Level 2
Level 3
Nominal
High
where x indicates the register bits from 0 through 7.
Table 28. IRQ0 Enable High Bit Register (IRQ0ENH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
T2ENH
T1ENH
T0ENH
U0RENH U0TENH
I2CENH
SPIENH ADCENH
0
R/W
FC1H
ADDR
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T2ENH—Timer 2 Interrupt Request Enable High Bit
T1ENH—Timer 1 Interrupt Request Enable High Bit
T0ENH—Timer 0 Interrupt Request Enable High Bit
U0RENH—UART 0 Receive Interrupt Request Enable High Bit
U0TENH—UART 0 Transmit Interrupt Request Enable High Bit
I2CENH—I2C Interrupt Request Enable High Bit
SPIENH—SPI Interrupt Request Enable High Bit
ADCENH—ADC Interrupt Request Enable High Bit
Table 29. IRQ0 Enable Low Bit Register (IRQ0ENL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
T2ENL
T1ENL
T0ENL
U0RENL
U0TENL
I2CENL
SPIENL
ADCENL
0
R/W
FC2H
ADDR
T2ENL—Timer 2 Interrupt Request Enable Low Bit
T1ENL—Timer 1 Interrupt Request Enable Low Bit
T0ENL—Timer 0 Interrupt Request Enable Low Bit
U0RENL—UART 0 Receive Interrupt Request Enable Low Bit
U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit
I2CENL—I2C Interrupt Request Enable Low Bit
SPIENL—SPI Interrupt Request Enable Low Bit
ADCENL—ADC Interrupt Request Enable Low Bit
IRQ1 Enable High and Low Bit Registers
The IRQ1 Enable High and Low Bit registers (Tables 31 and 32) form a priority encoded
enabling for interrupts in the Interrupt Request 1 register. Priority is generated by setting
bits in each register. Table 30 describes the priority control for IRQ1.
Table 30. IRQ1 Enable and Priority Encoding
IRQ1ENH[x] IRQ1ENL[x] Priority
Description
Disabled
Low
0
0
1
1
0
1
0
1
Disabled
Level 1
Level 2
Level 3
Nominal
High
where x indicates the register bits from 0 through 7.
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Table 31. IRQ1 Enable High Bit Register (IRQ1ENH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PAD7ENH PAD6ENH PAD5ENH PAD4ENH PAD3ENH PAD2ENH PAD1ENH PAD0ENH
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC4H
ADDR
PADxENH—Port A or Port D Bit[x] Interrupt Request Enable High Bit
Refer to the Interrupt Port Select register for selection of either Port A or Port D as the
interrupt source.
Table 32. IRQ1 Enable Low Bit Register (IRQ1ENL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PAD7ENL PAD6ENL PAD5ENL PAD4ENL PAD3ENL PAD2ENL PAD1ENL PAD0ENL
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC5H
ADDR
PADxENL—Port A or Port D Bit[x] Interrupt Request Enable Low Bit
Refer to the Interrupt Port Select register for selection of either Port A or Port D as the
interrupt source.
IRQ2 Enable High and Low Bit Registers
The IRQ2 Enable High and Low Bit registers (Tables 34 and 35) form a priority encoded
enabling for interrupts in the Interrupt Request 2 register. Priority is generated by setting
bits in each register. Table 33 describes the priority control for IRQ2.
Table 33. IRQ2 Enable and Priority Encoding
IRQ2ENH[x] IRQ2ENL[x] Priority
Description
Disabled
Low
0
0
1
1
0
1
0
1
Disabled
Level 1
Level 2
Level 3
Nominal
High
where x indicates the register bits from 0 through 7.
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Table 34. IRQ2 Enable High Bit Register (IRQ2ENH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
T3ENH
U1RENH U1TENH DMAENH
C3ENH
C2ENH
C1ENH
C0ENH
0
R/W
FC7H
ADDR
T3ENH—Timer 3 Interrupt Request Enable High Bit
U1RENH—UART 1 Receive Interrupt Request Enable High Bit
U1TENH—UART 1 Transmit Interrupt Request Enable High Bit
DMAENH—DMA Interrupt Request Enable High Bit
C3ENH—Port C3 Interrupt Request Enable High Bit
C2ENH—Port C2 Interrupt Request Enable High Bit
C1ENH—Port C1 Interrupt Request Enable High Bit
C0ENH—Port C0 Interrupt Request Enable High Bit
Table 35. IRQ2 Enable Low Bit Register (IRQ2ENL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
T3ENL
U1RENL
U1TENL DMAENL
C3ENL
C2ENL
C1ENL
C0ENL
0
R/W
FC8H
ADDR
T3ENL—Timer 3 Interrupt Request Enable Low Bit
U1RENL—UART 1 Receive Interrupt Request Enable Low Bit
U1TENL—UART 1 Transmit Interrupt Request Enable Low Bit
DMAENL—DMA Interrupt Request Enable Low Bit
C3ENL—Port C3 Interrupt Request Enable Low Bit
C2ENL—Port C2 Interrupt Request Enable Low Bit
C1ENL—Port C1 Interrupt Request Enable Low Bit
C0ENL—Port C0 Interrupt Request Enable Low Bit
Interrupt Edge Select Register
The Interrupt Edge Select (IRQES) register (Table 36) determines whether an interrupt is
generated for the rising edge or falling edge on the selected GPIO Port input pin. The
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Interrupt Port Select register selects between Port A and Port D for the individual inter-
rupts.
Table 36. Interrupt Edge Select Register (IRQES)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
IES7
IES6
IES5
IES4
IES3
IES2
IES1
IES0
0
R/W
FCDH
ADDR
IESx—Interrupt Edge Select x
The minimum pulse width should be greater than 1 system clock to guarantee capture of
the edge triggered interrupt. Shorter pulses may be captured but not guaranteed.
0 = An interrupt request is generated on the falling edge of the PAx/PDx input.
1 = An interrupt request is generated on the rising edge of the PAx/PDx input.
where x indicates the specific GPIO Port pin number (0 through 7),
Interrupt Port Select Register
The Port Select (IRQPS) register (Table 37) determines the port pin that generates the
PAx/PDx interrupts. This register allows either Port A or Port D pins to be used as inter-
rupts. The Interrupt Edge Select register controls the active interrupt edge.
Table 37. Interrupt Port Select Register (IRQPS)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PAD7S
PAD6S
PAD5S
PAD4S
PAD3S
PAD2S
PAD1S
PAD0S
0
R/W
FCEH
ADDR
PADxS—PAx/PDx Selection
0 = PAx is used for the interrupt for PAx/PDx interrupt request.
1 = PDx is used for the interrupt for PAx/PDx interrupt request.
where x indicates the specific GPIO Port pin number (0 through 7)
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Interrupt Control Register
The Interrupt Control (IRQCTL) register (Table 38) contains the master enable bit for all
interrupts.
Table 38. Interrupt Control Register (IRQCTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
IRQE
Reserved
0
R/W
R
FCFH
ADDR
IRQE—Interrupt Request Enable
This bit is set to 1 by execution of an EI (Enable Interrupts) or IRET (Interrupt Return)
instruction, or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI
instruction, eZ8 CPU acknowledgement of an interrupt request, or Reset.
0 = Interrupts are disabled
1 = Interrupts are enabled
Reserved
Must be 0.
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Timers
Overview
The 64K Series products contain up to four 16-bit reloadable timers that can be used for
timing, event counting, or generation of pulse-width modulated (PWM) signals. The tim-
ers’ features include:
•
•
•
•
•
16-bit reload counter
Programmable prescaler with prescale values from 1 to 128
PWM output generation
Capture and compare capability
External input pin for timer input, clock gating, or capture signal. External input pin
signal frequency is limited to a maximum of one-fourth the system clock frequency.
•
•
Timer output pin
Timer interrupt
In addition to the timers described in this chapter, the Baud Rate Generators for any
unused UART, SPI, or I2C peripherals may also be used to provide basic timing function-
ality. Refer to the respective serial communication peripheral chapters for information on
using the Baud Rate Generators as timers. Timer 3 is unavailable in the 44-pin package
devices.
Architecture
Figure 12 illustrates the architecture of the timers.
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Timer Block
Timer
Control
Data
Bus
Block
Control
16-Bit
Reload Register
Interrupt,
PWM,
Timer
Interrupt
and
Timer Output
Control
Timer
Output
System
Clock
16-Bit Counter
with Prescaler
Timer
Input
Gate
Input
16-Bit
PWM / Compare
Capture
Input
Figure 12. Timer Block Diagram
Operation
The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value
0001Hinto the Timer Reload High and Low Byte registers and setting the prescale value
to 1. Maximum time-out delay is set by loading the value 0000Hinto the Timer Reload
High and Low Byte registers and setting the prescale value to 128. If the Timer reaches
FFFFH, the timer rolls over to 0000Hand continues counting.
Timer Operating Modes
The timers can be configured to operate in the following modes:
ONE-SHOT Mode
In ONE-SHOT mode, the timer counts up to the 16-bit Reload value stored in the Timer
Reload High and Low Byte registers. The timer input is the system clock. Upon reaching
the Reload value, the timer generates an interrupt and the count value in the Timer High
and Low Byte registers is reset to 0001H. Then, the timer is automatically disabled and
stops counting.
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
for one system clock cycle (from Low to High or from High to Low) upon timer Reload. If
it is desired to have the Timer Output make a permanent state change upon One-Shot time-
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out, first set the TPOLbit in the Timer Control 1 Register to the start value before begin-
ning ONE-SHOT mode. Then, after starting the timer, set TPOLto the opposite bit value.
The steps for configuring a timer for ONE-SHOT mode and initiating the count are as fol-
lows:
1. Write to the Timer Control 1 register to:
–
–
–
–
Disable the timer
Configure the timer for ONE-SHOT mode
Set the prescale value
If using the Timer Output alternate function, set the initial output level (High or
Low)
2. Write to the Timer High and Low Byte registers to set the starting count value
3. Write to the Timer Reload High and Low Byte registers to set the Reload value
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function
6. Write to the Timer Control 1 register to enable the timer and initiate counting
In ONE-SHOT mode, the system clock always provides the timer input. The timer period
is given by the following equation:
(Reload Value – Start Value) × Prescale
One-Shot Mode Time-Out Period (s) = -----------------------------------------------------------------------------------------------------
System Clock Frequency (Hz)
CONTINUOUS Mode
In CONTINUOUS mode, the timer counts up to the 16-bit Reload value stored in the
Timer Reload High and Low Byte registers. The timer input is the system clock. Upon
reaching the Reload value, the timer generates an interrupt, the count value in the Timer
High and Low Byte registers is reset to 0001Hand counting resumes. Also, if the Timer
Output alternate function is enabled, the Timer Output pin changes state (from Low to
High or from High to Low) upon timer Reload.
The steps for configuring a timer for CONTINUOUS mode and initiating the count are as
follows:
1. Write to the Timer Control 1 register to:
–
–
–
Disable the timer
Configure the timer for CONTINUOUS mode
Set the prescale value
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–
If using the Timer Output alternate function, set the initial output level (High or
Low)
2. Write to the Timer High and Low Byte registers to set the starting count value (usually
0001H), affecting only the first pass in CONTINUOUS mode. After the first timer
Reload in CONTINUOUS mode, counting always begins at the reset value of 0001H.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control 1 register to enable the timer and initiate counting.
In CONTINUOUS mode, the system clock always provides the timer input. The timer
period is given by the following equation:
Reload Value × Prescale
Continuous Mode Time-Out Period (s) = ---------------------------------------------------------------------------
System Clock Frequency (Hz)
If an initial starting value other than 0001His loaded into the Timer High and Low Byte
registers, the ONE-SHOT mode equation must be used to determine the first time-out
period.
COUNTER Mode
In COUNTER mode, the timer counts input transitions from a GPIO port pin. The timer
input is taken from the GPIO Port pin Timer Input alternate function. The TPOLbit in the
Timer Control 1 Register selects whether the count occurs on the rising edge or the falling
edge of the Timer Input signal. In COUNTER mode, the prescaler is disabled.
Caution:
The input frequency of the Timer Input signal must not exceed one-fourth
the system clock frequency.
Upon reaching the Reload value stored in the Timer Reload High and Low Byte registers,
the timer generates an interrupt, the count value in the Timer High and Low Byte registers
is reset to 0001Hand counting resumes. Also, if the Timer Output alternate function is
enabled, the Timer Output pin changes state (from Low to High or from High to Low) at
timer Reload.
The steps for configuring a timer for COUNTER mode and initiating the count are as fol-
lows:
1. Write to the Timer Control 1 register to:
–
–
Disable the timer
Configure the timer for COUNTER mode
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–
Select either the rising edge or falling edge of the Timer Input signal for the count.
This also sets the initial logic level (High or Low) for the Timer Output alternate
function. However, the Timer Output function does not have to be enabled
2. Write to the Timer High and Low Byte registers to set the starting count value. This
only affects the first pass in COUNTER mode. After the first timer Reload in
COUNTER mode, counting always begins at the reset value of 0001H. Generally, in
COUNTER mode the Timer High and Low Byte registers must be written with the
value 0001H.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. Configure the associated GPIO port pin for the Timer Input alternate function.
6. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
7. Write to the Timer Control 1 register to enable the timer.
In COUNTER mode, the number of Timer Input transitions since the timer start is given
by the following equation:
Counter Mode Timer Input Transitions = Current Count Value – Start Value
PWM Mode
In PWM mode, the timer outputs a Pulse-Width Modulator (PWM) output signal through
a GPIO Port pin. The timer input is the system clock. The timer first counts up to the 16-
bit PWM match value stored in the Timer PWM High and Low Byte registers. When the
timer count value matches the PWM value, the Timer Output toggles. The timer continues
counting until it reaches the Reload value stored in the Timer Reload High and Low Byte
registers. Upon reaching the Reload value, the timer generates an interrupt, the count
value in the Timer High and Low Byte registers is reset to 0001Hand counting resumes.
If the TPOLbit in the Timer Control 1 register is set to 1, the Timer Output signal begins
as a High (1) and then transitions to a Low (0) when the timer value matches the PWM
value. The Timer Output signal returns to a High (1) after the timer reaches the Reload
value and is reset to 0001H.
If the TPOLbit in the Timer Control 1 register is set to 0, the Timer Output signal begins
as a Low (0) and then transitions to a High (1) when the timer value matches the PWM
value. The Timer Output signal returns to a Low (0) after the timer reaches the Reload
value and is reset to 0001H.
The steps for configuring a timer for PWM mode and initiating the PWM operation are as
follows:
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1. Write to the Timer Control 1 register to:
–
–
–
–
Disable the timer
Configure the timer for PWM mode
Set the prescale value
Set the initial logic level (High or Low) and PWM High/Low transition for the
Timer Output alternate function
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H). This only affects the first pass in PWM mode. After the first timer
reset in PWM mode, counting always begins at the reset value of 0001H.
3. Write to the PWM High and Low Byte registers to set the PWM value.
4. Write to the Timer Reload High and Low Byte registers to set the Reload value (PWM
period). The Reload value must be greater than the PWM value.
5. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
6. Configure the associated GPIO port pin for the Timer Output alternate function.
7. Write to the Timer Control 1 register to enable the timer and initiate counting.
The PWM period is given by the following equation:
Reload Value × Prescale
PWM Period (s) = ---------------------------------------------------------------------------
System Clock Frequency (Hz)
If an initial starting value other than 0001His loaded into the Timer High and Low Byte
registers, the One-Shot mode equation must be used to determine the first PWM time-out
period.
If TPOLis set to 0, the ratio of the PWM output High time to the total period is given by:
Reload Value – PWM Value
-----------------------------------------------------------------------
PWM Output High Time Ratio (%) =
× 100
Reload Value
If TPOLis set to 1, the ratio of the PWM output High time to the total period is given by:
PWM Value
Reload Value
---------------------------------
PWM Output High Time Ratio (%) =
× 100
Capture Mode
In CAPTURE mode, the current timer count value is recorded when the desired external
Timer Input transition occurs. The Capture count value is written to the Timer PWM High
and Low Byte Registers. The timer input is the system clock. The TPOLbit in the Timer
Control 1 register determines if the Capture occurs on a rising edge or a falling edge of the
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Timer Input signal. When the Capture event occurs, an interrupt is generated and the timer
continues counting.
The timer continues counting up to the 16-bit Reload value stored in the Timer Reload
High and Low Byte registers. Upon reaching the Reload value, the timer generates an
interrupt and continues counting.
The steps for configuring a timer for CAPTURE mode and initiating the count are as fol-
lows:
1. Write to the Timer Control 1 register to:
–
–
–
–
Disable the timer
Configure the timer for CAPTURE mode.
Set the prescale value.
Set the Capture edge (rising or falling) for the Timer Input.
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H).
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. Clear the Timer PWM High and Low Byte registers to 0000H. This allows user
software to determine if interrupts were generated by either a capture event or a
reload. If the PWM High and Low Byte registers still contain 0000Hafter the
interrupt, then the interrupt was generated by a Reload.
5. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
6. Configure the associated GPIO port pin for the Timer Input alternate function.
7. Write to the Timer Control 1 register to enable the timer and initiate counting.
In CAPTURE mode, the elapsed time from timer start to Capture event can be calculated
using the following equation:
(Capture Value – Start Value) × Prescale
Capture Elapsed Time (s) = ---------------------------------------------------------------------------------------------------------
System Clock Frequency (Hz)
Compare Mode
In COMPARE mode, the timer counts up to the 16-bit maximum Compare value stored in
the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon
reaching the Compare value, the timer generates an interrupt and counting continues (the
timer value is not reset to 0001H). Also, if the Timer Output alternate function is enabled,
the Timer Output pin changes state (from Low to High or from High to Low) upon Com-
pare.
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If the Timer reaches FFFFH, the timer rolls over to 0000Hand continue counting.
The steps for configuring a timer for COMPARE mode and initiating the count are as fol-
lows:
1. Write to the Timer Control 1 register to:
–
–
–
–
Disable the timer
Configure the timer for COMPARE mode
Set the prescale value
Set the initial logic level (High or Low) for the Timer Output alternate function, if
desired
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the Compare value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control 1 register to enable the timer and initiate counting.
In COMPARE mode, the system clock always provides the timer input. The Compare time
is given by the following equation:
(Compare Value – Start Value) × Prescale
Compare Mode Time (s) = -----------------------------------------------------------------------------------------------------------
System Clock Frequency (Hz)
GATED Mode
In GATED mode, the timer counts only when the Timer Input signal is in its active state
(asserted), as determined by the TPOLbit in the Timer Control 1 register. When the Timer
Input signal is asserted, counting begins. A timer interrupt is generated when the Timer
Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal
deassertion generated the interrupt, read the associated GPIO input value and compare to
the value stored in the TPOLbit.
The timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low
Byte registers. The timer input is the system clock. When reaching the Reload value, the
timer generates an interrupt, the count value in the Timer High and Low Byte registers is
reset to 0001Hand counting resumes (assuming the Timer Input signal is still asserted).
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
(from Low to High or from High to Low) at timer reset.
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The steps for configuring a timer for GATED mode and initiating the count are as follows:
1. Write to the Timer Control 1 register to:
–
–
–
Disable the timer
Configure the timer for GATED mode
Set the prescale value
2. Write to the Timer High and Low Byte registers to set the starting count value. This
only affects the first pass in GATED mode. After the first timer reset in GATED mode,
counting always begins at the reset value of 0001H.
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. Configure the associated GPIO port pin for the Timer Input alternate function.
6. Write to the Timer Control 1 register to enable the timer.
7. Assert the Timer Input signal to initiate the counting.
CAPTURE/COMPARE Mode
In CAPTURE/COMPARE mode, the timer begins counting on the first external Timer
Input transition. The desired transition (rising edge or falling edge) is set by the TPOLbit
in the Timer Control 1 Register. The timer input is the system clock.
Every subsequent desired transition (after the first) of the Timer Input signal captures the
current count value. The Capture value is written to the Timer PWM High and Low Byte
Registers. When the Capture event occurs, an interrupt is generated, the count value in the
Timer High and Low Byte registers is reset to 0001H, and counting resumes.
If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the Compare value, the timer
generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
0001H and counting resumes.
The steps for configuring a timer for CAPTURE/COMPARE mode and initiating the
count are as follows:
1. Write to the Timer Control 1 register to:
–
–
–
–
Disable the timer
Configure the timer for CAPTURE/COMPARE mode
Set the prescale value
Set the Capture edge (rising or falling) for the Timer Input
2. Write to the Timer High and Low Byte registers to set the starting count value
(typically 0001H).
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3. Write to the Timer Reload High and Low Byte registers to set the Compare value.
4. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
the relevant interrupt registers.
5. Configure the associated GPIO port pin for the Timer Input alternate function.
6. Write to the Timer Control 1 register to enable the timer.
7. Counting begins on the first appropriate transition of the Timer Input signal. No
interrupt is generated by this first edge.
In m/COMPARE mode, the elapsed time from timer start to Capture event can be calcu-
lated using the following equation:
(Capture Value – Start Value) × Prescale
---------------------------------------------------------------------------------------------------------
Capture Elapsed Time (s) =
System Clock Frequency (Hz)
Reading the Timer Count Values
The current count value in the timers can be read while counting (enabled). This capability
has no effect on timer operation. When the timer is enabled and the Timer High Byte reg-
ister is read, the contents of the Timer Low Byte register are placed in a holding register. A
subsequent read from the Timer Low Byte register returns the value in the holding register.
This operation allows accurate reads of the full 16-bit timer count value while enabled.
When the timers are not enabled, a read from the Timer Low Byte register returns the
actual value in the counter.
Timer Output Signal Operation
Timer Output is a GPIO Port pin alternate function. Generally, the Timer Output is toggled
every time the counter is reloaded.
Timer Control Register Definitions
Timers 0-2 are available in all packages. Timer 3 is only available in the 64-, 68-, and 80-
pin packages.
Timer 0-3 High and Low Byte Registers
The Timer 0-3 High and Low Byte (TxH and TxL) registers (Tables 38 and 39) contain the
current 16-bit timer count value. When the timer is enabled, a read from TxH causes the
value in TxL to be stored in a temporary holding register. A read from TMRL always
returns this temporary register when the timers are enabled. When the timer is disabled,
reads from the TMRL reads the register directly.
Writing to the Timer High and Low Byte registers while the timer is enabled is not recom-
mended. There are no temporary holding registers available for write operations, so simul-
taneous 16-bit writes are not possible. If either the Timer High or Low Byte registers are
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written during counting, the 8-bit written value is placed in the counter (High or Low
Byte) at the next clock edge. The counter continues counting from the new value.
Timer 3 is unavailable in the 40- and 44-pin packages.
Table 38. Timer 0-3 High Byte Register (TxH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TH
0
R/W
F00H, F08H, F10H, F18H
ADDR
Table 39>. Timer 0-3 Low Byte Register (TxL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TL
0
1
R/W
F01H, F09H, F11H, F19H
ADDR
TH and TL—Timer High and Low Bytes
These 2 bytes, {TMRH[7:0], TMRL[7:0]}, contain the current 16-bit timer count value.
Timer Reload High and Low Byte Registers
The Timer 0-3 Reload High and Low Byte (TxRH and TxRL) registers (Tables 40 and 41)
store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the Timer Reload
High Byte register are stored in a temporary holding register. When a write to the Timer
Reload Low Byte register occurs, the temporary holding register value is written to the
Timer High Byte register. This operation allows simultaneous updates of the 16-bit Timer
Reload value.
In COMPARE mode, the Timer Reload High and Low Byte registers store the 16-bit
Compare value.
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Table 40. Timer 0-3 Reload High Byte Register (TxRH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TRH
1
R/W
F02H, F0AH, F12H, F1AH
ADDR
Table 41. Timer 0-3 Reload Low Byte Register (TxRL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TRL
1
R/W
F03H, F0BH, F13H, F1BH
ADDR
TRH and TRL—Timer Reload Register High and Low
These two bytes form the 16-bit Reload value, {TRH[7:0], TRL[7:0]}. This value sets the
maximum count value which initiates a timer reload to 0001H. In COMPARE mode, these
two byte form the 16-bit Compare value.
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Timer 0-3 PWM High and Low Byte Registers
The Timer 0-3 PWM High and Low Byte (TxPWMH and TxPWML) registers (Tables 42
and 43) are used for Pulse-Width Modulator (PWM) operations. These registers also store
the Capture values for the Capture and Capture/COMPARE modes.
Table 42. Timer 0-3 PWM High Byte Register (TxPWMH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PWMH
0
R/W
F04H, F0CH, F14H, F1CH
ADDR
Table 43. Timer 0-3 PWM Low Byte Register (TxPWML)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PWML
0
R/W
F05H, F0DH, F15H, F1DH
ADDR
PWMH and PWML—Pulse-Width Modulator High and Low Bytes
These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the
current 16-bit timer count. When a match occurs, the PWM output changes state. The
PWM output value is set by the TPOLbit in the Timer Control 1 Register (TxCTL1) regis-
ter.
The TxPWMH and TxPWML registers also store the 16-bit captured timer value when
operating in Capture or Capture/COMPARE modes.
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Timer 0-3 Control 0 Registers
The Timer 0-3 Control 0 (TxCTL0) registers (Tables 44 and 45) allow cascading of the
Timers.
Table 44. Timer 0-3 Control 0 Register (TxCTL0)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
Reserved
CSC
Reserved
0
R/W
F06H, F0EH, F16H, F1EH
ADDR
CSC—Cascade Timers
0 = Timer Input signal comes from the pin.
1 = For Timer 0, Input signal is connected to Timer 3 output.
For Timer 1, Input signal is connected to Timer 0 output.
For Timer 2, Input signal is connected to Timer 1 output.
For Timer 3, Input signal is connected to Timer 2 output.
Timer 0-3 Control 1 Registers
The Timer 0-3 Control 1 (TxCTL1) registers enable/disable the timers, set the prescaler
value, and determine the timer operating mode.
Table 45. Timer 0-3 Control 1 Register (TxCTL1)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TEN
TPOL
PRES
TMODE
0
R/W
F07H, F0FH, F17H, F1FH
ADDR
TEN—Timer Enable
0 = Timer is disabled.
1 = Timer enabled to count.
TPOL—Timer Input/Output Polarity
Operation of this bit is a function of the current operating mode of the timer.
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ONE-SHOT mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
CONTINUOUS mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
COUNTER mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
PWM mode
0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the
Timer Output is forced High (1) upon PWM count match and forced Low (0) upon
Reload.
1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the
Timer Output is forced Low (0) upon PWM count match and forced High (1) upon
Reload.
CAPTURE mode
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
COMPARE mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
GATED mode
0 = Timer counts when the Timer Input signal is High (1) and interrupts are generated
on the falling edge of the Timer Input.
1 = Timer counts when the Timer Input signal is Low (0) and interrupts are generated
on the rising edge of the Timer Input.
CAPTURE/COMPARE mode
0 = Counting is started on the first rising edge of the Timer Input signal. The current
count is captured on subsequent rising edges of the Timer Input signal.
1 = Counting is started on the first falling edge of the Timer Input signal. The current
count is captured on subsequent falling edges of the Timer Input signal.
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When the Timer Output alternate function TxOUT on a GPIO port pin is
Caution:
enabled, TxOUT will change to whatever state the TPOL bit is in. The tim-
er does not need to be enabled for that to happen. Also, the Port data direc-
tion sub register is not needed to be set to output on TxOUT. Changing the
TPOL bit with the timer enabled and running does not immediately change
the TxOUT.
PRES—Prescale value.
The timer input clock is divided by 2PRES, where PRES can be set from 0 to 7. The
prescaler is reset each time the Timer is disabled. This insures proper clock division
each time the Timer is restarted.
000 = Divide by 1
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Divide by 128
TMODE—TIMER mode
000 = ONE-SHOT mode
001 = CONTINUOUS mode
010 = COUNTER mode
011 = PWM mode
100 = CAPTURE mode
101 = COMPARE mode
110 = GATED mode
111 = CAPTURE/COMPARe mode
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Watch-Dog Timer
Overview
The Watch-Dog Timer (WDT) helps protect against corrupt or unreliable software, power
faults, and other system-level problems which may place the Z8 Encore!® into unsuitable
operating states. The Watch-Dog Timer includes the following features:
•
•
•
•
On-chip RC oscillator
A selectable time-out response:
WDT Time-out response: Reset or interrupt
24-bit programmable time-out value
Operation
The Watch-Dog Timer (WDT) is a retriggerable one-shot timer that resets or interrupts the
64K Series devices when the WDT reaches its terminal count. The Watch-Dog Timer uses
its own dedicated on-chip RC oscillator as its clock source. The Watch-Dog Timer has
only two modes of operation—ON and OFF. Once enabled, it always counts and must be
refreshed to prevent a time-out. An enable can be performed by executing the WDT
instruction or by setting the WDT_AOOption Bit. The WDT_AObit enables the Watch-Dog
Timer to operate all the time, even if a WDT instruction has not been executed.
The Watch-Dog Timer is a 24-bit reloadable downcounter that uses three 8-bit registers in
the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is
given by the following equation:
WDT Reload Value
-------------------------------------------------
WDT Time-out Period (ms) =
10
where the WDT reload value is the decimal value of the 24-bit value given by
{WDTU[7:0], WDTH[7:0], WDTL[7:0]} and the typical Watch-Dog Timer RC oscillator
frequency is 10kHz. The Watch-Dog Timer cannot be refreshed once it reaches 000002H.
The WDT Reload Value must not be set to values below 000004H. Table 46 provides
information on approximate time-out delays for the minimum and maximum WDT reload
values.
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Table 46. Watch-Dog Timer Approximate Time-Out Delays
Approximate Time-Out Delay
(with 10kHz typical WDT oscillator frequency)
WDT Reload Value
WDT Reload Value
(Hex)
000004
FFFFFF
(Decimal)
4
Typical
400µs
Description
Minimum time-out delay
Maximum time-out delay
16,777,215
1677.5s
Watch-Dog Timer Refresh
When first enabled, the Watch-Dog Timer is loaded with the value in the Watch-Dog
Timer Reload registers. The Watch-Dog Timer then counts down to 000000Hunless a
WDT instruction is executed by the eZ8 CPU. Execution of the WDT instruction causes
the downcounter to be reloaded with the WDT Reload value stored in the Watch-Dog
Timer Reload registers. Counting resumes following the reload operation.
When the 64K Series devices are operating in Debug Mode (through the On-Chip Debug-
ger), the Watch-Dog Timer is continuously refreshed to prevent spurious Watch-Dog
Timer time-outs.
Watch-Dog Timer Time-Out Response
The Watch-Dog Timer times out when the counter reaches 000000H. A time-out of the
Watch-Dog Timer generates either an interrupt or a Reset. The WDT_RESOption Bit
determines the time-out response of the Watch-Dog Timer. Refer to the Option Bits chap-
ter for information regarding programming of the WDT_RESOption Bit.
WDT Interrupt in Normal Operation
If configured to generate an interrupt when a time-out occurs, the Watch-Dog Timer issues
an interrupt request to the interrupt controller and sets the WDTstatus bit in the Watch-Dog
Timer Control register. If interrupts are enabled, the eZ8 CPU responds to the interrupt
request by fetching the Watch-Dog Timer interrupt vector and executing code from the
vector address. After time-out and interrupt generation, the Watch-Dog Timer counter
rolls over to its maximum value of FFFFFHand continues counting. The Watch-Dog
Timer counter is not automatically returned to its Reload Value.
WDT Interrupt in STOP Mode
If configured to generate an interrupt when a time-out occurs and the 64K Series devices
are in STOP mode, the Watch-Dog Timer automatically initiates a STOP Mode Recovery
and generates an interrupt request. Both the WDTstatus bit and the STOPbit in the Watch-
Dog Timer Control register are set to 1 following WDT time-out in STOP mode. Refer to
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the Reset and STOP Mode Recovery chapter for more information on STOP Mode
Recovery.
If interrupts are enabled, following completion of the STOP Mode Recovery the eZ8 CPU
responds to the interrupt request by fetching the Watch-Dog Timer interrupt vector and
executing code from the vector address.
WDT Reset in Normal Operation
If configured to generate a Reset when a time-out occurs, the Watch-Dog Timer forces the
device into the Reset state. The WDTstatus bit in the Watch-Dog Timer Control register is
set to 1. Refer to the Reset and STOP Mode Recovery chapter for more information on
Reset.
WDT Reset in STOP Mode
If enabled in STOP mode and configured to generate a Reset when a time-out occurs and
the device is in STOP mode, the Watch-Dog Timer initiates a STOP Mode Recovery. Both
the WDTstatus bit and the STOPbit in the Watch-Dog Timer Control register are set to 1
following WDT time-out in STOP mode. Refer to the Reset and STOP Mode Recovery
chapter for more information. Default operation is for the WDT and its RC oscillator to be
enabled during STOP mode.
WDT RC Disable in STOP Mode
To minimize power consumption in STOP Mode, the WDT and its RC oscillator can be
disabled in STOP mode. The following sequence configures the WDT to be disabled when
the 64K Series devices enter STOP Mode following execution of a STOP instruction:
1. Write 55Hto the Watch-Dog Timer Control register (WDTCTL).
2. Write AAHto the Watch-Dog Timer Control register (WDTCTL).
3. Write 81Hto the Watch-Dog Timer Control register (WDTCTL) to configure the
WDT and its oscillator to be disabled during STOP Mode. Alternatively, write 00Hto
the Watch-Dog Timer Control register (WDTCTL) as the third step in this sequence to
reconfigure the WDT and its oscillator to be enabled during STOP Mode.
This sequence only affects WDT operation in STOP mode.
Watch-Dog Timer Reload Unlock Sequence
Writing the unlock sequence to the Watch-Dog Timer (WDTCTL) Control register address
unlocks the three Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL)
to allow changes to the time-out period. These write operations to the WDTCTL register
address produce no effect on the bits in the WDTCTL register. The locking mechanism
prevents spurious writes to the Reload registers. The follow sequence is required to unlock
the Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) for write
access.
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1. Write 55Hto the Watch-Dog Timer Control register (WDTCTL).
2. Write AAHto the Watch-Dog Timer Control register (WDTCTL).
3. Write the Watch-Dog Timer Reload Upper Byte register (WDTU).
4. Write the Watch-Dog Timer Reload High Byte register (WDTH).
5. Write the Watch-Dog Timer Reload Low Byte register (WDTL).
All steps of the Watch-Dog Timer Reload Unlock sequence must be written in the order
just listed. There must be no other register writes between each of these operations. If a
register write occurs, the lock state machine resets and no further writes can occur, unless
the sequence is restarted. The value in the Watch-Dog Timer Reload registers is loaded
into the counter when the Watch-Dog Timer is first enabled and every time a WDT
instruction is executed.
Watch-Dog Timer Control Register Definitions
Watch-Dog Timer Control Register
The Watch-Dog Timer Control (WDTCTL) register, detailed in Table 47, is a Read-Only
register that indicates the source of the most recent Reset event, indicates a STOP Mode
Recovery event, and indicates a Watch-Dog Timer time-out. Reading this register resets
the upper four bits to 0.
Writing the 55H, AAHunlock sequence to the Watch-Dog Timer Control (WDTCTL) reg-
ister address unlocks the three Watch-Dog Timer Reload Byte registers (WDTU, WDTH,
and WDTL) to allow changes to the time-out period. These write operations to the
WDTCTL register address produce no effect on the bits in the WDTCTL register. The
locking mechanism prevents spurious writes to the Reload registers.
Table 47. Watch-Dog Timer Control Register (WDTCTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
POR
STOP
WDT
EXT
Reserved
SM
See descriptions below
0
R
FF0H
ADDR
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Reset or STOP Mode Recovery Event
Power-On Reset
POR
STOP
WDT
EXT
1
0
0
1
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
Reset using RESET pin assertion
0
0
0
0
1
1
Reset using Watch-Dog Timer time-out
Reset using the On-Chip Debugger (OCDCTL[1] set to 1)
Reset from STOP Mode using DBG Pin driven Low
STOP Mode Recovery using GPIO pin transition
STOP Mode Recovery using Watch-Dog Timer time-out
POR—Power-On Reset Indicator
If this bit is set to 1, a Power-On Reset event occurred. This bit is reset to 0 if a WDT time-
out or STOP Mode Recovery occurs. This bit is also reset to 0 when the register is read.
STOP—STOP Mode Recovery Indicator
If this bit is set to 1, a STOP Mode Recovery occurred. If the STOPand WDTbits are both
set to 1, the STOP Mode Recovery occurred due to a WDT time-out. If the STOPbit is 1
and the WDTbit is 0, the STOP Mode Recovery was not caused by a WDT time-out. This
bit is reset by a Power-On Reset or a WDT time-out that occurred while not in STOP
mode. Reading this register also resets this bit.
WDT—Watch-Dog Timer Time-Out Indicator
If this bit is set to 1, a WDT time-out occurred. A Power-On Reset resets this pin. A STOP
Mode Recovery from a change in an input pin also resets this bit. Reading this register
resets this bit.
EXT—External Reset Indicator
If this bit is set to 1, a Reset initiated by the external RESET pin occurred. A Power-On
Reset or a STOP Mode Recovery from a change in an input pin resets this bit. Reading this
register resets this bit.
Reserved
These bits are reserved and must be 0.
SM—STOP Mode Configuration Indicator
0 = Watch-Dog Timer and its internal RC oscillator will continue to operate in STOP
Mode.
1 = Watch-Dog Timer and its internal RC oscillator will be disabled in STOP Mode.
Watch-Dog Timer Reload Upper, High and Low Byte Registers
The Watch-Dog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) reg-
isters (Tables 48 through 50) form the 24-bit reload value that is loaded into the Watch-
Dog Timer when a WDT instruction executes. The 24-bit reload value is {WDTU[7:0],
WDTH[7:0], WDTL[7:0]}. Writing to these registers sets the desired Reload Value. Read-
ing from these registers returns the current Watch-Dog Timer count value.
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Caution:
The 24-bit WDT Reload Value must not be set to a value less than
000004H.
Table 48. Watch-Dog Timer Reload Upper Byte Register (WDTU)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
WDTU
1
R/W*
FF1H
ADDR
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
WDTU—WDT Reload Upper Byte
Most significant byte (MSB), Bits[23:16], of the 24-bit WDT reload value.
Table 49. Watch-Dog Timer Reload High Byte Register (WDTH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
WDTH
1
R/W*
FF2H
ADDR
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
WDTH—WDT Reload High Byte
Middle byte, Bits[15:8], of the 24-bit WDT reload value.
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Table 50. Watch-Dog Timer Reload Low Byte Register (WDTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
WDTL
1
R/W*
FF3H
ADDR
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
WDTL—WDT Reload Low
Least significant byte (LSB), Bits[7:0], of the 24-bit WDT reload value.
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UART
Overview
The Universal Asynchronous Receiver/Transmitter (UART) is a full-duplex communica-
tion channel capable of handling asynchronous data transfers. The UART uses a single
8-bit data mode with selectable parity. Features of the UART include:
•
•
•
•
•
•
•
•
•
•
8-bit asynchronous data transfer
Selectable even- and odd-parity generation and checking
Option of one or two Stop bits
Separate transmit and receive interrupts
Framing, parity, overrun and break detection
Separate transmit and receive enables
16-bit Baud Rate Generator (BRG)
Selectable Multiprocessor (9-bit) mode with three configurable interrupt schemes
Baud Rate Generator timer mode
Driver Enable output for external bus transceivers
Architecture
The UART consists of three primary functional blocks: transmitter, receiver, and baud rate
generator. The UART’s transmitter and receiver function independently, but employ the
same baud rate and data format. Figure 13 illustrates the UART architecture.
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Z8 Encore!® 64K Series
Product Specification
99
Parity Checker
Receive Shifter
Receiver Control
with address compare
RXD
Receive Data
Register
Control Registers
System Bus
Transmit Data
Status Register
Baud Rate
Generator
Register
Transmit Shift
Register
TXD
Transmitter Control
Parity Generator
CTS
DE
Figure 13. UART Block Diagram
Operation
Data Format
The UART always transmits and receives data in an 8-bit data format, least-significant bit
first. An even or odd parity bit can be optionally added to the data stream. Each character
begins with an active Low Start bit and ends with either 1 or 2 active High Stop bits.
Figures 14 and 15 illustrates the asynchronous data format employed by the UART with-
out parity and with parity, respectively.
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100
Data Field
Stop Bit(s)
msb
Idle State
of Line
lsb
1
0
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
1
2
Figure 14. UART Asynchronous Data Format without Parity
Data Field
Stop Bit(s)
Idle State
of Line
lsb
msb
Bit7
1
0
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Parity
1
2
Figure 15. UART Asynchronous Data Format with Parity
Transmitting Data using the Polled Method
Follow these steps to transmit data using the polled method of operation:
1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO Port pins for
alternate function operation.
3. If multiprocessor mode is desired, write to the UART Control 1 register to enable
Multiprocessor (9-bit) mode functions.
–
Set the MULTIPROCESSOR Mode Select (MPEN) to Enable
MULTIPROCESSOR mode.
4. Write to the UART Control 0 register to:
–
–
Set the transmit enable bit (TEN) to enable the UART for data transmission
If parity is desired and MULTIPROCESSOR mode is not enabled, set the parity
enable bit (PEN) and select either Even or Odd parity (PSEL).
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–
Set or clear the CTSEbit to enable or disable control from the remote receiver
using the CTS pin.
5. Check the TDREbit in the UART Status 0 register to determine if the Transmit Data
register is empty (indicated by a 1). If empty, continue to Step 6. If the Transmit Data
register is full (indicated by a 0), continue to monitor the TDREbit until the Transmit
Data register becomes available to receive new data.
6. Write the UART Control 1 register to select the outgoing address bit.
7. Set the MULTIPROCESSOR Bit Transmitter (MPBT) if sending an address byte, clear
it if sending a data byte.
8. Write the data byte to the UART Transmit Data register. The transmitter automatically
transfers the data to the Transmit Shift register and transmits the data.
9. If desired and MULTIPROCESSOR mode is enabled, make any changes to the
MULTIPROCESSOR Bit Transmitter (MPBT) value.
10. To transmit additional bytes, return to Step 5.
Transmitting Data using the Interrupt-Driven Method
The UART transmitter interrupt indicates the availability of the Transmit Data register to
accept new data for transmission. Follow these steps to configure the UART for interrupt-
driven data transmission:
1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO Port pins for
alternate function operation.
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt control registers to enable the UART Transmitter interrupt and
set the desired priority.
5. If MULTIPROCESSOR mode is desired, write to the UART Control 1 register to
enable MULTIPROCESSOR (9-bit) mode functions.
6. Set the MULTIPROCESSOR Mode Select (MPEN) to Enable MULTIPROCESSOR
mode
7. Write to the UART Control 0 register to:
–
–
Set the transmit enable bit (TEN) to enable the UART for data transmission
Enable parity, if desired and if multiprocessor mode is not enabled, and select
either even or odd parity
–
Set or clear the CTSEbit to enable or disable control from the remote receiver via
the CTS pin
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8. Execute an EI instruction to enable interrupts.
The UART is now configured for interrupt-driven data transmission. Because the UART
Transmit Data register is empty, an interrupt is generated immediately. When the UART
Transmit interrupt is detected, the associated interrupt service routine (ISR) performs the
following:
1. Write the UART Control 1 register to select the outgoing address bit:
–
Set the MULTIPROCESSOR Bit Transmitter (MPBT) if sending an address byte,
clear it if sending a data byte.
2. Write the data byte to the UART Transmit Data register. The transmitter automatically
transfers the data to the Transmit Shift register and transmits the data.
3. Clear the UART Transmit interrupt bit in the applicable Interrupt Request register.
4. Execute the IRET instruction to return from the interrupt-service routine and wait for
the Transmit Data register to again become empty.
Receiving Data using the Polled Method
Follow these steps to configure the UART for polled data reception:
1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO Port pins for
alternate function operation.
3. Write to the UART Control 1 register to enable Multiprocessor mode functions, if
desired.
4. Write to the UART Control 0 register to:
–
–
Set the receive enable bit (REN) to enable the UART for data reception
Enable parity, if desired and if multiprocessor mode is not enabled, and select
either even or odd parity
5. Check the RDAbit in the UART Status 0 register to determine if the Receive Data
register contains a valid data byte (indicated by a 1). If RDAis set to 1 to indicate
available data, continue to Step 6. If the Receive Data register is empty (indicated by a
0), continue to monitor the RDA bit awaiting reception of the valid data.
6. Read data from the UART Receive Data register. If operating in Multiprocessor (9-bit)
mode, further actions may be required depending on the Multiprocessor Mode bits
MPMD[1:0].
7. Return to Step 5 to receive additional data.
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Receiving Data using the Interrupt-Driven Method
The UART Receiver interrupt indicates the availability of new data (as well as error con-
ditions). Follow these steps to configure the UART receiver for interrupt-driven operation:
1. Write to the UART Baud Rate High and Low Byte registers to set the desired baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO Port pins for
alternate function operation.
3. Execute a DIinstruction to disable interrupts.
4. Write to the Interrupt control registers to enable the UART Receiver interrupt and set
the desired priority.
5. Clear the UART Receiver interrupt in the applicable Interrupt Request register.
6. Write to the UART Control 1 Register to enable Multiprocessor (9-bit) mode
functions, if desired.
–
–
–
Set the MULTIPROCESSOR Mode Select (MPEN) to Enable Multiprocessor
mode
Set the MULTIPROCESSOR Mode Bits, MPMD[1:0],to select the desired
address matching scheme
Configure the UART to interrupt on received data and errors or errors only
(interrupt on errors only is unlikely to be useful for Z8 Encore! devices without a
DMA block)
7. Write the device address to the Address Compare Register (automatic multiprocessor
modes only).
8. Write to the UART Control 0 register to:
–
–
Set the receive enable bit (REN) to enable the UART for data reception
Enable parity, if desired and if multiprocessor mode is not enabled, and select
either even or odd parity
9. Execute an EIinstruction to enable interrupts.
The UART is now configured for interrupt-driven data reception. When the UART
Receiver interrupt is detected, the associated interrupt service routine (ISR) performs the
following:
1. Check the UART Status 0 register to determine the source of the interrupt - error,
break, or received data.
2. If the interrupt was caused by data available, read the data from the UART Receive
Data register. If operating in MULTIPROCESSOR (9-bit) mode, further actions may
be required depending on the MULTIPROCESSOR Mode bits MPMD[1:0].
3. Clear the UART Receiver interrupt in the applicable Interrupt Request register.
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4. Execute the IRET instruction to return from the interrupt-service routine and await
more data.
Clear To Send (CTS) Operation
The CTS pin, if enabled by the CTSE bit of the UART Control 0 register, performs flow
control on the outgoing transmit datastream. The Clear To Send (CTS) input pin is sam-
pled one system clock before beginning any new character transmission. To delay trans-
mission of the next data character, an external receiver must deassert CTS at least one
system clock cycle before a new data transmission begins. For multiple character trans-
missions, this would typically be done during Stop Bit transmission. If CTS deasserts in
the middle of a character transmission, the current character is sent completely.
MULTIPROCESSOR (9-bit) Mode
The UART has a MULTIPROCESSOR (9-bit) mode that uses an extra (9th) bit for selec-
tive communication when a number of processors share a common UART bus. In MULTI-
PROCESSOR mode (also referred to as 9-Bit mode), the multiprocessor bit (MP) is
transmitted immediately following the 8-bits of data and immediately preceding the Stop
bit(s) as illustrated in Figure 16. The character format is:
Data Field
Stop Bit(s)
Idle State
of Line
lsb
msb
Bit7
1
0
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
MP
1
2
Figure 16. UART Asynchronous MULTIPROCESSOR Mode Data Format
In MULTIPROCESSOR (9-bit) mode, the Parity bit location (9th bit) becomes the MUL-
TIPROCESSOR control bit. The UART Control 1 and Status 1 registers provide MULTI-
PROCESSOR (9-bit) mode control and status information. If an automatic address
matching scheme is enabled, the UART Address Compare register holds the network
address of the device.
MULTIPROCESSOR (9-bit) Mode Receive Interrupts
When MULTIPROCESSOR mode is enabled, the UART only processes frames addressed
to it. The determination of whether a frame of data is addressed to the UART can be made
in hardware, software or some combination of the two, depending on the multiprocessor
configuration bits. In general, the address compare feature reduces the load on the CPU,
since it does not need to access the UART when it receives data directed to other devices
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on the multi-node network. The following three MULTIPROCESSOR modes are avail-
able in hardware:
•
•
•
Interrupt on all address bytes
Interrupt on matched address bytes and correctly framed data bytes
Interrupt only on correctly framed data bytes
These modes are selected with MPMD[1:0]in the UART Control 1 Register. For all
MULTIPROCESSOR modes, bit MPENof the UART Control 1 Register must be set to 1.
The first scheme is enabled by writing 01b to MPMD[1:0]. In this mode, all incoming
address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt
service routine must manually check the address byte that caused triggered the interrupt. If
it matches the UART address, the software clears MPMD[0]. At this point, each new
incoming byte interrupts the CPU. The software is then responsible for determining the
end of the frame. It checks for end-of-frame by reading the MPRXbit of the UART Status
1 Register for each incoming byte. If MPRX=1, a new frame has begun. If the address of
this new frame is different from the UART’s address, then set MPMD[0]to 1 causing the
UART interrupts to go inactive until the next address byte. If the new frame’s address
matches the UART’s, the data in the new frame is processed as well.
The second scheme is enabled by setting MPMD[1:0]to 10b and writing the UART’s
address into the UART Address Compare Register. This mode introduces more hardware
control, interrupting only on frames that match the UART’s address. When an incoming
address byte does not match the UART’s address, it is ignored. All successive data bytes in
this frame are also ignored. When a matching address byte occurs, an interrupt is issued
and further interrupts now occur on each succesive data byte. The first data byte in the
frame contains the NEWFRM=1 in the UART Status 1 Register. When the next address byte
occurs, the hardware compares it to the UART’s address. If there is a match, the interrupts
continue sand the NEWFRMbit is set for the first byte of the new frame. If there is no
match, then the UART ignores all incoming bytes until the next address match.
The third scheme is enabled by setting MPMD[1:0]to 11b and by writing the UART’s
address into the UART Address Compare Register. This mode is identical to the second
scheme, except that there are no interrupts on address bytes. The first data byte of each
frame is still accompanied by a NEWFRMassertion.
External Driver Enable
The UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This feature
reduces the software overhead associated with using a GPIO pin to control the transceiver
when communicating on a multi-transceiver bus, such as RS-485.
Driver Enable is an active High signal that envelopes the entire transmitted data frame
including parity and Stop bits as illustrated in Figure 17. The Driver Enable signal asserts
when a byte is written to the UART Transmit Data register. The Driver Enable signal
asserts at least one UART bit period and no greater than two UART bit periods before the
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Start bit is transmitted. This timing allows a setup time to enable the transceiver. The
Driver Enable signal deasserts one system clock period after the last Stop bit is transmit-
ted. This one system clock delay allows both time for data to clear the transceiver before
disabling it, as well as the ability to determine if another character follows the current
character. In the event of back to back characters (new data must be written to the Trans-
mit Data Register before the previous character is completely transmitted) the DEsignal is
not deasserted between characters. The DEPOLbit in the UART Control Register 1 sets the
polarity of the Driver Enable signal.
1
DE
0
Data Field
Stop Bit
Idle State
of Line
lsb
msb
Bit7
1
0
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Parity
1
Figure 17. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)
The Driver Enable to Startbit setup time is calculated as follows:
1
2
⎛
⎝
⎞
⎠
⎛
⎝
⎞
⎠
-------------------------------------
-------------------------------------
≤ DE to Start Bit Setup Time (s) ≤
Baud Rate (Hz)
Baud Rate (Hz)
UART Interrupts
The UART features separate interrupts for the transmitter and the receiver. In addition,
when the UART primary functionality is disabled, the Baud Rate Generator can also func-
tion as a basic timer with interrupt capability.
Transmitter Interrupts
The transmitter generates a single interrupt when the Transmit Data Register Empty bit
(TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for trans-
mission. The TDREinterrupt occurs after the Transmit shift register has shifted the first bit
of data out. At this point, the Transmit Data register may be written with the next character
to send. This provides 7 bit periods of latency to load the Transmit Data register before the
Transmit shift register completes shifting the current character. Writing to the UART
Transmit Data register clears the TDREbit to 0.
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Receiver Interrupts
The receiver generates an interrupt when any of the following occurs:
•
A data byte has been received and is available in the UART Receive Data register.
This interrupt can be disabled independent of the other receiver interrupt sources. The
received data interrupt occurs once the receive character has been received and placed
in the Receive Data register. Software must respond to this received data available
condition before the next character is completely received to avoid an overrun error.
Note that in multiprocessor mode (MPEN= 1), the receive data interrupts are
dependent on the multiprocessor configuration and the most recent address byte.
•
•
•
A break is received
An overrun is detected
A data framing error is detected
UART Overrun Errors
When an overrun error condition occurs the UART prevents overwriting of the valid data
currently in the Receive Data register. The Break Detect and Overrun status bits are not
displayed until after the valid data has been read.
After the valid data has been read, the UART Status 0 register is updated to indicate the
overrun condition (and Break Detect, if applicable). The RDAbit is set to 1 to indicate that
the Receive Data register contains a data byte. However, because the overrun error
occurred, this byte may not contain valid data and should be ignored. The BRKDbit indi-
cates if the overrun was caused by a break condition on the line. After reading the status
byte indicating an overrun error, the Receive Data register must be read again to clear the
error bits is the UART Status 0 register. Updates to the Receive Data register occur only
when the next data word is received.
UART Data and Error Handling Procedure
Figure 18 illustrates the recommended procedure for use in UART receiver interrupt ser-
vice routines.
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Receiver
Ready
Receiver
Interrupt
Read Status
No
Errors?
Yes
Read Data which
clears RDA bit and
resets error bits
Read Data
Discard Data
Figure 18. UART Receiver Interrupt Service Routine Flow
Baud Rate Generator Interrupts
If the Baud Rate Generator (BRG) interrupt enable is set, the UART Receiver interrupt
asserts when the UART Baud Rate Generator reloads. This action allows the Baud Rate
Generator to function as an additional counter if the UART functionality is not employed.
UART Baud Rate Generator
The UART Baud Rate Generator creates a lower frequency baud rate clock for data trans-
mission. The input to the Baud Rate Generator is the system clock. The UART Baud Rate
High and Low Byte registers combine to create a 16-bit baud rate divisor value
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(BRG[15:0]) that sets the data transmission rate (baud rate) of the UART. The UART data
rate is calculated using the following equation:
System Clock Frequency (Hz)
16 × UART Baud Rate Divisor Value
----------------------------------------------------------------------------------------------
UART Data Rate (bits/s) =
When the UART is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt
on time-out, complete the following procedure:
1. Disable the UART by clearing the RENand TENbits in the UART Control 0 register
to 0.
2. Load the desired 16-bit count value into the UART Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BRGCTLbit in the UART Control 1 register to 1.
When configured as a general purpose timer, the interrupt interval is calculated using the
following equation:
Interrupt Interval (s) = System Clock Period (s) ×BRG[15:0]
]
UART Control Register Definitions
The UART control registers support the UART and the associated Infrared Encoder/
Decoders. For more information on the infrared operation, refer to the Infrared Encoder/
Decoder chapter on page 119.
UART Transmit Data Register
Data bytes written to the UART Transmit Data register (Table 51) are shifted out on the
TXDx pin. The Write-only UART Transmit Data register shares a Register File address
with the Read-only UART Receive Data register.
Table 51. UART Transmit Data Register (UxTXD)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TXD
X
W
F40H and F48H
ADDR
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TXD—Transmit Data
UART transmitter data byte to be shifted out through the TXDx pin.
UART Receive Data Register
Data bytes received through the RXDx pin are stored in the UART Receive Data register
(Table 52). The Read-only UART Receive Data register shares a Register File address
with the Write-only UART Transmit Data register.
Table 52. UART Receive Data Register (UxRXD)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
RXD
X
R
F40H and F48H
ADDR
RXD—Receive Data
UART receiver data byte from the RXDx pin
UART Status 0 Register
The UART Status 0 and Status 1 registers (Table 53 and 54) identify the current UART
operating configuration and status.
Table 53. UART Status 0 Register (UxSTAT0)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
RDA
PE
OE
FE
BRKD
TDRE
TXE
CTS
0
1
X
R
F41H and F49H
ADDR
RDA—Receive Data Available
This bit indicates that the UART Receive Data register has received data. Reading the
UART Receive Data register clears this bit.
0 = The UART Receive Data register is empty.
1 = There is a byte in the UART Receive Data register.
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PE—Parity Error
This bit indicates that a parity error has occurred. Reading the UART Receive Data regis-
ter clears this bit.
0 = No parity error occurred.
1 = A parity error occurred.
OE—Overrun Error
This bit indicates that an overrun error has occurred. An overrun occurs when new data is
received and the UART Receive Data register has not been read. If the RDA bit is reset to
0, then reading the UART Receive Data register clears this bit.
0 = No overrun error occurred.
1 = An overrun error occurred.
FE—Framing Error
This bit indicates that a framing error (no Stop bit following data reception) was detected.
Reading the UART Receive Data register clears this bit.
0 = No framing error occurred.
1 = A framing error occurred.
BRKD—Break Detect
This bit indicates that a break occurred. If the data bits, parity/multiprocessor bit, and Stop
bit(s) are all zeros then this bit is set to 1. Reading the UART Receive Data register clears
this bit.
0 = No break occurred.
1 = A break occurred.
TDRE—Transmitter Data Register Empty
This bit indicates that the UART Transmit Data register is empty and ready for additional
data. Writing to the UART Transmit Data register resets this bit.
0 = Do not write to the UART Transmit Data register.
1 = The UART Transmit Data register is ready to receive an additional byte to be transmit-
ted.
TXE—Transmitter Empty
This bit indicates that the transmit shift register is empty and character transmission is fin-
ished.
0 = Data is currently transmitting.
1 = Transmission is complete.
CTS—CTS signal
When this bit is read it returns the level of the CTS signal.
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UART Status 1 Register
This register contains multiprocessor control and status bits.
Table 54. UART Status 1 Register (UxSTAT1)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
Reserved
NEWFRM
MPRX
0
R
R/W
R
F44H and F4CH
ADDR
Reserved—Must be 0.
NEWFRM—Status bit denoting the start of a new frame. Reading the UART Receive
Data register resets this bit to 0.
0 = The current byte is not the first data byte of a new frame.
1 = The current byte is the first data byte of a new frame.
MPRX—Multiprocessor Receive
Returns the value of the last multiprocessor bit received. Reading from the UART Receive
Data register resets this bit to 0.
UART Control 0 and Control 1 Registers
The UART Control 0 and Control 1 registers (Tables 55 and 56) configure the properties
of the UART’s transmit and receive operations. The UART Control registers must not
been written while the UART is enabled.
Table 55. UART Control 0 Register (UxCTL0)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TEN
REN
CTSE
PEN
PSEL
SBRK
STOP
LBEN
0
R/W
F42H and F4AH
ADDR
TEN—Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSEbit. If the CTS signal is low and the CTSEbit is 1, the transmitter is
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enabled.
0 = Transmitter disabled.
1 = Transmitter enabled.
REN—Receive Enable
This bit enables or disables the receiver.
0 = Receiver disabled.
1 = Receiver enabled.
CTSE—CTS Enable
0 = The CTS signal has no effect on the transmitter.
1 = The UART recognizes the CTS signal as an enable control from the transmitter.
PEN—Parity Enable
This bit enables or disables parity. Even or odd is determined by the PSELbit. It is over-
ridden by the MPENbit.
0 = Parity is disabled.
1 = The transmitter sends data with an additional parity bit and the receiver receives an
additional parity bit.
PSEL—Parity Select
0 = Even parity is transmitted and expected on all received data.
1 = Odd parity is transmitted and expected on all received data.
SBRK—Send Break
This bit pauses or breaks data transmission. Sending a break interrupts any transmission in
progress, so ensure that the transmitter has finished sending data before setting this bit.
0 = No break is sent.
1 = The output of the transmitter is zero.
STOP—Stop Bit Select
0 = The transmitter sends one stop bit.
1 = The transmitter sends two stop bits.
LBEN—Loop Back Enable
0 = Normal operation.
1 = All transmitted data is looped back to the receiver.
Table 56. UART Control 1 Register (UxCTL1)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
MPMD[1]
MPEN
MPMD[0]
MPBT
DEPOL
BRGCTL
RDAIRQ
IREN
0
R/W
F43H and F4BH
ADDR
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MPMD[1:0]—MULTIPROCESSOR Mode
If MULTIPROCESSOR (9-bit) mode is enabled,
00 = The UART generates an interrupt request on all received bytes (data and address).
01 = The UART generates an interrupt request only on received address bytes.
10 = The UART generates an interrupt request when a received address byte matches the
value stored in the Address Compare Register and on all successive data bytes until an
address mismatch occurs.
11 = The UART generates an interrupt request on all received data bytes for which the
most recent address byte matched the value in the Address Compare Register.
MPEN—MULTIPROCESSOR (9-bit) Enable
This bit is used to enable MULTIPROCESSOR (9-bit) mode.
0 = Disable MULTIPROCESSOR (9-bit) mode.
1 = Enable MULTIPROCESSOR (9-bit) mode.
MPBT—MULTIPROCESSOR Bit Transmit
This bit is applicable only when MULTIPROCESSOR (9-bit) mode is enabled.
0 = Send a 0 in the multiprocessor bit location of the data stream (9th bit).
1 = Send a 1 in the multiprocessor bit location of the data stream (9th bit).
DEPOL—Driver Enable Polarity
0 = DEsignal is Active High.
1 = DEsignal is Active Low.
BRGCTL—Baud Rate Control
This bit causes different UART behavior depending on whether the UART receiver is
enabled (REN = 1 in the UART Control 0 Register).
When the UART receiver is not enabled, this bit determines whether the Baud Rate Gener-
ator issues interrupts.
0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value
1 = The Baud Rate Generator generates a receive interrupt when it counts down to 0.
Reads from the Baud Rate High and Low Byte registers return the current BRG count
value.
When the UART receiver is enabled, this bit allows reads from the Baud Rate Registers to
return the BRG count value instead of the Reload Value.
0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value.
1 = Reads from the Baud Rate High and Low Byte registers return the current BRG count
value. Unlike the Timers, there is no mechanism to latch the High Byte when the Low
Byte is read.
RDAIRQ—Receive Data Interrupt Enable
0 = Received data and receiver errors generates an interrupt request to the Interrupt Con-
troller.
1 = Received data does not generate an interrupt request to the Interrupt Controller. Only
receiver errors generate an interrupt request.
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IREN—Infrared Encoder/Decoder Enable
0 = Infrared Encoder/Decoder is disabled. UART operates normally operation.
1 = Infrared Encoder/Decoder is enabled. The UART transmits and receives data through
the Infrared Encoder/Decoder.
UART Address Compare Register
The UART Address Compare register (Table 57) stores the multi-node network address of
the UART. When the MPMD[1] bit of UART Control Register 0 is set, all incoming
address bytes are compared to the value stored in the Address Compare register. Receive
interrupts and RDA assertions only occur in the event of a match.
Table 57. UART Address Compare Register (UxADDR)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
COMP_ADDR
0
R/W
F45H and F4DH
ADDR
COMP_ADDR—Compare Address
This 8-bit value is compared to the incoming address bytes.
UART Baud Rate High and Low Byte Registers
The UART Baud Rate High and Low Byte registers (Tables 58 and 59) combine to create
a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmission rate (baud
rate) of the UART. To configure the Baud Rate Generator as a timer with interrupt on
time-out, complete the following procedure:
1. Disable the UART by clearing the RENand TENbits in the UART Control 0 register
to 0.
2. Load the desired 16-bit count value into the UART Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BRGCTLbit in the UART Control 1 register to 1.
When congured as a general purpose timer, the UART BRG interrupt interval is calculated
using the following equation:
UART BRG Interrupt Interval (s) = System Clock Period (s) ×BRG[15:0]
]
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Product Specification
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Table 58. UART Baud Rate High Byte Register (UxBRH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
BRH
1
R/W
F46H and F4EH
ADDR
Table 59. UART Baud Rate Low Byte Register (UxBRL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
BRL
1
R/W
F47H and F4FH
ADDR
For a given UART data rate, the integer baud rate divisor value is calculated using the fol-
lowing equation:
System Clock Frequency (Hz)
16 × UART Data Rate (bits/s)
⎛
⎝
⎞
⎠
---------------------------------------------------------------------------
UART Baud Rate Divisor Value (BRG) = Round
The baud rate error relative to the desired baud rate is calculated using the following equa-
tion:
Actual Data Rate – Desired Data Rate
⎛
⎝
⎞
⎠
------------------------------------------------------------------------------------------------
UART Baud Rate Error (%) = 100 ×
Desired Data Rate
For reliable communication, the UART baud rate error must never exceed 5 percent.
Table 60 provides information on data rate errors for popular baud rates and commonly
used crystal oscillator frequencies.
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Z8 Encore!® 64K Series
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Table 60. UART Baud Rates
20.0 MHz System Clock
18.432 MHz System Clock
Desired Rate BRG Divisor Actual Rate
Desired Rate BRG Divisor
Actual Rate
Error
Error
(kHz)
1250.0
625.0
250.0
115.2
57.6
(Decimal)
1
(kHz)
1250.0
625.0
250.0
113.6
56.8
(%)
0.00
0.00
0.00
-1.36
-1.36
-1.36
0.16
0.16
0.16
-0.03
-0.03
0.02
-0.01
(kHz)
1250.0
625.0
250.0
115.2
57.6
(Decimal)
1
(kHz)
1152.0
576.0
230.4
115.2
57.6
(%)
-7.84%
-7.84%
-7.84%
0.00
2
2
5
5
11
10
22
20
0.00
38.4
33
37.9
38.4
30
38.4
0.00
19.2
65
19.2
19.2
60
19.2
0.00
9.60
130
260
521
1042
2083
4167
9.62
9.60
120
240
480
960
1920
3840
9.60
0.00
4.80
4.81
4.80
4.80
0.00
2.40
2.40
2.40
2.40
0.00
1.20
1.20
1.20
1.20
0.00
0.60
0.60
0.60
0.60
0.00
0.30
0.30
0.30
0.30
0.00
16.667 MHz System Clock
Desired Rate BRG Divisor
11.0592 MHz System Clock
Desired Rate BRG Divisor Actual Rate
Actual Rate
Error
Error
(kHz)
1250.0
625.0
250.0
115.2
57.6
(Decimal)
(kHz)
1041.69
520.8
260.4
115.7
57.87
38.6
(%)
-16.67
-16.67
4.17
(kHz)
1250.0
625.0
250.0
115.2
57.6
(Decimal)
(kHz)
N/A
(%)
N/A
10.59
-7.84
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
1
2
N/A
1
691.2
230.4
115.2
57.6
38.4
19.2
9.60
4.80
2.40
1.20
0.60
4
3
9
0.47
6
18
0.47
12
38.4
27
0.47
38.4
18
19.2
54
19.3
0.47
19.2
36
9.60
109
217
434
868
1736
9.56
-0.45
-0.83
0.01
9.60
72
4.80
4.80
4.80
144
288
576
1152
2.40
2.40
2.40
1.20
1.20
0.01
1.20
0.60
0.60
0.01
0.60
PS019913-0305
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UART
Z8 Encore!® 64K Series
Product Specification
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Table 60. UART Baud Rates (Continued)
0.30
3472
0.30
0.01
0.30
2304
0.30
0.00
10.0 MHz System Clock
5.5296 MHz System Clock
Desired Rate BRG Divisor Actual Rate
Desired Rate BRG Divisor
Actual Rate
Error
Error
(kHz)
1250.0
625.0
250.0
115.2
57.6
(Decimal)
N/A
1
(kHz)
N/A
(%)
N/A
0.00
-16.67
8.51
-1.36
1.73
0.16
0.16
0.16
-0.03
-0.03
-0.03
0.2
(kHz)
1250.0
625.0
250.0
115.2
57.6
(Decimal)
(kHz)
N/A
N/A
345.6
115.2
57.6
38.4
19.2
9.60
4.80
2.40
1.20
0.60
0.30
(%)
N/A
N/A
38.24
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
N/A
N/A
1
625.0
208.33
125.0
56.8
3
5
3
11
6
38.4
16
39.1
38.4
9
19.2
33
18.9
19.2
18
9.60
65
9.62
9.60
36
4.80
130
260
521
1042
2083
4.81
4.80
72
2.40
2.40
2.40
144
288
576
1152
1.20
1.20
1.20
0.60
0.60
0.60
0.30
0.30
0.30
3.579545 MHz System Clock
Desired Rate BRG Divisor
1.8432 MHz System Clock
Desired Rate BRG Divisor Actual Rate
Actual Rate
Error
Error
(kHz)
1250.0
625.0
250.0
115.2
57.6
(Decimal)
(kHz)
N/A
(%)
N/A
(kHz)
1250.0
625.0
250.0
115.2
57.6
(Decimal)
(kHz)
N/A
N/A
N/A
115.2
57.6
38.4
19.2
9.60
4.80
2.40
1.20
(%)
N/A
N/A
N/A
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
N/A
N/A
1
N/A
N/A
N/A
1
N/A
N/A
223.72
111.9
55.9
-10.51
-2.90
-2.90
-2.90
-2.90
1.32
2
4
2
38.4
6
37.3
38.4
3
19.2
12
23
47
93
186
18.6
19.2
6
9.60
9.73
9.60
12
24
48
96
4.80
4.76
-0.83
0.23
4.80
2.40
2.41
2.40
1.20
1.20
0.23
1.20
PS019913-0305
P r e l i m i n a r y
UART
Z8 Encore!® 64K Series
Product Specification
119
Table 60. UART Baud Rates (Continued)
0.60
0.30
373
746
0.60
0.30
-0.04
-0.04
0.60
0.30
192
384
0.60
0.30
0.00
0.00
PS019913-0305
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UART
Z8 Encore!® 64K Series
Product Specification
119
Infrared Encoder/Decoder
Overview
The 64K Series products contain two fully-functional, high-performance UART to Infra-
red Encoder/Decoders (Endecs). Each Infrared Endec is integrated with an on-chip UART
to allow easy communication between the 64K Series and IrDA Physical Layer Specifica-
tion, Version 1.3-compliant infrared transceivers. Infrared communication provides
secure, reliable, low-cost, point-to-point communication between PCs, PDAs, cell phones,
printers and other infrared enabled devices.
Architecture
Figure 19 illustrates the architecture of the Infrared Endec.
System
Clock
ZiLOG
ZHX1810
RxD
RXD
TXD
RXD
Infrared
TxD
Encoder/Decoder
(Endec)
TXD
Infrared
Transceiver
UART
Baud Rate
Clock
Interrupt
I/O
Data
Signal Address
Figure 19. Infrared Data Communication System Block Diagram
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Operation
When the Infrared Endec is enabled, the transmit data from the associated on-chip UART
is encoded as digital signals in accordance with the IrDA standard and output to the infra-
red transceiver via the TXD pin. Likewise, data received from the infrared transceiver is
passed to the Infrared Endec via the RXD pin, decoded by the Infrared Endec, and then
passed to the UART. Communication is half-duplex, which means simultaneous data
transmission and reception is not allowed.
The baud rate is set by the UART’s Baud Rate Generator and supports IrDA standard baud
rates from 9600 baud to 115.2 Kbaud. Higher baud rates are possible, but do not meet
IrDA specifications. The UART must be enabled to use the Infrared Endec. The Infrared
Endec data rate is calculated using the following equation:
System Clock Frequency (Hz)
16 × UART Baud Rate Divisor Value
----------------------------------------------------------------------------------------------
Infrared Data Rate (bits/s) =
Transmitting IrDA Data
The data to be transmitted using the infrared transceiver is first sent to the UART. The
UART’s transmit signal (TXD) and baud rate clock are used by the IrDA to generate the
modulation signal (IR_TXD) that drives the infrared transceiver. Each UART/Infrared
data bit is 16-clocks wide. If the data to be transmitted is 1, the IR_TXD signal remains
low for the full 16-clock period. If the data to be transmitted is 0, a 3-clock high pulse is
output following a 7-clock low period. After the 3-clock high pulse, a 6-clock low pulse is
output to complete the full 16-clock data period. Figure 20 illustrates IrDA data transmis-
sion. When the Infrared Endec is enabled, the UART’s TXD signal is internal to the 64K
Series products while the IR_TXD signal is output through the TXD pin.
PS019913-0305
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16-clock
period
Baud Rate
Clock
UART’s
TXD
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
3-clock
pulse
IR_TXD
7-clock
delay
Figure 20. Infrared Data Transmission
Receiving IrDA Data
Data received from the infrared transceiver via the IR_RXD signal through the RXDpin is
decoded by the Infrared Endec and passed to the UART. The UART’s baud rate clock is
used by the Infrared Endec to generate the demodulated signal (RXD) that drives the
UART. Each UART/Infrared data bit is 16-clocks wide. Figure 21 illustrates data recep-
tion. When the Infrared Endec is enabled, the UART’s RXD signal is internal to the 64K
Series products while the IR_RXD signal is received through the RXDpin.
PS019913-0305
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16-clock
period
Baud Rate
Clock
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
IR_RXD
min. 1.6µs
pulse
UART’s
RXD
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
8-clock
delay
16-clock
period
16-clock
period
16-clock
period
16-clock
period
Figure 21. Infrared Data Reception
Caution:
The system clock frequency must be at least 1.0MHz to ensure proper re-
ception of the 1.6µs minimum width pulses allowed by the IrDA standard.
Endec Receiver Synchronization
The IrDA receiver uses a local baud rate clock counter (0 to 15 clock periods) to generate
an input stream for the UART and to create a sampling window for detection of incoming
pulses. The generated UART input (UART RXD) is delayed by 8 baud rate clock periods
with respect to the incoming IrDA data stream. When a falling edge in the input data
stream is detected, the Endec counter is reset. When the count reaches a value of 8, the
UART RXD value is updated to reflect the value of the decoded data. When the count
reaches 12 baud clock periods, the sampling window for the next incoming pulse opens.
The window remains open until the count again reaches 8 (or in other words 24 baud clock
periods since the previous pulse was detected). This gives the Endec a sampling window
of minus four baudrate clocks to plus eight baudrate clocks around the expected time of an
incoming pulse. If an incoming pulse is detected inside this window this process is
repeated. If the incoming data is a logical 1 (no pulse), the Endec returns to the initial state
and waits for the next falling edge. As each falling edge is detected, the Endec clock
counter is reset, resynchronizing the Endec to the incoming signal. This action allows the
Endec to tolerate jitter and baud rate errors in the incoming data stream. Resynchronizing
the Endec does not alter the operation of the UART, which ultimately receives the data.
The UART is only synchronized to the incoming data stream when a Start bit is received.
PS019913-0305
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Infrared Encoder/Decoder Control Register Definitions
All Infrared Endec configuration and status information is set by the UART control regis-
ters as defined beginning on page 109.
Caution:
To prevent spurious signals during IrDA data transmission, set the IREN
bit in the UARTx Control 1 register to 1 to enable the Infrared Encoder/
Decoder before enabling the GPIO Port alternate function for the corre-
sponding pin.
PS019913-0305
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Serial Peripheral Interface
Overview
TM
The Serial Peripheral Interface (SPI) is a synchronous interface allowing several SPI-
type devices to be interconnected. SPI-compatible devices include EEPROMs, Analog-to-
Digital Converters, and ISDN devices. Features of the SPI include:
•
•
•
•
•
Full-duplex, synchronous, character-oriented communication
Four-wire interface
Data transfers rates up to a maximum of one-half the system clock frequency
Error detection
Dedicated Baud Rate Generator
Architecture
The SPI may be configured as either a Master (in single or multi-master systems) or a
Slave as illustrated in Figures 22 through 24.
SPI Master
To Slave’s SS Pin
From Slave
SS
8-bit Shift Register
Bit 0 Bit 7
MISO
MOSI
SCK
To Slave
To Slave
Baud Rate
Generator
Figure 22. SPI Configured as a Master in a Single Master, Single Slave System
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VCC
SPI Master
SS
To Slave #2’s SS Pin
To Slave #1’s SS Pin
From Slave
GPIO
GPIO
8-bit Shift Register
Bit 0
Bit 7
MISO
MOSI
To Slave
To Slave
SCK
Baud Rate
Generator
Figure 23. SPI Configured as a Master in a Single Master, Multiple Slave System
SPI Slave
From Master
SS
8-bit Shift Register
Bit 7 Bit 0
MISO
MOSI
To Master
From Master
SCK
From Master
Figure 24. SPI Configured as a Slave
Operation
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire
interface (serial clock, transmit, receive and Slave select). The SPI block consists of a
transmit/receive shift register, a Baud Rate (clock) Generator and a control unit.
PS019913-0305
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During an SPI transfer, data is sent and received simultaneously by both the Master and
the Slave SPI devices. Separate signals are required for data and the serial clock. When an
SPI transfer occurs, a multi-bit (typically 8-bit) character is shifted out one data pin and an
multi-bit character is simultaneously shifted in on a second data pin. An 8-bit shift register
in the Master and another 8-bit shift register in the Slave are connected as a circular buffer.
The SPI shift register is single-buffered in the transmit and receive directions. New data to
be transmitted cannot be written into the shift register until the previous transmission is
complete and receive data (if valid) has been read.
SPI Signals
The four basic SPI signals are:
•
•
•
•
MISO (Master-In, Slave-Out)
MOSI (Master-Out, Slave-In)
SCK (SPI Serial Clock)
SS (Slave Select)
The following paragraphs discuss these SPI signals. Each signal is described in both Mas-
ter and Slave modes.
Master-In, Slave-Out
The Master-In, Slave-Out (MISO) pin is configured as an input in a Master device and as
an output in a Slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. The MISO pin of a Slave device is placed in a high-impedance
state if the Slave is not selected. When the SPI is not enabled, this signal is in a high-
impedance state.
Master-Out, Slave-In
The Master-Out, Slave-In (MOSI) pin is configured as an output in a Master device and as
an input in a Slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. When the SPI is not enabled, this signal is in a high-impedance
state.
Serial Clock
The Serial Clock (SCK) synchronizes data movement both in and out of the device
through its MOSI and MISO pins. In MASTER mode, the SPI’s Baud Rate Generator cre-
ates the serial clock. The Master drives the serial clock out its own SCK pin to the Slave’s
SCK pin. When the SPI is configured as a Slave, the SCK pin is an input and the clock sig-
nal from the Master synchronizes the data transfer between the Master and Slave devices.
Slave devices ignore the SCK signal, unless the SS pin is asserted. When configured as a
slave, the SPI block requires a minimum SCK period of greater than or equal to 8 times
the system (XIN) clock period.
PS019913-0305
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The Master and Slave are each capable of exchanging a character of data during a
sequence of NUMBITS clock cycles (refer to NUMBITS field in the SPIMODE register).
In both Master and Slave SPI devices, data is shifted on one edge of the SCK and is sam-
pled on the opposite edge where data is stable. Edge polarity is determined by the SPI
phase and polarity control.
Slave Select
The active Low Slave Select (SS) input signal selects a Slave SPI device. SS must be Low
prior to all data communication to and from the Slave device. SS must stay Low for the
full duration of each character transferred. The SS signal may stay Low during the transfer
of multiple characters or may deassert between each character.
When the SPI is configured as the only Master in an SPI system, the SS pin can be set as
either an input or an output. For communication between the Z8F642x familyZ8R642x
family device’s SPI Master and external Slave devices, the SS signal, as an output, can
assert the SS input pin on one of the Slave devices. Other GPIO output pins can also be
employed to select external SPI Slave devices.
When the SPI is configured as one Master in a multi-master SPI system, the SS pin must
be set as an input. The SS input signal on the Master must be High. If the SS signal goes
Low (indicating another Master is driving the SPI bus), a Collision error flag is set in the
SPI Status register.
SPI Clock Phase and Polarity Control
The SPI supports four combinations of serial clock phase and polarity using two bits in the
SPI Control register. The clock polarity bit, CLKPOL, selects an active high or active low
clock and has no effect on the transfer format. Table 61 lists the SPI Clock Phase and
Polarity Operation parameters. The clock phase bit, PHASE, selects one of two fundamen-
tally different transfer formats. For proper data transmission, the clock phase and polarity
must be identical for the SPI Master and the SPI Slave. The Master always places data on
the MOSI line a half-cycle before the receive clock edge (SCK signal), in order for the
Slave to latch the data.
Table 61. SPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation
SCK Transmit
Edge
SCK Receive
Edge
SCK Idle
State
PHASE
CLKPOL
0
0
1
1
0
1
0
1
Falling
Rising
Rising
Falling
Rising
Falling
Falling
Rising
Low
High
Low
High
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Transfer Format PHASE Equals Zero
Figure 25 illustrates the timing diagram for an SPI transfer in which PHASEis cleared to
0. The two SCK waveforms show polarity with CLKPOLreset to 0 and with CLKPOLset
to one. The diagram may be interpreted as either a Master or Slave timing diagram
because the SCK Master-In/Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are
directly connected between the Master and the Slave.
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit7
Bit7
Bit6
Bit6
Bit5
Bit5
Bit4
Bit4
Bit3
Bit3
Bit2
Bit2
Bit1
Bit1
Bit0
Bit0
MISO
Input Sample Time
SS
Figure 25. SPI Timing When PHASE is 0
Transfer Format PHASE Equals One
Figure 26 illustrates the timing diagram for an SPI transfer in which PHASEis one. Two
waveforms are depicted for SCK, one for CLKPOLreset to 0 and another for CLKPOLset
to 1.
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SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
MOSI
Bit7
Bit7
Bit6
Bit6
Bit5
Bit5
Bit4
Bit4
Bit3
Bit3
Bit2
Bit2
Bit1
Bit1
Bit0
Bit0
MISO
Input Sample Time
SS
Figure 26. SPI Timing When PHASE is 1
Multi-Master Operation
In a multi-master SPI system, all SCK pins are tied together, all MOSI pins are tied
together and all MISO pins are tied together. All SPI pins must then be configured in
open-drain mode to prevent bus contention. At any one time, only one SPI device is con-
figured as the Master and all other SPI devices on the bus are configured as Slaves. The
Master enables a single Slave by asserting the SS pin on that Slave only. Then, the single
Master drives data out its SCK and MOSI pins to the SCK and MOSI pins on the Slaves
(including those which are not enabled). The enabled Slave drives data out its MISO pin to
the MISO Master pin.
For a Master device operating in a multi-master system, if the SS pin is configured as an
input and is driven Low by another Master, the COLbit is set to 1 in the SPI Status Regis-
ter. The COLbit indicates the occurrence of a multi-master collision (mode fault error con-
dition).
Slave Operation
The SPI block is configured for slave mode operation by setting the SPIEN bit to 1 and the
MMEN bit to 0 in the SPICTL register and setting the SSIO bit to 0 in the SPIMODE reg-
PS019913-0305
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130
ister. The IRQE, PHASE, CLKPOL, WOR bits in the SPICTL register and the NUMBITS
field in the SPIMODE register must be set to be consistent with the other SPI devices. The
STR bit in the SPICTL register may be used if desired to force a “startup” interrupt. The
BIRQ bit in the SPICTL register and the SSV bit in the SPIMODE register are not used in
slave mode. The SPI baud rate generator is not used in slave mode so the SPIBRH and
SPIBRL registers need not be initialized.
If the slave has data to send to the master, the data must be written to the SPIDAT register
before the transaction starts (first edge of SCK when SS is asserted). If the SPIDAT regis-
ter is not written prior to the slave transaction, the MISO pin outputs whatever value is
currently in the SPIDAT register.
Due to the delay resulting from synchronization of the SPI input signals to the internal sys-
tem clock, the maximum SPICLK baud rate that can be supported in slave mode is the sys-
tem clock frequency (XIN) divided by 8. This rate is controlled by the SPI master.
Error Detection
The SPI contains error detection logic to support SPI communication protocols and recog-
nize when communication errors have occurred. The SPI Status register indicates when a
data transmission error has been detected.
Overrun (Write Collision)
An overrun error (write collision) indicates a write to the SPI Data register was attempted
while a data transfer is in progress (in either master or slave modes). An overrun sets the
OVRbit in the SPI Status register to 1. Writing a 1 to OVRclears this error flag. The data
register is not altered when a write occurs while data transfer is in progress.
Mode Fault (Multi-Master Collision)
A mode fault indicates when more than one Master is trying to communicate at the same
time (a multi-master collision). The mode fault is detected when the enabled Master’s SS
pin is asserted. A mode fault sets the COLbit in the SPI Status register to 1. Writing a 1 to
COLclears this error flag.
Slave Mode Abort
In slave mode of operation if the SS pin deasserts before all bits in a character have been
transferred, the transaction is aborted. When this condition occurs the ABT bit is set in the
SPISTAT register as well as the IRQ bit (indicating the transaction is complete). The next
time SS asserts, the MISO pin outputs SPIDAT[7], regardless of where the previous trans-
action left off. Writing a 1 to ABT clears this error flag.
SPI Interrupts
When SPI interrupts are enabled, the SPI generates an interrupt after character transmis-
sion/reception completes in both master and slave modes. A character can be defined to be
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1 through 8 bits by the NUMBITSfield in the SPI Mode register. In slave mode it is not
necessary for SS to deassert between characters to generate the interrupt. The SPI in Slave
mode can also generate an interrupt if the SS signal deasserts prior to transfer of all the bits
in a character (see description of slave abort error above). Writing a 1 to the IRQbit in the
SPI Status Register clears the pending SPI interrupt request. The IRQ bit must be cleared
to 0 by the Interrupt Service Routine to generate future interrupts. To start the transfer pro-
cess, an SPI interrupt may be forced by software writing a 1 to the STR bit in the SPICTL
register.
If the SPI is disabled, an SPI interrupt can be generated by a Baud Rate Generator time-
out. This timer function must be enabled by setting the BIRQ bit in the SPICTL register.
This Baud Rate Generator time-out does not set the IRQ bit in the SPISTAT register, just
the SPI interrupt bit in the interrupt controller.
SPI Baud Rate Generator
In SPI Master mode, the Baud Rate Generator creates a lower frequency serial clock
(SCK) for data transmission synchronization between the Master and the external Slave.
The input to the Baud Rate Generator is the system clock. The SPI Baud Rate High and
Low Byte registers combine to form a 16-bit reload value, BRG[15:0], for the SPI Baud
Rate Generator. The SPI baud rate is calculated using the following equation:
System Clock Frequency (Hz)
---------------------------------------------------------------------------
SPI Baud Rate (bits/s) =
2 × BRG[15:0]
Minimum baud rate is obtained by setting BRG[15:0] to 0000Hfor a clock divisor value
of (2 X 65536 = 131072).
When the SPI is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt
on time-out, complete the following procedure:
1. Disable the SPI by clearing the SPIENbit in the SPI Control register to 0.
2. Load the desired 16-bit count value into the SPI Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BIRQbit in the SPI Control register to 1.
When configured as a general purpose timer, the interrupt interval is calculated using the
following equation:
Interrupt Interval (s) = System Clock Period (s) ×BRG[15:0]
]
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SPI Control Register Definitions
SPI Data Register
The SPI Data register (Table 62) stores both the outgoing (transmit) data and the incoming
(receive) data. Reads from the SPI Data register always return the current contents of the
8-bit shift register. Data is shifted out starting with bit 7. The last bit received resides in bit
position 0.
With the SPI configured as a Master, writing a data byte to this register initiates the data
transmission. With the SPI configured as a Slave, writing a data byte to this register loads
the shift register in preparation for the next data transfer with the external Master. In either
the Master or Slave modes, if a transmission is already in progress, writes to this register
are ignored and the Overrun error flag, OVR, is set in the SPI Status register.
When the character length is less than 8 bits (as set by the NUMBITSfield in the SPI Mode
register), the transmit character must be left justified in the SPI Data register. A received
character of less than 8 bits is right justified (last bit received is in bit position 0). For
example, if the SPI is configured for 4-bit characters, the transmit characters must be writ-
ten to SPIDATA[7:4] and the received characters are read from SPIDATA[3:0].
Table 62. SPI Data Register (SPIDATA)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DATA
X
R/W
F60H
ADDR
DATA—Data
Transmit and/or receive data.
SPI Control Register
The SPI Control register (Table 63) configures the SPI for transmit and receive operations.
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Table 63. SPI Control Register (SPICTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
IRQE
STR
BIRQ
PHASE
CLKPOL
WOR
MMEN
SPIEN
0
R/W
F61H
ADDR
IRQE—Interrupt Request Enable
0 = SPI interrupts are disabled. No interrupt requests are sent to the Interrupt Controller.
1 = SPI interrupts are enabled. Interrupt requests are sent to the Interrupt Controller.
STR—Start an SPI Interrupt Request
0 = No effect.
1 = Setting this bit to 1 also sets the IRQbit in the SPI Status register to 1. Setting this bit
forces the SPI to send an interrupt request to the Interrupt Control. This bit can be used by
software for a function similar to transmit buffer empty in a UART. Writing a 1 to the
IRQbit in the SPI Status register clears this bit to 0.
BIRQ—BRG Timer Interrupt Request
If the SPI is enabled, this bit has no effect. If the SPI is disabled:
0 = The Baud Rate Generator timer function is disabled.
1 = The Baud Rate Generator timer function and time-out interrupt are enabled.
PHASE—Phase Select
Sets the phase relationship of the data to the clock. Refer to the SPI Clock Phase and
Polarity Control section for more information on operation of the PHASEbit.
CLKPOL—Clock Polarity
0 = SCK idles Low (0).
1 = SCK idle High (1).
WOR—Wire-OR (Open-Drain) Mode Enabled
0 = SPI signal pins not configured for open-drain.
1 = All four SPI signal pins (SCK, SS, MISO, MOSI) configured for open-drain function.
This setting is typically used for multi-master and/or multi-slave configurations.
MMEN—SPI Master Mode Enable
0 = SPI configured in Slave mode.
1 = SPI configured in Master mode.
SPIEN—SPI Enable
0 = SPI disabled.
1 = SPI enabled.
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SPI Status Register
The SPI Status register (Table 64) indicates the current state of the SPI. All bits revert to
their reset state if the SPIEN bit in the SPICTL register = 0.
Table 64. SPI Status Register (SPISTAT)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
IRQ
OVR
COL
ABT
Reserved
TXST
SLAS
0
1
R/W*
R
F62H
ADDR
R/W* = Read access. Write a 1 to clear the bit to 0.
IRQ—Interrupt Request
If SPIEN = 1, this bit is set if the STR bit in the SPICTL register is set, or upon completion
of an SPI master or slave transaction. This bit does not set if SPIEN = 0 and the SPI Baud
Rate Generator is used as a timer to generate the SPI interrupt.
0 = No SPI interrupt request pending.
1 = SPI interrupt request is pending.
OVR—Overrun
0 = An overrun error has not occurred.
1 = An overrun error has been detected.
COL—Collision
0 = A multi-master collision (mode fault) has not occurred.
1 = A multi-master collision (mode fault) has been detected.
ABT—Slave mode transaction abort
This bit is set if the SPI is configured in slave mode, a transaction is occurring and SS
deasserts before all bits of a character have been transferred as defined by the NUMBITS
field of the SPIMODE register. The IRQ bit also sets, indicating the transaction has com-
pleted.
0 = A slave mode transaction abort has not occurred.
1 = A slave mode transaction abort has been detected.
Reserved—Must be 0.
TXST—Transmit Status
0 = No data transmission currently in progress.
1 = Data transmission currently in progress.
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SLAS—Slave Select
If SPI enabled as a Slave,
0 = SS input pin is asserted (Low)
1 = SS input is not asserted (High).
If SPI enabled as a Master, this bit is not applicable.
SPI Mode Register
The SPI Mode register (Table 65) configures the character bit width and the direction and
value of the SS pin.
Table 65. SPI Mode Register (SPIMODE)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
Reserved
R
DIAG
NUMBITS[2:0]
SSIO
SSV
0
R/W
F63H
ADDR
Reserved—Must be 0.
DIAG - Diagnostic Mode Control bit
This bit is for SPI diagnostics. Setting this bit allows the Baud Rate Generator value to be
read using the SPIBRH and SPIBRL register locations.
0 = Reading SPIBRH, SPIBRL returns the value in the SPIBRH and SPIBRL registers
1 = Reading SPIBRH returns bits [15:8] of the SPI Baud Rate Generator; and reading SPI-
BRL returns bits [7:0] of the SPI Baud Rate Counter. The Baud Rate Counter High and
Low byte values are not buffered.
Exercise caution if reading the values while the BRG is counting.
Caution:
NUMBITS[2:0]—Number of Data Bits Per Character to Transfer
This field contains the number of bits to shift for each character transfer. Refer to the SPI
Data Register description for information on valid bit positions when the character length
is less than 8-bits.
000 = 8 bits
001 = 1 bit
010 = 2 bits
011 = 3 bits
100 = 4 bits
101 = 5 bits
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110 = 6 bits
111 = 7 bits.
SSIO—Slave Select I/O
0 = SS pin configured as an input.
1 = SS pin configured as an output (Master mode only).
SSV—Slave Select Value
If SSIO = 1 and SPI configured as a Master:
0 = SS pin driven Low (0).
1 = SS pin driven High (1).
This bit has no effect if SSIO= 0 or SPI configured as a Slave.
SPI Diagnostic State Register
The SPI Diagnostic State register (Table 66) provides observability of internal state. This
is a read only register used for SPI diagnostics.
Table 66. SPI Diagnostic State Register (SPIDST)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
SCKEN
TCKEN
SPISTATE
0
R
F64H
ADDR
SCKEN - Shift Clock Enable
0 = The internal Shift Clock Enable signal is deasserted
1 = The internal Shift Clock Enable signal is asserted (shift register is updates on next sys-
tem clock)
TCKEN - Transmit Clock Enable
0 = The internal Transmit Clock Enable signal is deasserted.
1 = The internal Transmit Clock Enable signal is asserted. When this is asserted the serial
data out is updated on the next system clock (MOSI or MISO).
SPISTATE - SPI State Machine
Defines the current state of the internal SPI State Machine.
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SPI Baud Rate High and Low Byte Registers
The SPI Baud Rate High and Low Byte registers (Tables 67 and 68) combine to form a 16-
bit reload value, BRG[15:0], for the SPI Baud Rate Generator.
When congured as a general purpose timer, the SPI BRG interrupt interval is calculated
using the following equation:
SPI BRG Interrupt Interval (s) = System Clock Period (s) ×BRG[15:0] ].
Table 67. SPI Baud Rate High Byte Register (SPIBRH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
BRH
1
R/W
F66H
ADDR
BRH = SPI Baud Rate High Byte
Most significant byte, BRG[15:8], of the SPI Baud Rate Generator’s reload value.
Table 68. SPI Baud Rate Low Byte Register (SPIBRL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
BRL
1
R/W
F67H
ADDR
BRL = SPI Baud Rate Low Byte
Least significant byte, BRG[7:0], of the SPI Baud Rate Generator’s reload value.
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I2C Controller
Overview
2
2
TM
The I C Controller makes the 64K Series products bus-compatible with the I C proto-
col. The I2C Controller consists of two bidirectional bus lines—a serial data signal (SDA)
and a serial clock signal (SCL). Features of the I2C Controller include:
•
•
•
•
Transmit and Receive Operation in MASTER mode
Maximum data rate of 400kbit/sec
7- and 10-bit addressing modes for Slaves
Unrestricted number of data bytes transmitted per transfer
The I2C Controller in the 64K Series products does not operate in Slave mode.
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Architecture
Figure 27 illustrates the architecture of the I2C Controller.
SDA
SCL
Shift
ISHIFT
Load
2
I CDATA
Baud Rate Generator
2
Receive
I CBRH
2
I CBRL
Tx/Rx State Machine
2
2
I CSTAT
I CCTL
Register Bus
2
I C Interrupt
2
Figure 27. I C Controller Block Diagram
Operation
The I2C Controller operates in MASTER mode to transmit and receive data. Only a single
master is supported. Arbitration between two masters must be accomplished in software.
I2C supports the following operations:
•
•
Master transmits to a 7-bit slave
Master transmits to a 10-bit slave
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•
•
Master receives from a 7-bit slave
Master receives from a 10-bit slave
SDA and SCL Signals
I2C sends all addresses, data and acknowledge signals over the SDA line, most-significant
bit first. SCL is the common clock for the I2C Controller. When the SDA and SCL pin
alternate functions are selected for their respective GPIO ports, the pins are automatically
configured for open-drain operation.
The master (I2C) is responsible for driving the SCL clock signal, although the clock signal
can become skewed by a slow slave device. During the low period of the clock, the slave
pulls the SCL signal Low to suspend the transaction. The master releases the clock at the
end of the low period and notices that the clock remains low instead of returning to a high
level. When the slave releases the clock, the I2C Controller continues the transaction. All
data is transferred in bytes and there is no limit to the amount of data transferred in one
operation. When transmitting data or acknowledging read data from the slave, the SDA
signal changes in the middle of the low period of SCL and is sampled in the middle of the
high period of SCL.
I2C Interrupts
The I2C Controller contains four sources of interrupts—Transmit, Receive, Not Acknowl-
edge and baud rate generator. These four interrupt sources are combined into a single
interrupt request signal to the Interrupt Controller. The Transmit interrupt is enabled by the
IEN and TXI bits of the Control register. The Receive and Not Acknowledge interrupts are
enabled by the IEN bit of the Control register. The baud rate generator interrupt is enabled
by the BIRQ and IEN bits of the Control register.
Not Acknowledge interrupts occur when a Not Acknowledge condition is received from
the slave or sent by the I2C Controller and neither the STARTor STOPbit is set. The Not
Acknowledge event sets the NCKI bit of the I2C Status register and can only be cleared by
setting the STARTor STOPbit in the I2C Control register. When this interrupt occurs, the
I2C Controller waits until either the STOP or START bit is set before performing any
action. In an interrupt service routine, the NCKI bit should always be checked prior to ser-
vicing transmit or receive interrupt conditions because it indicates the transaction is being
terminated.
Receive interrupts occur when a byte of data has been received by the I2C Controller
(master reading data from slave). This procedure sets the RDRF bit of the I2C Status regis-
ter. The RDRF bit is cleared by reading the I2C Data register. The RDRF bit is set during
the acknowledge phase. The I2C Controller pauses after the acknowledge phase until the
receive interrupt is cleared before performing any other action.
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Transmit interrupts occur when the TDRE bit of the I2C Status register sets and the TXI
bit in the I2C Control register is set. Transmit interrupts occur under the following condi-
tions when the transmit data register is empty:
•
•
The I2C Controller is enabled
The first bit of the byte of an address is shifting out and the RDbit of the I2C Status
register is deasserted.
•
•
The first bit of a 10-bit address shifts out.
The first bit of write data shifts out.
Note: Writing to the I2C Data register always clears the TRDE bit to 0. When TDRE is asserted,
the I2C Controller pauses at the beginning of the Acknowledge cycle of the byte currently
shifting out until the Data register is written with the next value to send or the STOP or
START bits are set indicating the current byte is the last one to send.
The fourth interrupt source is the baud rate generator. If the I2C Controller is disabled
(IEN bit in the I2CCTL register = 0) and the BIRQ bit in the I2CCTL register = 1, an inter-
rupt is generated when the baud rate generator counts down to 1. This allows the I2C baud
rate generator to be used by software as a general purpose timer when IEN = 0.
2
Software Control of I C Transactions
Software can control I2C transactions by using the I2C Controller interrupt, by polling the
I2C Status register or by DMA. Note that not all products include a DMA Controller.
To use interrupts, the I2C interrupt must be enabled in the Interrupt Controller. The TXI bit
in the I2C Control register must be set to enable transmit interrupts.
To control transactions by polling, the interrupt bits (TDRE, RDRF and NCKI) in the I2C
Status register should be polled. The TDRE bit asserts regardless of the state of the TXI
bit.
Either or both transmit and receive data movement can be controlled by the DMA Control-
ler. The DMA Controller channel(s) must be initialized to select the I2C transmit and
receive requests. Transmit DMA requests require that the TXI bit in the I2C Control regis-
ter be set.
Caution:
A transmit (write) DMA operation hangs if the slave responds with a Not
Acknowledge before the last byte has been sent. After receiving the Not
Acknowledge, the I2C Controller sets the NCKI bit in the Status register
and pauses until either the STOP or START bits in the Control register are
set.
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In order for a receive (read) DMA transaction to send a Not Acknowledge
on the last byte, the receive DMA must be set up to receive n-1 bytes, then
software must set the NAK bit and receive the last (nth) byte directly.
Start and Stop Conditions
The master (I2C) drives all Start and Stop signals and initiates all transactions. To start a
transaction, the I2C Controller generates a START condition by pulling the SDA signal
Low while SCL is High. To complete a transaction, the I2C Controller generates a Stop
condition by creating a low-to-high transition of the SDA signal while the SCL signal is
high. The START and STOP bits in the I2C Control register control the sending of the
Start and Stop conditions. A master is also allowed to end one transaction and begin a new
one by issuing a Restart. This is accomplished by setting the START bit at the end of a
transaction, rather than the STOP bit. Note that the Start condition not sent until the
START bit is set and data has been written to the I2C Data register.
Master Write and Read Transactions
The following sections provide a recommended procedure for performing I2C write and
read transactions from the I2C Controller (master) to slave I2C devices. In general soft-
ware should rely on the TDRE, RDRF and NCKI bits of the status register (these bits gen-
erate interrupts) to initiate software actions. When using interrupts or DMA, the TXI bit is
set to start each transaction and cleared at the end of each transaction to eliminate a “trail-
ing” Transmit interrupt.
Caution should be used in using the ACK status bit within a transaction because it is diffi-
cult for software to tell when it is updated by hardware.
When writing data to a slave, the I2C pauses at the beginning of the Acknowledge cycle if
the data register has not been written with the next value to be sent (TDRE bit in the I2C
Status register = 1). In this scenario where software is not keeping up with the I2C bus
(TDRE asserted longer than one byte time), the Acknowledge clock cycle for byte n is
delayed until the Data register is written with byte n + 1, and appears to be grouped with
the data clock cycles for byte n+1. If either the START or STOP bit is set, the I2C does not
pause prior to the Acknowledge cycle because no additional data is sent.
When a Not Acknowledge condition is received during a write (either during the address
or data phases), the I2C Controller generates the Not Acknowledge interrupt (NCKI = 1)
and pause until either the STOP or START bit is set. Unless the Not Acknowledge was
received on the last byte, the Data register will already have been written with the next
address or data byte to send. In this case the FLUSH bit of the Control register should be
set at the same time the STOP or START bit is set to remove the stale transmit data and
enable subsequent Transmit interrupts.
When reading data from the slave, the I2C pauses after the data Acknowledge cycle until
the receive interrupt is serviced and the RDRF bit of the status register is cleared by read-
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ing the I2C Data register. Once the I2C data register has been read, the I2C reads the next
data byte.
Address Only Transaction with a 7-bit Address
In the situation where software determines if a slave with a 7-bit address is responding
without sending or receiving data, a transaction can be done which only consists of an
address phase. Figure 28 illustrates this “address only” transaction to determine if a slave
with a 7-bit address will acknowledge. As an example, this transaction can be used after a
“write” has been done to a EEPROM to determine when the EEPROM completes its inter-
nal write operation and is once again responding to I2C transactions. If the slave does not
Acknowledge, the transaction can be repeated until the slave does Acknowledge.
S
Slave Address W = 0 A/A
P
Figure 28. 7-Bit Address Only Transaction Format
The procedure for an address only transaction to a 7-bit addressed slave is as follows:
1. Software asserts the IENbit in the I2C Control register.
2. Software asserts the TXIbit of the I2C Control register to enable Transmit interrupts.
3. The I2C interrupt asserts, because the I2C Data register is empty (TDRE = 1)
4. Software responds to the TDREbit by writing a 7-bit slave address plus write bit (=0)
to the I2C Data register. As an alternative this could be a read operation instead of a
write operation.
5. Software sets the START and STOP bits of the I2C Control register and clears the TXI
bit.
6. The I2C Controller sends the START condition to the I2C slave.
7. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register.
8. Software polls the STOP bit of the I2C Control register. Hardware deasserts the STOP
bit when the address only transaction is completed.
9. Software checks the ACK bit of the I2C Status register. If the slave acknowledged,
the ACK bit is = 1. If the slave does not acknowledge, the ACK bit is = 0. The NCKI
interrupt does not occur in the not acknowledge case because the STOP bit was set.
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Write Transaction with a 7-Bit Address
Figure 29 illustrates the data transfer format for a 7-bit addressed slave. Shaded regions
indicate data transferred from the I2C Controller to slaves and unshaded regions indicate
data transferred from the slaves to the I2C Controller.
S
Slave Address W = 0
A
Data
A
Data
A
Data
A/A P/S
Figure 29. 7-Bit Addressed Slave Data Transfer Format
The procedure for a transmit operation to a 7-bit addressed slave is as follows:
1. Software asserts the IENbit in the I2C Control register.
2. Software asserts the TXIbit of the I2C Control register to enable Transmit interrupts.
3. The I2C interrupt asserts, because the I2C Data register is empty
4. Software responds to the TDREbit by writing a 7-bit slave address plus write bit (=0)
to the I2C Data register.
5. Software asserts the START bit of the I2C Control register.
6. The I2C Controller sends the START condition to the I2C slave.
7. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register.
8. After one bit of address has been shifted out by the SDA signal, the Transmit interrupt
is asserted (TDRE = 1).
9. Software responds by writing the transmit data into the I2C Data register.
10. The I2C Controller shifts the rest of the address and write bit out by the SDA signal.
11. If the I2C slave sends an acknowledge (by pulling the SDA signal low) during the next
high period of SCL the I2C Controller sets the ACKbit in the I2C Status register.
Continue with step 12.
If the slave does not acknowledge, the Not Acknowledge interrupt occurs (NCKI bit is
set in the Status register, ACK bit is cleared). Software responds to the Not
Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit.
The I2C Controller sends the STOP condition on the bus and clears the STOP and
NCKI bits. The transaction is complete (ignore following steps).
12. The I2C Controller loads the contents of the I2C Shift register with the contents of the
I2C Data register.
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13. The I2C Controller shifts the data out of using the SDA signal. After the first bit is
sent, the Transmit interrupt is asserted.
14. If more bytes remain to be sent, return to step 9.
15. Software responds by setting the STOPbit of the I2C Control register (or START bit
to initiate a new transaction). In the STOP case, software clears the TXIbit of the I2C
Control register at the same time.
16. The I2C Controller completes transmission of the data on the SDA signal.
17. The slave may either Acknowledge or Not Acknowledge the last byte. Because either
the STOP or START bit is already set, the NCKI interrupt does not occur.
18. The I2C Controller sends the STOP (or RESTART) condition to the I2C bus. The
STOP or START bit is cleared.
Address Only Transaction with a 10-bit Address
In the situation where software wants to determine if a slave with a 10-bit address is
responding without sending or receiving data, a transaction can be done which only con-
sists of an address phase. Figure 30 illustrates this “address only” transaction to determine
if a slave with 10-bit address will acknowledge. As an example, this transaction can be
used after a “write” has been done to a EEPROM to determine when the EEPROM com-
pletes its internal write operation and is once again responding to I2C transactions. If the
slave does not Acknowledge the transaction can be repeated until the slave is able to
Acknowledge.
Slave Address
1st 7 bits
Slave Address
2nd Byte
S
W = 0 A/A
A/A P
Figure 30. 10-Bit Address Only Transaction Format
The procedure for an address only transaction to a 10-bit addressed slave is as follows:
1. Software asserts the IENbit in the I2C Control register.
2. Software asserts the TXIbit of the I2C Control register to enable Transmit interrupts.
3. The I2C interrupt asserts, because the I2C Data register is empty (TDRE = 1)
4. Software responds to the TDREinterrupt by writing the first slave address byte. The
least-significant bit must be 0 for the write operation.
5. Software asserts the START bit of the I2C Control register.
6. The I2C Controller sends the START condition to the I2C slave.
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7. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register.
8. After one bit of address is shifted out by the SDA signal, the Transmit interrupt is
asserted.
9. Software responds by writing the second byte of address into the contents of the I2C
Data register.
10. The I2C Controller shifts the rest of the first byte of address and write bit out the SDA
signal.
11. If the I2C slave sends an acknowledge by pulling the SDA signal low during the next
high period of SCL the I2C Controller sets the ACKbit in the I2C Status register.
Continue with step 12.
If the slave does not acknowledge the first address byte, the I2C Controller sets the
NCKIbit and clears the ACK bit in the I2C Status register. Software respons to the
Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI
bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and
NCKI bits. The transaction is complete (ignore following steps).
12. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register (2nd byte of address).
13. The I2C Controller shifts the second address byte out the SDA signal. After the first
bit has been sent, the Transmit interrupt is asserted.
14. Software responds by setting the STOP bit in the I2C Control register. The TXI bit can
be cleared at the same time.
15. Software polls the STOP bit of the I2C Control register. Hardware deasserts the STOP
bit when the transaction is completed (STOP condition has been sent).
16. Software checks the ACK bit of the I2C Status register. If the slave acknowledged, the
ACK bit is = 1. If the slave does not acknowledge, the ACK bit is = 0. The NCKI
interrupt do not occur because the STOP bit was set.
Write Transaction with a 10-Bit Address
Figure 31 illustrates the data transfer format for a 10-bit addressed slave. Shaded regions
indicate data transferred from the I2C Controller to slaves and unshaded regions indicate
data transferred from the slaves to the I2C Controller.
Slave Address
1st 7 bits
Slave Address
2nd Byte
S
W = 0 A
A Data A Data A/A P/S
Figure 31. 10-Bit Addressed Slave Data Transfer Format
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The first seven bits transmitted in the first byte are 11110XX. The two bits XXare the two
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
read/write control bit (=0). The transmit operation is carried out in the same manner as 7-
bit addressing.
The procedure for a transmit operation on a 10-bit addressed slave is as follows:
1. Software asserts the IENbit in the I2C Control register.
2. Software asserts the TXIbit of the I2C Control register to enable Transmit interrupts.
3. The I2C interrupt asserts because the I2C Data register is empty.
4. Software responds to the TDREinterrupt by writing the first slave address byte to the
I2C Data register. The least-significant bit must be 0 for the write operation.
5. Software asserts the START bit of the I2C Control register.
6. The I2C Controller sends the START condition to the I2C slave.
7. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register.
8. After one bit of address is shifted out by the SDA signal, the Transmit interrupt is
asserted.
9. Software responds by writing the second byte of address into the contents of the I2C
Data register.
10. The I2C Controller shifts the rest of the first byte of address and write bit out the SDA
signal.
11. If the I2C slave acknowledges the first address byte by pulling the SDA signal low
during the next high period of SCL, the I2C Controller sets the ACKbit in the I2C
Status register. Continue with step 12.
If the slave does not acknowledge the first address byte, the I2C Controller sets the
NCKIbit and clears the ACK bit in the I2C Status register. Software responds to the
Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI
bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and
NCKI bits. The transaction is complete (ignore the following steps).
12. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register.
13. The I2C Controller shifts the second address byte out the SDA signal. After the first
bit has been sent, the Transmit interrupt is asserted.
14. Software responds by writing a data byte to the I2C Data register.
15. The I2C Controller completes shifting the contents of the shift register on the SDA
signal.
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16. If the I2C slave sends an acknowledge by pulling the SDA signal low during the next
high period of SCL, the I2C Controller sets the ACKbit in the I2C Status register.
Continue with step 17.
If the slave does not acknowledge the second address byte or one of the data bytes, the
I2C Controller sets the NCKIbit and clears the ACK bit in the I2C Status register.
Software responds to the Not Acknowledge interrupt by setting the STOP and FLUSH
bits and clearing the TXI bit. The I2C Controller sends the STOP condition on the bus
and clears the STOP and NCKI bits. The transaction is complete (ignore the following
steps).
17. The I2C Controller shifts the data out by the SDA signal. After the first bit is sent, the
Transmit interrupt is asserted.
18. If more bytes remain to be sent, return to step 14.
19. If the last byte is currently being sent, software sets the STOPbit of the I2C Control
register (or START bit to initiate a new transaction). In the STOP case, software also
clears the TXIbit of the I2C Control register at the same time.
20. The I2C Controller completes transmission of the last data byte on the SDA signal.
21. The slave may either Acknowledge or Not Acknowledge the last byte. Because either
the STOP or START bit is already set, the NCKI interrupt does not occur.
22. The I2C Controller sends the STOP (or RESTART) condition to the I2C bus and clears
the STOP (or START) bit.
Read Transaction with a 7-Bit Address
Figure 32 illustrates the data transfer format for a read operation to a 7-bit addressed slave.
The shaded regions indicate data transferred from the I2C Controller to slaves and
unshaded regions indicate data transferred from the slaves to the I2C Controller.
S
Slave Address
R = 1
A
Data
A
Data
A
P/S
Figure 32. Receive Data Transfer Format for a 7-Bit Addressed Slave
The procedure for a read operation to a 7-bit addressed slave is as follows:
1. Software writes the I2C Data register with a 7-bit slave address plus the read bit (=1).
2. Software asserts the START bit of the I2C Control register.
3. If this is a single byte transfer, Software asserts the NAKbit of the I2C Control register
so that after the first byte of data has been read by the I2C Controller, a Not
Acknowledge is sent to the I2C slave.
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4. The I2C Controller sends the START condition.
5. The I2C Controller shifts the address and read bit out the SDA signal.
6. If the I2C slave acknowledges the address by pulling the SDA signal Low during the
next high period of SCL, the I2C Controller sets the ACK bit in the I2C Status register.
Continue with step 7.
If the slave does not acknowledge, the Not Acknowledge interrupt occurs (NCKI bit is
set in the Status register, ACK bit is cleared). Software responds to the Not
Acknowledge interrupt by setting the STOP bit and clearing the TXI bit. The I2C
Controller sends the STOP condition on the bus and clears the STOP and NCKI bits.
The transaction is complete (ignore the following steps).
7. The I2C Controller shifts in the byte of data from the I2C slave on the SDA signal. The
I2C Controller sends a Not Acknowledge to the I2C slave if the NAK bit is set (last
byte), else it sends an Acknowledge.
8. The I2C Controller asserts the Receive interrupt (RDRF bit set in the Status register).
9. Software responds by reading the I2C Data register which clears the RDRF bit. If there
is only one more byte to receive, set the NAK bit of the I2C Control register.
10. If there are more bytes to transfer, return to step 7.
11. After the last byte is shifted in, a Not Acknowledge interrupt is generated by the I2C
Controller.
12. Software responds by setting the STOPbit of the I2C Control register.
13. A STOP condition is sent to the I2C slave, the STOP and NCKI bits are cleared.
Read Transaction with a 10-Bit Address
Figure 33 illustrates the read transaction format for a 10-bit addressed slave. The shaded
regions indicate data transferred from the I2C Controller to slaves and unshaded regions
indicate data transferred from the slaves to the I2C Controller.
Slave Address
1st 7 bits
Slave Address
2nd Byte
Slave Address
1st 7 bits
S
W=0 A
A S
R=1 A Data A Data A P
Figure 33. Receive Data Format for a 10-Bit Addressed Slave
The first seven bits transmitted in the first byte are 11110XX. The two bits XXare the two
most-significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write control bit.
The data transfer procedure for a read operation to a 10-bit addressed slave is as follows:
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1. Software writes 11110B followed by the two address bits and a 0 (write) to the I2C
Data register.
2. Software asserts the STARTand TXI bits of the I2C Control register.
3. The I2C Controller sends the Start condition.
4. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register.
5. After the first bit has been shifted out, a Transmit interrupt is asserted.
6. Software responds by writing the lower eight bits of address to the I2C Data register.
7. The I2C Controller completes shifting of the two address bits and a 0 (write).
8. If the I2C slave acknowledges the first address byte by pulling the SDA signal low
during the next high period of SCL, the I2C Controller sets the ACKbit in the I2C
Status register. Continue with step 9.
If the slave does not acknowledge the first address byte, the I2C Controller sets the
NCKIbit and clears the ACK bit in the I2C Status register. Software responds to the
Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI
bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and
NCKI bits. The transaction is complete (ignore following steps).
9. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register (second address byte).
10. The I2C Controller shifts out the second address byte. After the first bit is shifted, the
I2C Controller generates a Transmit interrupt.
11. Software responds by setting the STARTbit of the I2C Control register to generate a
repeated START and by clearing the TXI bit.
12. Software responds by writing 11110Bfollowed by the 2-bit slave address and a 1
(read) to the I2C Data register.
13. If only one byte is to be read, software sets the NAK bit of the I2C Control register.
14. After the I2C Controller shifts out the 2nd address byte, the I2C slave sends an
acknowledge by pulling the SDA signal low during the next high period of SCL, the
I2C Controller sets the ACKbit in the I2C Status register. Continue with step 15.
If the slave does not acknowledge the second address byte, the I2C Controller sets the
NCKIbit and clears the ACK bit in the I2C Status register. Software responds to the
Not Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI
bit. The I2C Controller sends the STOP condition on the bus and clears the STOP and
NCKI bits. The transaction is complete (ignore the following steps).
15. The I2C Controller sends the repeated START condition.
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16. The I2C Controller loads the I2C Shift register with the contents of the I2C Data
register (third address transfer).
17. The I2C Controller sends 11110Bfollowed by the two most significant bits of the
slave read address and a 1 (read).
18. The I2C slave sends an acknowledge by pulling the SDA signal Low during the next
high period of SCL
If the slave were to Not Acknowledge at this point (this should not happen because the
slave did acknowledge the first two address bytes), software would respond by setting
the STOP and FLUSH bits and clearing the TXI bit. The I2C Controller sends the
STOP condition on the bus and clears the STOP and NCKI bits. The transaction is
complete (ignore the following steps).
19. The I2C Controller shifts in a byte of data from the I2C slave on the SDA signal. The
I2C Controller sends a Not Acknowledge to the I2C slave if the NAK bit is set (last
byte), else it sends an Acknowledge.
20. The I2C Controller asserts the Receive interrupt (RDRF bit set in the Status register).
21. Software responds by reading the I2C Data register which clears the RDRF bit. If there
is only one more byte to receive, set the NAK bit of the I2C Control register.
22. If there are one or more bytes to transfer, return to step 19.
23. After the last byte is shifted in, a Not Acknowledge interrupt is generated by the I2C
Controller.
24. Software responds by setting the STOPbit of the I2C Control register.
25. A STOP condition is sent to the I2C slave and the STOP and NCKI bits are cleared.
2
I C Control Register Definitions
2
I C Data Register
The I2C Data register (Table 69) holds the data that is to be loaded into the I2C Shift regis-
ter during a write to a slave. This register also holds data that is loaded from the I2C Shift
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register during a read from a slave. The I2C Shift Register is not accessible in the Register
File address space, but is used only to buffer incoming and outgoing data.
2
Table 69. I C Data Register (I2CDATA)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DATA
0
R/W
F50H
ADDR
I2C Status Register
The Read-only I2C Status register (Table 70) indicates the status of the I2C Controller.
2
Table 70. I C Status Register (I2CSTAT)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TDRE
RDRF
ACK
10B
RD
TAS
DSS
NCKI
1
0
R
F51H
ADDR
TDRE—Transmit Data Register Empty
When the I2C Controller is enabled, this bit is 1 when the I2C Data register is empty.
When this bit is set, an interrupt is generated if the TXI bit is set, except when the I2C
Controller is shifting in data during the reception of a byte or when shifting an address and
the RDbit is set. This bit is cleared by writing to the I2CDATA register.
RDRF—Receive Data Register Full
This bit is set = 1 when the I2C Controller is enabled and the I2C Controller has received a
byte of data. When asserted, this bit causes the I2C Controller to generate an interrupt.
This bit is cleared by reading the I2C Data register (unless the read is performed using exe-
cution of the On-Chip Debugger’s Read Register command).
ACK—Acknowledge
This bit indicates the status of the Acknowledge for the last byte transmitted or received.
When set, this bit indicates that an Acknowledge occurred for the last byte transmitted or
received. This bit is cleared when IEN = 0 or when a Not Acknowledge occurred for the
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last byte transmitted or received. It is not reset at the beginning of each transaction and is
not reset when this register is read.
Caution:
Software must be cautious in making decisions based on this bit within a
transaction because software cannot tell when the bit is updated by hard-
ware. In the case of write transactions, the I2C pauses at the beginning of
the Acknowledge cycle if the next transmit data or address byte has not
been written (TDRE = 1) and STOP and START = 0. In this case the ACK
bit is not updated until the transmit interrupt is serviced and the Acknowl-
edge cycle for the previous byte completes. Refer to Address Only Trans-
action with a 7-bit Address on page 143 and Address Only Transaction
with a 10-bit Address on page 145 for examples of how the ACK bit can
be used.
10B—10-Bit Address
This bit indicates whether a 10- or 7-bit address is being transmitted. After the STARTbit
is set, if the five most-significant bits of the address are 11110B, this bit is set. When set,
it is reset once the first byte of the address has been sent.
RD—Read
This bit indicates the direction of transfer of the data. It is active high during a read. The
status of this bit is determined by the least-significant bit of the I2C Shift register after the
STARTbit is set.
TAS—Transmit Address State
This bit is active high while the address is being shifted out of the I2C Shift register.
DSS—Data Shift State
This bit is active high while data is being shifted to or from the I2C Shift register.
NCKI—NACK Interrupt
This bit is set high when a Not Acknowledge condition is received or sent and neither the
START nor the STOP bit is active. When set, this bit generates an interrupt that can only
be cleared by setting the STARTor STOPbit, allowing the user to specify whether he
wants to perform a STOPor a repeated START.
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I2C Control Register
The I2C Control register (Table 71) enables the I2C operation.
2
Table 71. I C Control Register (I2CCTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
IEN
START
STOP
BIRQ
TXI
NAK
FLUSH
FILTEN
0
R/W
R/W1
R/W1
R/W
R/W
R/W1
W1
R/W
F52H
ADDR
IEN—I2C Enable
1 = The I2C transmitter and receiver are enabled.
0 = The I2C transmitter and receiver are disabled.
START—Send Start Condition
This bit sends the Start condition. Once asserted, it is cleared by the I2C Controller after it
sends the START condition or if the IENbit is deasserted. If this bit is 1, it cannot be
cleared to 0 by writing to the register. After this bit is set, the Start condition is sent if there
is data in the I2C Data or I2C Shift register. If there is no data in one of these registers, the
I2C Controller waits until the Data register is written. If this bit is set while the I2C Con-
troller is shifting out data, it generates a START condition after the byte shifts and the
acknowledge phase completes. If the STOPbit is also set, it also waits until the STOP con-
dition is sent before the sending the START condition.
STOP—Send Stop Condition
This bit causes the I2C Controller to issue a Stop condition after the byte in the I2C Shift
register has completed transmission or after a byte has been received in a receive opera-
tion. Once set, this bit is reset by the I2C Controller after a Stop condition has been sent or
by deasserting the IENbit. If this bit is 1, it cannot be cleared to 0 by writing to the regis-
ter.
BIRQ—Baud Rate Generator Interrupt Request
This bit allows the I2C Controller to be used as an additional timer when the I2C Control-
ler is disabled. This bit is ignored when the I2C Controller is enabled.
1 = An interrupt occurs every time the baud rate generator counts down to one.
0 = No baud rate generator interrupt occurs.
TXI—Enable TDRE interrupts
This bit enables the transmit interrupt when the I2C Data register is empty (TDRE = 1).
1 = Transmit interrupt (and DMA transmit request) is enabled.
0 = Transmit interrupt (and DMA transmit request) is disabled.
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NAK—Send NAK
This bit sends a Not Acknowledge condition after the next byte of data has been read from
the I2C slave. Once asserted, it is deasserted after a Not Acknowledge is sent or the IEN
bit is deasserted. If this bit is 1, it cannot be cleared to 0 by writing to the register.
FLUSH—Flush Data
Setting this bit to 1 clears the I2C Data register and sets the TDRE bit to 1. This bit allows
flushing of the I2C Data register when a Not Acknowledge interrupt is received after the
data has been sent to the I2C Data register. Reading this bit always returns 0.
FILTEN—I2C Signal Filter Enable
This bit enables low-pass digital filters on the SDA and SCL input signals. These filters
reject any input pulse with periods less than a full system clock cycle. The filters introduce
a 3-system clock cycle latency on the inputs.
1 = low-pass filters are enabled.
0 = low-pass filters are disabled.
I2C Baud Rate High and Low Byte Registers
The I2C Baud Rate High and Low Byte registers (Tables 72 and 73) combine to form a 16-
bit reload value, BRG[15:0], for the I2C Baud Rate Generator.
When the I2C is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt
on time-out, complete the following procedure:
1. Disable the I2C by clearing the IENbit in the I2C Control register to 0.
2. Load the desired 16-bit count value into the I2C Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BIRQbit in the I2C Control register to 1.
When configured as a general purpose timer, the interrupt interval is calculated using the
following equation:
Interrupt Interval (s) = System Clock Period (s) ×BRG[15:0]
]
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.
2
Table 72. I C Baud Rate High Byte Register (I2CBRH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
BRH
FFH
R/W
F53H
ADDR
BRH = I2C Baud Rate High Byte
Most significant byte, BRG[15:8], of the I2C Baud Rate Generator’s reload value.
Note: If the DIAG bit in the I2C Diagnostic Control Register is set to 1, a read of the I2CBRH
register returns the current value of the I2C Baud Rate Counter[15:8].
2
Table 73. I C Baud Rate Low Byte Register (I2CBRL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
BRL
FFH
R/W
F54H
ADDR
BRL = I2C Baud Rate Low Byte
Least significant byte, BRG[7:0], of the I2C Baud Rate Generator’s reload value.
Note: If the DIAG bit in the I2C Diagnostic Control Register is set to 1, a read of the I2CBRL
register returns the current value of the I2C Baud Rate Counter[7:0].
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I2C Diagnostic State Register
The I2C Diagnostic State register (Table 74) provides observability of internal state. This
is a read only register used for I2C diagnostics and manufacturing test.
2
Table 74. I C Diagnostic State Register (I2CDST)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
SCLIN
SDAIN
STPCNT
TXRXSTATE
X
0
R
F55H
ADDR
SCLIN - Value of Serial Clock input signal
SDAIN - Value of the Serial Data input signal
STPCNT - Value of the internal Stop Count control signal
2
TXRXSTATE - Value of the internal I C state machine
TXRXSTATE
0_0000
0_0001
0_0010
0_0011
0_0100
0_0101
0_0110
0_0111
0_1000
0_1001
0_1010
0_1011
0_1100
0_1101
0_1110
State Description
Idle State
START State
Send/Receive data bit 7
Send/Receive data bit 6
Send/Receive data bit 5
Send/Receive data bit 4
Send/Receive data bit 3
Send/Receive data bit 2
Send/Receive data bit 1
Send/Receive data bit 0
Data Acknowledge State
Second half of data Acknowledge State used only for not acknowledge
First part of STOP state
Second part of STOP state
10-bit addressing: Acknowledge State for 2nd address byte
7-bit addressing: Address Acknowledge State
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TXRXSTATE
State Description
0_1111
10-bit address: Bit 0 (Least significant bit) of 2nd address byte
7-bit address: Bit 0 (Least significant bit) (R/W) of address byte
1_0000
1_0001
1_0010
1_0011
1_0100
1_0101
1_0110
1_0111
1_1000
1_1001
10-bit addressing: Bit 7 (Most significant bit) of 1st address byte
10-bit addressing: Bit 6 of 1st address byte
10-bit addressing: Bit 5 of 1st address byte
10-bit addressing: Bit 4 of 1st address byte
10-bit addressing: Bit 3 of 1st address byte
10-bit addressing: Bit 2 of 1st address byte
10-bit addressing: Bit 1 of 1st address byte
10-bit addressing: Bit 0 (R/W) of 1st address byte
10-bit addressing: Acknowledge state for 1st address byte
10-bit addressing: Bit 7 of 2nd address byte
7-bit addressing: Bit 7 of address byte
1_1010
1_1011
1_1100
1_1101
1_1110
1_1111
10-bit addressing: Bit 6 of 2nd address byte
7-bit addressing: Bit 6 of address byte
10-bit addressing: Bit 5 of 2nd address byte
7-bit addressing: Bit 5 of address byte
10-bit addressing: Bit 4 of 2nd address byte
7-bit addressing: Bit 4 of address byte
10-bit addressing: Bit 3 of 2nd address byte
7-bit addressing: Bit 3 of address byte
10-bit addressing: Bit 2 of 2nd address byte
7-bit addressing: Bit 2 of address byte
10-bit addressing: Bit 1 of 2nd address byte
7-bit addressing: Bit 1 of address byte
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I2C Diagnostic Control Register
The I2C Diagnostic register (Table 75) provides control over diagnostic modes. This regis-
ter is a read/write register used for I2C diagnostics.
2
Table 75. I C Diagnostic Control Register (I2CDIAG)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
Reserved
DIAG
0
R
R/W
F56H
ADDR
DIAG = Diagnostic Control Bit - Selects read back value of the Baud Rate Reload regis-
ters.
0 = Normal mode. Reading the Baud Rate High and Low Byte registers returns the baud
rate reload value.
1 = Diagnostic mode. Reading the Baud Rate High and Low Byte registers returns the
baud rate counter value.
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Direct Memory Access Controller
Overview
The 64K Series Direct Memory Access (DMA) Controller provides three independent
Direct Memory Access channels. Two of the channels (DMA0 and DMA1) transfer data
between the on-chip peripherals and the Register File. The third channel (DMA_ADC)
controls the Analog-to-Digital Converter (ADC) operation and transfers SINGLE-SHOT
mode ADC output data to the Register File.
Operation
DMA0 and DMA1 Operation
DMA0 and DMA1, referred to collectively as DMAx, transfer data either from the on-chip
peripheral control registers to the Register File, or from the Register File to the on-chip
peripheral control registers. The sequence of operations in a DMAx data transfer is:
1. DMAx trigger source requests a DMA data transfer.
2. DMAx requests control of the system bus (address and data) from the eZ8 CPU.
3. After the eZ8 CPU acknowledges the bus request, DMAx transfers either a single byte
or a two-byte word (depending upon configuration) and then returns system bus
control back to the eZ8 CPU.
4. If Current Address equals End Address:
–
–
DMAx reloads the original Start Address
If configured to generate an interrupt, DMAx sends an interrupt request to the
Interrupt Controller
–
If configured for single-pass operation, DMAx resets the DENbit in the DMAx
Control register to 0 and the DMA is disabled.
If Current Address does not equal End Address, the Current Address increments by 1
(single-byte transfer) or 2 (two-byte word transfer).
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Configuring DMA0 and DMA1 for Data Transfer
Follow these steps to configure and enable DMA0 or DMA1:
1. Write to the DMAx I/O Address register to set the Register File address identifying the
on-chip peripheral control register. The upper nibble of the 12-bit address for on-chip
peripheral control registers is always FH. The full address is {FH, DMAx_IO[7:0]}
2. Determine the 12-bit Start and End Register File addresses. The 12-bit Start Address
is given by {DMAx_H[3:0], DMA_START[7:0]}. The 12-bit End Address is given by
{DMAx_H[7:4], DMA_END[7:0]}.
3. Write the Start and End Register File address high nibbles to the DMAx End/Start
Address High Nibble register.
4. Write the lower byte of the Start Address to the DMAx Start/Current Address register.
5. Write the lower byte of the End Address to the DMAx End Address register.
6. Write to the DMAx Control register to complete the following:
–
–
Select loop or single-pass mode operation
Select the data transfer direction (either from the Register File RAM to the on-
chip peripheral control register; or from the on-chip peripheral control register to
the Register File RAM)
–
–
–
–
Enable the DMAx interrupt request, if desired
Select Word or Byte mode
Select the DMAx request trigger
Enable the DMAx channel
DMA_ADC Operation
DMA_ADC transfers data from the ADC to the Register File. The sequence of operations
in a DMA_ADC data transfer is:
1. ADC completes conversion on the current ADC input channel and signals the DMA
controller that two-bytes of ADC data are ready for transfer.
2. DMA_ADC requests control of the system bus (address and data) from the eZ8 CPU.
3. After the eZ8 CPU acknowledges the bus request, DMA_ADC transfers the two-byte
ADC output value to the Register File and then returns system bus control back to the
eZ8 CPU.
4. If the current ADC Analog Input is the highest numbered input to be converted:
–
DMA_ADC resets the ADC Analog Input number to 0 and initiates data
conversion on ADC Analog Input 0.
–
If configured to generate an interrupt, DMA_ADC sends an interrupt request to
the Interrupt Controller
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If the current ADC Analog Input is not the highest numbered input to be converted,
DMA_ADC initiates data conversion in the next higher numbered ADC Analog Input.
Configuring DMA_ADC for Data Transfer
Follow these steps to configure and enable DMA_ADC:
1. Write the DMA_ADC Address register with the 7 most-significant bits of the Register
File address for data transfers.
2. Write to the DMA_ADC Control register to complete the following:
–
–
–
Enable the DMA_ADC interrupt request, if desired
Select the number of ADC Analog Inputs to convert
Enable the DMA_ADC channel
Caution:
When using the DMA_ADC to perform conversions on multiple ADC in-
puts, the Analog-to-Digital Converter must be configured for SINGLE-
SHOT mode. If the ADC_INfield in the DMA_ADC Control Register is
greater than 000b, the ADC must be in SINGLE-SHOT mode.
CONTINUOUS mode operation of the ADC can only be used in conjunc-
tion with DMA_ADC if the ADC_INfield in the DMA_ADC Control
Register is reset to 000b to enable conversion on ADC Analog Input 0
only.
DMA Control Register Definitions
DMAx Control Register
The DMAx Control register (Table 76) enables and selects the mode of operation for
DMAx.
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Table 76. DMAx Control Register (DMAxCTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DEN
DLE
DDIR
IRQEN
WSEL
RSS
0
R/W
FB0H, FB8H
ADDR
DEN—DMAx Enable
0 = DMAx is disabled and data transfer requests are disregarded.
1 = DMAx is enabled and initiates a data transfer upon receipt of a request from the trigger
source.
DLE—DMAx Loop Enable
0 = DMAx reloads the original Start Address and is then disabled after the End Address
data is transferred.
1 = DMAx, after the End Address data is transferred, reloads the original Start Address
and continues operating.
DDIR—DMAx Data Transfer Direction
0 = Register File → on-chip peripheral control register.
1 = on-chip peripheral control register → Register File.
IRQEN—DMAx Interrupt Enable
0 = DMAx does not generate any interrupts.
1 = DMAx generates an interrupt when the End Address data is transferred.
WSEL—Word Select
0 = DMAx transfers a single byte per request.
1 = DMAx transfers a two-byte word per request. The address for the on-chip peripheral
control register must be an even address.
RSS—Request Trigger Source Select
The Request Trigger Source Select field determines the peripheral that can initiate a DMA
transfer. The corresponding interrupts do not need to be enabled within the Interrupt Con-
troller to initiate a DMA transfer. However, if the Request Trigger Source can enable or
disable the interrupt request sent to the Interrupt Controller, the interrupt request must be
enabled within the Request Trigger Source block.
000 = Timer 0.
001 = Timer 1.
010 = Timer 2.
011 = Timer 3.
100 = DMA0 Control register: UART0 Received Data register contains valid data. DMA1
Control register: UART0 Transmit Data register empty.
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101 = DMA0 Control register: UART1 Received Data register contains valid data. DMA1
Control register: UART1 Transmit Data register empty.
110 = DMA0 Control register: I2C Receiver Interrupt. DMA1 Control register: I2C Trans-
mitter Interrupt register empty.
111 = Reserved.
DMAx I/O Address Register
The DMAx I/O Address register (Table 77) contains the low byte of the on-chip peripheral
address for data transfer. The full 12-bit Register File address is given by {FH,
DMAx_IO[7:0]}. When the DMA is configured for two-byte word transfers, the DMAx I/
O Address register must contain an even numbered address.
Table 77. DMAx I/O Address Register (DMAxIO)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DMA_IO
X
R/W
FB1H, FB9H
ADDR
DMA_IO—DMA on-chip peripheral control register address
This byte sets the low byte of the on-chip peripheral control register address on Register
File Page FH(addresses F00Hto FFFH).
DMAx Address High Nibble Register
The DMAx Address High register (Table 78) specifies the upper four bits of address for
the Start/Current and End Addresses of DMAx.
Table 78. DMAx Address High Nibble Register (DMAxH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DMA_END_H
DMA_START_H
X
R/W
FB2H, FBAH
ADDR
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DMA_END_H—DMAx End Address High Nibble
These bits, used with the DMAx End Address Low register, form a 12-bit End Address.
The full 12-bit address is given by {DMA_END_H[3:0], DMA_END[7:0]}.
DMA_START_H—DMAx Start/Current Address High Nibble
These bits, used with the DMAx Start/Current Address Low register, form a 12-bit Start/
Current Address. The full 12-bit address is given by {DMA_START_H[3:0],
DMA_START[7:0]}.
DMAx Start/Current Address Low Byte Register
The DMAx Start/Current Address Low register, in conjunction with the DMAx Address
High Nibble register, forms a 12-bit Start/Current Address. Writes to this register set the
Start Address for DMA operations. Each time the DMA completes a data transfer, the 12-
bit Start/Current Address increments by either 1 (single-byte transfer) or 2 (two-byte word
transfer). Reads from this register return the low byte of the Current Address to be used for
the next DMA data transfer.
Table 79. DMAx Start/Current Address Low Byte Register (DMAxSTART)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DMA_START
X
R/W
FB3H, FBBH
ADDR
DMA_START—DMAx Start/Current Address Low
These bits, with the four lower bits of the DMAx_H register, form the 12-bit Start/Current
address. The full 12-bit address is given by {DMA_START_H[3:0], DMA_START[7:0]}.
DMAx End Address Low Byte Register
The DMAx End Address Low Byte register (Table 79), in conjunction with the DMAx_H
register (Table 80), forms a 12-bit End Address.
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Table 80. DMAx End Address Low Byte Register (DMAxEND)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DMA_END
X
R/W
FB4H, FBCH
ADDR
DMA_END—DMAx End Address Low
These bits, with the four upper bits of the DMAx_H register, form a 12-bit address. This
address is the ending location of the DMAx transfer. The full 12-bit address is given by
{DMA_END_H[3:0], DMA_END[7:0]}.
DMA_ADC Address Register
The DMA_ADC Address register (Table 82) points to a block of the Register File to store
ADC conversion values as illustrated in Table 81. This register contains the seven most-
significant bits of the 12-bit Register File addresses. The five least-significant bits are cal-
culated from the ADC Analog Input number (5-bit base address is equal to twice the ADC
Analog Input number). The 10-bit ADC conversion data is stored as two bytes with the
most significant byte of the ADC data stored at the even numbered Register File address.
Table 81 provides an example of the Register File addresses if the DMA_ADC Address
register contains the value 72H.
Table 81. DMA_ADC Register File Address Example
1
ADC Analog Input Register File Address (Hex)
0
1
2
3
4
5
6
7
8
720H-721H
722H-723H
724H-725H
726H-727H
728H-729H
72AH-72BH
72CH-72DH
72EH-72FH
730H-731H
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Table 81. DMA_ADC Register File Address Example
1
ADC Analog Input Register File Address (Hex)
9
732H-733H
734H-735H
736H-737H
10
11
1
DMAA_ADDR set to 72H.
Table 82. DMA_ADC Address Register (DMAA_ADDR)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DMAA_ADDR
Reserved
X
R/W
FBDH
ADDR
DMAA_ADDR—DMA_ADC Address
These bits specify the seven most-significant bits of the 12-bit Register File addresses
used for storing the ADC output data. The ADC Analog Input Number defines the five
least-significant bits of the Register File address. Full 12-bit address is
{DMAA_ADDR[7:1], 4-bit ADC Analog Input Number, 0}.
Reserved
This bit is reserved and must be 0.
DMA_ADC Control Register
The DMA_ADC Control register (Table 83) enables and sets options (DMA enable and
interrupt enable) for ADC operation.
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Table 83. DMA_ADC Control Register (DMAACTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DAEN
IRQEN
Reserved
ADC_IN
0
R/W
FBEH
ADDR
DAEN—DMA_ADC Enable
0 = DMA_ADC is disabled and the ADC Analog Input Number (ADC_IN) is reset to 0.
1 = DMA_ADC is enabled.
IRQEN—Interrupt Enable
0 = DMA_ADC does not generate any interrupts.
1 = DMA_ADC generates an interrupt after transferring data from the last ADC Analog
Input specified by the ADC_IN field.
Reserved
These bits are reserved and must be 0.
ADC_IN—ADC Analog Input Number
These bits set the number of ADC Analog Inputs to be used in the continuous update (data
conversion followed by DMA data transfer). The conversion always begins with ADC
Analog Input 0 and then progresses sequentially through the other selected ADC Analog
Inputs.
0000 = ADC Analog Input 0 updated.
0001 = ADC Analog Inputs 0-1 updated.
0010 = ADC Analog Inputs 0-2 updated.
0011 = ADC Analog Inputs 0-3 updated.
0100 = ADC Analog Inputs 0-4 updated.
0101 = ADC Analog Inputs 0-5 updated.
0110 = ADC Analog Inputs 0-6 updated.
0111 = ADC Analog Inputs 0-7 updated.
1000 = ADC Analog Inputs 0-8 updated.
1001 = ADC Analog Inputs 0-9 updated.
1010 = ADC Analog Inputs 0-10 updated.
1011 = ADC Analog Inputs 0-11 updated.
1100-1111 = Reserved.
DMA Status Register
The DMA Status register (Table 84) indicates the DMA channel that generated the inter-
rupt and the ADC Analog Input that is currently undergoing conversion. Reads from this
register reset the Interrupt Request Indicator bits (IRQA, IRQ1, and IRQ0) to 0. There-
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fore, software interrupt service routines that read this register must process all three inter-
rupt sources from the DMA.
Table 84. DMA_ADC Status Register (DMAA_STAT)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
CADC[3:0]
Reserved
IRQA
IRQ1
IRQ0
0
R
FBFH
ADDR
CADC[3:0]—Current ADC Analog Input
This field identifies the Analog Input that the ADC is currently converting.
Reserved
This bit is reserved and must be 0.
IRQA—DMA_ADC Interrupt Request Indicator
This bit is automatically reset to 0 each time a read from this register occurs.
0 = DMA_ADC is not the source of the interrupt from the DMA Controller.
1 = DMA_ADC completed transfer of data from the last ADC Analog Input and generated
an interrupt.
IRQ1—DMA1 Interrupt Request Indicator
This bit is automatically reset to 0 each time a read from this register occurs.
0 = DMA1 is not the source of the interrupt from the DMA Controller.
1 = DMA1 completed transfer of data to/from the End Address and generated an interrupt.
IRQ0—DMA0 Interrupt Request Indicator
This bit is automatically reset to 0 each time a read from this register occurs.
0 = DMA0 is not the source of the interrupt from the DMA Controller.
1 = DMA0 completed transfer of data to/from the End Address and generated an interrupt.
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Analog-to-Digital Converter
Overview
The Analog-to-Digital Converter (ADC) converts an analog input signal to a 10-bit binary
number. The features of the sigma-delta ADC include:
•
•
•
•
12 analog input sources are multiplexed with general-purpose I/O ports
Interrupt upon conversion complete
Internal voltage reference generator
Direct Memory Access (DMA) controller can automatically initiate data conversion
and transfer of the data from 1 to 12 of the analog inputs
Architecture
Figure 34 illustrates the three major functional blocks (converter, analog multiplexer, and
voltage reference generator) of the ADC. The ADC converts an analog input signal to its
digital representation. The 12-input analog multiplexer selects one of the 12 analog input
sources. The ADC requires an input reference voltage for the conversion. The voltage ref-
erence for the conversion may be input through the external VREF pin or generated inter-
nally by the voltage reference generator.
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VREF
Internal Voltage
Reference Generator
Analog Input
Multiplexer
ANA0
ANA1
ANA2
ANA3
ANA4
ANA5
ANA6
ANA7
ANA8
ANA9
ANA10
ANA11
Analog-to-Digital
Converter
Reference Input
Analog Input
ANAIN[3:0]
Figure 34. Analog-to-Digital Converter Block Diagram
The sigma-delta ADC architecture provides alias and image attenuation below the ampli-
tude resolution of the ADC in the frequency range of DC to one-half the ADC clock rate
(one-fourth the system clock rate). The ADC provides alias free conversion for frequen-
cies up to one-half the ADC clock rate. Thus the sigma-delta ADC exhibits high noise
immunity making it ideal for embedded applications. In addition, monotonicity (no miss-
ing codes) is guaranteed by design.
Operation
Automatic Power-Down
If the ADC is idle (no conversions in progress) for 160 consecutive system clock cycles,
portions of the ADC are automatically powered-down. From this power-down state, the
ADC requires 40 system clock cycles to power-up. The ADC powers up when a conver-
sion is requested using the ADC Control register.
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Single-Shot Conversion
When configured for single-shot conversion, the ADC performs a single analog-to-digital
conversion on the selected analog input channel. After completion of the conversion, the
ADC shuts down. The steps for setting up the ADC and initiating a single-shot conversion
are as follows:
1. Enable the desired analog inputs by configuring the general-purpose I/O pins for
alternate function. This configuration disables the digital input and output drivers.
2. Write to the ADC Control register to configure the ADC and begin the conversion.
The bit fields in the ADC Control register can be written simultaneously:
–
–
–
–
Write to the ANAIN[3:0]field to select one of the 12 analog input sources.
Clear CONTto 0 to select a single-shot conversion.
Write to the VREFbit to enable or disable the internal voltage reference generator.
Set CENto 1 to start the conversion.
3. CENremains 1 while the conversion is in progress. A single-shot conversion requires
5129 system clock cycles to complete. If a single-shot conversion is requested from an
ADC powered-down state, the ADC uses 40 additional clock cycles to power-up
before beginning the 5129 cycle conversion.
4. When the conversion is complete, the ADC control logic performs the following
operations:
–
–
–
10-bit data result written to {ADCD_H[7:0], ADCD_L[7:6]}.
CENresets to 0 to indicate the conversion is complete.
An interrupt request is sent to the Interrupt Controller.
5. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically
powered-down.
Continuous Conversion
When configured for continuous conversion, the ADC continuously performs an analog-
to-digital conversion on the selected analog input. Each new data value over-writes the
previous value stored in the ADC Data registers. An interrupt is generated after each con-
version.
Caution:
In CONTINUOUS mode, users must be aware that ADC updates are lim-
ited by the input signal bandwidth of the ADC and the latency of the ADC
and its digital filter. Step changes at the input are not seen at the next output
from the ADC. The response of the ADC (in all modes) is limited by the
input signal bandwidth and the latency.
The steps for setting up the ADC and initiating continuous conversion are as follows:
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1. Enable the desired analog input by configuring the general-purpose I/O pins for
alternate function. This disables the digital input and output driver.
2. Write to the ADC Control register to configure the ADC for continuous conversion.
The bit fields in the ADC Control register may be written simultaneously:
–
–
–
–
Write to the ANAIN[3:0]field to select one of the 12 analog input sources.
Set CONTto 1 to select continuous conversion.
Write to the VREFbit to enable or disable the internal voltage reference generator.
Set CENto 1 to start the conversions.
3. When the first conversion in continuous operation is complete (after 5129 system
clock cycles, plus the 40 cycles for power-up, if necessary), the ADC control logic
performs the following operations:
–
CENresets to 0 to indicate the first conversion is complete. CENremains 0 for all
subsequent conversions in continuous operation.
–
An interrupt request is sent to the Interrupt Controller to indicate the conversion is
complete.
4. Thereafter, the ADC writes a new 10-bit data result to {ADCD_H[7:0],
ADCD_L[7:6]} every 256 system clock cycles. An interrupt request is sent to the
Interrupt Controller when each conversion is complete.
5. To disable continuous conversion, clear the CONTbit in the ADC Control register
to 0.
DMA Control of the ADC
The Direct Memory Access (DMA) Controller can control operation of the ADC includ-
ing analog input selection and conversion enable. For more information on the DMA and
configuring for ADC operations refer to the chapter Direct Memory Access Controller
on page 160.
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ADC Control Register Definitions
ADC Control Register
The ADC Control register selects the analog input channel and initiates the analog-to-dig-
ital conversion.
Table 85. ADC Control Register (ADCCTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
CEN
Reserved
VREF
CONT
ANAIN[3:0]
0
1
0
R/W
F70H
ADDR
CEN—Conversion Enable
0 = Conversion is complete. Writing a 0 produces no effect. The ADC automatically clears
this bit to 0 when a conversion has been completed.
1 = Begin conversion. Writing a 1 to this bit starts a conversion. If a conversion is already
in progress, the conversion restarts. This bit remains 1 until the conversion is complete.
Reserved—Must be 0.
VREF
0 = Internal voltage reference generator enabled. The VREF pin should be left uncon-
nected (or capacitively coupled to analog ground) if the internal voltage reference is
selected as the ADC reference voltage.
1 = Internal voltage reference generator disabled. An external voltage reference must be
provided through the VREF pin.
CONT
0 = Single-shot conversion. ADC data is output once at completion of the 5129 system
clock cycles.
1 = Continuous conversion. ADC data updated every 256 system clock cycles.
ANAIN—Analog Input Select
These bits select the analog input for conversion. Not all Port pins in this list are available
in all packages for the Z8F642x familyZ8R642x family of products. Refer to the Signal
and Pin Descriptions chapter for information regarding the Port pins available with each
package style. Do not enable unavailable analog inputs.
0000 = ANA0
0001 = ANA1
0010 = ANA2
0011 = ANA3
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0100 = ANA4
0101 = ANA5
0110 = ANA6
0111 = ANA7
1000 = ANA8
1001 = ANA9
1010 = ANA10
1011 = ANA11
11XX = Reserved.
ADC Data High Byte Register
The ADC Data High Byte register (Table 86) contains the upper eight bits of the 10-bit
ADC output. During a single-shot conversion, this value is invalid. Access to the ADC
Data High Byte register is read-only. The full 10-bit ADC result is given by
{ADCD_H[7:0], ADCD_L[7:6]}. Reading the ADC Data High Byte register latches data
in the ADC Low Bits register
.
Table 86. ADC Data High Byte Register (ADCD_H)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
ADCD_H
X
R
F72H
ADDR
ADCD_H—ADC Data High Byte
This byte contains the upper eight bits of the 10-bit ADC output. These bits are not valid
during a single-shot conversion. During a continuous conversion, the last conversion out-
put is held in this register. These bits are undefined after a Reset.
ADC Data Low Bits Register
The ADC Data Low Bits register (Table 87) contains the lower two bits of the conversion
value. The data in the ADC Data Low Bits register is latched each time the ADC Data
High Byte register is read. Reading this register always returns the lower two bits of the
conversion last read into the ADC High Byte register. Access to the ADC Data Low Bits
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register is read-only. The full 10-bit ADC result is given by {ADCD_H[7:0],
ADCD_L[7:6]}.
Table 87. ADC Data Low Bits Register (ADCD_L)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
ADCD_L
Reserved
X
R
F73H
ADDR
ADCD_L—ADC Data Low Bits
These are the least significant two bits of the 10-bit ADC output. These bits are undefined
after a Reset.
Reserved
These bits are reserved and are always undefined.
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Program Memory
The Z8 Encore!® 64K Series devices feature either Flash or Read-Only Memory (ROM)
with up to 64KB capacity as program memory. Refer to Ordering Information on page 265
for Flash or ROM device-related information.
This section describes the Flash program memory features, followed by a section describ-
ing the ROM features.
Flash memory features apply only to Z8F046x2/Z8F0482x/Z8F0322x/ Z8F0242x/
Z8F0162x devices.
Flash Memory
The products in the Z8 Encore!® 64K Series feature up to 64KB (65,536 bytes) of non-
volatile Flash memory with read/write/erase capability. The Flash memory can be pro-
grammed and erased in-circuit by either user code or through the On-Chip Debugger.
The Flash memory array is arranged in 512-byte per page. The 512-byte page is the mini-
mum Flash block size that can be erased. The Flash memory is also divided into 8 sectors
which can be protected from programming and erase operations on a per sector basis.
Table 88 describes the Flash memory configuration for each device in the 64K Series.
Table 89 lists the sector address ranges. Figure 35 illustrates the Flash memory arrange-
ment.
Table 88. Flash Memory Configurations
Number of Program Memory
Number of Pages per
Part Number
Z8F162x
Z8F242x
Z8F322x
Z8F482x
Z8F642x
Flash Size
16K (16,384)
24K (24,576)
32K (32,768)
48K (49,152)
64K (65,536)
Pages
32
Addresses
Sector Size
2K (2048)
4K (4096)
4K (4096)
8K (8192)
8K (8192)
Sectors
Sector
0000H - 3FFFH
0000H - 5FFFH
0000H - 7FFFH
0000H - BFFFH
0000H - FFFFH
8
6
8
6
8
4
8
48
64
8
96
16
16
128
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Table 89. Flash Memory Sector Addresses
Flash Sector Address Ranges
Sector Number
Z8F162x
0000H-07FFH
0800H-0FFFH
1000H-17FFH
1800H-1FFFH
2000H-27FFH
2800H-2FFFH
3000H-37FFH
3800H-3FFFH
Z8F242x
Z8F322x
0000H-0FFFH
1000H-1FFFH
2000H-2FFFH
3000H-3FFFH
4000H-4FFFH
5000H-5FFFH
6000H-6FFFH
7000H-7FFFH
Z8F482x
Z8F642x
0000H-1FFFH
2000H-3FFFH
4000H-5FFFH
6000H-7FFFH
8000H-9FFFH
0
1
2
3
4
5
6
7
0000H-0FFFH
1000H-1FFFH
2000H-2FFFH
3000H-3FFFH
4000H-4FFFH
5000H-5FFFH
N/A
0000H-1FFFH
2000H-3FFFH
4000H-5FFFH
6000H-7FFFH
8000H-9FFFH
A000H-BFFFH A000H-BFFFH
N/A
N/A
C000H-DFFFH
E000H-FFFFH
N/A
64KB Flash
Program Memory
Addresses
FFFFH
FE00H
FDFFH
FC00H
FBFFH
FA00H
128 Pages
512 Bytes per Page
05FFH
0400H
03FFH
0200H
01FFH
0000H
Figure 35. Flash Memory Arrangement
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Information Area
Table 90 describes the 64K Series Information Area. This 512-byte Information Area is
accessed by setting bit 7 of the Page Select Register to 1. When access is enabled, the
Information Area is mapped into Program Memory and overlays the 512 bytes at
addresses FE00Hto FFFFH. When the Information Area access is enabled, LDC instruc-
tions return data from the Information Area. CPU instruction fetches always comes from
Program Memory regardless of the Information Area access bit. Access to the Information
Area is read-only.
Table 90. 64K Series Information Area Map
Program Memory Address (Hex) Function
FE00H-FE3FH
FE40H-FE53H
Reserved
Part Number
20-character ASCII alphanumeric code
Left justified and filled with zeros
FE54H-FFFFH
Reserved
Operation
The Flash Controller provides the proper signals and timing for Byte Programming, Page
Erase, and Mass Erase of the Flash memory. The Flash Controller contains a protection
mechanism, via the Flash Control register (FCTL), to prevent accidental programming or
erasure. The following subsections provide details on the various operations (Lock,
Unlock, Sector Protect, Byte Programming, Page Erase, and Mass Erase).
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Timing Using the Flash Frequency Registers
Before performing a program or erase operation on the Flash memory, the user must first
configure the Flash Frequency High and Low Byte registers. The Flash Frequency regis-
ters allow programming and erasure of the Flash with system clock frequencies ranging
from 20kHz through 20MHz (the valid range is limited to the device operating frequen-
cies).
The Flash Frequency High and Low Byte registers combine to form a 16-bit value,
FFREQ, to control timing for Flash program and erase operations. The 16-bit Flash Fre-
quency value must contain the system clock frequency in KHz. This value is calculated
using the following equation:.
System Clock Frequency (Hz)
---------------------------------------------------------------------------
FFREQ[15:0] =
1000
Caution:
Flash programming and erasure are not supported for system clock fre-
quencies below 20KHz, above 20MHz, or outside of the device operating
frequency range. The Flash Frequency High and Low Byte registers must
be loaded with the correct value to insure proper Flash programming and
erase operations.
Flash Read Protection
The user code contained within the Flash memory can be protected from external access.
Programming the Flash Read Protect Option Bit prevents reading of user code by the On-
Chip Debugger or by using the Flash Controller Bypass mode. Refer to the Option Bits
chapter and the On-Chip Debugger chapter for more information.
Flash Write/Erase Protection
The 64K Series provides several levels of protection against accidental program and era-
sure of the Flash memory contents. This protection is provided by the Flash Controller
unlock mechanism, the Flash Sector Protect register, and the Flash Write Protect option
bit.
Flash Controller Unlock Mechanism
At Reset, the Flash Controller locks to prevent accidental program or erasure of the Flash
memory. To program or erase the Flash memory, the Flash controller must be unlocked.
After unlocking the Flash Controller, the Flash can be programmed or erased. Any value
written by user code to the Flash Control register or Page Select Register out of sequence
will lock the Flash Controller.
The proper steps to unlock the Flash Controller from user code are:
1. Write 00Hto the Flash Control register to reset the Flash Controller.
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2. Write the page to be programmed or erased to the Page Select register.
3. Write the first unlock command 73Hto the Flash Control register.
4. Write the second unlock command 8CHto the Flash Control register.
5. Re-write the page written in step 2 to the Page Select register.
Flash Sector Protection
The Flash Sector Protect register can be configured to prevent sectors from being pro-
grammed or erased. Once a sector is protected, it cannot be unprotected by user code. The
Flash Sector Protect register is cleared after reset and any previously written protection
values is lost. User code must write this register in their initialization routine if they want
to enable sector protection.
The Flash Sector Protect register shares its Register File address with the Page Select reg-
ister. The Flash Sector Protect register is accessed by writing the Flash Control register
with 5EH. Once the Flash Sector Protect register is selected, it can be accessed at the Page
Select Register address. When user code writes the Flash Sector Protect register, bits can
only be set to 1. Thus, sectors can be protected, but not unprotected, via register write
operations. Writing a value other than 5EHto the Flash Control register de-selects the
Flash Sector Protect register and re-enables access to the Page Select register.
The steps to setup the Flash Sector Protect register from user code are:
1. Write 00Hto the Flash Control register to reset the Flash Controller.
2. Write 5EHto the Flash Control register to select the Flash Sector Protect register.
3. Read and/or write the Flash Sector Protect register which is now at Register File
address FF9H.
4. Write 00Hto the Flash Control register to return the Flash Controller to its reset state.
Flash Write Protection Option Bit
The Flash Write Protect option bit can be enabled to block all program and erase opera-
tions from user code. Refer to the Option Bits chapter for more information.
Byte Programming
When the Flash Controller is unlocked, writes to Program Memory from user code will
program a byte into the Flash if the address is located in the unlocked page. An erased
Flash byte contains all ones (FFH). The programming operation can only be used to
change bits from one to zero. To change a Flash bit (or multiple bits) from zero to one
requires a Page Erase or Mass Erase operation.
Byte Programming can be accomplished using the eZ8 CPU’s LDC or LDCI instructions.
Refer to the eZ8 CPU User Manual for a description of the LDC and LDCI instructions.
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While the Flash Controller programs the Flash memory, the eZ8 CPU idles but the system
clock and on-chip peripherals continue to operate. Interrupts that occur when a Program-
ming operation is in progress are serviced once the Programming operation is complete.
To exit Programming mode and lock the Flash Controller, write 00Hto the Flash Control
register.
User code cannot program Flash Memory on a page that lies in a protected sector. When
user code writes memory locations, only addresses located in the unlocked page are pro-
grammed. Memory writes outside of the unlocked page are ignored.
Caution:
Each memory location must not be programmed more than twice before an
erase occurs.
The proper steps to program the Flash from user code are:
1. Write 00Hto the Flash Control register to reset the Flash Controller.
2. Write the page of memory to be programmed to the Page Select register.
3. Write the first unlock command 73Hto the Flash Control register.
4. Write the second unlock command 8CHto the Flash Control register.
5. Re-write the page written in step 2 to the Page Select register.
6. Write Program Memory using LDC or LDCI instructions to program the Flash.
7. Repeat step 6 to program additional memory locations on the same page.
8. Write 00Hto the Flash Control register to lock the Flash Controller.
Page Erase
The Flash memory can be erased one page (512 bytes) at a time. Page Erasing the Flash
memory sets all bytes in that page to the value FFH. The Page Select register identifies the
page to be erased. While the Flash Controller executes the Page Erase operation, the eZ8
CPU idles but the system clock and on-chip peripherals continue to operate. The eZ8 CPU
resumes operation after the Page Erase operation completes. Interrupts that occur when
the Page Erase operation is in progress are serviced once the Page Erase operation is com-
plete. When the Page Erase operation is complete, the Flash Controller returns to its
locked state. Only pages located in unprotected sectors can be erased.
The proper steps to perform a Page Erase operation are:
1. Write 00Hto the Flash Control register to reset the Flash Controller.
2. Write the page to be erased to the Page Select register.
3. Write the first unlock command 73Hto the Flash Control register.
4. Write the second unlock command 8CHto the Flash Control register.
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5. Re-write the page written in step 2 to the Page Select register.
6. Write the Page Erase command 95Hto the Flash Control register.
Mass Erase
The Flash memory cannot be Mass Erased by user code.
Flash Controller Bypass
The Flash Controller can be bypassed and the control signals for the Flash memory
brought out to the GPIO pins. Bypassing the Flash Controller allows faster Programming
algorithms by controlling the Flash programming signals directly.
Flash Controller Bypass is recommended for gang programming applications and large
volume customers who do not require in-circuit programming of the Flash memory.
Refer to the document entitled Third-Party Flash Programming Support for Z8 Encore!®
for more information on bypassing the Flash Controller. This document is available for
download at www.zilog.com.
Flash Controller Behavior in Debug Mode
The following changes in behavior of the Flash Controller occur when the Flash Control-
ler is accessed using the On-Chip Debugger:
•
•
•
The Flash Write Protect option bit is ignored.
The Flash Sector Protect register is ignored for programming and erase operations.
Programming operations are not limited to the page selected in the Page Select
register.
•
•
Bits in the Flash Sector Protect register can be written to one or zero.
The second write of the Page Select register to unlock the Flash Controller is not
necessary.
•
•
The Page Select register can be written when the Flash Controller is unlocked.
The Mass Erase command is enabled through the Flash Control register.
For security reasons, flash controller allows only a single page to be
opened for write/erase. When writing multiple flash pages, the flash con-
troller must go through the unlock sequence again to select another page.
Caution:
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Flash Control Register Definitions
Flash Control Register
The Flash Control register (Table 91) unlocks the Flash Controller for programming and
erase operations, or to select the Flash Sector Protect register.
The Write-only Flash Control Register shares its Register File address with the Read-only
Flash Status Register.
Table 91. Flash Control Register (FCTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
FCMD
0
W
FF8H
ADDR
FCMD—Flash Command
73H = First unlock command.
8CH = Second unlock command.
95H = Page erase command.
63H = Mass erase command
5EH = Flash Sector Protect register select.
* All other commands, or any command out of sequence, lock the Flash Controller.
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Flash Status Register
The Flash Status register (Table 92) indicates the current state of the Flash Controller. This
register can be read at any time. The Read-only Flash Status Register shares its Register
File address with the Write-only Flash Control Register.
Table 92. Flash Status Register (FSTAT)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
Reserved
FSTAT
0
R
FF8H
ADDR
Reserved
These bits are reserved and must be 0.
FSTAT—Flash Controller Status
00_0000 = Flash Controller locked
00_0001 = First unlock command received
00_0010 = Second unlock command received
00_0011 = Flash Controller unlocked
00_0100 = Flash Sector Protect register selected
00_1xxx = Program operation in progress
01_0xxx = Page erase operation in progress
10_0xxx = Mass erase operation in progress
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Page Select Register
The Page Select (FPS) register (Table 93) selects one of the 128 available Flash memory
pages to be erased or programmed. Each Flash Page contains 512 bytes of Flash memory.
During a Page Erase operation, all Flash memory locations with the 7 most significant bits
of the address given by the PAGE field are erased to FFH.
The Page Select register shares its Register File address with the Flash Sector Protect Reg-
ister. The Page Select register cannot be accessed when the Flash Sector Protect register is
enabled.
Table 93. Page Select Register (FPS)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
INFO_EN
PAGE
0
R/W
FF9H
ADDR
INFO_EN—Information Area Enable
0 = Information Area is not selected.
1 = Information Area is selected. The Information area is mapped into the Program Mem-
ory address space at addresses FE00Hthrough FFFFH.
PAGE—Page Select
This 7-bit field selects the Flash memory page for Programming and Page Erase opera-
tions. Program Memory Address[15:9] = PAGE[6:0].
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Flash Sector Protect Register
The Flash Sector Protect register (Table 94) protects Flash memory sectors from being
programmed or erased from user code. The Flash Sector Protect register shares its Regis-
ter File address with the Page Select register. The Flash Sector protect register can be
accessed only after writing the Flash Control register with 5EH.
User code can only write bits in this register to 1 (bits cannot be cleared to 0 by user code).
Table 94. Flash Sector Protect Register (FPROT)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
SECT7
SECT6
SECT5
SECT4
SECT3
SECT2
SECT1
SECT0
0
R/W1
FF9H
ADDR
R/W1 = Register is accessible for Read operations. Register can be written to 1 only (via user code).
SECTn—Sector Protect
0 = Sector n can be programmed or erased from user code.
1 = Sector n is protected and cannot be programmed or erased from user code.
* User code can only write bits from 0 to 1.
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Flash Frequency High and Low Byte Registers
The Flash Frequency High and Low Byte registers (Tables 95 and 96) combine to form a
16-bit value, FFREQ, to control timing for Flash program and erase operations. The 16-bit
Flash Frequency registers must be written with the system clock frequency in KHz for
Program and Erase operations. Calculate the Flash Frequency value using the following
equation:
System Clock Frequency
---------------------------------------------------------------
FFREQ[15:0] = {FFREQH[7:0],FFREQL[7:0]} =
1000
Caution:
Flash programming and erasure is not supported for system clock frequen-
cies below 20KHz, above 20MHz, or outside of the valid operating fre-
quency range for the device. The Flash Frequency High and Low Byte
registers must be loaded with the correct value to insure proper program
and erase times.
Table 95. Flash Frequency High Byte Register (FFREQH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
FFREQH
0
R/W
FFAH
ADDR
Table 96. Flash Frequency Low Byte Register (FFREQL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
FFREQL
0
R/W
FFBH
ADDR
FFREQH and FFREQL—Flash Frequency High and Low Bytes
These 2 bytes, {FFREQH[7:0], FFREQL[7:0]}, contain the 16-bit Flash Frequency value.
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Read-Only Memory
The products in the 64K Series feature up to 64KB (65,536 bytes) of non-volatile read-
only memory (ROM). The ROM can be accessed in-circuit by either user code or through
the On-Chip Debugger.
Table 97 describes the ROM configuration for each device in the 64K Series.
®
Table 97. Z8 Encore! 64K Series Memory Configurations
Part Number
Z8R162x
Z8R242x
Z8R322x
Z8R482x
Z8R642x
ROM Size (KB) Program Memory Addresses
16 (16,384)
24 (24,576)
32 (32,768)
48 (49,152)
64 (65,536)
0000H - 3FFFH
0000H - 5FFFH
0000H - 7FFFH
0000H - BFFFH
0000H - FFFFH
Information Area
Table 98 describes the 64K Series Information Area. This 512-byte Information Area is
accessed by setting bit 7 of the Page Select Register to 1. When access is enabled, the
Information Area is mapped into the Program Memory address space and overlays the 512
bytes at addresses FE00Hto FFFFH. When the Information Area access is enabled, all
reads from these Program Memory addresses return the Information Area data rather than
the Program Memory data.
®
Table 98. Z8 Encore! 64K Series ROM Information Area Map
Program Memory Address (Hex) Function
FE00H-FE3FH
FE40H-FE53H
Reserved
Part Number
20-character ASCII alphanumeric code
Left justified and filled with zeros
FE54H-FFFH
Reserved
ROM Code Protection Against External Access
The user code contained within the ROM can be protected against external access via the
On-Chip Debugger. Programming the Read Protect (RP) Option Bit prevents reading of
the user code through the On-Chip Debugger. The integrity of the ROM contents can still
be verified by using the On-Chip Debugger’s Read Program Memory CRC command.
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Refer to the Option Bits chapter and the On-Chip Debugger chapter for more informa-
tion on Read Protection and the Read Program Memory CRC command.
ROM Control Register Definitions
Page Select Register
The Page Select register enables access to the Information Area data.
Table 99. Page Select Register (RPS)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
INFO_EN
Reserved
0
R/W
FF9H
ADDR
INFO_EN—Information Area Enable
0 = Information Area access is disabled.
1 = Information Area access is enabled. The 512 byte Information area is mapped into the
Program Memory address space at addresses FE00Hthrough FFFFH.
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Option Bits
Overview
Option Bits allow user configuration of certain aspects of the 64K Series operation. The
feature configuration data is stored in the Program Memory and read during Reset. The
features available for control via the Option Bits are:
•
•
•
•
Watch-Dog Timer time-out response selection–interrupt or Reset.
Watch-Dog Timer enabled at Reset.
The ability to prevent unwanted read access to user code in Program Memory.
The ability to prevent accidental programming and erasure of the user code in
Program Memory.
•
•
Voltage Brown-Out configuration-always enabled or disabled during STOP mode to
reduce STOP mode power consumption.
Oscillator mode selection-for high, medium, and low power crystal oscillators, or
external RC oscillator.
Operation
Option Bit Configuration By Reset
Each time the Option Bits are programmed or erased, the device must be Reset for the
change to take place. During any reset operation (System Reset, Reset, or STOP Mode
Recovery), the Option Bits are automatically read from the Program Memory and written
to Option Configuration registers. The Option Configuration registers control operation of
the devices within the 64K Series. Option Bit control is established before the device exits
Reset and the eZ8 CPU begins code execution. The Option Configuration registers are not
part of the Register File and are not accessible for read or write access.
Option Bit Address Space
The first two bytes of Program Memory at addresses 0000H(Table 100 and 101)and
0001H(Table 102) are reserved for the user Option Bits. Table 100 shows the option bits
for Z8 Encore! 64K Series Flash devices. Table 101 shows the same information for the
64K Series ROM devices. The byte at Program Memory address 0000Hconfigures user
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options. The byte at Program Memory address 0001His reserved for future use and must
remain unprogrammed.
Program Memory Address 0000H
Table 100. Flash Option Bits At Program Memory Address 0000H
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
WDT_RES WDT_AO
OSC_SEL[1:0]
VBO_AO
RP
Reserved
FWP
U
R/W
Program Memory 0000H
ADDR
Note: U = Unchanged by Reset. R/W = Read/Write.
Table 101. ROM Option Bits At Program Memory Address 0000H
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
WDT_RES WDT_AO
OSC_SEL[1:0]
VBO_AO
RP
Reserved
U
R/W
Program Memory 0000H
ADDR
Note: U = Unchanged by Reset. R/W = Read/Write.
WDT_RES—Watch-Dog Timer Reset
0 = Watch-Dog Timer time-out generates an interrupt request. Interrupts must be globally
enabled for the eZ8 CPU to acknowledge the interrupt request.
1 = Watch-Dog Timer time-out causes a Short Reset. This setting is the default for unpro-
grammed (erased) Flash.
WDT_AO—Watch-Dog Timer Always On
0 = Watch-Dog Timer is automatically enabled upon application of system power. Watch-
Dog Timer can not be disabled except during STOP Mode (if configured to power down
during STOP Mode).
1 = Watch-Dog Timer is enabled upon execution of the WDT instruction. Once enabled,
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the Watch-Dog Timer can only be disabled by a Reset or STOP Mode Recovery. This set-
ting is the default for unprogrammed (erased) Flash.
OSC_SEL[1:0]—Oscillator Mode Selection
00 = On-chip oscillator configured for use with external RC networks (<4MHz).
01 = Minimum power for use with very low frequency crystals (32KHz to 1.0MHz).
10 = Medium power for use with medium frequency crystals or ceramic resonators
(0.5MHz to 10.0MHz).
11 = Maximum power for use with high frequency crystals (8.0MHz to 20.0MHz). This
setting is the default for unprogrammed (erased) Flash.
VBO_AO—Voltage Brown-Out Protection Always On
0 = Voltage Brown-Out Protection is disabled in STOP mode to reduce total power con-
sumption.
1 = Voltage Brown-Out Protection is always enabled including during STOP mode. This
setting is the default for unprogrammed (erased) Flash.
RP—Read Protect
0 = User program code is inaccessible. Limited control features are available through the
On-Chip Debugger.
1 = User program code is accessible. All On-Chip Debugger commands are enabled. This
setting is the default for unprogrammed (erased) Flash.
Reserved
These Option Bits are reserved for future use and must always be 1.This setting is the
default for unprogrammed (erased) Flash.
FWP—Flash Write Protect (Flash version only)
FWP Description
0
Programming, Page Erase, and Mass Erase through User Code is disabled. Mass Erase
is available through the On-Chip Debugger.
1
Programming, and Page Erase are enabled for all of Flash Program Memory.
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Program Memory Address 0001H
Table 102. Options Bits at Program Memory Address 0001H
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
Reserved
U
R/W
Program Memory 0001H
ADDR
Note: U = Unchanged by Reset. R = Read-Only. R/W = Read/Write.
Reserved
These Option Bits are reserved for future use and must always be 1. This setting is the
default for unprogrammed (erased) Flash.
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On-Chip Debugger
Overview
The 64K Series products contain an integrated On-Chip Debugger (OCD) that provides
advanced debugging features including:
•
•
•
•
Reading and writing of the Register File
Reading and writing of Program and Data Memory
Setting of Breakpoints
Execution of eZ8 CPU instructions
Architecture
The On-Chip Debugger consists of four primary functional blocks: transmitter, receiver,
auto-baud generator, and debug controller. Figure 36 illustrates the architecture of the On-
Chip Debugger
System
Clock
Auto-Baud
Detector/Generator
eZ8 CPU
Control
Transmitter
Receiver
Debug Controller
DBG
Pin
Figure 36. On-Chip Debugger Block Diagram
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Operation
OCD Interface
The On-Chip Debugger uses the DBG pin for communication with an external host. This
one-pin interface is a bi-directional open-drain interface that transmits and receives data.
Data transmission is half-duplex, in that transmit and receive cannot occur simultaneously.
The serial data on the DBG pin is sent using the standard asynchronous data format
defined in RS-232. This pin can interface the 64K Series products to the serial port of a
host PC using minimal external hardware.Two different methods for connecting the DBG
pin to an RS-232 interface are depicted in Figures 37 and 38.
Caution:
For operation of the On-Chip Debugger, all power pins (VDD and AVDD)
must be supplied with power, and all ground pins (VSS and AVSS) must be
properly grounded.
The DBG pin is open-drain and must always be connected to VDD through
an external pull-up resistor to ensure proper operation.
V
DD
RS-232
Transceiver
10K Ohm
DBG Pin
Diode
RS-232 TX
RS-232 RX
Figure 37. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (1)
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V
DD
RS-232
Transceiver
10K Ohm
DBG Pin
Open-Drain
Buffer
RS-232 TX
RS-232 RX
Figure 38. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2)
Debug Mode
The operating characteristics of the 64K Series devices in DEBUG mode are:
•
The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to
execute specific instructions.
•
•
•
•
The system clock operates unless in STOP mode.
All enabled on-chip peripherals operate unless in STOP mode.
Automatically exits HALT mode.
Constantly refreshes the Watch-Dog Timer, if enabled.
Entering Debug Mode
The device enters DEBUG mode following any of the following operations:
•
•
•
Writing the DBGMODEbit in the OCD Control Register to 1 using the OCD interface.
eZ8 CPU execution of a BRK (Breakpoint) instruction (when enabled).
If the DBG pin is Low when the device exits Reset, the On-Chip Debugger
automatically puts the device into DEBUG mode.
Exiting Debug Mode
The device exits DEBUG mode following any of the following operations:
•
•
•
Clearing the DBGMODEbit in the OCD Control Register to 0.
Power-on reset
Voltage Brown Out reset
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•
•
Asserting the RESET pin Low to initiate a Reset.
Driving the DBG pin Low while the device is in STOP mode initiates a System Reset.
OCD Data Format
The OCD interface uses the asynchronous data format defined for RS-232. Each character
is transmitted as 1 Start bit, 8 data bits (least-significant bit first), and 1 Stop bit
(Figure 39).
START
D0
D1
D2
D3
D4
D5
D6
D7
STOP
Figure 39. OCD Data Format
OCD Auto-Baud Detector/Generator
To run over a range of baud rates (bits per second) with various system clock frequencies,
the On-Chip Debugger has an Auto-Baud Detector/Generator. After a reset, the OCD is
idle until it receives data. The OCD requires that the first character sent from the host is
the character 80H. The character 80Hhas eight continuous bits Low (one Start bit plus 7
data bits). The Auto-Baud Detector measures this period and sets the OCD Baud Rate
Generator accordingly.
The Auto-Baud Detector/Generator is clocked by the system clock. The minimum baud
rate is the system clock frequency divided by 512. For optimal operation, the maximum
recommended baud rate is the system clock frequency divided by 8. The theoretical maxi-
mum baud rate is the system clock frequency divided by 4. This theoretical maximum is
possible for low noise designs with clean signals. Table 103 lists minimum and recom-
mended maximum baud rates for sample crystal frequencies.
Table 103. OCD Baud-Rate Limits
System Clock Frequency Recommended Maximum Baud Rate
Minimum Baud Rate
(kbits/s)
(MHz)
(kbits/s)
20.0
1.0
2500
39.1
1.96
125.0
0.032768 (32KHz)
4.096
0.064
If the OCD receives a Serial Break (nine or more continuous bits Low) the Auto-Baud
Detector/Generator resets. The Auto-Baud Detector/Generator can then be reconfigured
by sending 80H.
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OCD Serial Errors
The On-Chip Debugger can detect any of the following error conditions on the DBG pin:
•
•
•
Serial Break (a minimum of nine continuous bits Low)
Framing Error (received Stop bit is Low)
Transmit Collision (OCD and host simultaneous transmission detected by the OCD)
When the OCD detects one of these errors, it aborts any command currently in progress,
transmits a Serial Break 4096 system clock cycles long back to the host, and resets the
Auto-Baud Detector/Generator. A Framing Error or Transmit Collision may be caused by
the host sending a Serial Break to the OCD. Because of the open-drain nature of the inter-
face, returning a Serial Break break back to the host only extends the length of the Serial
Break if the host releases the Serial Break early.
The host transmits a Serial Break on the DBG pin when first connecting to the 64K Series
devices or when recovering from an error. A Serial Break from the host resets the Auto-
Baud Generator/Detector but does not reset the OCD Control register. A Serial Break
leaves the device in DEBUG mode if that is the current mode. The OCD is held in Reset
until the end of the Serial Break when the DBG pin returns High. Because of the open-
drain nature of the DBG pin, the host can send a Serial Break to the OCD even if the OCD
is transmitting a character.
Breakpoints
Execution Breakpoints are generated using the BRK instruction (opcode 00H). When the
eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If Breakpoints are
enabled, the OCD idles the eZ8 CPU and enters DEBUG mode. If Breakpoints are not
enabled, the OCD ignores the BRK signal and the BRK instruction operates as an NOP.
If breakpoints are enabled, the OCD can be configured to automatically enter DEBUG
mode, or to loop on the break instruction. If the OCD is configured to loop on the BRK
instruction, then the CPU is still enabled to service DMA and interrupt requests.
The loop on BRK instruction can be used to service interrupts in the background. For
interrupts to be serviced in the background, there cannot be any breakpoints in the inter-
rupt service routine. Otherwise, the CPU stops on the breakpoint in the interrupt routine.
For interrupts to be serviced in the background, interrupts must also be enabled. Debug-
ging software should not automatically enable interrupts when using this feature, since
interrupts are typically disabled during critical sections of code where interrupts should
not occur (such as adjusting the stack pointer or modifying shared data).
Software can poll the IDLE bit of the OCDSTAT register to determine if the OCD is loop-
ing on a BRK instruction. When software wants to stop the CPU on the BRK instruction it
is looping on, software should not set the DBGMODE bit of the OCDCTL register. The
CPU may have vectored to and be in the middle of an interrupt service routine when this
bit gets set. Instead, software must clear the BRKLP bit. This action allows the CPU to
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finish the interrupt service routine it may be in and return the BRK instruction. When the
CPU returns to the BRK instruction it was previously looping on, it automatically sets the
DBGMODE bit and enter DEBUG mode.
Software detects that the majority of the OCD commands are still disabled when the eZ8
CPU is looping on a BRK instruction. The eZ8 CPU must be stopped and the part must be
in DEBUG mode before these commands can be issued.
Breakpoints in Flash Memory
The BRK instruction is opcode 00H, which corresponds to the fully programmed state of a
byte in Flash memory. To implement a Breakpoint, write 00Hto the desired address, over-
writing the current instruction. To remove a Breakpoint, the corresponding page of Flash
memory must be erased and reprogrammed with the original data.
On-Chip Debugger Commands
The host communicates to the On-Chip Debugger by sending OCD commands using the
DBG interface. During normal operation, only a subset of the OCD commands are avail-
able. In DEBUG mode, all OCD commands become available unless the user code and
control registers are protected by programming the Read Protect Option Bit (RP). The
Read Protect Option Bit prevents the code in memory from being read out of the 64K
Series products. When this option is enabled, several of the OCD commands are disabled.
Table 104 contains a summary of the On-Chip Debugger commands. Each OCD com-
mand is described in further detail in the bulleted list following Table 104. Table 104 indi-
cates those commands that operate when the device is not in DEBUG mode (normal
operation) and those commands that are disabled by programming the Read Protect
Option Bit.
Table 104. On-Chip Debugger Commands
Enabled when NOT
Command Byte in DEBUG mode?
Disabled by
Read Protect Option Bit
Debug Command
Read OCD Revision
00H
02H
03H
04H
05H
06H
07H
Yes
Yes
-
-
Read OCD Status Register
Read Runtime Counter
Write OCD Control Register
Read OCD Control Register
Write Program Counter
Read Program Counter
-
-
Yes
Yes
-
Cannot clear DBGMODEbit
-
Disabled
Disabled
-
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Table 104. On-Chip Debugger Commands (Continued)
Enabled when NOT
Command Byte in DEBUG mode?
Disabled by
Read Protect Option Bit
Debug Command
Write Register
08H
-
Only writes of the Flash Memory Control
registers are allowed. Additionally, only the
Mass Erase command is allowed to be
written to the Flash Control register.
Read Register
09H
0AH
-
-
-
-
-
-
-
-
-
-
-
Disabled-
Disabled
Disabled
Disabled
Disabled
-
Write Program Memory
Read Program Memory
Write Data Memory
Read Data Memory
Read Program Memory CRC
Reserved
0BH
0CH
0DH
0EH
0FH
-
Step Instruction
10H
Disabled
Disabled
Disabled
-
Stuff Instruction
11H
Execute Instruction
Reserved
12H
13H - FFH
In the following bulleted list of OCD Commands, data and commands sent from the host
to the On-Chip Debugger are identified by ’DBG ← Command/Data’. Data sent from the
On-Chip Debugger back to the host is identified by ’DBG → Data’
•
Read OCD Revision (00H)—The Read OCD Revision command determines the
version of the On-Chip Debugger. If OCD commands are added, removed, or
changed, this revision number changes.
DBG ← 00H
DBG → OCDREV[15:8] (Major revision number)
DBG → OCDREV[7:0] (Minor revision number)
•
•
Read OCD Status Register (02H)—The Read OCD Status Register command reads
the OCDSTAT register.
DBG ← 02H
DBG → OCDSTAT[7:0]
Write OCD Control Register (04H)—The Write OCD Control Register command
writes the data that follows to the OCDCTL register. When the Read Protect Option
Bit is enabled, the DBGMODEbit (OCDCTL[7]) can only be set to 1, it cannot be
cleared to 0 and the only method of putting the device back into normal operating
mode is to reset the device.
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DBG ← 04H
DBG ← OCDCTL[7:0]
•
•
Read OCD Control Register (05H)—The Read OCD Control Register command
reads the value of the OCDCTL register.
DBG ← 05H
DBG → OCDCTL[7:0]
Write Program Counter (06H)—The Write Program Counter command writes the
data that follows to the eZ8 CPU’s Program Counter (PC). If the device is not in
DEBUG mode or if the Read Protect Option Bit is enabled, the Program Counter (PC)
values are discarded.
DBG ← 06H
DBG ← ProgramCounter[15:8]
DBG ← ProgramCounter[7:0]
•
•
Read Program Counter (07H)—The Read Program Counter command reads the
value in the eZ8 CPU’s Program Counter (PC). If the device is not in DEBUG mode
or if the Read Protect Option Bit is enabled, this command returns FFFFH.
DBG ← 07H
DBG → ProgramCounter[15:8]
DBG → ProgramCounter[7:0]
Write Register (08H)—The Write Register command writes data to the Register File.
Data can be written 1-256 bytes at a time (256 bytes can be written by setting size to
zero). If the device is not in DEBUG mode, the address and data values are discarded.
If the Read Protect Option Bit is enabled, then only writes to the Flash Control
Registers are allowed and all other register write data values are discarded.
DBG ← 08H
DBG ← {4’h0,Register Address[11:8]}
DBG ← Register Address[7:0]
DBG ← Size[7:0]
DBG ← 1-256 data bytes
•
•
Read Register (09H)—The Read Register command reads data from the Register
File. Data can be read 1-256 bytes at a time (256 bytes can be read by setting size to
zero). If the device is not in DEBUG mode or if the Read Protect Option Bit is
enabled, this command returns FFHfor all the data values.
DBG ← 09H
DBG ← {4’h0,Register Address[11:8]
DBG ← Register Address[7:0]
DBG ← Size[7:0]
DBG → 1-256 data bytes
Flash Version Only: Write Program Memory (0AH)—The Write Program Memory
command writes data to Program Memory. This command is equivalent to the LDC
and LDCI instructions. Data can be written 1-65536 bytes at a time (65536 bytes can
be written by setting size to zero). The on-chip Flash Controller must be written to and
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unlocked for the programming operation to occur. If the Flash Controller is not
unlocked, the data is discarded. If the device is not in DEBUG mode or if the Read
Protect Option Bit is enabled, the data is discarded. This command has no affect on
ROM parts.
DBG ← 0AH
DBG ← Program Memory Address[15:8]
DBG ← Program Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG ← 1-65536 data bytes
•
•
•
Read Program Memory (0BH)—The Read Program Memory command reads data
from Program Memory. This command is equivalent to the LDC and LDCI
instructions. Data can be read 1-65536 bytes at a time (65536 bytes can be read by
setting size to zero). If the device is not in DEBUG mode or if the Read Protect Option
Bit is enabled, this command returns FFHfor the data.
DBG ← 0BH
DBG ← Program Memory Address[15:8]
DBG ← Program Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG → 1-65536 data bytes
Write Data Memory (0CH)—The Write Data Memory command writes data to Data
Memory. This command is equivalent to the LDE and LDEI instructions. Data can be
written 1-65536 bytes at a time (65536 bytes can be written by setting size to zero). If
the device is not in DEBUG mode or if the Read Protect Option Bit is enabled, the
data is discarded.
DBG ← 0CH
DBG ← Data Memory Address[15:8]
DBG ← Data Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG ← 1-65536 data bytes
Read Data Memory (0DH)—The Read Data Memory command reads from Data
Memory. This command is equivalent to the LDE and LDEI instructions. Data can be
read 1-65536 bytes at a time (65536 bytes can be read by setting size to zero). If the
device is not in DEBUG mode, this command returns FFHfor the data.
DBG ← 0DH
DBG ← Data Memory Address[15:8]
DBG ← Data Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG → 1-65536 data bytes
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•
Read Program Memory CRC (0EH)—The Read Program Memory CRC command
computes and returns the CRC (cyclic redundancy check) of Program Memory using
the 16-bit CRC-CCITT polynomial. If the device is not in DEBUG mode, this
command returns FFFFHfor the CRC value. Unlike most other OCD Read
commands, there is a delay from issuing of the command until the OCD returns the
data. The OCD reads the Program Memory, calculates the CRC value, and returns the
result. The delay is a function of the Program Memory size and is approximately equal
to the system clock period multiplied by the number of bytes in the Program Memory.
DBG ← 0EH
DBG → CRC[15:8]
DBG → CRC[7:0]
•
•
Step Instruction (10H)—The Step Instruction command steps one assembly
instruction at the current Program Counter (PC) location. If the device is not in
DEBUG mode or the Read Protect Option Bit is enabled, the OCD ignores this
command.
DBG ← 10H
Stuff Instruction (11H)—The Stuff Instruction command steps one assembly
instruction and allows specification of the first byte of the instruction. The remaining
0-4 bytes of the instruction are read from Program Memory. This command is useful
for stepping over instructions where the first byte of the instruction has been
overwritten by a Breakpoint. If the device is not in DEBUG mode or the Read Protect
Option Bit is enabled, the OCD ignores this command.
DBG ← 11H
DBG ← opcode[7:0]
•
Execute Instruction (12H)—The Execute Instruction command allows sending an
entire instruction to be executed to the eZ8 CPU. This command can also step over
Breakpoints. The number of bytes to send for the instruction depends on the opcode. If
the device is not in DEBUG mode or the Read Protect Option Bit is enabled, the OCD
ignores this command
DBG ← 12H
DBG ← 1-5 byte opcode
On-Chip Debugger Control Register Definitions
OCD Control Register
The OCD Control register (Table 105) controls the state of the On-Chip Debugger. This
register enters or exits DEBUG mode and enables the BRK instruction. It can also reset
the Z8F642x familyZ8R642x family device.
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A “reset and stop” function can be achieved by writing 81Hto this register. A “reset and
go” function can be achieved by writing 41Hto this register. If the device is in DEBUG
mode, a “run” function can be implemented by writing 40Hto this register.
Table 105. OCD Control Register (OCDCTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DBGMODE
BRKEN
DBGACK BRKLOOP
Reserved
RST
0
R/W
R
R/W
DBGMODE—Debug Mode
Setting this bit to 1 causes the device to enter DEBUG mode. When in DEBUG mode, the
eZ8 CPU stops fetching new instructions. Clearing this bit causes the eZ8 CPU to start
running again. This bit is automatically set when a BRK instruction is decoded and Break-
points are enabled. If the Read Protect Option Bit is enabled, this bit can only be cleared
by resetting the device, it cannot be written to 0.
0 = The 64K Series device is operating in Normal mode.
1 = The 64K Series device is in DEBUG mode.
BRKEN—Breakpoint Enable
This bit controls the behavior of the BRK instruction (opcode 00H). By default, Break-
points are disabled and the BRK instruction behaves like a NOP. If this bit is set to 1 and a
BRK instruction is decoded, the OCD takes action dependent upon the BRKLOOP bit.
0 = BRK instruction is disabled.
1 = BRK instruction is enabled.
DBGACK—Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, then the OCD sends
an Debug Acknowledge character (FFH) to the host when a Breakpoint occurs.
0 = Debug Acknowledge is disabled.
1 = Debug Acknowledge is enabled.
BRKLOOP—Breakpoint Loop
This bit determines what action the OCD takes when a BRK instruction is decoded if
breakpoints are enabled (BRKEN is 1). If this bit is 0, then the DBGMODE bit is automat-
ically set to 1 and the OCD entered DEBUG mode. If BRKLOOP is set to 1, then the eZ8
CPU loops on the BRK instruction.
0 = BRK instruction sets DBGMODE to 1.
1 = eZ8 CPU loops on BRK instruction.
Reserved
These bits are reserved and must be 0.
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RST—Reset
Setting this bit to 1 resets the 64K Series devices. The devices go through a normal Power-
On Reset sequence with the exception that the On-Chip Debugger is not reset. This bit is
automatically cleared to 0 when the reset finishes.
0 = No effect
1 = Reset the 64K Series device
OCD Status Register
The OCD Status register (Table 106) reports status information about the current state of
the debugger and the system.
Table 106. OCD Status Register (OCDSTAT)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
IDLE
HALT
RPEN
Reserved
0
R
IDLE—CPU idling
This bit is set if the part is in DEBUG mode (DBGMODE is 1), or if a BRK instruction
occurred since the last time OCDCTL was written. This can be used to determine if the
CPU is running or if it is idling.
0 = The eZ8 CPU is running.
1 = The eZ8 CPU is either stopped or looping on a BRK instruction.
HALT—HALT Mode
0 = The device is not in HALT mode.
1 = The device is in HALT mode.
RPEN—Read Protect Option Bit Enabled
0 = The Read Protect Option Bit is disabled (1).
1 = The Read Protect Option Bit is enabled (0), disabling many OCD commands.
Reserved
These bits are always 0.
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On-Chip Oscillator
Overview
The products in the 64K Series feature an on-chip oscillator for use with external crystals
with frequencies from 32KHz to 20MHz. In addition, the oscillator can support external
RC networks with oscillation frequencies up to 4MHz or ceramic resonators with oscilla-
tion frequencies up to 20MHz. This oscillator generates the primary system clock for the
internal eZ8 CPU and the majority of the on-chip peripherals. Alternatively, the XIN input
pin can also accept a CMOS-level clock input signal (32KHz–20MHz). If an external
clock generator is used, the XOUT pin must be left unconnected.
When configured for use with crystal oscillators or external clock drivers, the frequency of
the signal on the XIN input pin determines the frequency of the system clock (that is, no
internal clock divider). In RC operation, the system clock is driven by a clock divider
(divide by 2) to ensure 50% duty cycle.
Operating Modes
The 64K Series products support 4 different oscillator modes:
•
•
•
On-chip oscillator configured for use with external RC networks (<4MHz).
Minimum power for use with very low frequency crystals (32KHz to 1.0MHz).
Medium power for use with medium frequency crystals or ceramic resonators
(0.5MHz to 10.0MHz).
•
Maximum power for use with high frequency crystals or ceramic resonators (8.0MHz
to 20.0MHz).
The oscillator mode is selected through user-programmable Option Bits. Refer to the
Option Bits chapter for information.
Crystal Oscillator Operation
Figure 40 illustrates a recommended configuration for connection with an external funda-
mental-mode, parallel-resonant crystal operating at 20MHz. Recommended 20MHz crys-
tal specifications are provided in Table 107. Resistor R1 is optional and limits total power
dissipation by the crystal. The printed circuit board layout must add no more than 4pF of
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stray capacitance to either the XIN or XOUT pins. If oscillation does not occur, reduce the
values of capacitors C1 and C2 to decrease loading.
On-Chip Oscillator
XIN
XOUT
R1 = 220
Ω
Crystal
C1 = 22pF
C2 = 22pF
Figure 40. Recommended 20MHz Crystal Oscillator Configuration
Table 107. Recommended Crystal Oscillator Specifications (20MHz Operation)
Parameter
Frequency
Resonance
Mode
Value
Units
Comments
20
MHz
Parallel
Fundamental
Series Resistance (R )
25
20
7
Ω
pF
Maximum
Maximum
Maximum
Maximum
S
Load Capacitance (C )
L
Shunt Capacitance (C )
pF
0
Drive Level
1
mW
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Oscillator Operation with an External RC Network
The External RC oscillator mode is applicable to timing insensitive applications.
Figure 41 illustrates a recommended configuration for connection with an external resis-
tor-capacitor (RC) network.
V
DD
R
C
X
IN
Figure 41. Connecting the On-Chip Oscillator to an External RC Network
An external resistance value of 45kΩ is recommended for oscillator operation with an
external RC network. The minimum resistance value to ensure operation is 40kΩ. The
typical oscillator frequency can be estimated from the values of the resistor (R in kΩ) and
capacitor (C in pF) elements using the following equation:
1×106
(0.4 × R × C) + (4 × C)
--------------------------------------------------------
Oscillator Frequency (kHz) =
Figure 42 illustrates the typical (3.3V and 250C) oscillator frequency as a function of the
capacitor (C in pF) employed in the RC network assuming a 45kΩ external resistor. For
very small values of C, the parasitic capacitance of the oscillator XIN pin and the printed
circuit board should be included in the estimation of the oscillator frequency.
It is possible to operate the RC oscillator using only the parasitic capacitance of the pack-
age and printed circuit board. To minimize sensitivity to external parasitics, external
capacitance values in excess of 20pF are recommended.
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4000
3750
3500
3250
3000
2750
2500
2250
2000
1750
1500
1250
1000
750
500
250
0
0
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500
C (pF)
Figure 42. Typical RC Oscillator Frequency as a Function of the External Capacitance with a 45kΩ Resistor
Caution:
When using the external RC oscillator mode, the oscillator may stop oscil-
lating if the power supply drops below 2.7V, but before the power supply
drops to the voltage brown-out threshold. The oscillator will resume oscil-
lation as soon as the supply voltage exceeds 2.7V.
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Electrical Characteristics
All data in this chapter is pre-qualification and pre-characterization and is subject to
change.
Absolute Maximum Ratings
Stresses greater than those listed in Table 108 may cause permanent damage to the device.
These ratings are stress ratings only. Operation of the device at any condition outside those
indicated in the operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
For improved reliability, unused inputs must be tied to one of the supply voltages (VDD or
VSS).
Table 108. Absolute Maximum Ratings
Parameter
Minimum Maximum
Units
C
Notes
Ambient temperature under bias
Storage temperature
-40
–65
–0.3
–0.3
–5
+105
+150
+5.5
+3.6
+5
C
Voltage on any pin with respect to V
V
1
SS
Voltage on V pin with respect to V
V
DD
SS
Maximum current on input and/or inactive output pin
Maximum output current from active output pin
80-Pin QFP Maximum Ratings at -40°C to 70°C
Total power dissipation
µA
mA
-25
+25
550
150
mW
mA
Maximum current into V or out of V
DD
SS
80-Pin QFP Maximum Ratings at 70°C to 105°C
Total power dissipation
200
56
mW
mA
Maximum current into V or out of V
DD
SS
Notes:
1. This voltage applies to all pins except the following: VDD, AVDD, pins supporting analog input (Ports B and H),
RESET, and where noted otherwise.
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Table 108. Absolute Maximum Ratings (Continued)
Parameter
Minimum Maximum
Units
Notes
68-Pin PLCC Maximum Ratings at -40°C to 70°C
Total power dissipation
1000
275
mW
mA
Maximum current into V or out of V
DD
SS
0
0
68-Pin PLCC Maximum Ratings at 70 C to 105 C
Total power dissipation
500
140
mW
mA
Maximum current into V or out of V
DD
SS
64-Pin LQFP Maximum Ratings at -40°C to 70°C
Total power dissipation
1000
275
mW
mA
Maximum current into V or out of V
DD
SS
0
0
64-Pin LQFP Maximum Ratings at 70 C to 105 C
Total power dissipation
540
150
mW
mA
Maximum current into V or out of V
DD
SS
44-Pin PLCC Maximum Ratings at -40°C to 70°C
Total power dissipation
750
200
mW
mA
Maximum current into V or out of V
DD
SS
0
0
44-Pin PLCC Maximum Ratings at 70 C to 105 C
Total power dissipation
295
83
mW
mA
Maximum current into V or out of V
DD
SS
44-pin LQFP Maximum Ratings at -40°C to 70°C
Total power dissipation
750
200
mW
mA
Maximum current into V or out of V
DD
SS
0
0
44-pin LQFP Maximum Ratings at 70 C to 105 C
Total power dissipation
410
114
mW
mA
Maximum current into V or out of V
DD
SS
Notes:
1. This voltage applies to all pins except the following: VDD, AVDD, pins supporting analog input (Ports B and H),
RESET, and where noted otherwise.
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213
Table 108. Absolute Maximum Ratings (Continued)
Parameter
Minimum Maximum
Units
Notes
40-pin PDIP Maximum Ratings at -40°C to 70°C
Total power dissipation
1000
275
mW
mA
Maximum current into V or out of V
DD
SS
0
0
40-pin PDIP Maximum Ratings at 70 C to 105 C
Total power dissipation
540
150
mW
mA
Maximum current into V or out of V
DD
SS
Notes:
1. This voltage applies to all pins except the following: VDD, AVDD, pins supporting analog input (Ports B and H),
RESET, and where noted otherwise.
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214
DC Characteristics
Table 109 lists the DC characteristics of the 64K Series products. All voltages are refer-
enced to VSS, the primary system ground.
Table 109. DC Characteristics
0
0
T = -40 C to 105 C
A
Symbol Parameter
Minimum Typical Maximum Units Conditions
V
V
Supply Voltage
3.0
–
–
3.6
V
V
DD
IL1
Low Level Input Voltage
-0.3
0.3*V
For all input pins except RESET,
DBG, XIN
DD
DD
V
V
V
V
V
Low Level Input Voltage
High Level Input Voltage
High Level Input Voltage
High Level Input Voltage
-0.3
–
–
–
–
–
0.2*V
5.5
V
V
V
V
V
For RESET, DBG, and XIN.
Port A, C, D, E, F, and G pins.
Port B and H pins.
IL2
0.7*V
0.7*V
0.8*V
–
IH1
IH2
IH3
OL1
DD
DD
DD
V
V
+0.3
DD
DD
+0.3
RESET, DBG, and XIN pins
Low Level Output Voltage
Standard Drive
0.4
I
= 2mA; VDD = 3.0V
OL
High Output Drive disabled.
I = -2mA; VDD = 3.0V
OH
V
V
High Level Output Voltage
Standard Drive
2.4
–
–
–
–
V
V
OH1
OL2
High Output Drive disabled.
Low Level Output Voltage
High Drive
0.6
I
OL
= 20mA; VDD = 3.3V
High Output Drive enabled
0
0
T = -40 C to +70 C
A
V
V
V
High Level Output Voltage
High Drive
2.4
–
–
–
–
–
0.6
–
V
V
V
V
I
= -20mA; VDD = 3.3V
OH
OH2
OL3
OH3
RAM
High Output Drive enabled;
T = -40 C to +70 C
0
0
A
Low Level Output Voltage
High Drive
I
= 15mA; VDD = 3.3V
OL
High Output Drive enabled;
T = +70 C to +105 C
0
0
A
High Level Output Voltage
High Drive
2.4
I
= 15mA; VDD = 3.3V
OH
High Output Drive enabled;
T = +70 C to +105 C
0
0
A
V
I
RAM Data Retention
Input Leakage Current
0.7
-5
–
–
–
+5
µA V = 3.6V;
DD
IL
1
V
= VDD or VSS
IN
I
Tri-State Leakage Current
GPIO Port Pad Capacitance
XIN Pad Capacitance
-5
–
–
+5
–
µA V = 3.6V
TL
DD
2
2
C
C
8.0
8.0
pF
pF
PAD
XIN
–
–
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215
Table 109. DC Characteristics (Continued)
0
0
T = -40 C to 105 C
A
Symbol Parameter
Minimum Typical Maximum Units Conditions
2
C
XOUT Pad Capacitance
Weak Pull-up Current
–
30
–
9.5
–
pF
XOUT
I
100
10.7
350
11.7
µA V = 3.0 - 3.6V
PU
DD
I
I
I
Active Mode Supply Current
(See Figures 43 and 44)
mA V = 3.3V
DD
DDA
Fsysclk = 20 MHz
–
7.4
3.6
8.4
4.6
mA V = 3.3V
DD
Fsysclk = 10 MHz
Halt Mode Supply Current
(See Figures 45 and 46)
mA V = 3.3V
DDH
DDS
DD
Fsysclk = 20 MHz
–
–
2.2
3.3
mA V = 3.3V
DD
Fsysclk = 10 MHz
Stop Mode Supply Current
(See Figures 47 and 48)
502.7
9.5
621.8
81.7
µA V = 3.3V
DD
VBO and WDT Enabled
µA V = 3.3V
DD
VBO Disabled
WDT Enabled
1
2
This condition excludes all pins that have on-chip pull-ups, when driven Low.
These values are provided for design guidance only and are not tested in production.
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Figure 43 illustrates the typical active mode current consumption while operating at 25ºC
versus the system clock frequency. All GPIO pins are configured as outputs and driven
High.
stics
15
12
9
6
3
0
0
5
10
15
20
System Clock Frequency (MHz)
3.0V
3.3V
3.6V
Figure 43. Typical Active Mode Idd Versus System Clock Frequency
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217
Figure 44 illustrates the maximum active mode current consumption across the full oper-
ating temperature range of the device and versus the system clock frequency. All GPIO
pins are configured as outputs and driven High.
stics
15
12
9
6
3
0
0
5
10
15
20
System Clock Frequency (MHz)
3.0V
3.3V
3.6V
Figure 44. Maximum Active Mode Idd Versus System Clock Frequency
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Figure 45 illustrates the typical current consumption in HALT mode while operating at
25ºC versus the system clock frequency. All GPIO pins are configured as outputs and
driven High.
5
4
3
2
1
0
0
5
10
15
20
System Clock Frequency (MHz)
3.0V
3.3V
3.6V
Figure 45. Typical HALT Mode Idd Versus System Clock Frequency
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219
Figure 45 illustrates the maximum HALT mode current consumption across the full oper-
ating temperature range of the device and versus the system clock frequency. All GPIO
pins are configured as outputs and driven High.
6
5
4
3
2
1
0
0
5
10
15
20
System Clock Frequency (MHz)
3.0V
3.3V
3.6V
Figure 46. Maximum HALT Mode Icc Versus System Clock Frequency
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220
Figure 47 illustrates the maximum current consumption in STOP mode with the VBO and
Watch-Dog Timer enabled versus the power supply voltage. All GPIO pins are configured
as outputs and driven High.
700
650
600
550
500
450
400
3.0
3.2
3.4
3.6
Vdd (V)
-40/105C
0/70C
25C Typical
Figure 47. Maximum STOP Mode Idd with VBO enabled versus Power Supply Voltage
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Figure 48 illustrates the maximum current consumption in STOP mode with the VBO dis-
abled and Watch-Dog Timer enabled versus the power supply voltage. All GPIO pins are
configured as outputs and driven High. Disabling the Watch-Dog Timer and its internal
RC oscillator in STOP mode will provide some additional reduction in STOP mode cur-
rent consumption. This small current reduction would be indistinquishable on the scale of
Figure 48.
100
75
50
25
0
3.0
3.2
3.4
3.6
Vdd (V)
0/70C
-40/+105C
25C Typical
Figure 48. Maximum STOP Mode Idd with VBO Disabled versus Power Supply Voltage
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222
On-Chip Peripheral AC and DC Electrical Characteristics
Table 110. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing
0
0
T = -40 C to 105 C
A
1
Symbol Parameter
Minimum Typical Maximum Units Conditions
V
Power-On Reset Voltage
Threshold
2.40
2.70
2.60
100
2.90
V
V
= V
POR
DD
POR
V
Voltage Brown-Out Reset
Voltage Threshold
2.30
2.85
V
V
= V
VBO
DD
VBO
V
to V
hysteresis
VBO
50
–
–
–
mV
V
POR
Starting V voltage to
V
SS
DD
ensure valid Power-On
Reset.
T
Power-On Reset Analog
Delay
–
–
50
–
–
µs
V
> V
; T
Digital
ANA
DD
POR POR
Reset delay follows T
ANA
T
Power-On Reset Digital
Delay
6.6
ms
66 WDT Oscillator cycles
(10KHz) + 16 System Clock
cycles (20MHz)
POR
T
T
Voltage Brown-Out Pulse
Rejection Period
–
10
–
–
µs
V
Reset.
< V
to generate a
VBO
VBO
DD
Time for VDD to transition
0.10
100
ms
RAMP
from V to V
to ensure
SS
POR
valid Reset
0
1 Data in the typical column is from characterization at 3.3V and 0 C. These values are provided for design guidance
only and are not tested in production.
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223
Table 111. External RC Oscillator Electrical Characteristics and Timing
0
0
T = -40 C to 105 C
A
1
Symbol Parameter
Minimum Typical Maximum Units Conditions
1
V
R
Operating Voltage Range
2.70
40
–
–
V
DD
External Resistance from
XIN to VDD
45
200
kΩ
V
= V
DD VBO
EXT
EXT
OSC
C
External Capacitance from
XIN to VSS
0
–
20
–
1000
4
pF
F
External RC Oscillation
Frequency
MHz
1 When using the external RC oscillator mode, the oscillator may stop oscillating if the power supply drops below
2.7V, but before the power supply drops to the voltage brown-out threshold. The oscillator will resume oscillation as
soon as the supply voltage exceeds 2.7V.
Table 112. Reset and STOP Mode Recovery Pin Timing
0
0
T = -40 C to 105 C
A
Symbol Parameter
Minimum Typical Maximum Units Conditions
T
RESET pin assertion to
initiate a System Reset.
4
–
–
T
Not in STOP Mode.
= System Clock period.
RESET
CLK
T
CLK
T
STOP Mode Recovery pin
Pulse Rejection Period
10
20
40
ns
RESET, DBG, and GPIO pins
configured as SMR sources.
SMR
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Table 113 list the Flash Memory electrical characteristics and timing.
Table 113. Flash Memory Electrical Characteristics and Timing
= 3.0 - 3.6V
V
DD
0
0
T = -40 C to 105 C
A
Parameter
Minimum Typical Maximum Units Notes
Flash Byte Read Time
Flash Byte Program Time
Flash Page Erase Time
Flash Mass Erase Time
50
20
10
200
–
–
–
–
–
–
–
40
–
ns
µs
ms
ms
–
Writes to Single Address Before
Next Erase
2
Flash Row Program Time
–
–
8
ms
Cumulative program time for
single row cannot exceed limit
before next erase. This parameter
is only an issue when bypassing
the Flash Controller.
0
Data Retention
Endurance
100
–
–
–
–
years 25 C
10,000
cycles Program / erase cycles
Table 114 lists the Watch-Dog Timer electrical characteristics and timing.
Table 114. Watch-Dog Timer Electrical Characteristics and Timing
V
= 3.0 - 3.6V
DD
0
0
T = -40 C to 105 C
A
Symbol Parameter
Minimum Typical Maximum Units Conditions
F
WDT Oscillator Frequency
5
–
10
20
5
kHz
WDT
I
WDT Oscillator Current including
internal RC oscillator
< 1
µA
WDT
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Table 115 provides electrical characteristics and timing information for the Analog-to-Digital Converter.
Figure 49 illustrates the input frequency response of the ADC.
Table 115. Analog-to-Digital Converter Electrical Characteristics and Timing
V
= 3.0 - 3.6V
DD
0
0
T = -40 C to 105 C
A
Symbol Parameter
Minimum Typical Maximum Units Conditions
Resolution
10
–
–
–
bits External V
= 3.0V;
REF
Differential Nonlinearity
-0.25
0.25
lsb
Guaranteed by design
(DNL)
Integral Nonlinearity (INL)
DC Offset Error
DC Offset Error
-2.0
-35
-50
–
–
–
2.0
25
25
lsb
External V = 3.0V
REF
mV
mV 44-pin LQFP, 44-pin
PLCC, and 68-pin PLCC
packages.
V
Internal Reference Voltage
1.9
–
2.0
78
2.4
–
V
V
= 3.0 - 3.6V
DD
REF
0
0
T = -40 C to 105 C
A
VC
Voltage Coefficient of
Internal Reference Voltage
mV/V
V
variation as a
REF
REF
REF
function of AVDD.
0
TC
Temperature Coefficient of
Internal Reference Voltage
–
1
–
mV/ C
Single-Shot Conversion
Period
–
5129
256
–
cycles System clock cycles
cycles System clock cycles
Continuous Conversion
Period
–
–
R
Analog Source Impedance
Input Impedance
–
–
150
Ω
kΩ
V
Recommended
S
Zin
V
150
External Reference Voltage
AVDD
AVDD <= VDD. When
using an external reference
voltage, decoupling
capacitance should be
placed from VREF to
AVSS.
REF
I
Current draw into VREF pin
when driving with external
source.
25.0
40.0
µA
REF
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Z8 Encore!® 64K Series
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226
ADC Magnitude Transfer Function (Linear Scale)
1
0.9
0.8
-3 dB
0.7
0.6
0.5
0.4
-6 dB
0.3
0.2
0.1
0
0
5
10
15
20
25
30
Frequency (kHz)
Figure 49. Analog-to-Digital Converter Frequency Response
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227
AC Characteristics
The section provides information on the AC characteristics and timing. All AC timing
information assumes a standard load of 50pF on all outputs. Table 116 lists the 64K Series
AC characteristics and timing.
Table 116. AC Characteristics
V
= 3.0 - 3.6V
DD
0
0
T = -40 C to 105 C
A
Symbol Parameter
Minimum Maximum Units Conditions
F
F
System Clock Frequency
–
20.0
20.0
MHz Read-only from Flash memory.
sysclk
XTAL
0.032768
MHz Program or erasure of the Flash
memory.
Crystal Oscillator Frequency
0.032768
20.0
–
MHz System clock frequencies below
the crystal oscillator minimum
require an external clock driver.
T
T
T
T
Crystal Oscillator Clock Period
System Clock High Time
System Clock Low Time
System Clock Rise Time
50
20
20
–
ns
ns
ns
ns
T
= 1/F
sysclk
XIN
CLK
XINH
XINL
XINR
3
3
T
= 50ns. Slower rise times
CLK
can be tolerated with longer clock
periods.
T
System Clock Fall Time
–
ns
T
= 50ns. Slower fall times can
CLK
XINF
be tolerated with longer clock
periods.
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Z8 Encore!® 64K Series
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228
General Purpose I/O Port Input Data Sample Timing
Figure 50 illustrates timing of the GPIO Port input sampling. Table 117 lists the GPIO port
input timing.
TCLK
System
Clock
Port Value
Changes to 0
GPIO Pin
Input Value
GPIO Input
Data Latch
0 Latched
Into Port Input
Data Register
GPIO Data Register
Value 0 Read
GPIO Data
by eZ8 CPU
Read on Data Bus
Figure 50. Port Input Sample Timing
Table 117. GPIO Port Input Timing
Delay (ns)
Parameter Abbreviation
Min
Max
T
T
T
Port Input Transition to XIN Fall Setup Time
(Not pictured)
5
–
S_PORT
H_PORT
SMR
XIN Fall to Port Input Transition Hold Time
(Not pictured)
5
–
GPIO Port Pin Pulse Width to Insure STOP Mode
Recovery
1µs
(for GPIO Port Pins enabled as SMR sources)
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General Purpose I/O Port Output Timing
Figure 51 and Table 118 provide timing information for GPIO Port pins.
TCLK
XIN
T1
T2
Port Output
Figure 51. GPIO Port Output Timing
Table 118. GPIO Port Output Timing
Delay (ns)
Parameter Abbreviation
GPIO Port pins
Min
Max
T
T
XIN Rise to Port Output Valid Delay
XIN Rise to Port Output Hold Time
–
2
15
–
1
2
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On-Chip Debugger Timing
Figure 52 and Table 119 provide timing information for the DBG pin. The DBG pin tim-
ing specifications assume a 4µs maximum rise and fall time.
TCLK
XIN
T1
T2
T4
DBG
(Output)
Output Data
T3
DBG
(Input)
Input Data
Figure 52. On-Chip Debugger Timing
Table 119. On-Chip Debugger Timing
Delay (ns)
Parameter Abbreviation
DBG
Min
Max
T
T
T
T
XIN Rise to DBG Valid Delay
–
2
15
–
1
2
3
4
XIN Rise to DBG Output Hold Time
DBG to XIN Rise Input Setup Time
DBG to XIN Rise Input Hold Time
DBG frequency
10
5
–
–
System
Clock / 4
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SPI Master Mode Timing
Figure 53 and Table 120 provide timing information for SPI Master mode pins. Timing is
shown with SCK rising edge used to source MOSI output data, SCK falling edge used to
sample MISO input data. Timing on the SS output pin(s) is controlled by software.
SCK
T1
MOSI
(Output)
Output Data
T2
T3
MISO
Input Data
(Input)
Figure 53. SPI Master Mode Timing
Table 120. SPI Master Mode Timing
Delay (ns)
Parameter Abbreviation
SPI Master
Min
Max
T
T
T
SCK Rise to MOSI output Valid Delay
-5
20
0
+5
1
2
3
MISO input to SCK (receive edge) Setup Time
MISO input to SCK (receive edge) Hold Time
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SPI Slave Mode Timing
Figure 54 and Table 121 provide timing information for the SPI slave mode pins. Timing
is shown with SCK rising edge used to source MISO output data, SCK falling edge used to
sample MOSI input data.
SCK
T1
MISO
(Output)
Output Data
T2
T3
MOSI
Input Data
(Input)
T4
SS
(Input)
Figure 54. SPI Slave Mode Timing
Table 121. SPI Slave Mode Timing
Delay (ns)
Parameter Abbreviation
SPI Slave
Min
Max
T
SCK (transmit edge) to MISO output Valid Delay
2 * Xin
period
3 * Xin
period +
20 nsec
1
T
T
MOSI input to SCK (receive edge) Setup Time
MOSI input to SCK (receive edge) Hold Time
0
2
3
3 * Xin
period
T
SS input assertion to SCK setup
1 * Xin
period
4
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2
I C Timing
Figure 55 and Table 122 provide timing information for I2C pins.
SCL
(Output)
T1
SDA
(Output)
Output Data
T3
T2
Input Data
SDA
(Input)
2
Figure 55. I C Timing
2
Table 122. I C Timing
Delay (ns)
Parameter Abbreviation
Minimum Maximum
2
I C
T
T
T
SCL Fall to SDA output delay
SCL period/4
1
2
3
SDA Input to SCL rising edge Setup Time
SDA Input to SCL falling edge Hold Time
0
0
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UART Timing
Figure 56 and Table 123 provide timing information for UART pins for the case where the
Clear To Send input pin (CTS) is used for flow control. In this example, it is assumed that
the Driver Enable polarity has been configured to be Active Low and is represented here
by DE. The CTS to DE assertion delay (T1) assumes the UART Transmit Data register has
been loaded with data prior to CTS assertion.
CTS
(Input)
T
1
DE
(Output)
T
T
3
2
TXD
(Output)
Stop
Start
Bit 0
Bit 1
Bit 7 Parity
End of
Stop Bit(s)
Figure 56. UART Timing with CTS
Table 123. UART Timing with CTS
Delay (ns)
Minimum Maximum
Parameter Abbreviation
T
T
T
CTS Fall to DE Assertion Delay
2 * XIN period 2 * XIN period
+ 1 Bit period
1
2
3
DE Assertion to TXD Falling Edge (Start) Delay 1 Bit period
1 Bit period +
1 * XIN period
End of Stop Bit(s) to DE Deassertion Delay
1 * XIN period 2 * XIN period
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Figure 57 and Table 124 provide timing information for UART pins for the case where the
Clear To Send input signal (CTS) is not used for flow control. In this example, it is
assumed that the Driver Enable polarity has been configured to be Active Low and is rep-
resented here by DE. DE asserts after the UART Transmit Data Register has been written.
DE remains asserted for multiple characters as long as the Transmit Data register is writ-
ten with the next character before the current character has completed.
DE
(Output)
T
T
2
1
TXD
(Output)
Stop
Start
Bit 0
Bit 1
Bit 7 Parity
End of
Stop Bit(s)
Figure 57. UART Timing without CTS
Table 124. UART Timing without CTS
Delay (ns)
Parameter Abbreviation
Minimum
Maximum
T
DE Assertion to TXD Falling Edge (Start) Delay
1 Bit period
1 Bit period +
1 * XIN period
1
T
End of Stop Bit(s) to DE Deassertion Delay
1 * XIN period 2 * XIN period
2
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Z8 Encore!® 64K Series
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236
eZ8 CPU Instruction Set
Assembly Language Programming Introduction
The eZ8 CPU assembly language provides a means for writing an application program
without having to be concerned with actual memory addresses or machine instruction for-
mats. A program written in assembly language is called a source program. Assembly lan-
guage allows the use of symbolic addresses to identify memory locations. It also allows
mnemonic codes (opcodes and operands) to represent the instructions themselves. The
opcodes identify the instruction while the operands represent memory locations, registers,
or immediate data values.
Each assembly language program consists of a series of symbolic commands called state-
ments. Each statement can contain labels, operations, operands and comments.
Labels can be assigned to a particular instruction step in a source program. The label iden-
tifies that step in the program as an entry point for use by other instructions.
The assembly language also includes assembler directives that supplement the machine
instruction. The assembler directives, or pseudo-ops, are not translated into a machine
instruction. Rather, the pseudo-ops are interpreted as directives that control or assist the
assembly process.
The source program is processed (assembled) by the assembler to obtain a machine lan-
guage program called the object code. The object code is executed by the eZ8 CPU. An
example segment of an assembly language program is detailed in the following example.
Assembly Language Source Program Example
JP START
START:
; Everything after the semicolon is a comment.
; A label called “START”. The first instruction (JP START) in this
; example causes program execution to jump to the point within the
; program where the STARTlabel occurs.
LD R4, R7
; A Load (LD) instruction with two operands. The first operand,
; Working Register R4, is the destination. The second operand,
; Working Register R7, is the source. The contents of R7 is
; written into R4.
LD 234H, #%01 ; Another Load (LD) instruction with two operands.
; The first operand, Extended Mode Register Address 234H,
; identifies the destination. The second operand, Immediate Data
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; value 01H, is the source. The value 01His written into the
; Register at address 234H.
Assembly Language Syntax
For proper instruction execution, eZ8 CPU assembly language syntax requires that the
operands be written as ‘destination, source’. After assembly, the object code usually has
the operands in the order ’source, destination’, but ordering is opcode-dependent. The fol-
lowing instruction examples illustrate the format of some basic assembly instructions and
the resulting object code produced by the assembler. This binary format must be followed
by users that prefer manual program coding or intend to implement their own assembler.
Example 1: If the contents of Registers 43H and 08H are added and the result is stored in
43H, the assembly syntax and resulting object code is:
Assembly Language Syntax Example 1
ADD
43H,
08
08H
43
(ADD dst, src)
(OPC src, dst)
Assembly Language Code
Object Code
04
Example 2: In general, when an instruction format requires an 8-bit register address, that
address can specify any register location in the range 0 - 255 or, using Escaped Mode
Addressing, a Working Register R0 - R15. If the contents of Register 43H and Working
Register R8 are added and the result is stored in 43H, the assembly syntax and resulting
object code is:
Assembly Language Syntax Example 2
ADD
43H,
E8
R8
43
(ADD dst, src)
(OPC src, dst)
Assembly Language Code
Object Code
04
See the device-specific Product Specification to determine the exact register file range
available. The register file size varies, depending on the device type.
eZ8 CPU Instruction Notation
In the eZ8 CPU Instruction Summary and Description sections, the operands, condition
codes, status flags, and address modes are represented by a notational shorthand that is
described in Table 125.
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.
Table 125. Notational Shorthand
Notation Description
Operand Range
b
Bit
b
b represents a value from 0 to 7 (000B to 111B).
cc
Condition Code
—
See Condition Codes overview in the eZ8 CPU User
Manual.
DA
ER
Direct Address
Addrs
Reg
Addrs. represents a number in the range of 0000H to
FFFFH
Extended Addressing Register
Reg. represents a number in the range of 000H to
FFFH
IM
Ir
Immediate Data
#Data
@Rn
Data is a number between 00H to FFH
n = 0 –15
Indirect Working Register
Indirect Register
IR
@Reg
@RRp
@Reg
Reg. represents a number in the range of 00H to FFH
p = 0, 2, 4, 6, 8, 10, 12, or 14
Irr
Indirect Working Register Pair
Indirect Register Pair
IRR
Reg. represents an even number in the range 00H to
FEH
p
Polarity
p
Polarity is a single bit binary value of either 0B or 1B.
n = 0 – 15
r
Working Register
Register
Rn
Reg
X
R
RA
Reg. represents a number in the range of 00H to FFH
Relative Address
X represents an index in the range of +127 to –128
which is an offset relative to the address of the next
instruction
rr
Working Register Pair
Register Pair
RRp
Reg
p = 0, 2, 4, 6, 8, 10, 12, or 14
RR
Reg. represents an even number in the range of 00H to
FEH
Vector
X
Vector Address
Indexed
Vector
#Index
Vector represents a number in the range of 00H to FFH
The register or register pair to be indexed is offset by
the signed Index value (#Index) in a +127 to -128
range.
Table 126 contains additional symbols that are used throughout the Instruction Summary
and Instruction Set Description sections.
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Table 126. Additional Symbols
Symbol
Definition
dst
src
@
Destination Operand
Source Operand
Indirect Address Prefix
Stack Pointer
SP
PC
FLAGS
RP
#
Program Counter
Flags Register
Register Pointer
Immediate Operand Prefix
Binary Number Suffix
Hexadecimal Number Prefix
Hexadecimal Number Suffix
B
%
H
Assignment of a value is indicated by an arrow. For example,
dst ← dst + src
indicates the source data is added to the destination data and the result is stored in the des-
tination location.
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Condition Codes
The C, Z, S and V flags control the operation of the conditional jump (JP cc and JR cc)
instructions. Sixteen frequently useful functions of the flag settings are encoded in a 4-bit
field called the condition code (cc), which forms Bits 7:4 of the conditional jump instruc-
tions. The condition codes are summarized in Table 127. Some binary condition codes can
be created using more than one assembly code mnemonic. The result of the flag test oper-
ation decides if the conditional jump is executed.
Table 127. Condition Codes
Assembly
Binary
0000
0001
0010
0011
0100
0101
0110
0110
0111
0111
1000
1001
1010
1011
1100
1101
1110
1110
1111
1111
Hex Mnemonic Definition
Flag Test Operation
0
1
F
Always False
Less Than
–
LT
LE
ULE
OV
Ml
Z
(S XOR V) = 1
2
Less Than or Equal
Unsigned Less Than or Equal
Overflow
(Z OR (S XOR V)) = 1
3
(C OR Z) = 1
4
V = 1
5
Minus
S = 1
6
Zero
Z = 1
6
EQ
C
Equal
Z = 1
7
Carry
C = 1
7
ULT
Unsigned Less Than
C = 1
8
T (or blank) Always True
–
9
GE
Greater Than or Equal
(S XOR V) = 0
A
B
C
D
E
E
F
F
GT
Greater Than
Unsigned Greater Than
No Overflow
Plus
(Z OR (S XOR V)) = 0
UGT
NOV
PL
(C = 0 AND Z = 0) = 1
V = 0
S = 0
Z = 0
Z = 0
C = 0
NZ
Non-Zero
NE
Not Equal
NC
No Carry
UGE
Unsigned Greater Than or Equal C = 0
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eZ8 CPU Instruction Classes
eZ8 CPU instructions can be divided functionally into the following groups:
Arithmetic
Bit Manipulation
•
•
•
•
•
•
•
•
Block Transfer
CPU Control
Load
Logical
Program Control
Rotate and Shift
Tables 128 through 135 contain the instructions belonging to each group and the number
of operands required for each instruction. Some instructions appear in more than one table
as these instruction can be considered as a subset of more than one category. Within these
tables, the source operand is identified as ’src’, the destination operand is ’dst’ and a con-
dition code is ’cc’.
Table 128. Arithmetic Instructions
Mnemonic
ADC
Operands
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst
Instruction
Add with Carry
ADCX
ADD
ADDX
CP
Add with Carry using Extended Addressing
Add
Add using Extended Addressing
Compare
CPC
Compare with Carry
Compare with Carry using Extended Addressing
Compare using Extended Addressing
Decimal Adjust
CPCX
CPX
DA
DEC
dst
Decrement
DECW
INC
dst
Decrement Word
dst
Increment
INCW
MULT
dst
Increment Word
dst
Multiply
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Table 128. Arithmetic Instructions (Continued)
Mnemonic
SBC
Operands
dst, src
dst, src
dst, src
dst, src
Instruction
Subtract with Carry
SBCX
SUB
Subtract with Carry using Extended Addressing
Subtract
SUBX
Subtract using Extended Addressing
Table 129. Bit Manipulation Instructions
Mnemonic
BCLR
BIT
Operands
bit, dst
p, bit, dst
bit, dst
dst
Instruction
Bit Clear
Bit Set or Clear
BSET
BSWAP
CCF
Bit Set
Bit Swap
—
Complement Carry Flag
RCF
—
Reset Carry Flag
SCF
—
Set Carry Flag
TCM
dst, src
dst, src
dst, src
dst, src
Test Complement Under Mask
Test Complement Under Mask using Extended Addressing
Test Under Mask
TCMX
TM
TMX
Test Under Mask using Extended Addressing
Table 130. Block Transfer Instructions
Mnemonic
Operands
Instruction
LDCI
dst, src
Load Constant to/from Program Memory and Auto-Increment
Addresses
LDEI
dst, src
Load External Data to/from Data Memory and Auto-Increment
Addresses
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Table 131. CPU Control Instructions
Mnemonic
ATM
CCF
Operands
Instruction
—
—
—
—
—
—
—
—
src
—
—
Atomic Execution
Complement Carry Flag
Disable Interrupts
Enable Interrupts
HALT Mode
DI
EI
HALT
NOP
RCF
No Operation
Reset Carry Flag
Set Carry Flag
SCF
SRP
Set Register Pointer
STOP Mode
STOP
WDT
Watch-Dog Timer Refresh
Table 132. Load Instructions
Mnemonic Operands Instruction
CLR
LD
dst
Clear
dst, src
dst, src
dst, src
Load
LDC
LDCI
Load Constant to/from Program Memory
Load Constant to/from Program Memory and Auto-Increment
Addresses
LDE
dst, src
dst, src
Load External Data to/from Data Memory
LDEI
Load External Data to/from Data Memory and Auto-Increment
Addresses
LDWX
LDX
dst, src
dst, src
Load Word using Extended Addressing
Load using Extended Addressing
LEA
dst, X(src) Load Effective Address
POP
dst
dst
src
src
Pop
POPX
PUSH
PUSHX
Pop using Extended Addressing
Push
Push using Extended Addressing
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Table 133. Logical Instructions
Mnemonic Operands Instruction
AND
ANDX
COM
OR
dst, src
dst, src
dst
Logical AND
Logical AND using Extended Addressing
Complement
dst, src
dst, src
dst, src
dst, src
Logical OR
ORX
XOR
XORX
Logical OR using Extended Addressing
Logical Exclusive OR
Logical Exclusive OR using Extended Addressing
Table 134. Program Control Instructions
Mnemonic
BRK
BTJ
Operands
Instruction
—
On-Chip Debugger Break
p, bit, src, DA Bit Test and Jump
BTJNZ
BTJZ
CALL
DJNZ
IRET
JP
bit, src, DA
Bit Test and Jump if Non-Zero
bit, src, DA
Bit Test and Jump if Zero
Call Procedure
dst
dst, src, RA
Decrement and Jump Non-Zero
Interrupt Return
Jump
—
dst
JP cc
JR
dst
Jump Conditional
Jump Relative
DA
DA
—
JR cc
RET
Jump Relative Conditional
Return
TRAP
vector
Software Trap
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Table 135. Rotate and Shift Instructions
Mnemonic
BSWAP
RL
Operands
dst
Instruction
Bit Swap
dst
Rotate Left
RLC
dst
Rotate Left through Carry
Rotate Right
RR
dst
RRC
dst
Rotate Right through Carry
Shift Right Arithmetic
Shift Right Logical
Swap Nibbles
SRA
dst
SRL
dst
SWAP
dst
eZ8 CPU Instruction Summary
Table 136 summarizes the eZ8 CPU instructions. The table identifies the addressing
modes employed by the instruction, the effect upon the Flags register, the number of CPU
clock cycles required for the instruction fetch, and the number of CPU clock cycles
required for the instruction execution.
.
Table 136. eZ8 CPU Instruction Summary
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
r
src
r
C
Z
S
V
D
ADC dst, src
dst ← dst + src + C
12
13
14
15
16
17
18
19
*
*
*
*
0
*
2
2
3
3
3
3
4
4
3
4
3
4
3
4
3
3
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
ADCX dst, src
Flags Notation:
dst ← dst + src + C
*
*
*
*
0
*
0 = Reset to 0
1 = Set to 1
* = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
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Table 136. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
r
src
r
C
Z
S
V
D
ADD dst, src
dst ← dst + src
02
03
04
05
06
07
08
09
52
53
54
55
56
57
58
59
2F
*
*
*
*
0
*
2
2
3
3
3
3
4
4
2
2
3
3
3
3
4
4
1
3
4
3
4
3
4
3
3
3
4
3
4
3
4
3
3
2
r
Ir
R
R
R
IR
IM
IM
ER
IM
r
R
IR
ER
ER
r
ADDX dst, src
AND dst, src
dst ← dst + src
*
-
*
*
*
*
*
0
0
-
*
-
dst ← dst AND src
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
ANDX dst, src
ATM
dst ← dst AND src
-
-
*
-
*
-
0
-
-
-
-
-
Block all interrupt and
DMA requests during
execution of the next 3
instructions
BCLR bit, dst
BIT p, bit, dst
BRK
dst[bit] ← 0
r
r
E2
E2
00
-
-
*
*
-
*
*
-
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
2
2
1
2
2
3
3
2
2
1
2
2
3
4
dst[bit] ← p
Debugger Break
dst[bit] ← 1
-
BSET bit, dst
BSWAP dst
r
E2
D5
F6
F7
-
*
*
-
*
*
-
0
0
-
dst[7:0] ← dst[0:7]
R
X
-
BTJ p, bit, src, dst if src[bit] = p
r
PC ← PC + X
Ir
0 = Reset to 0
1 = Set to 1
Flags Notation:
* = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
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Table 136. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
src
r
C
Z
S
V
D
BTJNZ bit, src, dst if src[bit] = 1
F6
F7
F6
F7
D4
D6
-
-
-
-
-
-
-
-
3
3
3
3
2
3
3
4
3
4
6
3
PC ← PC + X
Ir
r
BTJZ bit, src, dst if src[bit] = 0
-
-
-
-
-
-
-
-
-
-
PC ← PC + X
Ir
CALL dst
SP ← SP -2
@SP ← PC
PC ← dst
IRR
DA
CCF
C ← ~C
EF
B0
*
-
-
-
-
-
-
-
-
-
-
-
1
2
2
2
2
2
2
3
3
3
3
3
3
4
4
4
4
5
5
2
2
3
2
3
3
4
3
4
3
4
3
4
3
4
3
4
3
3
CLR dst
dst ← 00H
R
IR
R
B1
COM dst
dst ← ~dst
60
-
*
*
*
*
0
*
-
-
-
-
IR
r
61
CP dst, src
dst - src
r
A2
*
r
Ir
A3
R
R
A4
R
IR
IM
IM
r
A5
R
A6
IR
r
A7
CPC dst, src
dst - src - C
1F A2
1F A3
1F A4
1F A5
1F A6
1F A7
1F A8
1F A9
*
*
*
*
-
-
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
CPCX dst, src
Flags Notation:
dst - src - C
*
*
*
*
-
-
0 = Reset to 0
1 = Set to 1
* = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
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Table 136. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
ER
ER
R
src
ER
IM
C
Z
S
V
D
CPX dst, src
DA dst
dst - src
A8
A9
40
*
*
*
*
-
-
-
-
-
4
4
2
2
2
2
2
2
1
2
3
3
2
3
2
3
5
6
2
3
dst ← DA(dst)
dst ← dst - 1
*
-
*
*
*
*
*
*
X
*
-
-
-
IR
41
DEC dst
R
30
IR
31
DECW dst
dst ← dst - 1
RR
IRR
80
-
*
81
DI
IRQCTL[7] ← 0
8F
-
-
-
-
-
-
-
-
-
-
-
-
DJNZ dst, RA
dst ← dst – 1
if dst ≠ 0
r
0A-FA
PC ← PC + X
EI
IRQCTL[7] ← 1
HALT Mode
9F
7F
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
2
2
1
2
2
1
2
2
2
3
2
5
6
5
HALT
INC dst
dst ← dst + 1
R
IR
20
*
*
*
21
r
0E-FE
A0
INCW dst
IRET
dst ← dst + 1
RR
IRR
-
*
*
*
*
*
*
-
-
A1
FLAGS ← @SP
SP ← SP + 1
PC ← @SP
BF
*
*
*
SP ← SP + 2
IRQCTL[7] ← 1
JP dst
PC ← dst
DA
IRR
DA
8D
C4
-
-
-
-
-
-
-
-
-
-
-
-
3
2
3
2
3
2
JP cc, dst
if cc is true
0D-FD
PC ← dst
0 = Reset to 0
1 = Set to 1
Flags Notation:
* = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
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Table 136. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
DA
DA
src
C
-
Z
-
S
-
V
-
D
-
JR dst
PC ← PC + X
8B
-
-
2
2
2
2
JR cc, dst
if cc is true
0B-FB
-
-
-
-
-
PC ← PC + X
LD dst, rc
dst ← src
r
r
IM
X(r)
r
0C-FC
C7
D7
E3
-
-
-
-
-
-
2
3
3
2
3
3
3
3
2
3
2
2
2
2
2
2
3
4
3
2
4
2
3
3
3
5
9
5
9
9
X(r)
r
Ir
R
R
E4
R
IR
IM
IM
r
E5
R
E6
IR
Ir
E7
F3
IR
r
R
F5
LDC dst, src
LDCI dst, src
dst ← src
Irr
Irr
r
C2
C5
D2
C3
D3
-
-
-
-
-
-
-
-
-
-
-
-
Ir
Irr
Ir
dst ← src
r ← r + 1
rr ← rr + 1
Irr
Ir
Irr
LDE dst, src
LDEI dst, src
dst ← src
r
Irr
r
82
92
83
93
-
-
-
-
-
-
-
-
-
-
-
-
2
2
2
2
5
5
9
9
Irr
Ir
dst ← src
r ← r + 1
rr ← rr + 1
Irr
Ir
Irr
LDWX dst, src
Flags Notation:
dst ← src
ER
ER
1F E8
-
-
-
-
-
-
5
4
0 = Reset to 0
1 = Set to 1
* = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
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Table 136. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
r
src
ER
ER
IRR
IRR
X(rr)
r
C
Z
S
V
D
LDX dst, src
dst ← src
84
85
86
87
88
89
94
95
96
97
E8
E9
98
99
F4
-
-
-
-
-
-
3
3
3
3
3
3
3
3
3
3
4
4
3
3
2
2
3
4
5
4
4
2
3
4
5
2
2
3
5
8
Ir
R
IR
r
X(rr)
ER
ER
IRR
IRR
ER
ER
r
r
Ir
R
IR
ER
IM
X(r)
X(rr)
LEA dst, X(src)
MULT dst
dst ← src + X
-
-
-
-
-
-
-
-
-
-
-
-
rr
dst[15:0] ←
RR
dst[15:8] * dst[7:0]
NOP
No operation
0F
42
43
44
45
46
47
48
49
-
-
-
-
-
-
-
-
-
1
2
2
3
3
3
3
4
4
2
3
4
3
4
3
4
3
3
OR dst, src
dst ← dst OR src
r
r
r
*
*
0
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
ORX dst, src
dst ← dst OR src
-
*
*
0
-
-
0 = Reset to 0
1 = Set to 1
Flags Notation:
* = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
PS019913-0305
P r e l i m i n a r y
eZ8 CPU Instruction Set
Z8 Encore!® 64K Series
Product Specification
251
Table 136. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
R
src
C
Z
S
V
D
POP dst
dst ← @SP
SP ← SP + 1
50
51
-
-
-
-
-
-
2
2
3
2
3
2
IR
ER
POPX dst
PUSH src
dst ← @SP
SP ← SP + 1
D8
-
-
-
-
-
-
-
-
-
-
-
-
SP ← SP – 1
@SP ← src
R
70
71
2
2
3
3
2
3
2
2
IR
IM
ER
1F 70
C8
PUSHX src
SP ← SP – 1
@SP ← src
-
-
-
-
-
-
RCF
RET
C ← 0
CF
AF
0
-
-
-
-
-
-
-
-
-
-
-
1
1
2
4
PC ← @SP
SP ← SP + 2
RL dst
R
90
91
*
*
*
*
-
-
2
2
2
3
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
IR
RLC dst
RR dst
R
10
11
*
*
*
*
*
*
*
*
-
-
-
-
2
2
2
3
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
IR
R
E0
E1
2
2
2
3
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
IR
RRC dst
R
C0
C1
*
*
*
*
-
-
2
2
2
3
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
IR
0 = Reset to 0
1 = Set to 1
Flags Notation:
* = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
PS019913-0305
P r e l i m i n a r y
eZ8 CPU Instruction Set
Z8 Encore!® 64K Series
Product Specification
252
Table 136. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
r
src
r
C
Z
S
V
D
SBC dst, src
dst ← dst – src - C
32
33
34
35
36
37
38
39
DF
D0
D1
*
*
*
*
1
*
2
2
3
3
3
3
4
4
1
2
2
3
4
3
4
3
4
3
3
2
2
3
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
SBCX dst, src
dst ← dst – src - C
C ← 1
*
*
*
*
1
*
SCF
1
*
-
-
-
-
-
-
-
SRA dst
R
*
*
0
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
C
IR
SRL dst
R
1F C0
1F C1
*
*
0
*
-
-
3
3
2
3
0
D7 D6 D5 D4 D3 D2 D1 D0
dst
IR
SRP src
RP ← src
IM
01
6F
22
23
24
25
26
27
28
29
F0
F1
-
-
-
-
-
-
-
-
-
-
-
-
2
1
2
2
3
3
3
3
4
4
2
2
2
2
3
4
3
4
3
4
3
3
2
3
STOP
STOP Mode
dst ← dst – src
SUB dst, src
r
r
r
*
*
*
*
1
*
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
R
SUBX dst, src
SWAP dst
dst ← dst – src
*
*
*
*
*
*
1
-
*
-
dst[7:4] ↔ dst[3:0]
X
X
IR
0 = Reset to 0
1 = Set to 1
Flags Notation:
* = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
PS019913-0305
P r e l i m i n a r y
eZ8 CPU Instruction Set
Z8 Encore!® 64K Series
Product Specification
253
Table 136. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
r
src
r
C
Z
S
V
D
TCM dst, src
(NOT dst) AND src
62
63
64
65
66
67
68
69
72
73
74
75
76
77
78
79
F2
-
*
*
0
-
-
2
2
3
3
3
3
4
4
2
2
3
3
3
3
4
4
2
3
4
3
4
3
4
3
3
3
4
3
4
3
4
3
3
6
r
Ir
R
R
R
IR
R
IM
IM
ER
IM
r
IR
ER
ER
r
TCMX dst, src
TM dst, src
(NOT dst) AND src
dst AND src
-
-
*
*
*
*
0
0
-
-
-
-
r
Ir
R
R
R
IR
R
IM
IM
ER
IM
Vector
IR
ER
ER
TMX dst, src
TRAP Vector
dst AND src
-
-
*
-
*
-
0
-
-
-
-
-
SP ← SP – 2
@SP ← PC
SP ← SP – 1
@SP ← FLAGS
PC ← @Vector
WDT
5F
-
-
-
-
-
-
1
2
0 = Reset to 0
1 = Set to 1
Flags Notation:
* = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
PS019913-0305
P r e l i m i n a r y
eZ8 CPU Instruction Set
Z8 Encore!® 64K Series
Product Specification
254
Table 136. eZ8 CPU Instruction Summary (Continued)
Address Mode
Flags
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
H Cycles Cycles
Symbolic Operation
dst
r
src
r
C
Z
S
V
D
XOR dst, src
dst ← dst XOR src
B2
B3
B4
B5
B6
B7
B8
B9
-
*
*
0
-
-
2
2
3
3
3
3
4
4
3
4
3
4
3
4
3
3
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
XORX dst, src
Flags Notation:
dst ← dst XOR src
-
*
*
0
-
-
0 = Reset to 0
1 = Set to 1
* = Value is a function of the result of the operation.
- = Unaffected
X = Undefined
PS019913-0305
P r e l i m i n a r y
eZ8 CPU Instruction Set
Z8 Encore!® 64K Series
Product Specification
255
Flags Register
The Flags Register contains the status information regarding the most recent arithmetic,
logical, bit manipulation or rotate and shift operation. The Flags Register contains six bits
of status information that are set or cleared by CPU operations. Four of the bits (C, V, Z
and S) can be tested for use with conditional jump instructions. Two flags (H and D) can-
not be tested and are used for Binary-Coded Decimal (BCD) arithmetic.
The two remaining bits, User Flags (F1 and F2), are available as general-purpose status
bits. User Flags are unaffected by arithmetic operations and must be set or cleared by
instructions. The User Flags cannot be used with conditional Jumps. They are undefined at
initial power-up and are unaffected by Reset. Figure 58 illustrates the flags and their bit
positions in the Flags Register.
Bit
7
Bit
0
C
Z
S
V
D
H F2 F1 Flags Register
User Flags
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
U = Undefined
Figure 58. Flags Register
Interrupts, the Software Trap (TRAP) instruction, and Illegal Instruction Traps all write
the value of the Flags Register to the stack. Executing an Interrupt Return (IRET) instruc-
tion restores the value saved on the stack into the Flags Register.
PS019913-0305
P r e l i m i n a r y
eZ8 CPU Instruction Set
Z8 Encore!® 64K Series
Product Specification
256
Opcode Maps
A description of the opcode map data and the abbreviations are provided in Figure 59 and
Table 132. Figures 60 and 61 provide information on each of the eZ8 CPU instructions.
Opcode
Lower Nibble
Fetch Cycles
Instruction Cycles
4
3.3
CP
Opcode
Upper Nibble
A
R2,R1
First Operand
After Assembly
Second Operand
After Assembly
Figure 59. Opcode Map Cell Description
PS019913-0305
P r e l i m i n a r y
Opcode Maps
Z8 Encore!® 64K Series
Product Specification
257
Table 132. Opcode Map Abbreviations
Abbreviation
Description
Bit position
Abbreviation
Description
b
IRR
p
Indirect Register Pair
Polarity (0 or 1)
4-bit Working Register
8-bit register
cc
X
Condition code
8-bit signed index or displacement r
DA
ER
Destination address
R
Extended Addressing register
r1, R1, Ir1, Irr1, IR1, rr1, Destination address
RR1, IRR1, ER1
IM
Immediate data value
r2, R2, Ir2, Irr2, IR2, rr2, Source address
RR2, IRR2, ER2
Ir
Indirect Working Register
Indirect register
RA
rr
Relative
IR
Irr
Working Register Pair
Register Pair
Indirect Working Register Pair
RR
PS019913-0305
P r e l i m i n a r y
Opcode Maps
Z8 Encore!® 64K Series
Product Specification
258
Lower Nibble (Hex)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
1.2
2.2
2.3
2.4
3.3
3.4
3.3
3.4
4.3
4.3
2.3
2.2
JR
cc,X
2.2
LD
r1,IM
3.2
JP
cc,DA
1.2
INC
r1
1.2
NOP
BRK SRP ADD ADD ADD ADD ADD ADD ADDX ADDX DJNZ
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
IM
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
r1,X
2.2
RLC
R1
2.3
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
See 2nd
Opcode
Map
RLC ADC ADC ADC ADC ADC ADC ADCX ADCX
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
INC
R1
2.3
INC
IR1
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
1,2
SUB SUB SUB SUB SUB SUB SUBX SUBX
r1,r2
ATM
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
DEC DEC SBC SBC SBC SBC SBC SBC SBCX SBCX
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
DA
R1
2.3
DA
IR1
2.3
OR
r1,r2
2.4
OR
r1,Ir2
3.3
OR
R2,R1
3.4
OR
IR2,R1
3.3
OR
R1,IM
3.4
4.3
4.3
OR
ORX ORX
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
1.2
WDT
POP POP AND AND AND AND AND AND ANDX ANDX
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
1.2
STOP
COM COM TCM TCM TCM TCM TCM TCM TCMX TCMX
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.3
2.4
TM
r1,Ir2
3.3
TM
R2,R1
3.4
TM
IR2,R1
3.3
TM
R1,IM
3.4
4.3
4.3
1.2
HALT
PUSH PUSH TM
R2
TM
TMX TMX
IR2
r1,r2
IR1,IM ER2,ER1 IM,ER1
2.5
2.6
2.5
2.9
3.2
3.3
LDX
3.4
LDX
3.5
3.4
3.4
1.2
DI
DECW DECW LDE LDEI LDX
RR1
LDX
LDX
LDX
IRR1
r1,Irr2
Ir1,Irr2 r1,ER2 Ir1,ER2 IRR2,R1 IRR2,IR1 r1,rr2,X rr1,r2,X
2.2
RL
R1
2.3
RL
IR1
2.5
2.9
3.2
3.3
LDX
3.4
LDX
3.5
3.3
3.5
1.2
EI
LDE LDEI LDX
r2,Irr1
LDX
LEA
LEA
Ir2,Irr1 r2,ER1 Ir2,ER1 R2,IRR1 IR2,IRR1 r1,r2,X rr1,rr2,X
2.5
2.6
2.3
CP
r1,r2
2.4
CP
r1,Ir2
3.3
CP
R2,R1
3.4
CP
IR2,R1
3.3
CP
R1,IM
3.4
4.3
4.3
1.4
RET
INCW INCW
RR1
CP
CPX
CPX
IRR1
IR1,IM ER2,ER1 IM,ER1
2.2
CLR
R1
2.3
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
1.5
IRET
CLR XOR XOR XOR XOR XOR XOR XORX XORX
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
3.4 3.2
LD PUSHX
2.2
2.3
2.5
2.9
2.3
JP
IRR1
2.9
LDC
Ir1,Irr2
1.2
RCF
RRC RRC LDC LDCI
R1
IR1
r1,Irr2
Ir1,Irr2
r1,r2,X
ER2
2.2
2.3
2.5
2.9
2.6
2.2
3.3
3.4
LD
r2,r1,X
3.2
POPX
ER1
1.2
SCF
SRA SRA
R1
LDC LDCI CALL BSWAP CALL
r2,Irr1
IR1
Ir2,Irr1
IRR1
R1
DA
2.2
RR
R1
2.3
RR
IR1
2.2
BIT
p,b,r1
2.3
LD
r1,Ir2
3.2
LD
R2,R1
3.3
LD
IR2,R1
3.2
LD
R1,IM
3.3
4.2
4.2
1.2
CCF
LD
LDX
LDX
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.6
2.3
LD
Ir1,r2
2.8
MULT
RR1
3.3
LD
3.3
BTJ
3.4
BTJ
SWAP SWAP TRAP
R1
IR1
Vector
R2,IR1 p,b,r1,X p,b,Ir1,X
Figure 60. First Opcode Map
PS019913-0305
P r e l i m i n a r y
Opcode Maps
Z8 Encore!® 64K Series
Product Specification
259
Lower Nibble (Hex)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
3,2
PUSH
IM
3.3
3.4
4.3
4.4
4.3
4.4
5.3
5.3
CPC CPC CPC CPC CPC CPC CPCX CPCX
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
3.2
SRL
R1
3.3
SRL
IR1
5,4
LDWX
ER2,ER1
Figure 61. Second Opcode Map after 1FH
PS019913-0305
P r e l i m i n a r y
Opcode Maps
Z8 Encore!® 64K Series
Product Specification
260
Packaging
Figure 62 illustrates the 40-pin PDIP (plastic dual-inline package) available for the
Z8X1601, Z8X2401, Z8X3201, Z8X4801, and Z8X6401 devices.
Figure 62. 40-Lead Plastic Dual-Inline Package (PDIP)
PS019913-0305
P r e l i m i n a r y
Packaging
Z8 Encore!® 64K Series
Product Specification
261
Figure 63 illustrates the 44-pin LQFP (low profile quad flat package) available for the
Z8X1621, Z8X2421, Z8X3221, Z8X4821, and Z8X6421 devices.
A
HD
D
A2
A1
E
HE
DETAIL A
LE
c
b
e
L
0-7°
Figure 63. 44-Lead Low-Profile Quad Flat Package (LQFP)
PS019913-0305
P r e l i m i n a r y
Packaging
Z8 Encore!® 64K Series
Product Specification
262
Figure 64 illustrates the 44-pin PLCC (plastic lead chip carrier) package available for the
Z8X1621, Z8X2421, Z8X3221, Z8X4821, and Z8X6421 devices.
A
D
A1
D1
0.71/0.51
.028/.020
45°
6
1
40
MILLIMETER
INCH
SYMBOL
7
39
MIN
4.27
MAX
4.57
MIN
MAX
0.180
0.115
0.695
0.656
0.630
e
A
A1
0.168
0.095
0.685
0.650
0.600
0.51/0.36
0.020/0.014
2.41
2.92
M
E1 E
D/E
D1/E1
D2
17.40
16.51
15.24
17.65
16.66
16.00
0.81/0.66
0.032/0.026
17
29
e
1.27 BSC
0.050 BSC
18
28
R 1.14/0.64
0.045/0.025
NOTES:
1. CONTROLLING DIMENSION : INCH
2. LEADS ARE COPLANAR WITHIN 0.004".
3. DIMENSION : MM
INCH
Figure 64. 44-Lead Plastic Lead Chip Carrier Package (PLCC)
Figure 64 illustrates the 64-pin LQFP (low-profile quad flat package) available for the
Z8X1622, Z8X2422, Z8X3222, Z8X4822, and Z8X6422 devices.
A
HD
A2
A1
D
E
HE
DETAIL A
LE
c
e
b
L
0-7°
Figure 65. 64-Lead Low-Profile Quad Flat Package (LQFP)
PS019913-0305
P r e l i m i n a r y
Packaging
Z8 Encore!® 64K Series
Product Specification
263
Figure 66 illustrates the 68-pin PLCC (plastic lead chip carrier) package available for the
Z8X1622, Z8X2422, Z8X3222, Z8X4822, and Z8X6422 devices.
Figure 66. 68-Lead Plastic Lead Chip Carrier Package (PLCC)
PS019913-0305
P r e l i m i n a r y
Packaging
Z8 Encore!® 64K Series
Product Specification
264
Figure 67 illustrates the 80-pin QFP (quad flat package) available for the Z8X4823 and
Z8X6423 devices.
HD
A2
D
MILLIMETER
INCH
A1
64
41
SYMBOL
MIN
MAX
0.38
MIN
.004
.102
.012
.005
.933
.783
.697
.547
MAX
.015
.110
.018
.008
.951
.791
.715
.555
A1
A2
b
0.10
65
40
2.60
2.80
0.30
0.45
c
0.13
0.20
E
HE
HD
D
23.70
19.90
17.70
13.90
24.15
20.10
18.15
14.10
HE
E
80
25
e
0.80 BSC
.0315 BSC
.028 .043
L
0.70
1.10
c
1
24
b
DETAIL A
e
NOTES:
CONTROLLING DIMENSIONS : MILLIMETER
LEAD COPLANARITY : MAX .10
.004"
2.
L
0-10°
DETAIL A
Figure 67. 80-Lead Quad-Flat Package (QFP)
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Z8 Encore!® 64K Series
Product Specification
265
Ordering Information
Z8F16xx with 16KB Flash, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0° to 70°C
Z8F1621PM020SC
Z8F1621AN020SC
Z8F1621VN020SC
Z8F1622AR020SC
Z8F1622VS020SC
16KB 2KB 29 23
16KB 2KB 31 23
16KB 2KB 31 23
16KB 2KB 46 24
16KB 2KB 46 24
3
3
3
4
4
8
8
1
1
1
1
1
1
1
1
1
1
2 PDIP 40-pin package
2 LQFP 44-pin package
2 PLCC 44-pin package
2 LQFP 64-pin package
2 PLCC 68-pin package
8
12
12
Extended Temperature: -40° to +105°C
Z8F1621PM020EC
Z8F1621AN020EC
Z8F1621VN020EC
Z8F1622AR020EC
Z8F1622VS020EC
16KB 2KB 29 23
3
3
3
4
4
8
8
1
1
1
1
1
1
1
1
1
1
2 PDIP 40-pin package
2 LQFP 44-pin package
2 PLCC 44-pin package
2 LQFP 64-pin package
2 PLCC 68-pin package
16KB 2KB 31 23
16KB 2KB 31 23
16KB 2KB 46 24
16KB 2KB 46 24
8
12
12
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Packaging
Z8 Encore!® 64K Series
Product Specification
266
Z8F24xx with 24KB Flash, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0° to 70°C
Z8F2421PM020SC
Z8F2421AN020SC
Z8F2421VN020SC
Z8F2422AR020SC
Z8F2422VS020SC
24KB 2KB 29 23
24KB 2KB 31 23
24KB 2KB 31 23
24KB 2KB 46 24
24KB 2KB 46 24
3
3
3
4
4
8
8
1
1
1
1
1
1
1
1
1
1
2 PDIP 40-pin package
2 LQFP 44-pin package
2 PLCC 44-pin package
2 LQFP 64-pin package
2 PLCC 68-pin package
8
12
12
Extended Temperature: -40° to +105°C
Z8F2421PM020EC
Z8F2421AN020EC
Z8F2421VN020EC
Z8F2422AR020EC
Z8F2422VS020EC
24KB 2KB 29 23
3
3
3
4
4
8
8
1
1
1
1
1
1
1
1
1
1
2 PDIP 40-pin package
2 LQFP 44-pin package
2 PLCC 44-pin package
2 LQFP 64-pin package
2 PLCC 68-pin package
24KB 2KB 31 23
24KB 2KB 31 23
24KB 2KB 46 24
24KB 2KB 46 24
8
12
12
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Packaging
Z8 Encore!® 64K Series
Product Specification
267
Z8F32xx with 32KB Flash, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0° to 70°C
Z8F3221PM020SC
Z8F3221AN020SC
Z8F3221VN020SC
Z8F3222AR020SC
Z8F3222VS020SC
32KB 2KB 29 23
32KB 2KB 31 23
32KB 2KB 31 23
32KB 2KB 46 24
32KB 2KB 46 24
3
3
3
4
4
8
8
1
1
1
1
1
1
1
1
1
1
2 PDIP 40-pin package
2 LQFP 44-pin package
2 PLCC 44-pin package
2 LQFP 64-pin package
2 PLCC 68-pin package
8
12
12
Extended Temperature: -40° to 105°C
Z8F3221PM020EC
Z8F3221AN020EC
Z8F3221VN020EC
Z8F3222AR020EC
Z8F3222VS020EC
32KB 2KB 29 23
3
3
3
4
4
8
8
1
1
1
1
1
1
1
1
1
1
2 PDIP 40-pin package
2 LQFP 44-pin package
2 PLCC 44-pin package
2 LQFP 64-pin package
2 PLCC 68-pin package
32KB 2KB 31 23
32KB 2KB 31 23
32KB 2KB 46 24
32KB 2KB 46 24
8
12
12
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Packaging
Z8 Encore!® 64K Series
Product Specification
268
Z8F48xx with 48KB Flash, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0° to 70°C
Z8F4821PM020SC
Z8F4821AN020SC
Z8F4821VN020SC
Z8F4822AR020SC
Z8F4822VS020SC
Z8F4823FT020SC
48KB 4KB 29 23
48KB 4KB 31 23
48KB 4KB 31 23
48KB 4KB 46 24
48KB 4KB 46 24
48KB 4KB 60 24
3
3
3
4
4
4
8
8
1
1
1
1
1
1
1
1
1
1
1
1
2 PDIP 40-pin package
2 LQFP 44-pin package
2 PLCC 44-pin package
2 LQFP 64-pin package
2 PLCC 68-pin package
2 QFP 80-pin package
8
12
12
12
Extended Temperature: -40° to 105°C
Z8F4821PM020EC
Z8F4821AN020EC
Z8F4821VN020EC
Z8F4822AR020EC
Z8F4822VS020EC
Z8F4823FT020EC
48KB 4KB 29 23
3
3
3
4
4
4
8
8
1
1
1
1
1
1
1
1
1
1
1
1
2 PDIP 40-pin package
2 LQFP 44-pin package
2 PLCC 44-pin package
2 LQFP 64-pin package
2 PLCC 68-pin package
2 QFP 80-pin package
48KB 4KB 31 23
48KB 4KB 31 23
48KB 4KB 46 24
48KB 4KB 46 24
48KB 4KB 60 24
8
12
12
12
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Packaging
Z8 Encore!® 64K Series
Product Specification
269
Z8F64xx with 64KB Flash, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0° to 70°C
Z8F6421PM020SC
Z8F6421AN020SC
Z8F6421VN020SC
Z8F6422AR020SC
Z8F6422VS020SC
Z8F6423FT020SC
64KB 4KB 29 23
64KB 4KB 31 23
64KB 4KB 31 23
64KB 4KB 46 24
64KB 4KB 46 24
64KB 4KB 60 24
3
3
3
4
4
4
8
8
1
1
1
1
1
1
1
1
1
1
1
1
2 PDIP 40-pin package
2 LQFP 44-pin package
2 PLCC 44-pin package
2 LQFP 64-pin package
2 PLCC 68-pin package
2 QFP 80-pin package
8
12
12
12
Extended Temperature: -40° to 105°C
Z8F6421PM020EC
Z8F6421AN020EC
Z8F6421VN020EC
Z8F6422AR020EC
Z8F6422VS020EC
Z8F6423FT020EC
64KB 4KB 29 23
3
3
3
4
4
4
8
8
1
1
1
1
1
1
1
1
1
1
1
1
2 PDIP 40-pin package
2 LQFP 44-pin package
2 PLCC 44-pin package
2 LQFP 64-pin package
2 PLCC 68-pin package
2 QFP 80-pin package
64KB 4KB 31 23
64KB 4KB 31 23
64KB 4KB 46 24
64KB 4KB 46 24
64KB 4KB 60 24
8
12
12
12
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Packaging
Z8 Encore!® 64K Series
Product Specification
270
Z8R16xx with 16KB ROM, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0° to 70°C
Z8R1621PM020SC
Z8R1621AN020SC
Z8R1621VN020SC
Z8R1622AR020SC
Z8R1622VS020SC
16KB 2KB 29 23
16KB 2KB 31 23
16KB 2KB 31 23
16KB 2KB 46 24
16KB 2KB 46 24
3
3
3
4
4
8
8
1
1
1
1
1
1
1
1
1
1
2 PDIP 40-pin package
2 LQFP 44-pin package
2 PLCC 44-pin package
2 LQFP 64-pin package
2 PLCC 68-pin package
8
12
12
Extended Temperature: -40° to +105°C
Z8R1621PM020EC
Z8R1621AN020EC
Z8R1621VN020EC
Z8R1622AR020EC
Z8R1622VS020EC
16KB 2KB 29 23
3
3
3
4
4
8
8
1
1
1
1
1
1
1
1
1
1
2 PDIP 40-pin package
2 LQFP 44-pin package
2 PLCC 44-pin package
2 LQFP 64-pin package
2 PLCC 68-pin package
16KB 2KB 31 23
16KB 2KB 31 23
16KB 2KB 46 24
16KB 2KB 46 24
8
12
12
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Z8 Encore!® 64K Series
Product Specification
271
Z8R24xx with 24KB ROM, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0° to 70°C
Z8R2421PM020SC
Z8R2421AN020SC
Z8R2421VN020SC
Z8R2422AR020SC
Z8R2422VS020SC
24KB 2KB
24KB 2KB
24KB 2KB
24KB 2KB
24KB 2KB
29 23
31 23
31 23
46 24
46 24
3
3
3
4
4
8
8
1
1
1
1
1
1
1
1
1
1
2 PDIP 40-pin package
2 LQFP 44-pin package
2 PLCC 44-pin package
2 LQFP 64-pin package
2 PLCC 68-pin package
8
12
12
Extended Temperature: -40° to +105°C
Z8R2421PM020EC
Z8R2421AN020EC
Z8R2421VN020EC
Z8R2422AR020EC
Z8R2422VS020EC
24KB 2KB
24KB 2KB
24KB 2KB
24KB 2KB
24KB 2KB
29 23
31 23
31 23
46 24
46 24
3
3
3
4
4
8
8
1
1
1
1
1
1
1
1
1
1
2 PDIP 40-pin package
2 LQFP 44-pin package
2 PLCC 44-pin package
2 LQFP 64-pin package
2 PLCC 68-pin package
8
12
12
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Z8 Encore!® 64K Series
Product Specification
272
Z8R32xx with 32KB ROM, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0° to 70°C
Z8R3221PM020SC
Z8R3221AN020SC
Z8R3221VN020SC
Z8R3222AR020SC
Z8R3222VS020SC
32KB 2KB 29 23
32KB 2KB 31 23
32KB 2KB 31 23
32KB 2KB 46 24
32KB 2KB 46 24
3
3
3
4
4
8
8
1
1
1
1
1
1
1
1
1
1
2 PDIP 40-pin package
2 LQFP 44-pin package
2 PLCC 44-pin package
2 LQFP 64-pin package
2 PLCC 68-pin package
8
12
12
Extended Temperature: -40° to +105°C
Z8R3221PM020EC
Z8R3221AN020EC
Z8R3221VN020EC
Z8R3222AR020EC
Z8R3222VS020EC
32KB 2KB 29 23
3
3
3
4
4
8
8
1
1
1
1
1
1
1
1
1
1
2 PDIP 40-pin package
2 LQFP 44-pin package
2 PLCC 44-pin package
2 LQFP 64-pin package
2 PLCC 68-pin package
32KB 2KB 31 23
32KB 2KB 31 23
32KB 2KB 46 24
32KB 2KB 46 24
8
12
12
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Packaging
Z8 Encore!® 64K Series
Product Specification
273
Z8R48xx with 48KB ROM, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0° to 70°C
Z8R4821PM020SC
Z8R4821AN020SC
Z8R4821VN020SC
Z8R4822AR020SC
Z8R4822VS020SC
Z8R4823FT020SC
48KB 4KB 29 23
48KB 4KB 31 23
48KB 4KB 31 23
48KB 4KB 46 24
48KB 4KB 46 24
48KB 4KB 60 24
3
3
3
4
4
4
8
8
1
1
1
1
1
1
1
1
1
1
1
1
2 PDIP 40-pin package
2 LQFP 44-pin package
2 PLCC 44-pin package
2 LQFP 64-pin package
2 PLCC 68-pin package
2 QFP 80-pin package
8
12
12
12
Extended Temperature: -40° to 105°C
Z8R4821PM020EC
Z8R4821AN020EC
Z8R4821VN020EC
Z8R4822AR020EC
Z8R4822VS020EC
Z8R4823FT020EC
48KB 4KB 29 23
3
3
3
4
4
4
8
8
1
1
1
1
1
1
1
1
1
1
1
1
2 PDIP 40-pin package
2 LQFP 44-pin package
2 PLCC 44-pin package
2 LQFP 64-pin package
2 PLCC 68-pin package
2 QFP 80-pin package
48KB 4KB 31 23
48KB 4KB 31 23
48KB 4KB 46 24
48KB 4KB 46 24
48KB 4KB 60 24
8
12
12
12
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Packaging
Z8 Encore!® 64K Series
Product Specification
274
Z8R64xx with 64KB ROM, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0° to 70°C
Z8R6421PM020SC
Z8R6421AN020SC
Z8R6421VN020SC
Z8R6422AR020SC
Z8R6422VS020SC
Z8R6423FT020SC
64KB 4KB 29 23
64KB 4KB 31 23
64KB 4KB 31 23
64KB 4KB 46 24
64KB 4KB 46 24
64KB 4KB 60 24
3
3
3
4
4
4
8
8
1
1
1
1
1
1
1
1
1
1
1
1
2 PDIP 40-pin package
2 LQFP 44-pin package
2 PLCC 44-pin package
2 LQFP 64-pin package
2 PLCC 68-pin package
2 QFP 80-pin package
8
12
12
12
Extended Temperature: -40° to 105°C
Z8R6421PM020EC
Z8R6421AN020EC
Z8R6421VN020EC
Z8R6422AR020EC
Z8R6422VS020EC
Z8R6423FT020EC
Z8F64200100KIT
64KB 4KB 29 23
3
3
3
4
4
4
8
8
1
1
1
1
1
1
1
1
1
1
1
1
2 PDIP 40-pin package
2 LQFP 44-pin package
2 PLCC 44-pin package
2 LQFP 64-pin package
2 PLCC 68-pin package
2 QFP 80-pin package
Development Kit
64KB 4KB 31 23
64KB 4KB 31 23
64KB 4KB 46 24
64KB 4KB 46 24
64KB 4KB 60 24
8
12
12
12
For technical and customer support, hardware and software development tools, visit the
ZiLOG web site at www.zilog.com. The latest released version of ZDS can be down-
loaded from this site.
PS019913-0305
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Z8 Encore!® 64K Series
Product Specification
275
Part Number Suffix Designations
Z8
F
64 21
A
N 020 S
C
Environmental Flow: C = Plastic Standard
Temperature Range (°C):
S = Standard, 0 to 70
E = Extended, -40 to +105
Speed:
020 = 20MHz
Pin Count:
M = 40 pins
N = 44 pins
R = 64 pins
S = 68 pins
T = 80 pins
Package:
A = LQFP
F = QFP
P = PDIP
V = PLCC
Device Type
Memory Size:
64KB Flash/ROM, 4KB RAM
48KB Flash/ROM, 4KB RAM
32KB Flash/ROM, 2KB RAM
24KB Flash/ROM, 2KB RAM
16KB Flash/ROM, 2KB RAM
Memory Type:
F = Flash
R = Read-Only Memory
Device Family
Example: Part number Z8F6421AN020SC is an 8-bit microcontroller product in an LQFP package,
using 44 pins, operating with a maximum 20MHz external clock frequency over a 0ºC to +70ºC
temperature range and built using the Plastic-Standard environmental flow.
Precharacterization Product
The product represented by this document is newly introduced and ZiLOG has not com-
pleted the full characterization of the product. The document states what ZiLOG knows
PS019913-0305
P r e l i m i n a r y
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Z8 Encore!® 64K Series
Product Specification
276
about this product at this time, but additional features or nonconformance with some
aspects of the document might be found, either by ZiLOG or its customers in the course of
further application and characterization work. In addition, ZiLOG cautions that delivery
might be uncertain at times, due to start-up yield issues.
ZiLOG, Inc.
532 Race Street
San Jose, CA 95126
Telephone (408) 558-8500
FAX 408 558-8300
Internet: www.zilog.com
Document Information
Document Number Description
The Document Control Number that appears in the footer on each page of this document
contains unique identifying attributes, as indicated in the following table:
PS
0199 Unique Document Number
07 Revision Number
0204 Month and Year Published
Product Specification
PS019913-0305
P r e l i m i n a r y
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Z8 Encore!® 64K Series
Product Specification
277
Customer Feedback Form
The Z8 Encore!® 64K Series Product Specification
If you experience any problems while operating this product, or if you note any inaccuracies while reading
this Product Specification, please copy and complete this form, then mail or fax it to ZiLOG (see Return
Information, below). We also welcome your suggestions!
Customer Information
Name
Country
Phone
Fax
Company
Address
City/State/Zip
E-Mail
Product Information
Part #, Serial #, Board Fab #, or Rev. #
Software Version
Document Number
Host Computer Description/Type
PS019913-0305
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Z8 Encore!® 64K Series
Product Specification
278
Return Information
ZiLOG, Inc.
532 Race Street
San Jose, CA 95126
Fax: (408) 558-8536
Problem Description or Suggestion
Provide a complete description of the problem or your suggestion. If you are reporting a specific problem,
include all steps leading up to the occurrence of the problem. Attach additional pages as necessary.
______________________________________________________________________________________
______________________________________________________________________________________
______________________________________________________________________________________
______________________________________________________________________________________
______________________________________________________________________________________
______________________________________________________________________________________
______________________________________________________________________________________
______________________________________________________________________________________
______________________________________________________________________________________
______________________________________________________________________________________
______________________________________________________________________________________
PS019913-0305
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Packaging
Z8 Encore!® 64K Series
Product Specification
279
additional symbols 239
address space 17
ADDX 241
Index
analog signals 14
Symbols
# 239
% 239
@ 239
analog-to-digital converter (ADC) 170
AND 244
ANDX 244
arithmetic instructions 241
assembly language programming 236
assembly language syntax 237
Numerics
10-bit ADC 4
B
B 239
b 238
40-lead plastic dual-inline package 260
44-lead low-profile quad flat package 261
44-lead plastic lead chip carrier package 262
64-lead low-profile quad flat package 262
68-lead plastic lead chip carrier package 263
80-lead quad flat package 264
baud rate generator, UART 108
BCLR 242
binary number suffix 239
BIT 242
bit 238
clear 242
A
manipulation instructions 242
set 242
set or clear 242
swap 242
absolute maximum ratings 211
AC characteristics 227
ADC 241
architecture 170
test and jump 244
test and jump if non-zero 244
test and jump if zero 244
bit jump and test if non-zero 244
bit swap 245
block diagram 3
block transfer instructions 242
BRK 244
BSET 242
BSWAP 242, 245
BTJ 244
BTJNZ 244
BTJZ 244
automatic power-down 171
block diagram 171
continuous conversion 172
control register 174
control register definitions 174
data high byte register 175
data low bits register 175
DMA control 173
electrical characteristics and timing 225
operation 171
single-shot conversion 172
ADCCTL register 174
ADCDH register 175
ADCDL register 175
ADCX 241
C
ADD 241
add - extended addressing 241
add with carry 241
CALL procedure 244
capture mode 89
add with carry - extended addressing 241
capture/compare mode 89
PS019913-0305
P r e l i m i n a r y
Index
Z8 Encore!® 64K Series
Product Specification
280
cc 238
direct address 238
CCF 243
characteristics, electrical 211
clear 243
direct memory access controller 160
disable interrupts 243
DJNZ 244
clock phase (SPI) 127
CLR 243
COM 244
compare 89
compare - extended addressing 241
compare mode 89
DMA
address high nibble register 164
configuring for DMA_ADC data transfer 162
confiigurting DMA0-1 data transfer 161
control of ADC 173
control register 162
compare with carry 241
compare with carry - extended addressing 241
complement 244
complement carry flag 242, 243
condition code 238
continuous conversion (ADC) 172
continuous mode 89
control register definition, UART 109
control register, I2C 154
counter modes 89
control register definitions 162
controller 5
DMA_ADC address register 166
DMA_ADC control register 167
DMA_ADC operation 161
end address low byte register 165
I/O address register 164
operation 160
start/current address low byte register 165
status register 168
CP 241
CPC 241
CPCX 241
CPU and peripheral overview 3
CPU control instructions 243
CPX 241
customer feedback form 277
customer information 277
DMAA_STAT register 168
DMAACTL register 167
DMAxCTL register 163
DMAxEND register 166
DMAxH register 164
DMAxI/O address (DMAxIO) 164
DMAxIO register 164
DMAxSTART register 165
document number description 276
dst 239
D
DA 238, 241
E
EI 243
data register, I2C 151
DC characteristics 214
debugger, on-chip 195
DEC 241
electrical characteristics 211
ADC 225
decimal adjust 241
decrement 241
decrement and jump non-zero 244
decrement word 241
DECW 241
flash memory and timing 224
GPIO input data sample timing 228
watch-dog timer 224
enable interrupt 243
ER 238
destination operand 239
device, port availability 51
DI 243
extended addressing register 238
external pin reset 46
external RC oscillator 223
PS019913-0305
P r e l i m i n a r y
Index
Z8 Encore!® 64K Series
Product Specification
281
eZ8 CPU features 3
architecture 52
eZ8 CPU instruction classes 241
eZ8 CPU instruction notation 237
eZ8 CPU instruction set 236
eZ8 CPU instruction summary 245
control register definitions 54
input data sample timing 228
interrupts 54
port A-H address registers 55
port A-H alternate function sub-registers 57
port A-H control registers 56
F
port A-H data direction sub-registers 57
port A-H high drive enable sub-registers 59
port A-H input data registers 60
port A-H output control sub-registers 58
port A-H output data registers 61
port A-H STOP mode recovery sub-registers 59
port availability by device 51
port input timing 228
FCTL register 184
features, Z8 Encore! 1
first opcode map 258
FLAGS 239
flags register 239
flash
controller 4
port output timing 229
option bit address space 191
option bit configuration - reset 191
program memory address 0000H 192
program memory address 0001H 194
flash memory
H
H 239
arrangement 178
HALT 243
byte programming 181
code protection 180
halt mode 50, 243
hexadecimal number prefix/suffix 239
configurations 177, 189
control register definitions 184
controller bypass 183
electrical characteristics and timing 224
flash control register 184
flash status register 185
frequency high and low byte registers 188
mass erase 183
I
I2C 4
10-bit address read transaction 149
10-bit address transaction 146
10-bit addressed slave data transfer format 146
10-bit receive data format 149
7-bit address transaction 144
7-bit address, reading a transaction 148
7-bit addressed slave data transfer format 143,
144, 145
operation 179
operation timing 180
page erase 182
page select register 186, 190
FPS register 186, 190
FSTAT register 185
7-bit receive data transfer format 148
baud high and low byte registers 155, 157, 159
C status register 152
control register definitions 151
controller 138
G
gated mode 89
controller signals 13
general-purpose I/O 51
GPIO 4, 51
interrupts 140
operation 139
SDA and SCL signals 140
alternate functions 52
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P r e l i m i n a r y
Index
Z8 Encore!® 64K Series
Product Specification
282
stop and start conditions 142
I2CBRH register 155, 157, 159
I2CBRL register 156
I2CCTL register 154
I2CDATA register 152
I2CSTAT register 152
IM 238
immediate data 238
immediate operand prefix 239
INC 241
CPC 241
CPCX 241
CPU control 243
CPX 241
DA 241
DEC 241
DECW 241
DI 243
DJNZ 244
EI 243
increment 241
increment word 241
INCW 241
HALT 243
INC 241
INCW 241
IRET 244
JP 244
indexed 238
indirect address prefix 239
indirect register 238
indirect register pair 238
indirect working register 238
indirect working register pair 238
infrared encoder/decoder (IrDA) 119
instruction set, ez8 CPU 236
instructions
LD 243
LDC 243
LDCI 242, 243
LDE 243
LDEI 242
LDX 243
LEA 243
load 243
ADC 241
ADCX 241
ADD 241
ADDX 241
AND 244
logical 244
MULT 241
NOP 243
OR 244
ANDX 244
arithmetic 241
BCLR 242
ORX 244
POP 243
POPX 243
BIT 242
program control 244
PUSH 243
PUSHX 243
RCF 242, 243
RET 244
bit manipulation 242
block transfer 242
BRK 244
BSET 242
BSWAP 242, 245
BTJ 244
RL 245
RLC 245
BTJNZ 244
BTJZ 244
rotate and shift 245
RR 245
CALL 244
RRC 245
CCF 242, 243
CLR 243
COM 244
SBC 242
SCF 242, 243
SRA 245
CP 241
SRL 245
PS019913-0305
P r e l i m i n a r y
Index
Z8 Encore!® 64K Series
Product Specification
283
SRP 243
STOP 243
transmitting data 120
IRET 244
IRQ0 enable high and low bit registers 69
IRQ1 enable high and low bit registers 70
IRQ2 enable high and low bit registers 71
IRR 238
SUB 242
SUBX 242
SWAP 245
TCM 242
Irr 238
TCMX 242
TM 242
TMX 242
J
TRAP 244
watch-dog timer refresh 243
XOR 244
JP 244
jump, conditional, relative, and relative conditional
244
XORX 244
instructions, eZ8 classes of 241
interrupt control register 74
interrupt controller 5, 62
architecture 62
L
LD 243
interrupt assertion types 65
interrupt vectors and priority 65
operation 64
LDC 243
LDCI 242, 243
LDE 243
register definitions 66
software interrupt assertion 65
interrupt edge select register 72
interrupt port select register 73
interrupt request 0 register 66
interrupt request 1 register 67
interrupt request 2 register 68
interrupt return 244
interrupt vector listing 62
interrupts
LDEI 242, 243
LDX 243
LEA 243
load 243
load constant 242
load constant to/from program memory 243
load constant with auto-increment addresses 243
load effective address 243
load external data 243
load external data to/from data memory and auto-
increment addresses 242
load external to/from data memory and auto-incre-
ment addresses 243
not acknowledge 140
receive 140
SPI 130
transmit 140
load instructions 243
UART 106
introduction 1
load using extended addressing 243
logical AND 244
IR 238
Ir 238
IrDA
logical AND/extended addressing 244
logical exclusive OR 244
logical exclusive OR/extended addressing 244
logical instructions 244
logical OR 244
architecture 119
block diagram 119
control register definitions 123
operation 120
logical OR/extended addressing 244
low power modes 49
receiving data 121
LQFP
PS019913-0305
P r e l i m i n a r y
Index
Z8 Encore!® 64K Series
Product Specification
284
44 lead 261
64 lead 262
vector 238
X 238
notational shorthand 238
M
O
OCD
master interrupt enable 64
master-in, slave-out and-in 126
memory
architecture 195
program 18
MISO 126
auto-baud detector/generator 198
baud rate limits 198
mode
block diagram 195
capture 89
breakpoints 199
capture/compare 89
continuous 89
counter 89
commands 200
control register 204
data format 198
gated 89
one-shot 89
DBG pin to RS-232 Interface 196
debug mode 197
PWM 89
debugger break 244
modes 89
interface 196
MOSI 126
serial errors 199
MULT 241
status register 206
multiply 241
timing 230
multiprocessor mode, UART 104
OCD commands
execute instruction (12H) 204
read data memory (0DH) 203
read OCD control register (05H) 202
read OCD revision (00H) 201
read OCD status register (02H) 201
read program counter (07H) 202
read program memory (0BH) 203
read program memory CRC (0EH) 204
read register (09H) 202
step instruction (10H) 204
stuff instruction (11H) 204
write data memory (0CH) 203
write OCD control register (04H) 201
write program counter (06H) 202
write program memory (0AH) 202
write register (08H) 202
on-chip debugger 5
N
NOP (no operation) 243
not acknowledge interrupt 140
notation
b 238
cc 238
DA 238
ER 238
IM 238
IR 238
Ir 238
IRR 238
Irr 238
p 238
R 238
r 238
on-chip debugger (OCD) 195
on-chip debugger signals 15
on-chip oscillator 207
RA 238
RR 238
rr 238
one-shot mode 89
PS019913-0305
P r e l i m i n a r y
Index
Z8 Encore!® 64K Series
Product Specification
285
opcode map
abbreviations 257
power-on reset (POR) 44
problem description or suggestion 278
product information 277
program control instructions 244
program counter 239
program memory 18
cell description 256
first 258
second after 1FH 259
Operational Description 98
OR 244
PUSH 243
ordering information 265
ORX 244
push using extended addressing 243
PUSHX 243
oscillator signals 14
PWM mode 89
PxADDR register 55
PxCTL register 56
P
p 238
packaging
Q
QFP 264
LQFP
44 lead 261
64 lead 262
PDIP 260
PLCC
R
R 238
44 lead 262
68 lead 263
r 238
RA
register address 238
QFP 264
RCF 242, 243
receive
part number description 275
part selection guide 2
PC 239
10-bit data format (I2C) 149
7-bit data transfer format (I2C) 148
IrDA data 121
PDIP 260
peripheral AC and DC electrical characteristics 222
PHASE=0 timing (SPI) 128
PHASE=1 timing (SPI) 129
pin characteristics 16
PLCC
receive interrupt 140
receiving UART data-interrupt-driven method 103
receiving UART data-polled method 102
register 135, 164, 238
ADC control (ADCCTL) 174
ADC data high byte (ADCDH) 175
ADC data low bits (ADCDL) 175
baud low and high byte (I2C) 155, 157, 159
baud rate high and low byte (SPI) 137
control (SPI) 132
44 lead 262
68-lead 263
polarity 238
POP 243
pop using extended addressing 243
POPX 243
control, I2C 154
data, SPI 131
DMA status (DMAA_STAT) 168
DMA_ADC address 166
DMA_ADC control DMAACTL) 167
DMAx address high nibble (DMAxH) 164
port availability, device 51
port input timing (GPIO) 228
port output timing, GPIO 229
power supply signals 15
power-down, automatic (ADC) 171
power-on and voltage brown-out 222
PS019913-0305
P r e l i m i n a r y
Index
Z8 Encore!® 64K Series
Product Specification
286
DMAx control (DMAxCTL) 163
DMAx end/address low byte (DMAxEND) 166
DMAx start/current address low byte register
(DMAxSTART) 165
flash control (FCTL) 184
flash high and low byte (FFREQH and FRE-
EQL) 188
register pair 238
register pointer 239
reset
and STOP mode characteristics 43
and STOP mode recovery 43
carry flag 242
controller 5
flash page select (FPS) 186, 190
flash status (FSTAT) 185
sources 44
RET 244
return 244
return information 278
RL 245
GPIO port A-H address (PxADDR) 55
GPIO port A-H alternate function sub-registers
57
RLC 245
ROM
code protection 189
control register definitions 190
rotate and shift instructions 245
rotate left 245
GPIO port A-H control address (PxCTL) 56
GPIO port A-H data direction sub-registers 57
I2C baud rate high (I2CBRH) 155, 157, 159
I2C control (I2CCTL) 154
I2C data (I2CDATA) 152
I2C status 152
rotate left through carry 245
rotate right 245
rotate right through carry 245
RP 239
I2C status (I2CSTAT) 152
I2Cbaud rate low (I2CBRL) 156
mode, SPI 135
OCD control 204
RR 238, 245
OCD status 206
rr 238
RRC 245
SPI baud rate high byte (SPIBRH) 137
SPI baud rate low byte (SPIBRL) 137
SPI control (SPICTL) 133
SPI data (SPIDATA) 132
SPI status (SPISTAT) 134
status, I2C 152
S
SBC 242
status, SPI 134
SCF 242, 243
UARTx baud rate high byte (UxBRH) 115
UARTx baud rate low byte (UxBRL) 116
UARTx Control 0 (UxCTL0) 112, 115
UARTx control 1 (UxCTL1) 113
UARTx receive data (UxRXD) 110
UARTx status 0 (UxSTAT0) 110
UARTx status 1 (UxSTAT1) 112
UARTx transmit data (UxTXD) 109
watch-dog timer control (WDTCTL) 94
watch-dog timer reload high byte (WDTH) 96
watch-dog timer reload low byte (WDTL) 97
watch-dog timer reload upper byte (WDTU) 96
SCK 126
SDA and SCL (IrDA) signals 140
second opcode map after 1FH 259
serial clock 126
serial peripheral interface (SPI) 124
set carry flag 242, 243
set register pointer 243
shift right arithmetic 245
shift right logical 245
signal descriptions 13
single-shot conversion (ADC) 172
SIO 5
register file 17
register file address map 21
slave data transfer formats (I2C) 146
slave select 127
PS019913-0305
P r e l i m i n a r y
Index
Z8 Encore!® 64K Series
Product Specification
287
software trap 244
source operand 239
SP 239
using a GPIO port pin transition 48
using watch-dog timer time-out 48
SUB 242
SPI
subtract 242
subtract - extended addressing 242
subtract with carry 242
subtract with carry - extended addressing 242
SUBX 242
architecture 124
baud rate generator 131
baud rate high and low byte register 137
clock phase 127
SWAP 245
swap nibbles 245
symbols, additional 239
system and core resets 44
configured as slave 125
control register 132
control register definitions 131
data register 131
error detection 130
interrupts 130
T
mode fault error 130
mode register 135
multi-master operation 129
operation 125
overrun error 130
signals 126
TCM 242
TCMX 242
test complement under mask 242
test complement under mask - extended addressing
242
single master, multiple slave system 125
single master, single slave system 124
status register 134
timing, PHASE = 0 128
timing, PHASE=1 129
SPI controller signals 13
SPI mode (SPIMODE) 135
SPIBRH register 137
SPIBRL register 137
SPICTL register 133
SPIDATA register 132
SPIMODE register 135
SPISTAT register 134
SRA 245
test under mask 242
test under mask - extended addressing 242
timer signals 14
timers 5, 75
architecture 75
block diagram 76
capture mode 80, 89
capture/compare mode 83, 89
compare mode 81, 89
continuous mode 77, 89
counter mode 78
counter modes 89
gated mode 82, 89
one-shot mode 76, 89
operating mode 76
src 239
SRL 245
PWM mode 79, 89
SRP 243
SS, SPI signal 126
stack pointer 239
status register, I2C 152
STOP 243
reading the timer count values 84
reload high and low byte registers 85
timer control register definitions 84
timer output signal operation 84
timers 0-3
STOP mode 49, 243
STOP mode recovery
sources 47
control 0 registers 88
control 1 registers 88
high and low byte registers 84, 87
PS019913-0305
P r e l i m i n a r y
Index
Z8 Encore!® 64K Series
Product Specification
288
TM 242
TMX 242
transmit
voltage brown-out reset (VBR) 45
IrDA data 120
transmit interrupt 140
transmitting UART data-interrupt-driven method
W
watch-dog timer
approximate time-out delay 92
approximate time-out delays 91
CNTL 46
101
transmitting UART data-polled method 100
TRAP 244
control register 94
electrical characteristics and timing 224
interrupt in normal operation 92
interrupt in STOP mode 92
operation 91
U
UART 4
architecture 98
asynchronous data format without/with parity
100
baud rate generator 108
baud rates table 116
control register definitions 109
controller signals 14
refresh 92, 243
reload unlock sequence 93
reload upper, high and low registers 95
reset 46
reset in normal operation 93
reset in STOP mode 93
time-out response 92
WDTCTL register 94
WDTH register 96
data format 99
interrupts 106
multiprocessor mode 104
receiving data using interrupt-driven method
103
receiving data using the polled method 102
transmitting data using the interrupt-driven
method 101
WDTL register 97
working register 238
working register pair 238
WTDU register 96
transmitting data using the polled method 100
x baud rate high and low registers 115
x control 0 and control 1 registers 112
x status 0 and status 1 registers 110, 112
UxBRH register 115
X
X 238
UxBRL register 116
UxCTL0 register 112, 115
UxCTL1 register 113
XOR 244
XORX 244
UxRXD register 110
UxSTAT0 register 110
UxSTAT1 register 112
UxTXD register 109
Z
Z8 Encore!
block diagram 3
features 1
V
introduction 1
part selection guide 2
vector 238
PS019913-0305
P r e l i m i n a r y
Index
相关型号：
Z8R4821PM020EG
IC 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP40, PLASTIC, DIP-40, Microcontroller
IXYS
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