Z8S18010FEG [IXYS]
IC 8-BIT, 10 MHz, MICROPROCESSOR, PQFP80, QFP-80, Microprocessor;
| 型号： | Z8S18010FEG |
| 厂家： | 
IXYS CORPORATION |
| 描述： | IC 8-BIT, 10 MHz, MICROPROCESSOR, PQFP80, QFP-80, Microprocessor |
| 文件： | 总71页 (文件大小：531K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24'.+/+0#4;ꢀ241&7%6ꢀ52'%+(+%#6+10
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'0*#0%'&ꢅ<ꢄꢆꢀꢅ/+%41241%'5514
1(('45ꢅ(#56'4ꢅ':'%76+10ꢇ
219'4ꢃ5#8'4ꢅ/1&'ꢇꢅ.19ꢅ'/+
('#674'5
®
Code Compatible with ZiLOG Z80 CPU
Extended Instructions
Two 16-Bit Counter/Timers
Two Enhanced UARTs (up to 512 Kbps)
Clock Speeds: 10, 20, 33 MHz
Two Chain-Linked DMA Channels
Low Power-Down Modes
Operating Range: 5V (3.3V@ 20 MHz)
Operating Temperature Range: 0°C to +70°C
–40°C to +85°C Extended Temperature Range
Three Packaging Styles
On-Chip Interrupt Controllers
Three On-Chip Wait-State Generators
On-Chip Oscillator/Generator
Expanded MMU Addressing (Up to 1 MB)
Clocked Serial I/O Port
–
–
–
68-Pin PLCC
64-Pin DIP
80-Pin QFP
)'0'4#.ꢄ&'5%4+26+10
™
three modes intended to further reduce power consumption.
Power consumption during 56#0&$; Mode is reduced to
10 µA by stopping the external oscillators and internal
clock. The 5.''2 mode reduces power by placing the CPU
into a stopped state, consuming less current while the on-
chip I/O devices still operate. The 5;56'/ꢅ5612 mode
places both the CPU and the on-chip peripherals into a
stopped mode, reducing power consumption even further.
The enhanced Z8S180/Z8L180 significantly improves on
previous Z80180 models, while still providing full back-
ward compatibility with existing ZiLOG Z80 devices. The
Z8S180/Z8L180 now offers faster execution speeds, pow-
er-saving modes, and EMI noise reduction.
™
This enhanced Z180 design also incorporates additional
feature enhancements to the ASCIs, DMAs, and 56#0&$;
mode power consumption. With the addition of ESCC-like
BaudRateGenerators(BRGs),thetwoASCIsoffertheflex-
ibility and capability to transfer data asynchronously atrates
of up to 512 Kbps. In addition, the ASCI receiver features
a 4-byte first in/first out (FIFO) buffer which reduces the
likelihoodofoverrunerrors.TheDMAshavebeenmodified
to allow for chain-linking of the two DMA channels when
set to take their DMA requests from the same peripherals
device. This feature allows for nonstop DMA operation be-
tween the two DMA channels.
A new clock-doubler feature in the Z8S180/Z8L180 allows
the internal clock speed to be twice the external clock speed.
As a result, system cost is reduced by allowing the use of
lower-cost, lower-frequency crystals.
The Enhanced Z180 is housed in 80-pin QFP, 68-pin PLCC,
and 64-pin DIP packages.
0QVGꢅ All Signals with an overline are active Low. For exam-
ple: B/W, in which WORD is active Low; or B/W, in
which BYTE is active Low.
NotonlydoestheZ8S180/Z8L180consumelesspowerdur-
ing normal operations than the previous model, it offers
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
ꢄ
ꢅꢅꢅꢅꢅꢅ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
)'0'4#.ꢄ&'5%4+26+10ꢄꢈ%QPVKPWGFꢉ
Powerconnectionsfollowtheconventionaldescriptionsbe-
low:
%QPPGEVKQP
2QYGT
%KTEWKV
8
&GXKEG
8
8
)TQWPF
)0&
$WUꢅ5VCVGꢅ%QPVTQN
+PVGTTWRV
ꢅ
ꢅ
6KOKPI
ꢅꢅ
2*+
)GPGTCVQT
%27
&4'3ꢄ
6'0&ꢄ
ꢄꢁꢃ$KV
&/#%U
ꢈꢂꢉ
2TQITCOOCDNG
#ꢄꢆꢌ6
4GNQCFꢅ6KOGTU
ꢅ
ꢈꢂꢉ
ꢅꢅꢅꢅꢅꢅꢅꢅꢅꢅ
6:5
4:5ꢌ%65ꢄ
%-5
6:#ꢀ
%NQEMGF
ꢅ
5GTKCNꢅ+ꢌ1
ꢅ
%-#ꢀꢇꢅ&4'3ꢀ
4:#ꢀ
2QTV
#U[PEJTQPQWU
5%+
ꢈ%JCPPGNꢅꢄꢉ
ꢅꢅꢅꢅ
465ꢀ
%65ꢀ
&%&ꢀ
6:#ꢄ
#U[PEJTQPQWU
//7
%-#ꢄꢇꢅ6'0&ꢀ
4:#ꢄ
5%+
ꢈ%JCPPGNꢅꢄꢉ
ꢅ
8
8
&CVC
$WHHGT
#FFTGUU
$WHHGT
#ꢄꢋ #ꢀ
&ꢊ &ꢀ
(KIWTG ꢁꢆ <ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂꢄ(WPEVKQPCNꢄ$NQEMꢄ&KCITCO
ꢂ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
2+0ꢄ+&'06+(+%#6+10
8
2*+
4&
94
/ꢄ
1
64
:6#.
':6#.
9#+6
$75#%-
$754'3
4'5'6
0/+
'
/4'3
+143
4(5*
*#.6
6'0&ꢄ
&4'3ꢄ
%-5
+06ꢀ
+06ꢄ
+06ꢂ
56
4:5ꢌ%65ꢄ
6:5
%-#ꢄꢌ6'0&ꢀ
#ꢀ
#ꢄ
#ꢂ
#ꢍ
#ꢎ
#ꢏ
#ꢁ
#ꢊ
#ꢆ
#ꢋ
4:#ꢄ
6:#ꢄ
%-#ꢀꢌ&4'3ꢀ
4:#ꢀ
6:#ꢀ
&%&ꢀ
%65ꢀ
465ꢀ
&ꢊ
&ꢁ
&ꢏ
&ꢎ
&ꢍ
<ꢀ5ꢁꢀꢂꢄ
ꢈꢉꢊ2KPꢄ&+2
#ꢄꢀ
#ꢄꢄ
#ꢄꢂ
#ꢄꢍ
#ꢄꢎ
#ꢄꢏ
#ꢄꢁ
#ꢄꢊ
#ꢄꢆꢌ6
&ꢂ
&ꢄ
&ꢀ
32
33
8
8
(KIWTG ꢇꢆ <ꢀ5ꢁꢀꢂꢄꢈꢉꢊ2KPꢄ&+2ꢄ2KPꢄ%QPHKIWTCVKQP
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢍ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
2+0ꢄ+&'06+(+%#6+10ꢄꢈ%QPVKPWGFꢉ
ꢋ
ꢄꢀ
ꢄ
ꢁꢄ
ꢁꢀ
+06ꢀ
+06ꢄ
+06ꢂ
56
#ꢀ
#ꢄ
#ꢂ
#ꢍ
8
#ꢎ
#ꢏ
*#.6
6'0&ꢄ
&4'3ꢄ
%-5
4:5ꢌ%65ꢄ
6:5
%-#ꢄꢌ6'0&ꢀ
4:#ꢄ
6'56
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀ
ꢂ
ꢈꢀꢊ2KPꢄ2.%%
6:#ꢄ
%-#ꢀꢌ&4'3ꢀ
4:#ꢀ
#ꢁ
#ꢊ
#ꢆ
6:#ꢀ
&%&ꢀ
#ꢋ
#ꢄꢀ
#ꢄꢄ
%65ꢀ
465ꢀ
&ꢊ
ꢂꢁ
ꢂꢊ
ꢎꢎ
ꢎꢍ
(KIWTG ꢋꢆ <ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂꢄꢈꢀꢊ2KPꢄ2.%%ꢄ2KPꢄ%QPHKIWTCVKQP
ꢎ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
ꢁꢎ
ꢁꢏ
ꢏꢏ
ꢏꢀ
ꢎꢏ
ꢎꢄ
ꢁꢀ
ꢎꢀ
&ꢏ
+143
/4'3
'
&ꢎ
&ꢍ
&ꢂ
&ꢄ
&ꢀ
8
/ꢄ
94
4&
2*+
8
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
ꢀꢂꢊ2KPꢄ3(2
#ꢄꢋ
8
8
:6#.
0ꢌ%
':6#.
9#+6
$75#%-
$754'3
4'5'6
#ꢄꢆꢌ6
0%
#ꢄꢊ
#ꢄꢁ
#ꢄꢏ
#ꢄꢎ
ꢆꢀ
ꢂꢏ
ꢂꢎ
#ꢄꢍ
ꢄ
ꢏ
ꢄꢀ
ꢄꢏ
ꢂꢀ
(KIWTG ꢉꢆ <ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂꢄꢀꢂꢊ2KPꢄ3(2ꢄ2KPꢄ%QPHKIWTCVKQP
6CDNG ꢁꢆ <ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂꢄ2KPꢄ+FGPVKHKECVKQPꢄ
2KPꢄ0WODGTꢄCPFꢄ2CEMCIGꢄ6[RG
&GHCWNV
(WPEVKQP
5GEQPFCT[ꢄ
(WPEVKQP
3(2
2.%%
&+2
%QPVTQNꢄ
ꢄ
ꢂ
ꢋ
ꢆ
0/+
0%
ꢍ
0%
ꢎ
ꢄꢀ
ꢄꢄ
ꢄꢂ
ꢄꢍ
ꢄꢎ
ꢄꢏ
ꢄꢁ
ꢄꢊ
ꢄꢆ
ꢋ
+06ꢀ
+06ꢄ
+06ꢂ
56
ꢏ
ꢄꢀ
ꢄꢄ
ꢄꢂ
ꢄꢍ
ꢄꢎ
ꢄꢏ
ꢄꢁ
ꢁ
ꢊ
ꢆ
#ꢀ
ꢋ
#ꢄ
ꢄꢀ
ꢄꢄ
ꢄꢂ
#ꢂ
#ꢍ
8
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢏ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
2+0ꢄ+&'06+(+%#6+10ꢄꢈ%QPVKPWGFꢉ
6CDNG ꢁꢆ <ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂꢄ2KPꢄ+FGPVKHKECVKQPꢄꢌ%QPVKPWGFꢍ
2KPꢄ0WODGTꢄCPFꢄ2CEMCIGꢄ6[RG
&GHCWNV
(WPEVKQP
5GEQPFCT[ꢄ
(WPEVKQP
3(2
2.%%
&+2
%QPVTQNꢄ
ꢄꢍ
ꢄꢎ
ꢄꢏ
ꢄꢁ
ꢄꢊ
ꢄꢆ
ꢄꢋ
ꢂꢀ
ꢂꢄ
ꢂꢂ
ꢂꢍ
ꢂꢎ
ꢂꢏ
ꢂꢁ
ꢂꢊ
ꢂꢆ
ꢂꢋ
ꢍꢀ
ꢍꢄ
ꢄꢋ
ꢄꢊ
#ꢎ
0%
ꢂꢀ
ꢂꢄ
ꢂꢂ
ꢂꢍ
ꢂꢎ
ꢂꢏ
ꢂꢁ
ꢄꢆ
ꢄꢋ
ꢂꢀ
ꢂꢄ
ꢂꢂ
ꢂꢍ
ꢂꢎ
#ꢏ
#ꢁ
#ꢊ
#ꢆ
#ꢋ
#ꢄꢀ
#ꢄꢄ
0%
0%
ꢂꢊ
ꢂꢆ
ꢂꢋ
ꢍꢀ
ꢍꢄ
ꢍꢂ
ꢂꢏ
ꢂꢁ
ꢂꢊ
ꢂꢆ
ꢂꢋ
ꢍꢀ
#ꢄꢂ
#ꢄꢍ
#ꢄꢎ
#ꢄꢏ
#ꢄꢁ
#ꢄꢊ
0%
ꢍꢍ
ꢍꢎ
ꢍꢄ
ꢍꢂ
#ꢄꢆ
6
$KVꢅꢂꢅQTꢅ$KVꢅꢍꢅQHꢅ6%4
ꢍꢂ
8
ꢍꢍ
ꢍꢎ
ꢍꢏ
ꢍꢁ
#ꢄꢋ
8
ꢍꢍ
ꢍꢏ
ꢍꢁ
ꢍꢊ
ꢍꢆ
ꢍꢋ
ꢎꢀ
ꢎꢄ
ꢎꢂ
ꢎꢍ
ꢎꢎ
ꢎꢏ
ꢎꢁ
ꢎꢊ
ꢎꢆ
ꢎꢋ
ꢏꢀ
ꢏꢄ
ꢏꢂ
ꢍꢊ
ꢍꢆ
ꢍꢋ
ꢎꢀ
ꢎꢄ
ꢎꢂ
ꢎꢍ
ꢍꢎ
ꢍꢏ
ꢍꢁ
ꢍꢊ
ꢍꢆ
ꢍꢋ
ꢎꢀ
&ꢀ
&ꢄ
&ꢂ
&ꢍ
&ꢎ
&ꢏ
&ꢁ
0%
0%
ꢎꢎ
ꢎꢏ
ꢎꢁ
ꢎꢊ
ꢎꢆ
ꢎꢋ
ꢏꢀ
ꢎꢄ
ꢎꢂ
ꢎꢍ
ꢎꢎ
ꢎꢏ
ꢎꢁ
ꢎꢊ
&ꢊ
465ꢀ
%65ꢀ
&%&ꢀ
6:#ꢀ
4:#ꢀ
%-#ꢀ
0%
&4'3ꢀ
$KVꢅꢍꢅQTꢅ$KVꢅꢏꢅQHꢅ&/1&'
ꢏꢄ
ꢎꢆ
6:#ꢄ
ꢁ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
6CDNG ꢁꢆ <ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂꢄ2KPꢄ+FGPVKHKECVKQPꢄꢌ%QPVKPWGFꢍ
2KPꢄ0WODGTꢄCPFꢄ2CEMCIGꢄ6[RG
&GHCWNV
(WPEVKQP
5GEQPFCT[ꢄ
(WPEVKQP
3(2
2.%%
&+2
%QPVTQNꢄ
ꢏꢍ
ꢏꢎ
ꢏꢏ
ꢏꢁ
ꢏꢊ
ꢏꢆ
ꢏꢋ
ꢁꢀ
ꢁꢄ
ꢁꢂ
ꢁꢍ
ꢁꢎ
ꢁꢏ
ꢁꢁ
ꢁꢊ
ꢁꢆ
ꢁꢋ
ꢊꢀ
ꢊꢄ
ꢊꢂ
ꢏꢂ
ꢏꢍ
ꢏꢎ
ꢏꢏ
ꢏꢁ
ꢏꢊ
ꢏꢆ
ꢏꢋ
ꢁꢀ
6'56
4:#ꢄ
%-#ꢄ
6:5
4:5
%-5
&4'3ꢄ
6'0&ꢄ
*#.6
0%
ꢎꢋ
ꢏꢀ
ꢏꢄ
ꢏꢂ
ꢏꢍ
ꢏꢎ
ꢏꢏ
ꢏꢁ
6'0&ꢀ
%65ꢄ
$KVꢅꢎꢅQHꢅ%06.#ꢄ
$KVꢅꢂꢅQHꢅ56#6ꢄ
0%
ꢁꢄ
ꢁꢂ
ꢁꢍ
ꢁꢎ
ꢁꢏ
ꢁꢁ
ꢁꢊ
ꢁꢆ
ꢄ
ꢏꢊ
ꢏꢆ
ꢏꢋ
ꢁꢀ
ꢁꢄ
ꢁꢂ
ꢁꢍ
ꢁꢎ
ꢄ
4(5*
+143
/4'3
'
/ꢄ
94
4&
2*+
8
ꢊꢍ
ꢂ
ꢍ
8
ꢊꢎ
ꢊꢏ
ꢊꢁ
ꢊꢊ
ꢊꢆ
ꢊꢋ
ꢆꢀ
ꢂ
:6#.
0%
ꢎ
ꢏ
ꢁ
ꢊ
ꢆ
ꢍ
ꢎ
ꢏ
ꢁ
ꢊ
':6#.
9#+6
$75#%-
$754'3
4'5'6
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢊ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
2+0ꢄ+&'06+(+%#6+10ꢄꢈ%QPVKPWGFꢉ
6CDNG ꢇꢆ 2KPꢄ5VCVWUꢄ&WTKPIꢄ4'5'6ꢎꢄ$75#%-ꢎꢄCPFꢄ5.''2ꢄ/QFGU
2KPꢄ0WODGTꢄCPFꢄ2CEMCIGꢄ6[RG
2KPꢄ5VCVWU
&GHCWNVꢄ
(WPEVKQP
5GEQPFCT[ꢄ
(WPEVKQP
3(2
2.%%
&+2
4'5'6
$75#%-
5.''2
ꢄ
ꢂ
ꢋ
ꢆ
0/+
0%
+0
+0
+0
ꢍ
0%
ꢎ
ꢄꢀ
ꢄꢄ
ꢄꢂ
ꢄꢍ
ꢄꢎ
ꢄꢏ
ꢄꢁ
ꢄꢊ
ꢄꢆ
ꢋ
+06ꢀ
+06ꢄ
+06ꢂ
56
+0
+0
+0
+0
+0
+0
ꢏ
ꢄꢀ
ꢄꢄ
ꢄꢂ
ꢄꢍ
ꢄꢎ
ꢄꢏ
ꢄꢁ
ꢁ
+0
+0
+0
ꢊ
*KIJ
ꢍ6
ꢍ6
ꢍ6
ꢍ6
8
*KIJ
ꢍ6
ꢍ6
ꢍ6
ꢍ6
8
*KIJ
*KIJ
*KIJ
*KIJ
*KIJ
8
ꢆ
#ꢀ
ꢋ
#ꢄ
ꢄꢀ
ꢄꢄ
ꢄꢂ
#ꢂ
#ꢍ
8
ꢄꢍ
ꢄꢎ
ꢄꢏ
ꢄꢁ
ꢄꢊ
ꢄꢆ
ꢄꢋ
ꢂꢀ
ꢂꢄ
ꢂꢂ
ꢂꢍ
ꢂꢎ
ꢂꢏ
ꢂꢁ
ꢂꢊ
ꢂꢆ
ꢂꢋ
ꢍꢀ
ꢍꢄ
ꢄꢋ
ꢄꢊ
#ꢎ
0%
ꢍ6
ꢍ6
*KIJ
ꢂꢀ
ꢂꢄ
ꢂꢂ
ꢂꢍ
ꢂꢎ
ꢂꢏ
ꢂꢁ
ꢄꢆ
ꢄꢋ
ꢂꢀ
ꢂꢄ
ꢂꢂ
ꢂꢍ
ꢂꢎ
#ꢏ
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
*KIJ
*KIJ
*KIJ
*KIJ
*KIJ
*KIJ
*KIJ
#ꢁ
#ꢊ
#ꢆ
#ꢋ
#ꢄꢀ
#ꢄꢄ
0%
0%
ꢂꢊ
ꢂꢆ
ꢂꢋ
ꢍꢀ
ꢍꢄ
ꢍꢂ
ꢂꢏ
ꢂꢁ
ꢂꢊ
ꢂꢆ
ꢂꢋ
ꢍꢀ
#ꢄꢂ
#ꢄꢍ
#ꢄꢎ
#ꢄꢏ
#ꢄꢁ
#ꢄꢊ
0%
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
*KIJ
*KIJ
*KIJ
*KIJ
*KIJ
*KIJ
ꢍꢍ
ꢍꢄ
ꢍꢂ
ꢍꢍ
#ꢄꢆ
6
ꢍ6
ꢍ6
*KIJ
176
0ꢌ#
176
ꢍꢂ
ꢍꢎ
8
8
8
8
ꢍꢍ
ꢍꢎ
ꢍꢏ
ꢍꢁ
#ꢄꢋ
8
ꢍ6
8
ꢍ6
8
*KIJ
8
ꢍꢏ
ꢍꢁ
ꢍꢊ
ꢍꢆ
ꢍꢊ
ꢍꢆ
ꢍꢋ
ꢎꢀ
ꢍꢎ
ꢍꢏ
ꢍꢁ
ꢍꢊ
&ꢀ
&ꢄ
&ꢂ
&ꢍ
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢆ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
6CDNG ꢇꢆ 2KPꢄ5VCVWUꢄ&WTKPIꢄ4'5'6ꢎꢄ$75#%-ꢎꢄCPFꢄ5.''2ꢄ/QFGU ꢌ%QPVKPWGFꢍ
2KPꢄ0WODGTꢄCPFꢄ2CEMCIGꢄ6[RG
2KPꢄ5VCVWU
&GHCWNVꢄ
(WPEVKQP
5GEQPFCT[ꢄ
(WPEVKQP
3(2
2.%%
&+2
4'5'6
$75#%-
5.''2
ꢍꢋ
ꢎꢀ
ꢎꢄ
ꢎꢂ
ꢎꢍ
ꢎꢎ
ꢎꢏ
ꢎꢁ
ꢎꢊ
ꢎꢆ
ꢎꢋ
ꢏꢀ
ꢎꢄ
ꢎꢂ
ꢎꢍ
ꢍꢆ
ꢍꢋ
ꢎꢀ
&ꢎ
&ꢏ
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
ꢍ6
&ꢁ
0%
0%
ꢎꢎ
ꢎꢏ
ꢎꢁ
ꢎꢊ
ꢎꢆ
ꢎꢋ
ꢏꢀ
ꢎꢄ
ꢎꢂ
ꢎꢍ
ꢎꢎ
ꢎꢏ
ꢎꢁ
ꢎꢊ
&ꢊ
ꢍ6
*KIJ
+0
ꢍ6
176
176
+0
ꢍ6
*KIJ
+0
465ꢀ
%65ꢀ
&%&ꢀ
6:#ꢀ
4:#ꢀ
%-#ꢀ
&4'3ꢀ
0%
+0
+0
*KIJ
+0
176
+0
176
+0
ꢍ6
+ꢌ1
+ꢌ1
+0
0ꢌ#
+0
ꢏꢄ
ꢏꢂ
ꢏꢍ
ꢏꢎ
ꢏꢏ
ꢏꢄ
ꢏꢂ
ꢏꢍ
ꢏꢎ
ꢎꢆ
6:#ꢄ
6'56
4:#ꢄ
%-#ꢄ
6'0&ꢀ
6:5
4:5
%65ꢄ
%-5
&4'3ꢄ
6'0&ꢄ
*#.6
0%
*KIJ
176
176
ꢎꢋ
ꢏꢀ
+0
ꢍ6
+0
+ꢌ1
+0
+ꢌ1
0ꢌ#
*KIJ
+0
*KIJ
176
+0
*KIJ
176
+0
ꢏꢁ
ꢏꢊ
ꢏꢏ
ꢏꢁ
ꢏꢄ
ꢏꢂ
0ꢌ#
ꢍ6
+0
+0
ꢏꢆ
ꢏꢋ
ꢁꢀ
ꢁꢄ
ꢁꢂ
ꢁꢍ
ꢁꢎ
ꢁꢏ
ꢁꢁ
ꢁꢊ
ꢁꢆ
ꢁꢋ
ꢊꢀ
ꢊꢄ
ꢊꢂ
ꢏꢊ
ꢏꢆ
ꢏꢋ
ꢁꢀ
ꢏꢍ
ꢏꢎ
ꢏꢏ
ꢏꢁ
+ꢌ1
+ꢌ1
+0
ꢍ6
+0
*KIJ
*KIJ
176
*KIJ
*KIJ
.QY
0%
ꢁꢄ
ꢁꢂ
ꢁꢍ
ꢁꢎ
ꢁꢏ
ꢁꢁ
ꢁꢊ
ꢁꢆ
ꢄ
ꢏꢊ
ꢏꢆ
ꢏꢋ
ꢁꢀ
ꢁꢄ
ꢁꢂ
ꢁꢍ
ꢁꢎ
ꢄ
4(5*
+143
/4'3
'
*KIJ
*KIJ
*KIJ
.QY
*KIJ
*KIJ
*KIJ
176
)0&
176
ꢍ6
*KIJ
*KIJ
*KIJ
176
*KIJ
*KIJ
*KIJ
176
)0&
ꢍ6
176
*KIJ
ꢍ6
/ꢄ
94
4&
ꢍ6
2*+
176
)0&
8
ꢊꢍ
ꢂ
ꢍ
8
)0&
176
)0&
176
)0&
176
ꢊꢎ
ꢊꢏ
ꢂ
:6#.
0%
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢋ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
2+0ꢄ+&'06+(+%#6+10ꢄꢈ%QPVKPWGFꢉ
6CDNG ꢇꢆ 2KPꢄ5VCVWUꢄ&WTKPIꢄ4'5'6ꢎꢄ$75#%-ꢎꢄCPFꢄ5.''2ꢄ/QFGU ꢌ%QPVKPWGFꢍ
2KPꢄ0WODGTꢄCPFꢄ2CEMCIGꢄ6[RG
2KPꢄ5VCVWU
&GHCWNVꢄ
(WPEVKQP
5GEQPFCT[ꢄ
(WPEVKQP
3(2
2.%%
&+2
4'5'6
$75#%-
5.''2
ꢊꢁ
ꢊꢊ
ꢊꢆ
ꢊꢋ
ꢆꢀ
ꢎ
ꢏ
ꢁ
ꢊ
ꢆ
ꢍ
ꢎ
ꢏ
ꢁ
ꢊ
':6#.
9#+6
+0
+0
+0
+0
+0
+0
$75#%-
$754'3
4'5'6
*KIJ
+0
176
+0
176
+0
+0
+0
+0
ꢄꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
2+0ꢄ&'5%4+26+105
#ꢂ #ꢁꢏ ꢄAddress Bus (Output, 3-state). #ꢀ #ꢄꢋ form a
20-bit address bus. The Address Bus provides the address
for memory data bus exchanges (up to 1 MB) and I/O data
bus exchanges (up to 64 KB). The address bus enters a
high–impedance state during reset and external bus ac-
knowledgecycles. Addressline#ꢄꢆismultiplexedwiththe
'ꢆꢄEnable Clock (Output). This pin functions as a synchro-
nous, machine-cycle clock output during bus transactions.
':6#.ꢆꢄExternal Clock Crystal (Input). Crystal oscillator
connections. An external clock can be input to the
Z8S180/Z8L180 on this pin when a crystal is not used. This
input is Schmitt triggered.
output of PRT channel 1 (6
, selected as address output
*#.6. *#.6/5.''2 (Output, active Low). This output is
asserted after the CPU executes either the *#.6 or 5.''2
instruction and is waiting for either a nonmaskable or a
maskable interrupt before operation can resume. It is also
used with the /ꢄ and 56 signals to decode the status of the
CPU machine cycle.
on reset), and address line #ꢄꢋ is not available in DIP ver-
sions of the Z8S180.
$75#%-. Bus Acknowledge (Output, active Low).
$75#%- indicates that the requesting device, the MPU ad-
dressanddatabus, andsomecontrolsignalsentertheirhigh-
impedance state.
+06ꢂ. Maskable Interrupt Request 0 (Input, active Low).
This signal is generated by external I/O devices. The CPU
honors these requests at the end of the current instruction
cycle as long as the 0/+ and $754'3 signals are inactive.
The CPU acknowledges this interrupt request with an in-
terrupt acknowledge cycle. During this cycle, both the /ꢄ
and +143 signals become active.
$754'3ꢆꢄBus Request (Input, active Low). This input is
used by external devices (such as DMA controllers) to re-
questaccesstothesystembus. Thisrequestdemandsahigh-
er priority than 0/+ and is always recognized at the end of
the current machine cycle. This signal stops the CPU from
executing further instructions, places addresses, data buses,
and other control signals into the high-impedance state.
+06ꢁꢎꢄ+06ꢇ. Maskable Interrupt Request 1 and 2 (Inputs,
active Low). This signal is generated by external I/O de-
vices. The CPU honors these requests at the end of the cur-
rentinstructioncycleaslongasthe0/+,$754'3,and+06ꢀ
signals are inactive. The CPU acknowledges these requests
with an interrupt acknowledge cycle. Unlike the acknowl-
edgment for +06ꢀ, neither the /ꢄ or +143 signals become
active during this cycle.
%-#ꢂꢎꢄ%-#ꢁꢆꢄAsynchronous Clock 0 and 1 (bidirection-
al). When in output mode, these pins are the transmit and
receive clock outputs from the ASCI baud rate generators.
When in input mode, these pins serve as the external clock
inputs for the ASCI baud rate generators. %-#ꢀ is multi-
plexedwith&4'3ꢀ, and%-#ꢄ ismultiplexed with6'0&ꢀ.
%-5ꢆꢄSerial Clock (bidirectional). This line is the clock for
the CSI/O channel.
+143. I/O Request (Output, active Low, 3-state). +143 in-
dicates that the address bus contains a valid I/O address for
an +ꢌ1ꢅ4'#& or +ꢌ1 94+6' operation. +143 is also gener-
ated, along with /ꢄ, during the acknowledgment of the
+06ꢀ input signal to indicate that an interrupt response vec-
tor can be place onto the data bus. This signal is analogous
to the +1' signal of the Z64180.
%65ꢂ %65ꢁ. Clear to send 0 and 1 (Inputs, active Low).
These lines are modem control signals for the ASCI chan-
nels. %65ꢄ is multiplexed with 4:5.
&ꢂ &ꢐꢆꢄData Bus = (bidirectional, 3-state). &ꢀ &ꢊ con-
stitute an 8-bit bidirectional data bus, used for the transfer
of information to and from I/O and memory devices. The
data bus enters the high-impedance state during reset and
external bus acknowledge cycles.
/ꢁ. Machine Cycle 1 (Output, active Low). Together with
/4'3, /ꢄ indicates that the current cycle is the opcode-
fetch cycle of instruction execution. Together with +143,
/ꢄ indicates that the current cycle is for interrupt acknowl-
edgment. It is also used with the *#.6 and 56 signal to de-
code the status of the CPU machine cycle. This signal is
analogous to the .+4 signal of the Z64180.
&%&ꢂ. Data Carrier Detect 0 (Input, active Low); a pro-
grammable modem control signal for ASCI channel 0.
&4'3ꢂꢎꢄ&4'3ꢁ. DMA Request 0 and 1 (Input, active
Low). &4'3 is used to request a DMA transfer from one
of the on-chip DMA channels. The DMA channels monitor
these inputs to determine when an external device is ready
for a 4'#& or 94+6' operation. These inputs can be pro-
grammed to be either level or edge sensed. &4'3ꢀ is mul-
tiplexed with %-#ꢀ.
/4'3. Memory Request (Output, active Low, 3-state).
/4'3 indicates that the address bus holds a valid address
for a memory 4'#& or memory 94+6' operation. This sig-
nal is analogous to the /' signal of Z64180.
0/+. Nonmaskable Interrupt (Input, negative edge trig-
gered). 0/+ demands a higher priority than +06 and is al-
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢄꢄ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
2+0ꢄ&'5%4+26+105ꢄꢈ%QPVKPWGFꢉ
ways recognized at the end of an instruction, regardless of
the stateoftheinterrupt-enableflip-flops. Thissignalforces
CPU execution to continue at location 0066H.
6'0&ꢂꢎꢄ6'0&ꢁꢆ Transfer End 0 and 1 (Outputs, active
Low). This output is asserted active during the most recent
94+6' cycle of a DMA operation. It is used to indicate the
endofthe blocktransfer.6'0&ꢀ is multiplexed with%-#ꢄ.
2*+ꢆꢄSystem Clock (Output). The output is used as a refer-
ence clock for the MPU and the external system. The fre-
quency of this output may be one-half, equal to, or twice
the crystal or input clock frequency.
6'56ꢆꢄTest (Output, not in DIP version). This pin is for test
and should be left open.
6
ꢆꢄTimer Out (Output). 6
is the output from PRT
4&ꢆꢄRead (Output, active Low, 3-state). 4& indicates that
the CPU wants to read data from either memory or an I/O
device. TheaddressedI/Oormemorydeviceshoulduse this
signal to gate data onto the CPU data bus.
channel 1. This line is multiplexed with #ꢄꢆ of the address
bus.
6:#ꢂꢎꢄ6:#ꢁꢆꢄTransmit Data 0 and 1 (Outputs). These sig-
nalsarethetransmitteddatafromtheASCIchannels. Trans-
mitted data changes are with respect to the falling edge of
the transmit clock.
4(5*ꢆ Refresh (Output, active Low). Together with/4'3,
4(5* indicates that the current CPU machine cycle and the
contents of the address bus should be used for refresh of dy-
namic memories. The low-order 8 bits of the address bus
(#ꢊ #ꢀ) containthe refreshaddress.This signalis analogous
to the REF signal of the Z64180.
6:5ꢆꢄClocked Serial Transmit Data (Output). This line is
the transmitted data from the CSI/O channel.
9#+6. Wait (Input, active Low). 9#+6 indicates to the
MPU that the addressed memory or I/O devices are not
ready for data transfer. This input is sampled on the falling
edge of 6ꢂ (and subsequent 9#+6 states). If the input is
sampled Low, then the additional 9#+6 states are inserted
until the 9#+6 input is sampled High, at which time exe-
cution continues.
465ꢂꢆ Request to Send 0 (Output, active Low); a program-
mable MODEM control signal for ASCI channel 0.
4:#ꢂꢎꢄ4:#ꢁꢆꢄReceive Data 0 and 1 (Input). These signals
are the receive data for the ASCI channels.
4:5ꢆꢄClocked Serial Receive Data (Input). This line is the
receivedatafortheCSI/Ochannel. RXSismultiplexedwith
the %65ꢄ signal for ASCI channel 1.
94.94+6'(Output,activeLow, 3-state).94indicatesthat
the CPU data bus holds valid data to be stored at the ad-
dressed I/O or memory location.
56ꢆꢄStatus (Output). This signal is used with the /ꢄ and
*#.6 output todecodethestatusof theCPUmachinecycle.
See Table 3.
:6#.ꢆꢄCrystal Oscillator Connection (Input). This pin
should be left open if an external clock is used instead of a
crystal. TheoscillatorinputisnotaTTLlevel(seeDCChar-
acteristics).
6CDNG ꢋꢆ 5VCVWUꢄ5WOOCT[
56 *#.6 /ꢁ 1RGTCVKQP
Several pins are used for different conditions, depending on
the circumstance.
ꢀ
ꢄ
ꢄ
ꢄ
ꢀ
ꢀ
%27ꢅ1RGTCVKQPꢅꢈꢄUVꢅ1REQFGꢅ(GVEJꢉ
%27ꢅ1RGTCVKQPꢅꢈꢂPFꢅ1REQFGꢅCPFꢅꢍTFꢅ
1REQFGꢅ(GVEJꢉ
ꢄ
ꢄ
ꢄ
%27ꢅ1RGTCVKQPꢅꢈ/%ꢅ'ZEGRVꢅ1REQFGꢅ
(GVEJꢉ
ꢀ
ꢀ
ꢄ
:
ꢀ
ꢀ
ꢄ
ꢀ
ꢄ
&/#ꢅ1RGTCVKQP
*#.6ꢅ/QFG
5.''2ꢅ/QFGꢅꢈ+PENWFKPIꢅ5;56'/ꢅ
5612ꢅ/QFGꢉ
Notes:
:ꢅꢐꢅ&QꢅPQVꢅECTGꢑ
/%ꢅꢐꢅ/CEJKPGꢅ%[ENGꢑ
ꢄꢂ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
6CDNG ꢉꢆ /WNVKRNGZGFꢄ2KPꢄ&GUETKRVKQPU
&WTKPIꢅ4'5'6ꢇꢅVJKUꢅRKPꢅKUꢅKPKVKCNK\GFꢅCUꢅ#ꢄꢆꢑꢅ+HꢅGKVJGTꢅVJGꢅ61%ꢄꢅQTꢅVJGꢅ61%ꢀꢅDKVꢅQHꢅVJGꢅ6KOGTꢅ
#ꢄꢆꢌ6176
%QPVTQNꢅTGIKUVGTꢅꢈ6%4ꢉꢅKUꢅUGVꢅVQ 1ꢇ VJGꢅ6
ꢅHWPEVKQPꢅKUꢅUGNGEVGFꢑꢅ+Hꢅ61%ꢄꢅCPFꢅ61%ꢀꢅCTGꢅENGCTGFꢅ
VQꢅ0ꢇꢅVJGꢅ#ꢄꢆꢅHWPEVKQPꢅKUꢅUGNGEVGFꢑ
%-#ꢀꢌ&4'3ꢀ
%-#ꢄꢌ6'0&ꢀ
&WTKPIꢅ4'5'6ꢇꢅVJKUꢅRKPꢅKUꢅKPKVKCNK\GFꢅCUꢅ%-#ꢀꢑꢅ+HꢅGKVJGTꢅ&/ꢄꢅQTꢅ5/ꢄꢅKPꢅVJGꢅ&/#ꢅ/QFGꢅTGIKUVGTꢅ
ꢈ&/1&'ꢉꢅKUꢅUGVꢅVQ 1ꢇ VJGꢅ&4'3ꢀꢅHWPEVKQPꢅKUꢅUGNGEVGFꢑ
&WTKPIꢅ4'5'6ꢇꢅVJKUꢅRKPꢅKUꢅKPKVKCNK\GFꢅCUꢅ%-#ꢄꢑꢅ+HꢅVJGꢅ%-#ꢄ&ꢅDKVꢅKPꢅ#5%+ꢅEQPVTQNꢅTGIKUVGTꢅEJꢄꢅ
ꢈ%06.#ꢄꢉꢅKUꢅUGVꢅVQ 1ꢇ VJGꢅ6'0&ꢀꢅHWPEVKQPꢅKUꢅUGNGEVGFꢑꢅ+HꢅVJGꢅ%-#ꢄ&ꢅDKVꢅKUꢅUGVꢅVQꢅ0ꢇꢅVJGꢅ%-#ꢄꢅ
HWPEVKQPꢅKUꢅUGNGEVGFꢑ
4:5ꢌ%65ꢄ
&WTKPIꢅ4'5'6ꢇꢅVJKUꢅRKPꢅKUꢅKPKVKCNK\GFꢅCUꢅ4:5ꢑꢅ+HꢅVJGꢅ%65ꢄ'ꢅDKVꢅKPꢅVJGꢅ#5%+ꢅUVCVWUꢅTGIKUVGTꢅEJꢄꢅ
ꢈ56#6ꢄꢉꢅKUꢅUGVꢅVQ 1ꢇ VJGꢅ%65ꢄꢅHWPEVKQPꢅKUꢅUGNGEVGFꢑꢅ+HꢅVJGꢅ%65ꢄ'ꢅDKVꢅKUꢅUGVꢅVQꢅ0ꢇꢅVJGꢅ4:5ꢅ
HWPEVKQPꢅKUꢅUGNGEVGFꢑ
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢄꢍ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
#4%*+6'%674'
The Z180 combines a high-performance CPU core with a
variety of system and I/O resources useful in a broad range
of applications. The CPU core consists of five functional
blocks: clock generator, bus state controller, Interrupt con-
troller, memory management unit (MMU), and the central
processing unit (CPU). The integrated I/O resources make
up the remaining four functional blocks: direct memory ac-
cess(DMA) control (2 channels), asynchronousserial com-
munication interface (ASCI, 2 channels) programmable re-
load timers (PRT, 2 channels), and a clock serial I/O
(CSI/O) channel.
code maintains compatibility with the Z80 CPU, while of-
fering access to an extended memory space. Accomplished
by using an effective common-area/banked-area scheme.
%GPVTCNꢄ2TQEGUUKPIꢄ7PKVꢆꢄThe CPU is microcoded to pro-
vide a core that is object-code compatible with the Z80
CPU. It also provides a superset of the Z80 instruction set,
including8-bitmultiplication. Thecore ismodifiedtoallow
many of the instructions to execute in fewer clock cycles.
&/#ꢄ%QPVTQNNGTꢆꢄThe DMA controller provides high-
speed transfers between memory and I/O devices. Transfer
operations supported are memory-to-memory, memory
to/from I/O, and I/O-to-I/O. Transfer modes supported are
request, burst, and cycle steal. DMA transfers can access
thefull1-MBaddressrangewithablocklengthupto64 KB,
and can cross over 64K boundaries.
%NQEMꢄ)GPGTCVQTꢆꢄThislogic generatesa system clock from
an external crystal or clock input. The external clock is di-
vided by 2 or 1 and provides the timing for both internal
and external devices.
$WUꢄ5VCVGꢄ%QPVTQNNGTꢆꢄThis logic performs all of the status
and bus-control activity associated with the CPU and some
on-chip peripherals. Also includes wait-state timing, reset
cycles, DRAM refresh, and DMA bus exchanges.
#U[PEJTQPQWUꢄ5GTKCNꢄ%QOOWPKECVKQPꢄ+PVGTHCEGꢄꢌ#5%+ꢍꢆ
The ASCI logic provides two individual full-duplex
UARTs. Each channel includes a programmable baud rate
generator and modem control signals. The ASCI channels
can also support a multiprocessor communication format as
well as break detection and generation
+PVGTTWRVꢄ%QPVTQNNGTꢆꢄThis logic monitors and prioritizes
the variety of internal and external interrupts and traps to
provide the correct responses from the CPU. To maintain
compatibility with the Z80 CPU, three different interrupts
modes are supported.
2TQITCOOCDNGꢄ4GNQCFꢄ6KOGTUꢄꢌ246ꢍꢆꢄThis logic consists
of two separate channels, each containing a 16-bit counter
(timer) and count reload register. The time base for the
counters is derived from the system clock (divided by 20)
before reaching the counter. PRT channel 1 provides an op-
tional output to allow for waveform generation.
/GOQT[ꢄ/CPCIGOGPVꢄ7PKVꢆꢄThe MMU allows the user to
map the memory used by the CPU (logically only 64KB)
into the 1-MB addressing range supported by the
Z8S180/Z8L180. The organization of the MMU object
ꢄꢎ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
6KOGTꢅ&CVCꢅ4GIKUVGT
9TKVGꢅꢈꢀꢀꢀꢎ*ꢉ
ꢀꢅꢒꢅVꢅꢒꢅꢂꢀꢅφ
ꢂꢀꢅφ ꢂꢀꢅφ ꢂꢀꢅφ ꢂꢀꢅφ ꢂꢀꢅφ ꢂꢀꢅφ ꢂꢀꢅφ ꢂꢀꢅφ ꢂꢀꢅφ
4GUGV
6KOGTꢅ&CVC
4GIKUVGT
ꢀꢀꢀꢂ* ꢀꢀꢀꢄ* ꢀꢀꢀꢀ* ꢀꢀꢀꢍ* ꢀꢀꢀꢂ*
ꢀꢀꢀꢀ* ꢀꢀꢀꢍ*
ꢀꢀꢀꢄ*
ꢀꢀꢀꢍ*
((((*
ꢀꢀꢀꢎ*
4GNQCF
4GNQCF
6KOGTꢅ4GNQCFꢅ4GIKUVGTꢅ9TKVGꢅꢈꢀꢀꢀꢍ*ꢉ
6KOGTꢅ4GNQCF
4GIKUVGT
((((* ꢀꢀꢀꢍ*
9TKVGꢅꢄꢅVQꢅ6&'
6&'ꢅ(NCI
6+(ꢅ(NCI
6KOGTꢅ&CVCꢅ4GIKUVGTꢅ4GCF
6KOGTꢅ%QPVTQNꢅ4GSWGUVQTꢅ4GCF
(KIWTG ꢑꢆ 6KOGTꢄ+PKVKCNK\CVKQPꢎꢄ%QWPVꢄ&QYPꢎꢄCPFꢄ4GNQCFꢄ6KOKPI
6KOGTꢅ&CVC
4GIꢑꢅꢐꢅꢀꢀꢀꢄ*
6KOGTꢅ&CVC
4GIꢑꢅꢐꢅꢀꢀꢀꢀ*
2*+
6
(KIWTG ꢈꢆ 6KOGTꢄ1WVRWVꢄ6KOKPI
%NQEMGFꢄ5GTKCNꢄ+ꢃ1ꢄꢌ%5+ꢃ1ꢍꢆꢄꢄThe CSI/O channel provides
a half-duplex serial transmitter and receiver. This channel
can be used for simple high-speed data connection to an-
other microprocessor or microcomputer. 64&4 is used for
both CSI/O transmission and reception. Thus, the system
design must ensure that the constraints of half-duplex op-
eration are met (Transmit and Receive operation cannot oc-
cur simultaneously). For example, if a CSI/O transmission
isattemptedwhile the CSI/Oisreceivingdata, a CSI/Odoes
not work.
0QVGꢅ 64&4 is not buffered. Performing a CSI/O transmit
while the previous transmission is still in progress causes
the data to be immediately updated and corrupts the
transmit operation. Similarly, reading 64&4 while a
transmit or receive is in progress should be avoided.
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢄꢏ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
#4%*+6'%674'ꢄꢈ%QPVKPWGFꢉ
+PVGTPCNꢅ#FFTGUUꢌ&CVCꢅ$WU
2*+
%-5
%5+ꢌ1ꢅ6TCPUOKVꢌ4GEGKXG
&CVCꢅ4GIKUVGTꢓ
64&4ꢅꢈꢆꢉ
$CWFꢅ4CVG
)GPGTCVQT
6:5
4:5
%5+ꢌ1ꢅ%QPVTQNꢅ4GIKUVGTꢓ
%064ꢅꢈꢆꢉ
+PVGTTWRVꢅ4GSWGUV
(KIWTG ꢐꢆ %5+ꢃ1ꢄ$NQEMꢄ&KCITCO
ꢄꢁ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
12'4#6+10ꢄ/1&'5
<ꢀꢂꢄXGTUWUꢄꢈꢉꢁꢀꢂꢄ%QORCVKDKNKV[ꢆꢄThe Z8S180/Z8L180
is descended from two different “ancestor” processors,
ZiLOG’s original Z80 and the Hitachi 64180. The Operat-
ing Mode Control Register (OMCR), illustrated in Figure
8, can be programmed to select between certain Z80 and
64180 differences.
/ꢁ'ꢄꢌ/ꢁꢄ'PCDNGꢍꢆꢄThis bit controls the /ꢄ output and is
set to a 1 during 4'5'6.
When /ꢄ'ꢅꢐꢅ1, the /ꢄ output is asserted Low during op-
code fetch cycles, Interrupt Acknowledge cycles, and the
first machine cycle of an 0/+ acknowledge.
On the Z8S180/Z8L180, this choice makes the processor
fetch a 4'6+ instruction one time. When fetching a 4'6+
from a zero-wait-state memory location, the processor uses
three clock bus cycles. These bus cycles are not fully Z80-
timing compatible.
&ꢊ &ꢁ &ꢏ
4GUGTXGF
+1%ꢅꢈ4ꢌ9ꢉ
/ꢄ6'ꢅꢈ9ꢉ
/ꢄ'ꢅꢈ4ꢌ9ꢉ
When /ꢄ' ꢐ 0, the processor does not drive /ꢄ Low dur-
ing the instruction fetch cycles. After fetching a 4'6+ in-
struction with normal timing, the processor goes back and
refetches the instruction using fully Z80-compatible cycles
that include driving /ꢄ Low. This option may be required
by some external Z80 peripherals to properly decode the
4'6+ instruction. Figure 9 and Table 5 show the 4'6+ se-
quence when /ꢄ' is 0.
(KIWTG ꢀꢆ 1RGTCVKPIꢄ%QPVTQNꢄ4GIKUVGT
ꢌ1/%4ꢅꢄ+ꢃ1ꢄ#FFTGUUꢄꢒꢄꢋ'*ꢍ
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
2*+
ꢅꢈ#
#
#
ꢉ
2%ꢔꢄ
2%
'&*
2%ꢔꢄ
ꢎ&*
2%
'&*
ꢎ&*
&
&
/ꢄ
/4'3
4&
56
(KIWTG ꢏꢆ 4'6+ꢄ+PUVTWEVKQPꢄ5GSWGPEGꢄYKVJꢄ/ꢁ'ꢄꢒꢄꢂ
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢄꢊ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
12'4#6+10ꢄ/1&'5ꢄꢈ%QPVKPWGFꢉ
6CDNG ꢑꢆ 4'6+ꢄ%QPVTQNꢄ5KIPCNꢄ5VCVGU
/ꢁ
/ꢁ
/CEJKPGꢄ
/ꢁ'ꢒ /ꢁ'ꢒ
%[ENG 5VCVGU
#FFTGUU
&CVC
4&
94 /4'3 +143
ꢁ
ꢂ
*#.6
56
ꢄ
ꢂ
6ꢄ 6ꢍ
6ꢄ 6ꢍ
6K
6K
6K
6ꢄ 6ꢍ
6K
6ꢄ 6ꢍ
6ꢄ 6ꢍ
6ꢄ 6ꢍ
ꢄUVꢅ1REQFG
ꢂPFꢅ1REQFG
0#
0#
0#
ꢄUVꢅ1REQFG
0#
ꢂPFꢅ1REQFG
52
'&*
ꢎ&*
ꢀ
ꢀ
ꢄ
ꢄ
ꢄ
ꢀ
ꢄ
ꢀ
ꢀ
ꢀ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢀ
ꢀ
ꢄ
ꢄ
ꢄ
ꢀ
ꢄ
ꢀ
ꢀ
ꢀ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢀ
ꢀ
ꢄ
ꢄ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢀ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢀ
ꢀ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢍꢃUVCVG
ꢍꢃUVCVG
ꢍꢃUVCVG
'&*
ꢍꢃUVCVG
ꢎ&*
ꢍ
ꢎ
ꢏ
ꢁ
&CVC
&CVC
52ꢔꢄ
/ꢁ6'ꢄꢌ/ꢁꢄ6GORQTCT[ꢄ'PCDNGꢍꢆꢄThis bit controls the tem-
porary assertion of the /ꢄ signal. It is always read back as
a 1 and is set to 1 during 4'5'6.
For example, when a control word is written to the Z80 PIO
to enable interrupts, no enable actually takes place until the
PIO sees an active /ꢄ signal. When /ꢄ6' =ꢅ1, there is no
change in the operation of the /ꢄ signal, and /ꢄ' controls
itsfunction. When /ꢄ6' =ꢅ0, the /ꢄ output isasserteddur-
ing the next opcode fetch cycle regardless of the state pro-
grammed into the /ꢄ' bit. This condition is only momen-
tary (one time) and it is not necessary to preprogram a 1
to disable the function (see Figure 10).
When /ꢄ' is set toꢅ0to accommodate certain external Z80
peripheral(s), those same device(s) may require a pulse on
/ꢄ after programming certain of their registers to complete
the function being programmed.
6
6
6
6
6
6
2*+
94
/ꢄ
9TKVGꢅKPVQꢅ1/%4
1REQFGꢅ(GVEJ
(KIWTG ꢁꢂꢆ /ꢁꢄ6GORQTCT[ꢄ'PCDNGꢄ6KOKPI
+1%ꢄꢌ+ꢃ1ꢄ%QORCVKDKNKV[ꢍꢆꢄThis bit controls the timing of the
+143 and 4& signals. The bit is set to 1 by 4'5'6.
When +1% =ꢅ1, the +143 and 4& signals function the same
as the Z64180 (Figure 11).
ꢄꢆ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
6
6
6
6
2*+
+143
4&
94
(KIWTG ꢁꢁꢆ +ꢃ1ꢄ4GCFꢄCPFꢄ9TKVGꢄ%[ENGUꢄYKVJꢄ+1%ꢄꢒꢄꢁ
When+1% =ꢅ0, the timing of the +143 and 4& signals match
the timing of the Z80. The +143 and 4& signals go active
as a result of the rising edge of T2. (Figure 12.)
6
6
6
6
2*+
+143
4&
94
(KIWTG ꢁꢇꢆ +ꢃ1ꢄ4GCFꢄCPFꢄ9TKVGꢄ%[ENGUꢄYKVJꢄ+1%ꢄꢒꢄꢂ
*#.6ꢄCPFꢄ.QYꢊ2QYGTꢄ1RGTCVKPIꢄ/QFGUꢆꢄThe
Z8S180/Z8L180 can operate in seven modes with respect
to activity and power consumption:
0QTOCNꢄ1RGTCVKQPꢆꢄIn this state, the Z8S180/Z8L180 pro-
cessor is fetching and running a program. All enabled func-
tions and portions of the device are active, and the *#.6
pin is High.
Normal Operation
*#.6ꢄ/QFGꢆꢄThis mode is entered by the *#.6 instruc-
tion. Thereafter, the Z8S180/Z8L180 processor continually
fetches the following opcode but does not execute it and
drives the *#.6, 56 and /ꢄ pins all Low. The oscillator
and 2*+ pin remain Active. Interrupts and bus granting to
external Masters, and DRAM refresh can occur, and all on-
chip I/O devices continue to operate including the DMA
channels.
*#.6 Mode
+15612 Mode
5.''2 Mode
5;56'/ꢅ5612 Mode
+&.' Mode
56#0&$; Mode (with or without 37+%-ꢅ 4'%18ꢃ
'4;
)
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢄꢋ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
12'4#6+10ꢄ/1&'5ꢄꢈ%QPVKPWGFꢉ
The Z8S180/Z8L180 leaves *#.6 mode in response to:
Low on 4'5'6
In case of an interrupt, the return address is the instruction
following the *#.6 instruction. The program can either
branch back to the *#.6 instruction to wait for another in-
terrupt or can examine the new state of the system/applica-
tion and respond appropriately.
Interrupt from an enabled on-chip source
External request on 0/+
Enabled external request on +06ꢀ, +06ꢄ, or +06ꢂ
Interrupt
HALT Opcode Fetch Cycle
HALT Mode
Acknowledge Cycle
T2
T3
T1 T2
PHI
INTi, NMI
A19–A0
HALT
M1
HALT Opcode Address + 1
HALT Opcode Address
MREQ
RD
Note:
indicates an indefinite delay.
(KIWTG ꢁꢋꢆ *#.6ꢄ6KOKPI
5.''2ꢄ/QFGꢆꢄThismodeisenteredbykeepingthe+15612
bit (ICR5) and bits 3 and 6 of the CPU Control Register
(CCR3, CCR6) all zero and executing the 5.2 instruction.
The oscillator and 2*+ output continue operating, but are
blocked from the CPU core and DMA channels to reduce
power consumption. DRAM refresh stops, but interrupts
and granting to an external Master can occur. Except when
the bus is granted to an external Master, A19–0 and all con-
trol signals except *#.6 are maintained High. *#.6 is
Low. I/O operations continue as before the 5.2 instruction,
except for the DMA channels.
an external request on 0/+, or an external request on +06ꢀ,
+06ꢄ, or +06ꢂ.
Ifaninterruptsourceisindividuallydisabled,itcannotbring
the Z8S180/Z8L180 out of 5.''2 mode. If an interrupt
source is individually enabled, and the +'( bit is 1 so that
interrupts are globally enabled (by an EI instruction), the
highest priority active interrupt occurs with the return ad-
dress being the instruction after the 5.2 instruction. If an
interrupt source is individually enabled, but the +'( bit isꢅ0
so that interrupts are globally disabled (by a DI instruction),
the Z8S180/Z8L180 leaves 5.''2 mode by simply execut-
ing the following instruction(s).
The Z8S180/Z8L180 leaves 5.''2 mode in response to a
Lowon4'5'6, aninterruptrequestfromanon-chipsource,
ꢂꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
This condition provides a technique for synchronization
with high-speed external events without incurring the la-
tencyimposedbyaninterrupt-responsesequence.Figure14
depicts the timing for exiting 5.''2 mode due to an inter-
rupt request.
0QVGꢅ The Z8S180/Z8L180 takes about 1.5 clock ticks to re-
start.
1REQFGꢅ(GVEJꢅQTꢅ+PVGTTWRV
#EMPQYNGFIGꢅ%[ENG
5.2ꢅꢂPFꢅ1REQFG
(GVEJꢅ%[ENG
5.''2ꢅ/QFG
6
6
6
6
6
6
6
6
6
2*+
+06Kꢇꢅ0/+
#
#
5.2ꢅꢂPFꢅ1REQFGꢅ#FFTGUU
(((((*
*#.6
/ꢄ
(KIWTG ꢁꢉꢆ 5.''2ꢄ6KOKPI
+15612ꢄ/QFGꢆꢄ+15612 mode is entered by setting the
+15612 bit of the I/O Control Register (+%4) to 1. In this
case, on-chip I/O (ASCI, CSI/O, PRT) stops operating.
However, the CPU continues to operate. Recovery from
+15612 mode is performed by resetting the +15612 bit in
+%4 to 0.
internal devices stop, but external interrupts can occur. Bus
granting to external Masters can occur if the $4'56 bit in
the CPU control Register (%%4ꢏ) was set to 1 before +&.'
mode was entered.
The Z8S180/Z8L180 leaves +&.' mode in response to a
Low on 4'5'6, an external interrupt request on 0/+, or an
external interrupt request on +06ꢀ, +06ꢄ or +06ꢂ that is en-
abled in the INT/TRAP Control Register. As previously de-
scribed for 5.''2 mode, when the Z8S180/Z8L180 leaves
+&.' mode due to an 0/+, or due to an enabled external in-
terrupt request when the +'( flag is 1 due to an '+ instruc-
tion, the device starts by performing the interrupt with the
return address of the instruction after the 5.2 instruction.
5;56'/ꢄ5612ꢄ/QFGꢆꢄ5;56'/ꢅ5612 mode is the com-
bination of 5.''2 and +15612 modes. 5;56'/ꢅ5612
mode is entered by setting the +15612 bit in +%4 to 1 fol-
lowed by execution of the 5.2 instruction. In this mode, on-
chipI/OandCPU stopoperating, reducingpower consump-
tion, but the 2*+output continuesto operate. Recoveryfrom
5;56'/ꢅ5612 mode is the same as recovery from 5.''2
mode exceptthat internal I/Osources(disabledby+15612)
cannot generate a recovery interrupt.
If an external interrupt enables the INT/TRAP control reg-
ister while the +'(ꢄ bit isꢅ0, Z8S180/Z8L180 leaves +&.'
mode; specifically, the processor restarts by executing the
instructions following the 5.2 instruction.
+&.'ꢄ/QFGꢆꢄSoftware puts the Z8S180/Z8L180 into this
mode by performing the following actions:
Set the +15612 bit (+%4ꢏ) to ꢄ
Set %%4ꢁ to ꢀ
Figure 15 indicates the timing for exiting +&.' mode due
to an interrupt request.
Set %%4ꢍ to ꢄ
0QVGꢅ The Z8S180/Z8L180 takes about 9.5 clocks to restart.
Execute the 5.2 instruction
The oscillator keeps operating but its output is blocked to
all circuitry including the 2*+ pin. DRAM refresh and all
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢂꢄ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
12'4#6+10ꢄ/1&'5ꢄꢈ%QPVKPWGFꢉ
1REQFGꢅ(GVEJꢅQTꢅ+PVGTTWRV
#EMPQYNGFIGꢅ%[ENG
+&.'ꢅ/QFG
6
6
6
6
2*+
ꢋꢑꢏꢅ%[ENGꢅ&GNC[ꢅHTQOꢅ+06Kꢅ#UUGTVGF
0/+
QT
+06ꢀꢇꢅ+06ꢄꢇꢅ+06ꢂ
#
#
(((((*
*#.6
/ꢄ
(KIWTG ꢁꢑꢆ <ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂꢄ+&.'ꢄ/QFGꢄ'ZKVꢄ&WGꢄ6Qꢄ'ZVGTPCNꢄ+PVGTTWRV
WhiletheZ8S180/Z8L180isin+&.' mode, it grants the bus
to an external Master if the BREXT bit (CCR5) is 1. Figure
16 depicts the timing for this sequence.
After the external Master negates the Bus Request, the
Z8S180/Z8L180 disables the2*+ clock andremainsin +&.'
mode.
0QVGꢅ A response to a bus request takes 8 clock cycles longer
than in normal operation.
ꢂꢂ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
+&.'ꢅ/QFG
$WUꢅ4GNGCUGꢅ/QFG
+&.'ꢅ/QFG
6:
6:
2*+
ꢋꢑꢏꢅ%[ENGꢅ&GNC[ꢅWPVKNꢅ$75#%-ꢅ#UUGTVGF
$754'3
$75#%-
#
#
(((((*
(((((*
*KIJꢅ+ORGFCPEG
*KIJ
*#.6
/ꢄ
.QY
(KIWTG ꢁꢈꢆ $WUꢄ)TCPVKPIꢄVQꢄ'ZVGTPCNꢄ/CUVGTꢄKPꢄ+&.'ꢄ/QFG
56#0&$;ꢄ/QFGꢄꢌ9KVJꢄQTꢄ9KVJQWVꢄ37+%-ꢄ4'%18'4;ꢍꢆ
When external logic drives 4'5'6 Low to bring the device
out of 56#0&$; mode, and a crystal is in use or an external
clock source is stopped, the external logic must hold4'5'6
Low until the on-chip oscillator or external clock source is
restarted and stabilized.
Software canput the Z8S180/Z8L180 into this mode by set-
ting the +15612 bit (ICR5) toꢅ1, CCR6 toꢅ1, and executing
the 5.2 instruction. This mode stops the on-chip oscillator
and thus draws the least power of any mode, less than 10µA.
Theclock-stabilityrequirementsoftheZ8S180/Z8L180are
much less in the divide-by-two mode that is selected by a
4'5'6 sequence and controlled by the Clock Divide bit in
theCPUControlRegister(CCR7). Asaresult, softwareper-
forms the following actions:
As with +&.' mode, the Z8S180/Z8L180 leaves 56#0&$;
mode in response to a Low on 4'5'6, on 0/+, or a Low
on +06ꢀ–2 that is enabled by a 1 in the corresponding bit
in the INT/TRAP Control Register. This action grants the
bus to an external Master if the BREXT bit in the CPU Con-
trol Register (CCR5) is 1. The time required for all of these
operations is greatly increased by the necessity for restart-
ing the on-chip oscillator, and ensuring that it stabilizes to
square-wave operation.
1. Sets CCR7 toꢅ0for divide-by-two mode before an 5.2
instruction and 56#0&$; mode.
2. Delays setting CCR7 back to 1 for divide-by-one
mode as long as possible to allow additional clock
stabilization time after a 4'5'6, interrupt, or in-line
RESTART after an 5.2 01 instruction.
WhenanexternalclockisconnectedtotheEXTALpinrath-
er than a crystal to the XTAL and EXTAL pins and the ex-
ternal clockrunscontinuously, there is little necessity to use
56#0&$; mode because no time is required to restart the
oscillator, and other modes restart faster. However, if ex-
ternal logic stops the clock during 56#0&$; mode (for ex-
ample, by decoding *#.6 Low and /ꢄ High for several
clock cycles), then 56#0&$; mode can be useful to allow
the external clock source to stabilize after it is re-enabled.
If CCR6 is set to 1 before the 5.2 instruction places the
MPU in 56#0&$; mode, the value of the CCR3 bit deter-
mines the length of the delay before the oscillator restarts
and stabilizes when it leaves 56#0&$; mode due to an ex-
ternal interrupt request. When CCR3 isꢅ 0, the
17
Z8S180/Z8L180 waits 2 (131,072) clock cycles. When
CCR3 isꢅ1, it waits 64 clock cycles. This state is called
37+%-ꢅ4'%18'4; mode. The same delay applies to grant-
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢂꢍ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
ing the bus to an external Master during 56#0&$; mode,
when the $4':6 bit in the CPU Control Register (%%4ꢏ)
is 1.
a &+ instruction, the processor restarts by executing the in-
struction(s) following the 5.2 instruction. If +06ꢀ, or +06ꢄ
or +06ꢂ goes inactive before the end of the clock stabiliza-
tion delay, the Z8S180/Z8L180 stays in 56#0&$; mode.
As described previously for 5.''2 and +&.' modes, when
the MPU leaves 56#0&$; mode due to 0/+ Low or an en-
abled +06ꢀ–+06ꢂ Low when the +'(, flag is 1 due to an
IE instruction, it starts by performing the interrupt with the
return address being that of the instruction following the
5.2 instruction. If the Z8S180/Z8L180 leaves 56#0&$;
mode due to an external interrupt request that's enabled in
the +06ꢌ64#2 Control Register, but the +'(, bit isꢅ0due to
Figure 17 indicates the timing for leaving 56#0&$; mode
due to an interrupt request.
17
0QVGꢅ The Z8S180/Z8L180 takes either 64 or 2 (131,072)
clocks to restart, depending on the CCR3 bit.
1REQFGꢅ(GVEJꢅQTꢅ+PVGTTWRV
#EMPQYNGFIGꢅ%[ENG
56#0&$;ꢅ/QFG
6
6
6
6
2*+
ꢂ
ꢃꢅQTꢅꢁꢎꢃ%[ENGꢅ&GNC[ꢅHTQOꢅ+06Kꢅ#UUGTVGF
0/+
QT
+06ꢀꢇꢅ+06ꢄꢇꢅ+06ꢂ
#
#
(((((*
*#.6
/ꢄ
(KIWTG ꢁꢐꢆ <ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂꢄ56#0&$;ꢄ/QFGꢄ'ZKVꢄ&WGꢄVQꢄ'ZVGTPCNꢄ+PVGTTWRV
While the Z8S180/Z8L180 is in 56#0&$; mode, it grants
the bus to an external Master if the $4':6 bit (%%4ꢏ) is 1.
Figure 18 indicates the timing of this sequence. The device
pending on the CCR3 bit. The latter (not the 37+%-ꢅ4'ꢃ
%18'4;)casemaybeprohibitive formanydemand-driven
external Masters. If so, 37+%-ꢅ4'%18'4; or +&.' mode
can be used.
17
takes 64 or 2 (131,072) clock cycles to grant the bus de-
ꢂꢎ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
$WUꢅ4GNGCUGꢅ/QFG
56#0&$;ꢅ/QFG
56#0&$;ꢅ/QFG
6:
6:
2*+
ꢁꢎꢃꢅQTꢅꢂ ꢃ%[ENGꢅ&GNC[ꢅ#HVGTꢅ$754'3ꢅ#UUGTVGF
$754'3
$75#%-
#
#
(((((*
(((((*
*#.6 .QY
*KIJ
/ꢄ
(KIWTG ꢁꢀꢆ $WUꢄ)TCPVKPIꢄVQꢄ'ZVGTPCNꢄ/CUVGTꢄ&WTKPIꢄ56#0&$;ꢄ/QFG
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢂꢏ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
56#0&ꢄ6'56ꢄ%10&+6+105
The following standard test conditions apply to DC Char-
acteristics, unless otherwise noted. All voltages are refer-
enced to V (0V). Positive current flows into the refer-
SS
enced pin.
All AC parameters assume a load capacitance of 100 pF.
Add a 10-ns delay for each 50-pF increase in load up to a
maximum of 200 pF for the data bus and 100 pF for the ad-
dress and control lines. AC timing measurements are ref-
erenced to V MAX or V MIN as indicated in Figures 20
OL
OL
through 30 (except for %.1%-, which is referenced to the
10% and 90% points). Ordering Information lists temper-
ature ranges and product numbers. Find package drawings
in Package Information.
(KIWTG ꢁꢏꢆ #%ꢄ2CTCOGVGTꢄ6GUVꢄ%KTEWKV
#$51.76'ꢄ/#:+/7/ꢄ4#6+0)5
+VGO
5[ODQN
8CNWG
ꢀꢑꢍꢅ`ꢅꢔꢊꢑꢀ
ꢀꢑꢍꢅ`ꢅ8 ꢅꢔꢀꢑꢍ
ꢀꢅ`ꢅꢊꢀ
7PKV
8
5WRRN[ꢅ8QNVCIG
+PRWVꢅ8QNVCIG
8
8
6
8
1RGTCVKPIꢅ6GORGTCVWTG
'ZVGPFGFꢅ6GORGTCVWTG
5VQTCIGꢅ6GORGTCVWTG
u%
u%
u%
6
ꢎꢀꢅ`ꢅꢆꢏ
6
ꢏꢏꢅ`ꢅꢔꢄꢏꢀ
0QVGꢅ Permanent damage may occur if maximum ratings are
exceeded. Normal operation should be under recom-
mended operating conditions. If these conditions are ex-
ceeded, it could affect reliability.
ꢂꢁ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
&%ꢄ%*#4#%6'4+56+%5 <ꢀ5ꢁꢀꢂ
6CDNG ꢈꢆ <ꢀ5ꢁꢀꢂꢄ&%ꢄ%JCTCEVGTKUVKEU
8
ꢄꢒꢄꢑ8ꢄvꢁꢂꢓꢔꢄ8 ꢒꢄꢂ8
5[ODQN
+VGO
%QPFKVKQP
/KP
ꢅ ꢀꢑꢁ
6[R
/CZ
7PKV
8
+PRWVꢅ*ꢅ8QNVCIG
8
8
ꢅ
8
4'5'6ꢇꢅ':6#.ꢇꢅ0/+
ꢔꢀꢑꢍ
8
8
+PRWVꢅ*ꢅ8QNVCIG
'ZEGRVꢅ4'5'6ꢇꢅ':6#.ꢇꢅ0/+
ꢂꢑꢀ
ꢂꢑꢎ
8
ꢔꢀꢑꢍ
8
ꢔꢀꢑꢍ
ꢀꢑꢁ
ꢅ
8
8
+PRWVꢅ*ꢅ8QNVCIG
%-5ꢇꢅ%-#ꢀꢇꢅ%-#ꢄ
ꢅ
8
8
8
+PRWVꢅ.ꢅ8QNVCIG
4'5'6ꢇꢅ':6#.ꢇꢅ0/+
+PRWVꢅ.ꢅ8QNVCIG
'ZEGRVꢅ4'5'6ꢇꢅ':6#.ꢇꢅ0/+
1WVRWVUꢅ*ꢅ8QNVCIG
#NNꢅQWVRWVU
ꢀꢑꢍ
ꢀꢑꢍ
ꢂꢑꢎ
8
8
8
ꢀꢑꢆ
+
+
+
ꢅꢐꢅ ꢂꢀꢀꢅz#
ꢅꢐꢅ ꢂꢀꢅz#
ꢅꢐꢅꢂꢑꢂꢅO#
8
ꢄꢑꢂ
8
+
1WVRWVUꢅ.ꢅ8QNVCIG
#NNꢅQWVRWVU
+PRWVꢅ.GCMCIG
%WTTGPVꢅ#NNꢅ+PRWVU
'ZEGRVꢅ:6#.ꢇꢅ':6#.
6JTGGꢅ5VCVGꢅ.GCMCIG
%WTTGPV
ꢀꢑꢎꢏ
ꢄꢑꢀ
8
8 ꢅꢐꢅꢀꢑꢏꢅ`ꢅ8 ꢅ ꢀꢑꢏ
8 ꢅꢐꢅꢀꢑꢏꢅ`ꢅ8 ꢅ ꢀꢑꢏ
z#
+
+
ꢄꢑꢀ
z#
2QYGTꢅ&KUUKRCVKQP
ꢈ0QTOCNꢅ1RGTCVKQPꢉ
(ꢅꢐꢅꢄꢀꢅ/*\
ꢂꢀ
ꢍꢍ
ꢂꢏ
ꢍꢀ
ꢁꢀ
ꢂ
ꢁꢀ
ꢏꢀ
ꢄꢀꢀ
ꢏ
O#
2QYGTꢅ&KUUKRCVKQP
(ꢅꢐꢅꢄꢀꢅ/*\
ꢈ5;56'/ꢅ5612ꢅOQFGꢉ
ꢂꢀ
ꢍ
ꢁ
ꢍꢍ
ꢏ
ꢋ
%
2KPꢅ%CRCEKVCPEG
8 ꢅꢐꢅꢀ ꢇꢅHꢅꢐꢅꢄꢅ/*\
6 ꢅꢐꢅꢂꢏu%
ꢄꢂ
R(
0QVGꢅꢄ
ꢄꢑ 8
ꢅꢐꢅ8
ꢄꢑꢀ8ꢇꢅ8
ꢅꢐꢅꢀꢑꢆ8ꢅꢈ#NNꢅQWVRWVꢅVGTOKPCNUꢅCTGꢅCVꢅ01ꢅ.1#&ꢑꢉꢅ8 ꢅꢐꢅꢏꢑꢀ8ꢑ
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢂꢊ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
6CDNG ꢐꢆ <ꢀ.ꢁꢀꢂꢄ&%ꢄ%JCTCEVGTKUVKEU
8
ꢄꢒꢄꢋꢆꢋ8ꢄvꢁꢂꢓꢔꢄ8 ꢄꢒꢄꢂ8
5[ODQN
+VGO
%QPFKVKQP
/KP
ꢅ ꢀꢑꢁ
6[R
/CZ
7PKV
8
+PRWVꢅ*ꢅ8QNVCIG
8
8
8
4'5'6ꢇꢅ':6#.ꢇꢅ0/+
ꢔꢀꢑꢍ
8
+PRWVꢅ*ꢅ8QNVCIG
'ZEGRVꢅ4'5'6ꢇꢅ':6#.ꢇꢅ0/+
ꢂꢑꢀ
8
ꢔꢀꢑꢍ
ꢀꢑꢁ
ꢅ
8
8
8
8
+PRWVꢅ.ꢅ8QNVCIG
4'5'6ꢇꢅ':6#.ꢇꢅ0/+
+PRWVꢅ.ꢅ8QNVCIG
'ZEGRVꢅ4'5'6ꢇꢅ':6#.ꢇꢅ0/+
1WVRWVUꢅ*ꢅ8QNVCIG
#NNꢅQWVRWVU
ꢀꢑꢍ
ꢀꢑꢍ
8
8
ꢀꢑꢆ
+
+
+
ꢅꢐꢅ ꢂꢀꢀꢅz#
ꢅꢐꢅ ꢂꢀꢅz#
ꢅꢐꢅꢎꢅO#
ꢂꢑꢄꢏ
8
8
8
8
ꢅ ꢀꢑꢁ
8
+
1WVRWVUꢅ.ꢅ8QNVCIG
#NNꢅ1WVRWVU
+PRWVꢅ.GCMCIG
%WTTGPVꢅ#NNꢅ+PRWVU
'ZEGRVꢅ:6#.ꢇꢅ':6#.
6JTGGꢅ5VCVGꢅ.GCMCIG
%WTTGPV
ꢀꢑꢎ
ꢄꢑꢀ
8 ꢅꢐꢅꢀꢑꢏꢅ`ꢅ8 ꢅ ꢀꢑꢏ
8 ꢅꢐꢅꢀꢑꢏꢅ`ꢅ8 ꢅ ꢀꢑꢏ
z#
+
+
ꢄꢑꢀ
z#
2QYGTꢅ&KUUKRCVKQP
ꢈ0QTOCNꢅ1RGTCVKQPꢉ
(ꢅꢐꢅꢂꢀꢅ/*\
ꢎꢅ/*\
ꢍꢀ
ꢎ
ꢁꢀ
ꢄꢀ
O#
2QYGTꢅ&KUUKRCVKQP
ꢈ5;56'/ꢅ5612ꢅOQFGꢉ
(ꢅꢐꢅꢂꢀꢅ/*\
ꢎꢅ/*\
ꢏ
ꢂ
ꢄꢀ
ꢏ
%
2KPꢅ%CRCEKVCPEG
8 ꢅꢐꢅꢀ8ꢇꢅHꢅꢐꢅꢄꢅ/*\
6 ꢅꢐꢅꢂꢏuꢅ%
ꢄꢂ
R(
0QVGꢅꢄ
ꢄꢑ 8
ꢅꢐꢅ8 ꢅ ꢄꢑꢀ8ꢇꢅ8
ꢅꢐꢅꢀꢑꢁ8ꢅꢈ#NNꢅQWVRWVꢅVGTOKPCNUꢅCTGꢅCVꢅ01ꢅ.1#&ꢑꢉꢅ8 ꢅꢐꢅꢍꢑꢀ8ꢑ
ꢂꢆ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
#%ꢄ%*#4#%6'4+56+%5 <ꢀ5ꢁꢀꢂ
6CDNG ꢀꢆ <ꢀ5ꢁꢀꢂꢄ#%ꢄ%JCTCEVGTKUVKEU
ꢄꢒꢄꢑ8ꢄvꢁꢂꢓꢄQTꢄ8 ꢄꢒꢄꢋꢆꢋ8ꢄvꢁꢂꢓꢔꢄꢋꢋꢊ/*\ꢄ%JCTCEVGTKUVKEUꢄ#RRN[ꢄ1PN[ꢄVQꢄꢑ8ꢄ1RGTCVKQP
8
<ꢀ5ꢁꢀꢂ ꢇꢂꢄ/*\ <ꢀ5ꢁꢀꢂ ꢋꢋꢄ/*\
0WODGT 5[ODQN
+VGO
/KP
ꢏꢀ
ꢄꢏ
ꢄꢏ
/CZ
/KP
ꢍꢀ
ꢄꢀ
ꢄꢀ
/CZ
7PKV
PU
PU
PU
PU
PU
PU
PU
PU
PU
ꢄ
ꢂ
ꢍ
ꢎ
ꢏ
ꢁ
ꢊ
ꢆ
ꢋ
V
V
V
V
V
V
V
V
V
%NQEMꢅ%[ENGꢅ6KOG
&%
&%
%NQEMꢅ * ꢅ2WNUGꢅ9KFVJ
%NQEMꢅ . ꢅ2WNUGꢅ9KFVJ
%NQEMꢅ(CNNꢅ6KOG
ꢄꢀ
ꢄꢀ
ꢍꢀ
ꢏ
ꢏ
%NQEMꢅ4KUGꢅ6KOG
2*+ꢅ4KUGꢅVQꢅ#FFTGUUꢅ8CNKFꢅ&GNC[
#FFTGUUꢅ8CNKFꢅVQꢅ/4'3ꢅ(CNNꢅQTꢅ+143ꢅ(CNNꢉ
2*+ꢅ(CNNꢅVQꢅ/4'3ꢅ(CNNꢅ&GNC[
ꢄꢏ
ꢏ
ꢏ
ꢏ
ꢏ
ꢂꢏ
ꢄꢏ
2*+ꢅ(CNNꢅVQꢅ4&ꢅ(CNNꢅ&GNC[
2*+ꢅ4KUGꢅVQꢅ4&ꢅ4KUGꢅ&GNC[
2*+ꢅ4KUGꢅVQꢅ/ꢄꢅ(CNNꢅ&GNC[
+1%ꢅꢐꢅꢄ
+1%ꢅꢐꢅꢀ
ꢂꢏ
ꢂꢏ
ꢍꢏ
ꢄꢏ
ꢄꢏ
ꢄꢏ
ꢄꢀ
ꢄꢄ
V
V
PU
PU
#FFTGUUꢅ*QNFꢅ6KOGꢅHTQOꢅ
/4'3ꢇꢅ+14'3ꢇꢅ4&ꢇꢅ94ꢅ*KIJ
ꢄꢂ
ꢄꢍ
ꢄꢎ
ꢄꢏ
ꢄꢁ
ꢄꢊ
ꢄꢆ
ꢄꢋ
ꢂꢀ
ꢂꢄ
ꢂꢂ
ꢂꢍ
ꢂꢎ
ꢂꢏ
ꢂꢁ
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
2*+ꢅ(CNNꢅVQꢅ/4'3ꢅ4KUGꢅ&GNC[
ꢂꢏ
ꢂꢏ
ꢎꢀ
ꢄꢏ
ꢄꢏ
ꢄꢏ
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
2*+ꢅ(CNNꢅVQꢅ4&ꢅ4KUGꢅ&GNC[
2*+ꢅ4KUGꢅVQꢅ/ꢄꢅ4KUGꢅ&GNC[
&CVCꢅ4GCFꢅ5GVꢃWRꢅ6KOG
ꢄꢀ
ꢀ
ꢏ
ꢀ
&CVCꢅ4GCFꢅ*QNFꢅ6KOG
2*+ꢅ(CNNꢅVQꢅ56ꢅ(CNNꢅ&GNC[
ꢍꢀ
ꢍꢀ
ꢄꢏ
ꢄꢏ
2*+ꢅ(CNNꢅVQꢅ56ꢅ4KUGꢅ&GNC[
9#+6ꢅ5GVꢃWRꢅ6KOGꢅVQꢅ2*+ꢅ(CNN
9#+6ꢅ*QNFꢅ6KOGꢅHTQOꢅ2*+ꢅ(CNN
2*+ꢅ4KUGꢅVQꢅ&CVCꢅ(NQCVꢅ&GNC[
2*+ꢅ4KUGꢅVQꢅ94ꢅ(CNNꢅ&GNC[
2*+ꢅ(CNNꢅVQꢅ9TKVGꢅ&CVCꢅ&GNC[ꢅ6KOG
9TKVGꢅ&CVCꢅ5GVꢃWRꢅ6KOGꢅVQꢅ94ꢅ(CNN
2*+ꢅ(CNNꢅVQꢅ94ꢅ4KUGꢅ&GNC[
94ꢅ2WNUGꢅ9KFVJꢅꢈ/GOQT[ꢅ9TKVGꢅ%[ENGꢉ
ꢄꢏ
ꢄꢀ
ꢄꢀ
ꢏ
ꢍꢏ
ꢂꢏ
ꢂꢏ
ꢂꢀ
ꢄꢏ
ꢄꢏ
ꢄꢀ
ꢆꢀ
ꢄꢀ
ꢎꢏ
ꢂꢏ
ꢄꢏ
ꢂꢁC
ꢂꢊ
94ꢅ2WNUGꢅ9KFVJꢅꢈ+ꢌ1ꢅ9TKVGꢅ%[ENGꢉ
9TKVGꢅ&CVCꢅ*QNFꢅ6KOGꢅHTQOꢅ94ꢅ4KUG
ꢄꢏꢀ
ꢄꢀ
ꢊꢀ
ꢏ
PU
PU
V
V
ꢂꢆ
2*+ꢅ(CNNꢅVQꢅ+143ꢅ(CNNꢅ&GNC[
2*+ꢅ4KUGꢅVQꢅ+143ꢅ(CNNꢅ&GNC[
2*+ꢅ(CNNꢅVQꢅ+143ꢅ4KUGꢅ&GNC[
+1%ꢅꢐꢅꢄ
+1%ꢅꢐꢅꢀ
ꢂꢏ
ꢂꢏ
ꢂꢏ
ꢄꢏ
ꢄꢏ
ꢄꢏ
PU
ꢂꢋ
ꢍꢀ
ꢍꢄ
V
V
V
PU
PU
PU
/ꢄꢅ(CNNꢅVQꢅ+143ꢅ(CNNꢅ&GNC[
+06ꢅ5GVꢃWRꢅ6KOGꢅVQꢅ2*+ꢅ(CNN
ꢄꢂꢏ
ꢂꢀ
ꢆꢀ
ꢄꢏ
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢂꢋ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
#%ꢄ%*#4#%6'4+56+%5 <ꢀ5ꢁꢀꢂꢄꢈ%QPVKPWGFꢉ
6CDNG ꢀꢆ <ꢀ5ꢁꢀꢂꢄ#%ꢄ%JCTCEVGTKUVKEU ꢌ%QPVKPWGFꢍ
ꢄꢒꢄꢑ8ꢄvꢁꢂꢓꢄQTꢄ8 ꢄꢒꢄꢋꢆꢋ8ꢄvꢁꢂꢓꢔꢄꢋꢋꢊ/*\ꢄ%JCTCEVGTKUVKEUꢄ#RRN[ꢄ1PN[ꢄVQꢄꢑ8ꢄ1RGTCVKQP
8
<ꢀ5ꢁꢀꢂ ꢇꢂꢄ/*\ <ꢀ5ꢁꢀꢂ ꢋꢋꢄ/*\
0WODGT 5[ODQN
+VGO
/KP
ꢄꢀ
ꢍꢏ
ꢄꢀ
ꢄꢀ
/CZ
/KP
ꢄꢀ
ꢂꢏ
ꢄꢀ
ꢄꢀ
/CZ
7PKV
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
VE[E
ꢍꢂ
ꢍꢍ
ꢍꢎ
ꢍꢏ
ꢍꢁ
ꢍꢊ
ꢍꢆ
ꢍꢋ
ꢎꢀ
ꢎꢄ
ꢎꢂ
ꢎꢍ
ꢎꢎ
ꢎꢏ
ꢎꢁ
ꢎꢊ
ꢎꢆ
ꢎꢋ
ꢏꢀ
ꢏꢄ
ꢏꢂ
ꢏꢍ
ꢏꢎ
ꢏꢏ
ꢏꢁ
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
2
2
V
V
V
V
+06ꢅ*QNFꢅ6KOGꢅHTQOꢅ2*+ꢅ(CNN
0/+ꢅ2WNUGꢅ9KFVJ
$754'3ꢅ5GVꢃWRꢅ6KOGꢅVQꢅ2*+ꢅ(CNNꢅ
$754'3ꢅ*QNFꢅ6KOGꢅHTQOꢅ2*+ꢅ(CNNꢅ
2*+ꢅ4KUGꢅVQꢅ$75#%-ꢅ(CNNꢅ&GNC[
2*+ꢅ(CNNꢅVQꢅ$75#%-ꢅ4KUGꢅ&GNC[
2*+ꢅ4KUGꢅVQꢅ$WUꢅ(NQCVKPIꢅ&GNC[ꢅ6KOG
/4'3ꢅ2WNUGꢅ9KFVJꢅꢈ*KIJꢉ
/4'3ꢅ2WNUGꢅ9KFVJꢅꢈ.QYꢉ
2*+ꢅ4KUGꢅVQꢅ4(5*ꢅ(CNNꢅ&GNC[
2*+ꢅ4KUGꢅVQꢅ4(5*ꢅ4KUGꢅ&GNC[
2*+ꢅ4KUGꢅVQꢅ*#.6ꢅ(CNNꢅ&GNC[
2*+ꢅ4KUGꢅVQꢅ*#.6ꢅ4KUGꢅ&GNC[
&4'3ꢄꢅ5GVꢃWRꢅ6KOGꢅVQꢅ2*+ꢅ4KUGꢅ
&4'3ꢄꢅ*QNFꢅ6KOGꢅHTQOꢅ2*+ꢅ4KUGꢅ
2*+ꢅ(CNN VQꢅ6'0&Kꢅ(CNN &GNC[
2*+ꢅ(CNNꢅVQꢅ6'0&Kꢅ4KUG &GNC[
2*+ꢅ4KUG VQꢅ'ꢅ4KUG &GNC[
2*+ꢅ(CNNꢅQTꢅ4KUG VQꢅ'ꢅ(CNN &GNC[
'ꢅ2WNUGꢅ9KFVJꢅꢈ*KIJꢉ
ꢂꢏ
ꢂꢏ
ꢎꢀ
ꢄꢏ
ꢄꢏ
ꢍꢀ
ꢍꢏ
ꢍꢏ
ꢂꢏ
ꢂꢏ
ꢂꢀ
ꢂꢀ
ꢄꢏ
ꢄꢏ
ꢄꢏ
ꢄꢏ
ꢄꢏ
ꢄꢏ
ꢂꢀ
ꢂꢀ
ꢄꢏ
ꢄꢏ
ꢂꢏ
ꢂꢏ
ꢍꢀ
ꢍꢀ
ꢄꢏ
ꢄꢏ
ꢄꢏ
ꢄꢏ
ꢂꢏ
ꢏꢀ
ꢂꢀ
ꢎꢀ
'ꢅ2WNUGꢅ9KFVJꢅꢈ.QYꢉ
'PCDNGꢅ4KUGꢅ6KOG
ꢄꢀ
ꢄꢀ
ꢊꢏ
ꢂ
ꢄꢀ
ꢄꢀ
ꢏꢀ
ꢂ
'PCDNGꢅ(CNNꢅ6KOG
2*+ꢅ(CNN VQꢅ6KOGTꢅ1WVRWVꢅ&GNC[
%5+ꢌ1ꢅ6TCPUOKVꢅ&CVCꢅ&GNC[ꢅ6KOGꢅꢈ+PVGTPCNꢅ
%NQEMꢅ1RGTCVKQPꢉ
ꢏꢊ
V
%5+ꢌ1ꢅ6TCPUOKVꢅ&CVCꢅ&GNC[ꢅ6KOGꢅꢈ'ZVGTPCNꢅ
%NQEMꢅ1RGTCVKQPꢉ
ꢊꢑꢏ V
ꢔꢊꢏ
ꢊꢏ V
ꢔꢁꢀ
PU
ꢏꢆ
ꢏꢋ
ꢁꢀ
ꢁꢄ
ꢁꢂ
V
V
V
V
V
%5+ꢌ1ꢅ4GEGKXGꢅ&CVCꢅ5GVꢃWRꢅ6KOGꢅꢈ+PVGTPCNꢅ
%NQEMꢅ1RGTCVKQPꢉ
ꢄ
ꢄ
ꢄ
ꢄ
VE[E
VE[E
VE[E
VE[E
PU
%5+ꢌ1ꢅ4GEGKXGꢅ&CVCꢅ*QNFꢅ6KOGꢅꢈ+PVGTPCNꢅ
%NQEMꢅ1RGTCVKQPꢉ
%5+ꢌ1ꢅ4GEGKXGꢅ&CVCꢅ5GVꢃWRꢅ6KOGꢅꢈ'ZVGTPCNꢅ
%NQEMꢅ1RGTCVKQPꢉ
ꢄ
ꢄ
%5+ꢌ1ꢅ4GEGKXGꢅ&CVCꢅ*QNFꢅ6KOGꢅꢈ'ZVGTPCNꢅ
%NQEMꢅ1RGTCVKQPꢉ
ꢄ
ꢄ
4'5'6ꢅ5GVꢃWRꢅ6KOGꢅVQꢅ2*+ꢅ(CNN
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢎꢀ
ꢂꢏ
ꢍꢀ
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
6CDNG ꢀꢆ <ꢀ5ꢁꢀꢂꢄ#%ꢄ%JCTCEVGTKUVKEU ꢌ%QPVKPWGFꢍ
ꢄꢒꢄꢑ8ꢄvꢁꢂꢓꢄQTꢄ8 ꢄꢒꢄꢋꢆꢋ8ꢄvꢁꢂꢓꢔꢄꢋꢋꢊ/*\ꢄ%JCTCEVGTKUVKEUꢄ#RRN[ꢄ1PN[ꢄVQꢄꢑ8ꢄ1RGTCVKQP
8
<ꢀ5ꢁꢀꢂ ꢇꢂꢄ/*\ <ꢀ5ꢁꢀꢂ ꢋꢋꢄ/*\
0WODGT 5[ODQN
+VGO
/KP
/CZ
/KP
/CZ
7PKV
PU
ꢁꢍ
ꢁꢎ
ꢁꢏ
ꢁꢁ
ꢁꢊ
ꢁꢆ
ꢁꢋ
ꢊꢀ
V
V
V
V
V
V
V
V
4'5'6ꢅ*QNFꢅ6KOGꢅHTQOꢅ2*+ꢅ(CNN
1UEKNNCVQTꢅ5VCDKNK\CVKQPꢅ6KOG
'ZVGTPCNꢅ%NQEMꢅ4KUGꢅ6KOGꢅꢈ':6#.ꢉ
'ZVGTPCNꢅ%NQEMꢅ(CNNꢅ6KOGꢅꢈ':6#.ꢉ
4'5'6ꢅ4KUGꢅ6KOG
ꢂꢏ
ꢄꢏ
ꢂꢀ
ꢏ
ꢂꢀ
ꢏ
PU
PU
ꢏ
ꢏ
PU
ꢏꢀ
ꢏꢀ
ꢏꢀ
ꢏꢀ
ꢏꢀ
ꢏꢀ
ꢏꢀ
ꢏꢀ
OU
OU
PU
4'5'6ꢅ(CNNꢅ6KOG
+PRWVꢅ4KUGꢅ6KOGꢅꢈGZEGRVꢅ':6#.ꢇꢅ4'5'6ꢉ
+PRWVꢅ(CNNꢅ6KOGꢅꢈGZEGRVꢅ':6#.ꢇꢅ4'5'6ꢉ
PU
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢍꢄ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
6+/+0)ꢄ&+#)4#/5
0QVGꢓꢅꢕ/GOQT[ꢅ4GCFꢌ9TKVGꢅ%[ENGꢅVKOKPIꢅKUꢅVJGꢅUCOGꢅCUꢅ+ꢌ1ꢅ
4GCFꢌ9TKVGꢅ%[ENGꢅGZEGRVꢅVJGTGꢅCTGꢅPQꢅCWVQOCVKEꢅYCKVꢅ
UVCVGUꢅꢈ6 ꢉꢇꢅCPFꢅ/4'3ꢅKUꢅCEVKXGꢅKPUVGCFꢅQHꢅ+143ꢑ
(KIWTG ꢇꢂꢆ %27ꢄ6KOKPIꢄ
ꢌ1REQFGꢄ(GVEJꢄ%[ENGꢎꢄ/GOQT[ꢄ4GCFꢄ%[ENGꢎꢄ
/GOQT[ꢄ9TKVGꢄ%[ENGꢎꢄ+ꢃ1ꢄ9TKVG %[ENGꢎ +ꢃ1 4GCFꢄ%[ENGꢍ
ꢍꢂ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
2*+
+06ꢀꢇꢄꢇꢂ
0/+
/ꢄ
+143ꢅ
&CVCꢅ+0ꢅ
/4'3ꢅ
4(5*ꢅ
$754'3
$75#%-
#ꢄꢋ ꢀꢇꢅ&ꢊ ꢀ
/4'3ꢇꢅ4&
94ꢇꢅ+143
1WVRWVꢅ$WHHGTꢅ1HH
*#.6
(KIWTG ꢇꢁꢆ %27ꢄ6KOKPIꢄ
ꢌ+06ꢂꢄ#EMPQYNGFIGꢄ%[ENGꢎꢄ4GHTGUJꢄ%[ENGꢎꢄ$75ꢄ4'.'#5'ꢄ/QFGꢎꢄ
*#.6ꢄ/QFGꢎꢄ5.''2ꢄ/QFGꢎꢄ5;56'/ꢄ5612ꢄ/QFGꢍ
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢍꢍ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
6+/+0)ꢄ&+#)4#/5ꢄꢈ%QPVKPWGFꢉ
+ꢌ1ꢅ9TKVGꢅ%[ENG
+ꢌ1ꢅ4GCFꢅ%[ENG
6
6
6
6
6
6
6
6
2*+
#&&4'55
ꢂꢆ
ꢋ
ꢂꢋ
ꢄꢍ
ꢂꢆ
ꢂꢂ
ꢂꢋ
+143
4&
ꢂꢏ
94
+ꢌ1ꢅ4GCFꢅ%[ENG
%27ꢅ6KOKPIꢅꢈ+1%ꢅꢐꢅꢀꢉ
+ꢌ1ꢅ9TKVGꢅ%[ENG
(KIWTG ꢇꢇꢆ %27ꢄ6KOKPIꢄꢌ+1%ꢄꢒꢄꢂꢍꢄ
ꢌ+ꢃ1ꢄ4GCFꢄ%[ENGꢎꢄ+ꢃ1ꢄ9TKVGꢄ%[ENGꢍ
%27ꢅQTꢅ&/#ꢅ4GCFꢌ9TKVGꢅ%[ENGꢅꢈ1PN[ꢅ&/#ꢅ9TKVGꢅ%[ENGꢅHQTꢅ6'0&Kꢉ
6
6
6
6
6
2*+
ꢎꢁ
ꢎꢏ
&4'3ꢄ
ꢈNGXGNꢅUGPUGꢉ
ꢎꢏ ꢎꢁ
&4'3ꢄ
ꢈGFIGꢅUGPUGꢉ
ꢄꢆ
ꢎꢊ
ꢎꢆ
ꢄꢊ
6'0&K
56
0QVGUꢅ
ꢕ6
ꢅCPFꢅ6
ꢅCPFꢅ6
ꢅCTGꢅURGEKHKGFꢅHQTꢅVJGꢅTKUKPIꢅGFIGꢅQHꢅVJGꢅENQEMꢅHQNNQYGFꢅD[ꢅ6 ꢑꢅ
ꢅCTGꢅURGEKHKGFꢅHQTꢅVJGꢅTKUKPIꢅGFIGꢅQHꢅVJGꢅENQEMꢑ
ꢕꢕ6
(KIWTG ꢇꢋꢆ &/#ꢄ%QPVTQNꢄ5KIPCNU
ꢍꢎ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
6
6
6
6
6
2*+
ꢎꢋ
ꢏꢀ
ꢏꢀ
'
ꢈ/GOQT[ꢅ4GCFꢌ9TKVGꢉ
ꢎꢋ
'
ꢈ+ꢌ1ꢅ4GCFꢉ
ꢎꢋ
ꢏꢀ
'
ꢄꢏ
ꢄꢁ
ꢈ+ꢌ1ꢅ9TKVGꢉ
&
&
(KIWTG ꢇꢉꢆ 'ꢄ%NQEMꢄ6KOKPIꢄ
ꢌ/GOQT[ꢄ4GCFꢃ9TKVGꢄ%[ENGꢎꢄ+ꢃ1ꢄ4GCFꢃ9TKVGꢄ%[ENGꢍ
2*+
'
ꢎꢋ
ꢏꢀ
$75ꢅ4'.'#5'ꢅOQFG
5.''2ꢅOQFG
5;56'/ꢅ5612ꢅOQFG
(KIWTG ꢇꢑꢆ 'ꢄ%NQEMꢄ6KOKPI
ꢌ$75ꢄ4'.'#5'ꢄ/QFGꢎꢄ5.''2ꢄ/QFGꢎꢄ5;56'/ꢄ5612ꢄ/QFGꢍ
6
6
6
6
6
2*+
'
ꢎꢋ
ꢏꢍ
ꢏꢀ
ꢏꢎ
ꢏꢂ
'ZCORNG
+ꢌ1ꢅ4GCF
→ꢅ1REQFGꢅ(GVEJ
ꢏꢀ
ꢎꢋ
ꢏꢍ
ꢏꢄ
'
ꢈ+ꢌ1ꢅ9TKVGꢉ
ꢏꢎ
(KIWTG ꢇꢈꢆ 'ꢄ%NQEMꢄ6KOKPIꢄ
ꢌ/KPKOWOꢄ6KOKPIꢄ'ZCORNGꢄQHꢄ2 ꢄCPFꢄ2
ꢍ
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢍꢏ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
6+/+0)ꢄ&+#)4#/5ꢄꢈ%QPVKPWGFꢉ
2*+
6KOGTꢅ&CVC
4GIꢑꢅꢐꢅꢀꢀꢀꢀ*
#
ꢌ6
ꢏꢏ
(KIWTG ꢇꢐꢆ 6KOGTꢄ1WVRWVꢄ6KOKPI
0GZVꢅ1REQFGꢅ(GVEJ
5.2ꢅ+PUVTWEVKQPꢅ(GVEJ
6
6
6
6
6
6
6
2*+
ꢍꢄ
ꢍꢂ
+06K
0/+
ꢍꢍ
#
#
/4'3ꢇꢅ/ꢄ
4&
ꢎꢍ
ꢎꢎ
*#.6
(KIWTG ꢇꢀꢆ 5.2ꢄ'ZGEWVKQPꢄ%[ENG
ꢍꢁ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
%5+ꢌ1ꢅ%NQEM
ꢏꢁ
ꢏꢁ
6TCPUOKVꢅ&CVC
ꢈ+PVGTPCNꢅ%NQEMꢉ
ꢏꢊ
ꢏꢊ
6TCPUOKVꢅ&CVC
ꢈ'ZVGTPCNꢅ%NQEMꢉ
ꢄꢄV
ꢄꢄV
ꢏꢆ
ꢏꢆ
ꢏꢋ
ꢏꢋ
4GEGKXGꢅ&CVC
ꢈ+PVGTPCNꢅ%NQEMꢉ
ꢄꢁꢑꢏV
ꢄꢄꢑꢏV
ꢄꢄꢑꢏV
ꢄꢁꢑꢏV
4GEGKXGꢅ&CVC
ꢈ'ZVGTPCNꢅ%NQEMꢉ
ꢁꢀ
ꢁꢄ
ꢁꢀ
ꢁꢄ
(KIWTG ꢇꢏꢆ %5+ꢃ1ꢄ4GEGKXGꢃ6TCPUOKVꢄ6KOKPI
ꢁꢋ
ꢊꢀ
ꢁꢏ
ꢁꢁ
':6#.ꢅ8
8
8
8
+PRWVꢅ4KUGꢅ6KOGꢅCPFꢅ(CNNꢅ6KOGꢅ
ꢈ'ZEGRVꢅ':6#.ꢇꢅ4'5'6ꢉ
'ZVGTPCNꢅ%NQEMꢅ4KUGꢅ6KOGꢅ
CPFꢅ(CNNꢅ6KOG
(KIWTG ꢋꢂꢆ 4KUGꢄ6KOGꢄCPFꢄ(CNNꢄ6KOGU
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢍꢊ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
%27ꢄ%10641.ꢄ4')+56'4
%27ꢄ%QPVTQNꢄ4GIKUVGTꢄꢌ%%4ꢍꢆꢄThis register controls the
basicclockrate, certainaspectsofPower-Downmodes, and
output drive/low-noise options (Figure 31).
%27ꢅ%QPVTQNꢅ4GIKUVGTꢅꢈ%%4ꢉ
&ꢍ
&ꢀ
&ꢂ &ꢄ
&ꢊ &ꢁ &ꢏ &ꢎ
%NQEMꢅ&KXKFG
ꢅꢀꢅꢐꢅ:6#.ꢌꢂ
ꢅꢄꢅꢐꢅ:6#.ꢌꢄ
.0#&ꢌ#
ꢀꢅꢐꢅ5VCPFCTFꢅ&TKXG
ꢄꢅꢐꢅꢍꢍꢖꢅ&TKXGꢅQP
ꢅꢅꢅꢅꢅꢅ#ꢄꢋ #ꢀꢇꢅ&ꢊ &ꢀ
56#0&$;ꢌ+&.'ꢅ'PCDNG
ꢅꢀꢀꢅꢐꢅ0Qꢅ56#0&$;
.0%27%6.
ꢅꢀꢅꢐꢅ5VCPFCTFꢅ&TKXG
ꢅꢄꢅꢐꢅꢍꢍꢖꢅ&TKXGꢅQPꢅ%27
ꢅꢅꢅꢅꢅꢅꢅꢅ%QPVTQNꢅ5KIPCNU
ꢅꢀꢄꢅꢐꢅ+&.'ꢅ#HVGTꢅ5.''2
ꢅꢄꢀꢅꢐꢅ56#0&$;ꢅ#HVGTꢅ5.''2
ꢅꢄꢄꢅꢐꢅ56#0&$;ꢅ#HVGTꢅ5.''2
ꢅꢅꢅꢅꢅꢅꢅꢅꢅꢅꢅꢁꢎꢃ%[ENGꢅ'ZKV
.0+1
ꢅꢅꢅꢅꢅꢅꢅꢅꢅꢅꢅꢈ37+%-ꢅ4'%18'4;ꢉ
ꢅꢀꢅꢐꢅ5VCPFCTFꢅ&TKXG
ꢅꢄꢅꢐꢅꢍꢍꢖꢅ&TKXGꢅQP
ꢅꢅꢅꢅꢅꢅꢅꢅ)TQWRꢅꢄꢅ+ꢌ1ꢅ5KIPCNU
$4':6
ꢅꢀꢅꢐꢅ+IPQTGꢅ$754'3
ꢅꢅꢅꢅꢅꢅꢅꢅQPꢅ56#0&$;ꢌ+&.'
ꢅꢄꢅꢐꢅ56#0&$;ꢌ+&.'ꢅ'ZKV
ꢅꢅꢅꢅꢅꢅꢅꢅꢅQPꢅ$754'3ꢅ
.02*+
ꢅꢀꢅꢐꢅ5VCPFCTFꢅ&TKXG
ꢅꢄꢅꢐꢅꢍꢍꢖꢅ&TKXGꢅQP
ꢅꢅꢅꢅꢅꢅꢅꢅ2*+ꢅ2KP
(KIWTG ꢋꢁꢆ %27ꢄ%QPVTQNꢄ4GIKUVGTꢄꢌ%%4ꢍꢄ#FFTGUUꢄꢁ(*
$KVꢄꢐꢆꢄClock Divide Select. If this bit isꢅ0, as it is after a 4'ꢃ
5'6, the Z8S180/Z8L180 divides the frequency on the
:6#. pin(s) by two to obtain its Master clock 2*+. If this
bit is programmed asꢅ1, the part uses the :6#. frequency
as 2*+ without division.
When D6 and D3 are both 1, setting +15612 (+%4ꢏ) and
executing a 5.2 instruction puts the part into 37+%-ꢅ4'ꢃ
%18'4; 56#0&$; mode, in which the on-chip oscillator
is stopped, and the part allows only 64 clock cycles for the
oscillator to stabilize when it restarts.
If an external oscillator is used in divide-by-one mode, the
minimum pulse width requirement provided in the AC
Characteristics must be satisfied.
The latter section, *#.6 and .19ꢅ219'4 modes, de-
scribes the subject more fully.
$KV ꢑ $4':6ꢆꢄThis bit controls the ability of the
Z8S180/Z8L180 to honor a bus request during 56#0&$;
mode. If this bit is set to 1 and the part is in 56#0&$;
mode, a $754'3 is honored after the clock stabilization
timer is timed out.
$KVUꢄꢈꢄCPFꢄꢋꢆꢄ56#0&$;/+&.' Control. When these bits
arebothꢅ0, a5.2 instructionmakes the Z8S180/Z8L180en-
ter 5.''2 or 5;56'/ꢅ5612 mode, depending on the
+15612 bit (ICR5).
When D6 isꢅ0and D3 isꢅ1, setting the +15612 bit (ICR5)
and executing a 5.2 instruction puts the Z8S180/Z8L180
into +&.' mode in which the on-chip oscillator runs, but its
output isblockedfromthe rest ofthe part, including2*+ out.
$KVꢄꢉꢄ.02*+ꢆꢄThis bit controls the drive capability on the
2*+ Clock output. If this bit is set to 1, the 2*+ Clock output
is reduced to 33 percent of its drive capability.
When D6 is 1 and D3 isꢅ0, setting +15612 (ICR5) and
executing a 5.2 instruction puts the part into 56#0&$;
mode, in which the on-chiposcillator is stopped and thepart
17
allows 2 (128K) clock cycles for the oscillator to stabilize
when it restarts.
ꢍꢆ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
$KVꢄꢇꢄ.0+1ꢆꢄThis bit controls the drive capability of certain
external I/O pins of the Z8S180/Z8L180. When this bit is
set to 1, the output drive capability of the following pins is
reduced to 33 percent of the original drive capability:
$KVꢄꢁꢄ.0%27%6.ꢆꢄThis bit controls the drive capability of
the CPU Control pins. When this bit is set to 1, the output
drive capability of the following pins is reduced to 33 per-
cent of the original drive capability:
465ꢀ
6Z5
$75#%-
94
4&
%-#ꢄꢌ6'0&ꢀ
6:#ꢀ
%-#ꢀꢌ&4'3ꢀ
6:#ꢄ
/ꢄ
/4'3
4(5*
'
+143
*#.6
6'56
6'0&K
%-5
56
$KVꢄꢂꢄ.0#&ꢃ#ꢆꢄThis bit controls the drivecapability of
the Address/Data bus output drivers. If this bit is set to 1,
the output drive capability of the Address and Data bus out-
puts is reduced to 33 percent of its original drive capability.
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢍꢋ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
#5%+ꢄ4')+56'4ꢄ&'5%4+26+10
+PVGTPCNꢅ#FFTGUUꢌ&CVCꢅ$WU
+PVGTTWRVꢅ4GSWGUV
#5%+ꢅ6TCPUOKVꢅ&CVCꢅ4GIKUVGT
%Jꢅꢀꢓꢅ6&4ꢀ
#5%+ꢅ6TCPUOKVꢅ&CVCꢅ4GIKUVGT
%Jꢅꢄꢓꢅ6&4ꢄ
6:#ꢀ
6:#ꢄ
#5%+ꢅ6TCPUOKVꢅ5JKHVꢅ4GIKUVGTꢕ
#5%+ꢅ6TCPUOKVꢅ5JKHVꢅ4GIKUVGTꢕ
#5%+ꢅ4GEGKXGꢅ&CVCꢅ(+(1
%Jꢅꢀꢓꢅ4&4ꢀ
#5%+ꢅ4GEGKXGꢅ&CVCꢅ(+(1
%Jꢅꢄꢓꢅ4&4ꢄ
4:#ꢀ
4:#ꢄ
%65ꢄ
#5%+ꢅ4GEGKXGꢅ5JKHVꢅ4GIKUVGTꢕ
%Jꢅꢀꢓꢅ454ꢀꢅꢈꢆꢉ
#5%+ꢅ4GEGKXGꢅ5JKHVꢅ4GIKUVGTꢕ
%Jꢅꢄꢓꢅ454ꢄꢅꢈꢆꢉ
#5%+ꢅ%QPVTQNꢅ4GIKUVGTꢅ#
%Jꢅꢀꢓꢅ%06.#ꢀꢅꢈꢆꢉ
#5%+ꢅ%QPVTQNꢅ4GIKUVGTꢅ#
%Jꢅꢄꢓꢅ%06.#ꢄꢅꢈꢆꢉ
#5%+
465ꢀ
%65ꢀ
%QPVTQN
#5%+ꢅ%QPVTQNꢅ4GIKUVGTꢅ$
%Jꢅꢀꢓꢅ%06$ꢀꢅꢈꢆꢉ
#5%+ꢅ%QPVTQNꢅ4GIKUVGTꢅ$
%Jꢅꢄꢓꢅ%06$ꢄꢅꢈꢆꢉ
#5%+ꢅ5VCVWUꢅ(+(1
%Jꢅꢀꢅ
#5%+ꢅ5VCVWUꢅ(+(1
%Jꢅꢄꢅ
#5%+ꢅ5VCVWUꢅ4GIKUVGT
%Jꢅꢀꢓꢅ56#6ꢀꢅꢈꢆꢉ
&%&ꢀ
#5%+ꢅ5VCVWUꢅ4GIKUVGT
%Jꢅꢄꢓꢅ56#6ꢄꢅꢈꢆꢉ
#5%+ꢅ'ZVGPUKQPꢅ%QPVTQNꢅ4GIꢑ
%Jꢅꢀꢓꢅ#5':6ꢀꢅꢈꢊꢉ
#5%+ꢅ'ZVGPUKQPꢅ%QPVTQNꢅ4GIꢑ
%Jꢅꢄꢓꢅ#5':6ꢄꢅꢈꢏꢉ
#5%+ꢅ6KOGꢅ%QPUVCPVꢅ.QY
%Jꢅꢀꢓꢅ#56%ꢀ.ꢅꢈꢆꢉ
#5%+ꢅ6KOGꢅ%QPUVCPVꢅ.QY
%Jꢅꢄꢓꢅ#56%ꢄ.ꢅꢈꢆꢉ
#5%+ꢅ6KOGꢅ%QPUVCPVꢅ*KIJ
%Jꢅꢀꢓꢅ#56%ꢀ*ꢅꢈꢆꢉ
#5%+ꢅ6KOGꢅ%QPUVCPVꢅ*KIJ
%Jꢅꢄꢓꢅ#56%ꢄ*ꢅꢈꢆꢉ
0QVGꢅꢅꢕ0QVꢅ2TQITCOꢅ
#EEGUUKDNGꢑ
%-#ꢀ
%-#ꢄ
$CWFꢅ4CVG
)GPGTCVQTꢅꢀ
2*+
$CWFꢅ4CVG
)GPGTCVQTꢅꢄ
(KIWTG ꢋꢇꢆ #5%+ꢄ$NQEMꢄ&KCITCO
#5%+ꢄ6TCPUOKVꢄ5JKHVꢄ4GIKUVGTꢄꢂꢎꢁꢆꢄWhen the ASCI
Transmit Shift Register (654) receives data from the ASCI
Transmit Data Register (6&4), the data is shifted out to the
6:# pin. When transmission is completed, the next byte (if
available) is automatically loaded from 6&4 into 654 and
the next transmission starts. If no data is available for trans-
mission, 654 idles by outputting a continuous High level.
This register is not program-accessible
#5%+ꢄ6TCPUOKVꢄ&CVCꢄ4GIKUVGTꢄꢂꢎꢁꢄꢌ6&4ꢂꢎꢄꢁꢅꢄ+ꢃ1ꢄCFFTGUU
ꢒꢄꢂꢈ*ꢎꢄꢂꢐ*ꢍꢆꢄData written to the ASCI Transmit Data
Register is transferred to the 654 as soon as 654 is empty.
Data can be written while 654 is shifting out the previous
byte of data. Thus, the ASCI transmitter is double buffered.
ꢎꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
#5%+ꢄ4GEGKXGꢄ&CVCꢄ(+(1ꢄꢂꢎꢁꢄꢌ4&4ꢂꢎꢄꢁꢅ+ꢃ1ꢄ#FFTGUUꢄꢒ
ꢂꢀ*ꢎꢄꢂꢏ*ꢍꢆꢄTheASCIReceiveDataRegisterisaread-only
register. When a complete incoming data byte is assembled
in 454, it is automatically transferred to the 4 character Re-
ceive Data First-In First-Out ((+(1) memory. The oldest
character in the (+(1 (if any) can be read from the Receive
Data Register (4&4). The next incoming data byte can be
shifted into 454 while the (+(1 is full. Thus, the ASCI re-
ceiver is well buffered.
Data can be written into and read from the ASCI Transmit
Data Register. If data is read from the ASCI Transmit Data
Register, the ASCI data transmit operation is not affected
by this 4'#& operation.
#5%+ꢄ4GEGKXGꢄ5JKHVꢄ4GIKUVGTꢄꢂꢎꢁꢄꢌ454ꢂꢎꢁꢍꢆꢄThis register
receives data shifted in on the 4:# pin. When full, data is
automatically transferred to the ASCI Receive Data Regis-
ter (4&4) if it is empty. If 454 is not empty when the next
incoming data byte is shifted in, an overrun error occurs.
This register is not program accessible.
#5%+ꢄ56#675ꢄ(+(1
This four-entry (+(1 contains Parity Error, Framing Error,
acter in the receive data (+(1. The status of the oldest char-
RxOverrun, andBreakstatusbitsassociatedwitheachchar-
acter (if any) can be read from the ASCI status registers.
#5%+ꢄ%*#00'.ꢄ%10641.ꢄ4')+56'4ꢄ#
#5%+ꢅ%QPVTQNꢅ4GIKUVGTꢅ#ꢅꢀꢅꢈ%06.#ꢀꢓꢅ+ꢌ1ꢅ#FFTGUUꢅꢐꢅꢀꢀ*ꢉ
ꢏ
ꢎ
ꢍ
ꢂ
ꢄ
ꢀ
$KV
$KV
ꢊ
ꢁ
/2$4ꢌ
'(4
/1&ꢂ
4ꢌ9
/1&ꢄ /1&ꢀ
4'
6'
465ꢀ
4ꢌ9
ꢅ/2'
4ꢌ9
4ꢌ9
4ꢌ9
4ꢌ9
4ꢌ9
4ꢌ9
#5%+ꢅ%QPVTQNꢅ4GIKUVGTꢅ#ꢅꢄꢅꢈ%06.#ꢄꢓꢅ+ꢌ1ꢅ#FFTGUUꢅꢐꢅꢀꢄ*ꢉ
ꢂ
ꢄ
ꢍ
ꢊ
ꢁ
ꢎ
ꢀ
ꢏ
/2$4ꢌ
/1&ꢂ
4ꢌ9
/1&ꢄ /1&ꢀ
4ꢌ9 4ꢌ9
4'
6'
ꢅ/2'
4ꢌ9
%-#ꢄ& '(4
4ꢌ9
4ꢌ9
4ꢌ9
4ꢌ9
(KIWTG ꢋꢋꢆ #5%+ꢄ%JCPPGNꢄ%QPVTQNꢄ4GIKUVGTꢄ#
/2'ꢅꢄ/WNVKꢊ2TQEGUUQTꢄ/QFGꢄ'PCDNGꢄꢌ$KVꢄꢐꢍꢆꢄThe ASCI
featuresamultiprocessorcommunicationmodethatutilizes
an extra data bit for selective communication when a num-
ber of processors share a common serial bus. Multiproces-
sor data format is selected when the /2 bit in %06.$ is set
to 1. If multiprocessor mode is not selected (/2 bit in
%06.$ꢅꢐꢅꢀ), /2' has no effect. If multiprocessor mode
is selected, /2' enables or disables the wake-up feature as
follows. If /$' is set to 1, only received bytes in which the
multiprocessorbitꢅ(/2$ )ꢅꢐꢅꢄ canaffectthe4&4(anderror
flags. Effectively, other bytes (with /2$ꢅꢐꢅꢀ) are ignored
by the ASCI. If /2' is reset toꢅ0, all bytes, regardless of
the state of the/2$ data bit, affect the4'&4 and errorflags.
/2' is cleared toꢅ0during 4'5'6.
4'ꢅꢄ4GEGKXGTꢄ'PCDNGꢄꢌ$KVꢄꢈꢍꢆꢄWhen4' is set to1, theASCI
transmitter is enabled. When 6' is reset toꢅ0, the transmitter
is disables and any transmit operation in progress is inter-
rupted. However, the 6&4'flagisnotresetandthe previous
contents of 6&4' are held. 6' is cleared toꢅ0in +15612
mode during 4'5'6.
6'ꢅꢄ6TCPUOKVVGTꢄ'PCDNGꢄꢌ$KVꢄꢑꢍꢆꢄWhen 6' is set to 1, the
ASCI receiver is enabled. When 6' is reset toꢅ0, the trans-
mitter is disabled and any transmit operation in progress is
interrupted. However, the6&4' flagisnot reset andthe pre-
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢎꢄ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
#5%+ꢄ%*#00'.ꢄ%10641.ꢄ4')+56'4ꢄ#ꢄꢈ%QPVKPWGFꢉ
/1&ꢁ
vious contents of 6&4' are held. 6' is cleared toꢅ0 in
+15612 mode during 4'5'6.
ꢐꢅꢀ→0QꢅRCTKV[
465ꢂꢅꢄ 4GSWGUVꢄ VQꢄ 5GPFꢄ %JCPPGNꢄ ꢂꢄ ꢌ$KVꢄ ꢉꢄ KPꢄ %06.#ꢂ
1PN[ꢍꢆꢄIf bit 4 of the System Configuration Register isꢅ0,
the465ꢀ/6:5pinexhibitsthe465ꢀ function.465ꢀ allows
the ASCI to control (start/stop) another communication de-
vices transmission (for example, by connecting to that de-
vice’s %65 input). 465ꢀ is essentially a 1-bit output port,
having no side effects on other ASCI registers or flags.
ꢐꢅꢄ→2CTKV[ꢅGPCDNGF
/1&ꢂ
ꢐꢅꢀ→ꢄꢅUVQRꢅDKV
ꢐꢅꢄ→ꢂꢅUVQRꢅDKVU
Bit 4 in %06.#ꢄ is used.
The data formats available based on all combinations of
/1&ꢂ, /1&ꢄ, and /1&ꢀ are indicated in Table 9.
%-#ꢄ&ꢅꢐꢅꢄꢇꢅ%-#ꢄꢌ6'0&ꢀꢅRKPꢅꢐꢅ6'0&ꢀ
6CDNG ꢏꢆ &CVCꢄ(QTOCVU
%-#ꢄ&ꢅꢐ ꢀ, %-#ꢄꢌ6'0&ꢀꢅRKPꢅꢐꢅ%-#ꢄ
/1&ꢇ /1&ꢁ /1&ꢂ &CVCꢄ(QTOCV
These bits are cleared toꢅ0on reset.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢄ
ꢀ
ꢄ
ꢀ
5VCTVꢅꢔꢅꢊꢅDKVꢅFCVCꢅꢔꢅꢄꢅUVQR
5VCTVꢅꢔꢅꢊꢅDKVꢅFCVCꢅꢔꢅꢂꢅUVQR
5VCTVꢅꢔꢅꢊꢅDKVꢅFCVCꢅꢔꢅRCTKV[ꢅꢔꢅ
ꢄꢅUVQR
/2$4ꢃ'(4ꢅꢄ/WNVKRTQEGUUQTꢄ$KVꢄ4GEGKXGꢃ'TTQTꢄ(NCIꢄ4GUGV
ꢌ$KVꢄꢋꢍꢆꢄWhen multiprocessor mode is enabled (/2 in
%06.$ꢅꢐꢅꢄ), /2$4, when read, contains the value of the
/2$ bit for the most recent receive operation. When written
toꢅ0, the '(4 function is selected to reset all error flags
(1840, (', 2' and $4- in the #5':6 Register) to 0.
/2$4/'(4 is undefined during 4'5'6.
ꢀ
ꢄ
ꢄ
5VCTVꢅꢔꢅꢊꢅDKVꢅFCVCꢅꢔꢅRCTKV[ꢅꢔꢅ
ꢂꢅUVQR
ꢄ
ꢄ
ꢄ
ꢀ
ꢀ
ꢄ
ꢀ
ꢄ
ꢀ
5VCTVꢅꢔꢅꢆꢅDKVꢅFCVCꢅꢔꢅꢄꢅUVQR
5VCTVꢅꢔꢅꢆꢅDKVꢅFCVCꢅꢔꢅꢂꢅUVQR
5VCTVꢅꢔꢅꢆꢅDKVꢅFCVCꢅꢔꢅRCTKV[ꢅꢔꢅ
ꢄꢅUVQR
/1&ꢇꢎꢄ ꢁꢎꢄ ꢂꢅꢄ #5%+ꢄ &CVCꢄ (QTOCVꢄ /QFGꢄ ꢇꢎꢁꢎꢂꢄ ꢌDKVUꢄ ꢇ ꢂꢍꢆ
These bits program the ASCI data format as follows.
ꢄ
ꢄ
ꢄ
5VCTVꢅꢔꢅꢆꢅDKVꢅFCVCꢅꢔꢅRCTKV[ꢅꢔꢅ
ꢂꢅUVQR
/1&ꢇ
ꢐꢅꢀ→ꢊ DKVꢅFCVC
ꢐꢅꢄ→ꢆꢅDKVꢅFCVC
ꢎꢂ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
#5%+ꢄ%*#00'.ꢄ%10641.ꢄ4')+56'4ꢄ$
#5%+ꢅ%QPVTQNꢅ4GIKUVGTꢅ$ꢅꢀꢅꢈ%06.$ꢀꢓꢅ+ꢌ1ꢅ#FFTGUUꢅꢐꢅꢀꢂ*ꢉ
#5%+ꢅ%QPVTQNꢅ4GIKUVGTꢅ$ꢅꢄꢅꢈ%06.$ꢄꢓꢅ+ꢌ1ꢅ#FFTGUUꢅꢐꢅꢀꢍ*ꢉ
ꢂ
ꢄ
$KV
ꢏ
ꢍ
ꢊ
ꢁ
ꢎ
ꢀ
%65ꢌ
25
/2
ꢅ/2$6
4ꢌ9
2'1
4ꢌ9
&4
55ꢂ
4ꢌ9
55ꢄ
4ꢌ9
55ꢀ
4ꢌ9
4ꢌ9
4ꢌ9
4ꢌ9
(KIWTG ꢋꢉꢆ #5%+ꢄ%JCPPGNꢄ%QPVTQNꢄ4GIKUVGTꢄ$
/2$6ꢅꢄ/WNVKRTQEGUUQTꢄ$KVꢄ6TCPUOKVꢄꢌ$KVꢄꢐꢍꢆꢄWhen multi-
processor communication format is selected (/2 bit = ꢄ),
/2$6 is used to specify the /2$ data bit for transmission.
If /2$6ꢅꢐ 1, then /2$ꢅꢐꢅꢄ is transmitted. If /2$6ꢅꢐ
0, then /2$ꢅꢐꢅ0is transmitted. The /2$6 state is unde-
fined during and after 4'5'6.
2'1ꢅꢄ2CTKV[ꢄ'XGPꢄ1FFꢄꢌ$KVꢄꢉꢍꢄꢆꢄ2'1 selects oven or odd
parity. 2'1 does not affect the enabling/disabling of parity
(/1&ꢄ bit of %06.#). If 2'1 is cleared toꢅ0, even parity
is selected. If 2'1 is set to 1, odd parity is selected. 2'1 is
cleared toꢅ0during 4'5'6.
&4ꢅꢄ&KXKFGꢄ4CVKQꢄꢌ$KVꢄꢋꢍꢆꢄIf the :ꢄ bit in the #5':6 reg-
ister isꢅ0, this bit specifies the divider used to obtain baud
rate from the data sampling clock. If &4 is reset toꢅ0, divide-
by-16 is used, while if &4 is set to 1, divide-by-64 is used.
&4 is cleared toꢅ0during 4'5'6.
/2ꢅꢄ/WNVKRTQEGUUQTꢄ/QFGꢄꢌ$KVꢄꢈꢍꢆꢄWhen /2 is set to 1,
thedataformatisconfiguredformultiprocessormodebased
on /1&ꢂ (number of data bits) and /1&ꢀ (number of stop
bits) in %06.#. The format is as follows:
5VCTVꢅDKVꢅꢔꢅꢊꢅQTꢅꢆꢅFCVCꢅDKVUꢅꢔꢅ/2$ꢅDKVꢅꢔꢅꢄꢅQTꢅꢂꢅUVQRꢅDKVU
55ꢇꢎꢁꢎꢂꢅꢄ5QWTEGꢃ5RGGFꢄ5GNGEVꢄꢇꢎꢁꢎꢂꢄꢌ$KVUꢄꢇ ꢂꢍꢆꢄFirst,
if these bits are ꢄꢄꢄ, as they are after a 4'5'6, the %-#
pin is used as a clock input, and is divided by 1, 16, or 64
depending on the &4 bit and the :ꢄ bit in the #5':6 reg-
ister.
Multiprocessor (/2ꢅꢐꢅꢄ) format offers no provision for
parity. If /2ꢅꢐꢅ0, the data format is based on /1&ꢀ,
/1&ꢄ, /1&ꢂ, and may include parity. The /2 bit is
cleared toꢅ0during 4'5'6.
If these bits are not ꢄꢄꢄ and the $4) mode bit is #5':6
isꢅ0, then these bits specify a power-of-two divider for the
2*+ clock as indicated in Table 10.
%65ꢃ25ꢅꢄ%NGCTꢄVQꢄ5GPFꢃ2TGUECNGꢄꢌ$KVꢄꢑꢍꢆꢄWhen read,
%65ꢌ25 reflects the state of the external %65 input. If the
%65 input pin is High, %65ꢌ25 is read as 1.
Setting or leaving these bits as ꢄꢄꢄ makes sense for a chan-
nel only when its %-# pin is selected for the %-# function.
%-#1ꢌ%-5 offers the%-#1 functionwhenbit4oftheSys-
tem Configuration Register is 0. &%&ꢀ/%-#ꢄ offers the
%-#ꢄ functionwhenbitꢅ0of theInterruptEdgeregisteris1.
0QVGꢅ When the %65 input pin is High, the 6&4' bit is inhib-
ited (that is, held at ꢀ).
For channel 1, the %65 input is multiplexed with 4:5 pin
(Clocked Serial Receive Data). Thus, %65ꢌ25 is only valid
when read if the channel 1 %65ꢄ' bit = 1 and the %65
input pin function is selected. The 4'#& data of %65ꢌ25
is not affected by 4'5'6.
6CDNG ꢁꢂꢆ &KXKFGꢄ4CVKQ
55ꢇ
55ꢁ
55ꢂ
&KXKFGꢄ4CVKQ
ꢀ
ꢀ
ꢀ
ꢀ
ꢄ
ꢄ
ꢄ
ꢄ
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
÷ꢄ
÷ꢂ
÷ꢎ
÷ꢆ
÷ꢄꢁ
If the 55ꢂ ꢀ bits in this register are not ꢄꢄꢄ, and the $4)
mode bit in the #5':6 register isꢅ0, then writing to this bit
sets the prescale (PS) control. Under those circumstances,
aꢅ0indicates a divide-by-10 prescale function while a 1
indicates divide-by-30. The bit resets to 0.
÷ꢍꢂ
÷ꢁꢎ
'ZVGTPCNꢅ%NQEM
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢎꢍ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
#5%+ꢄ56#675ꢄ4')+56'4ꢄꢂꢎꢁ
Each ASCI channel status register (56#6ꢀꢇꢄ) allows inter-
rogation of ASCI communication, error and modem control
signal status, and the enabling or disabling of ASCI inter-
rupts.
#5%+ꢅ5VCVWUꢅ4GIKUVGTꢅꢀꢅꢈ56#6ꢀꢓꢅ+ꢌ1ꢅ#FFTGUUꢅꢐꢅꢀꢎ*ꢉ
ꢎ
$KV
$KV
ꢊ
ꢁ
ꢏ
ꢍ
ꢂ
ꢄ
ꢀ
2'
4
('
4
4'
6&4'
4
6+'
4&4( 1840
&%&ꢀ
4
4
4
4ꢌ9
4ꢌ9
#5%+ꢅ5VCVWUꢅ4GIKUVGTꢅꢄꢅꢈ56#6ꢄꢓꢅ+ꢌ1ꢅ#FFTGUUꢅꢐꢅꢀꢏ*ꢉ
ꢎ
ꢏ
ꢍ
ꢂ
ꢄ
ꢀ
ꢊ
ꢁ
4&4(
4
4'
2'
4
('
4
6&4'
4
6+'
1840
4
%65ꢄ'
4ꢌ9
4ꢌ9
4ꢌ9
(KIWTG ꢋꢑꢆ #5%+ꢄ5VCVWUꢄ4GIKUVGTU
4&4(ꢅꢄ4GEGKXGꢄ&CVCꢄ4GIKUVGTꢄ(WNNꢄꢌ$KVꢄꢐꢍꢆꢄ4&4( is set to
1 when an incoming data byte is loaded into an empty 4Z
(+(1. If a framing or parity error occurs, 4&4( is still set
and the receive data (which generated the error) is still load-
ed into the (+(1. 4&4( is cleared toꢅ0by reading 4&4 and
most recently received character in the (+(1 from +15612
mode, during 4'5'6 and for #5%+ꢀ if the &%&ꢀ input is
auto-enabled and is negated (High).
%06.# register is 1, a character is assembled in which the
parity does not match the 2'1 bit in the %06.$ register.
However, this status bit is not set until or unless the error
character becomes the oldest one in the 4Zꢅ(+(1. 2' is
cleared when software writes a 1 to the '(4 bit in the
%064.# register. 2' is also cleared by 4'5'6 in +15612
mode, or on #5%+ꢀ, if the &%&ꢀ pin is auto-enabled and is
negated (High).
1840ꢅꢄ1XGTTWPꢄ'TTQTꢄꢌ$KVꢄꢈꢍꢆꢄAn overrun condition oc-
curs if the receiver finishes assembling a character but the
4Zꢅ(+(1 is full so there is no room for the character. How-
ever, this status bit is not set until the most recent character
received before the overrun becomes the oldest byte in the
(+(1. This bit is cleared when software writes a 1 to the
'(4 bit in the %06.# register. The bit may also be cleared
by 4'5'6 in +15612 mode or #5%+ꢀ if the &%&ꢀ pin is
auto enabled and is negated (High).
('ꢅꢄ(TCOKPIꢄ'TTQTꢄꢌ$KVꢄꢉꢍꢆꢄA framing error is detected
when the stop bit of a character is sampled as ꢀꢌ52#%'.
However, this status bit is not set until/unless the error char-
acter becomes the oldest one in the 4Zꢅ(+(1. (' is cleared
when software writes a 1 to the '(4 bit in the %06.# reg-
ister. (' is also cleared by 4'5'6 in +15612 mode, or on
#5%+ꢀ, if the &%&ꢀ pin is auto-enabled and is negated
(High).
4'+ꢅꢄ4GEGKXGꢄ+PVGTTWRVꢄ'PCDNGꢄꢌ$KVꢄꢋꢍꢆꢄ4+' should be set to
1 to enable ASCI receive interrupt requests. When 4+' is
1, the Receiver requests an interrupt when a character is re-
ceived and 4&4( is set, but only if neither DMA channel
requires its request-routing field to be set to receive data
from this ASCI. That is, if 5/ꢄ ꢀ are ꢄꢄ and 5#4ꢄꢊ ꢄꢁ
are ꢄꢀ, or &+/ꢄ is 1 and +#4ꢄꢊ ꢄꢁ are ꢄꢀ, then ASCI1
does not request an interrupt for 4&4(. If 4+' is 1, either
ASCI requests an interrupt when 1840, 2' or (' is set, and
0QVGꢅ When an overrun occurs, the receiver does not place the
character in the shift register into the (+(1, nor any sub-
sequent characters, until the most recent good character
enters the top of the (+(1 so that 1840 is set. Software
then writes a 1 to '(4 to clear it.
2'ꢅꢄ2CTKV[ꢄ'TTQTꢄꢌ$KVꢄꢑꢍꢆꢄA parity error is detected when
parity checking is enabled.When the /1&ꢄ bit in the
ꢎꢎ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
6&4'ꢅꢄ6TCPUOKVꢄ&CVCꢄ4GIKUVGTꢄ'ORV[ꢄꢌ$KVꢄꢁꢍꢆꢄ6&4'ꢅ ꢐ
1 indicates that the 6&4 is empty and the next transmit data
byte is written to 6&4. After the byte is written to 6&4,
6&4' is cleared toꢅ0until the ASCI transfers the byte from
6&4 to the 654 and then 6&4' is again set to 1. 6&4' is
set to 1 in +15612 mode and during 4'5'6. On ASCI0,
if the %65ꢀ pin is auto-enabled in the #5':6ꢀ register and
the pin is High, 6&4' is reset to 0.
#5%+ꢀ requests an interrupt when &%&ꢀ goes High. 4+' is
cleared toꢅ0by 4'5'6.
&%&ꢂꢅꢄ&CVCꢄ%CTTKGTꢄ&GVGEVꢄꢌ$KVꢄꢇꢄ56#6ꢂꢍꢆꢄThis bit is set
to 1 when the pin is High. It is cleared toꢅ0on the first
4'#& of 56#6ꢀ following the pin’s transition from High
to Low and during 4'5'6. When bit 6 of the #5':6ꢀ reg-
ister isꢅ0 to select auto-enabling, and the pin is negated
(High), the receiver is reset and its operation is inhibited.
6+'ꢅꢄ6TCPUOKVꢄ+PVGTTWRVꢄ'PCDNGꢄꢌ$KVꢄꢂꢍꢆꢄ6+' should be set
to 1 to enable ASCI transmit interrupt requests. If 6+'ꢅꢐ
1, an interrupt is requested when 6&4'ꢅꢐ 1. 6+' is cleared
toꢅ0during 4'5'6.
%65ꢁ'ꢅꢄ%NGCTꢄ6Qꢄ5GPFꢄꢌ$KVꢄꢇꢄ56#6ꢁꢍꢆꢄChannel 1 fea-
tures an external %65ꢄ input, which is multiplexed with the
receive data pin 45: for the CSI/O. Setting this bit to 1
selects the %65ꢄ function; clearing the bit toꢅ0selects the
4:5 function.
#5%+ꢄ64#05/+6ꢄ#ꢄ4')+56'45
Register addresses 06H and 07H hold the ASCI transmit
data for channel 0 and channel 1, respectively.
#5%+ꢄ6TCPUOKVꢄ&CVCꢄ4GIKUVGTUꢄ%JCPPGNꢄꢁ
/PGOQPKEꢄ6&4ꢁ
#FFTGUUꢄꢂꢐ*
#5%+ꢄ6TCPUOKVꢄ&CVCꢄ4GIKUVGTUꢄ%JCPPGNꢄꢂ
ꢂ
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢄ
ꢀ
/PGOQPKEꢄ6&4ꢂ
#FFTGUUꢄꢂꢈ*
ꢂ
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢄ
ꢀ
#5%+ꢅ6TCPUOKV
ꢅ%JCPPGNꢅꢄ
(KIWTG ꢋꢐꢆ #5%+ꢄ4GIKUVGT
#5%+ꢅ6TCPUOKV
ꢅ%JCPPGNꢅꢀ
(KIWTG ꢋꢈꢆ #5%+ꢄ4GIKUVGT
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢎꢏ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
#5%+ꢄ4'%'+8'ꢄ4')+56'4
Register addresses 08Hand 09Hhold the ASCI receive data
for channel 0 and channel 1, respectively.
#5%+ꢄ4GEGKXGꢄ4GIKUVGTꢄ%JCPPGNꢄꢁ
/PGOQPKEꢄ4&4ꢁ
#FFTGUUꢄꢂꢏ*
#5%+ꢄ4GEGKXGꢄ4GIKUVGTꢄ%JCPPGNꢄꢂ
/PGOQPKEꢄ4&4ꢂ
#FFTGUUꢄꢂꢀ*
ꢂ
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢄ
ꢀ
ꢂ
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢄ
ꢀ
#5%+ꢅ6TCPUOKVꢅ&CVC
(KIWTG ꢋꢏꢆ #5%+ꢄ4GEGKXGꢄ4GIKUVGTꢄ%JCPPGNꢄꢁ
#5%+ꢅ6TCPUOKVꢅ&CVC
(KIWTG ꢋꢀꢆ #5%+ꢄ4GEGKXGꢄ4GIKUVGTꢄ%JCPPGNꢄꢂ
%5+ꢃ1ꢄ%10641.ꢃ56#675ꢄ4')+56'4
The CSI/O Control/Status Register (%064) is used to mon-
itor CSI/O status, enable and disable the CSI/O, enable and
disable interrupt generation, and select the data clock speed
and source.
ꢏ
ꢎ
ꢍ
ꢂ
ꢄ
ꢀ
$KV
ꢊ
ꢁ
AA
55ꢂ
4ꢌ9
55ꢄ
4ꢌ9
55ꢀ
4ꢌ9
ꢅ'(
4
'+'
4'
6'
4ꢌ9
4ꢌ9
4ꢌ9
(KIWTG ꢉꢂꢆ %5+ꢃ1ꢄ%QPVTQNꢄ4GIKUVGTꢄꢌ%064ꢅꢄ+ꢃ1ꢄ#FFTGUUꢄꢒꢄꢂꢂꢂ#*ꢍ
'(ꢅꢄ'PFꢄ(NCIꢄꢌ$KVꢄꢐꢍꢆꢄ'( is set to 1bytheCSI/O toindicate
completion of an 8-bit data transmit or receive operation.
If End Interrupt Enableꢅ('+') bit = 1 when '( is set to 1,
a CPU interrupt request is generated. Program access of
64&4 only occurs if'(ꢅꢐ 1. The CSI/O clears '( toꢅ0when
64&4 is read or written. '( is cleared toꢅ0during 4'5'6
and +15612 mode.
pin in synchronization with the (internal or external) data
clock. After receiving 8 bits of data, the CSI/O automati-
cally clears4' toꢅ0, '( isset to1, and an interrupt(ifenabled
by '+'ꢅꢐꢅꢄ) is generated. 4' and 6' are never both set to
1 at the same time. 4' is cleared toꢅ0during 4'5'6 and
+15612 mode.
6'ꢅꢄ6TCPUOKVꢄ'PCDNGꢄꢌ$KVꢄꢉꢍꢆꢄA CSI/O transmit operation
is started by setting 6' to 1. When 6' is set to 1, the data
clock is enabled. When in internal clock mode, the data
clock is output from the %-5 pin. In external clock mode,
the clock isinput on the %-5 pin. In either case, data is shift-
ed out on the 6:5 pin synchronous with the (internal or ex-
ternal) data clock. After transmitting 8 bits of data, the
CSI/O automatically clears 6' toꢅ0, sets '( to 1, and re-
quests an interrupt if enabled by '+'ꢅꢐ 1. 6' and 4' are
'+'ꢅꢄ'PFꢄ+PVGTTWRVꢄ'PCDNGꢄꢌ$KVꢄꢈꢍꢆꢄ'+' is set to 1 to gen-
erate a CPU interrupt request. The interrupt request is in-
hibited if '+' is reset to 0. '+' is cleared toꢅ0during 4'5'6.
4'ꢅꢄ4GEGKXGꢄ'PCDNGꢄꢌ$KVꢄꢑꢍꢆꢄA CSI/O receive operation is
started by setting 4' to 1. When 4' is set to 1, the data clock
is enabled. In internal clock mode, the data clock is output
from the %-5 pin. In external clock mode, the clock is input
on the %-5 pin. In either case, data is shifted in on the4:5
ꢎꢁ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
never both set to 1 at the same time. 6' is cleared toꢅ0
during 4'5'6 and +15612 mode.
6KOGTꢄ&CVCꢄ4GIKUVGTꢄ%JCPPGNꢄꢂ*
/PGOQPKEꢄ6/&4ꢂ*
#FFTGUUꢄꢂ&*
55ꢇꢎꢄꢁꢎꢄꢂꢅꢄ5RGGFꢄ5GNGEVꢄꢇꢎꢄꢁꢎꢄꢂꢄꢌ$KVUꢄꢇ ꢂꢍꢆꢄ55ꢂ, 55ꢄ
and 55ꢀ select the CSI/O transmit/receive clock source and
speed. 55ꢂ, 55ꢄ and 55ꢀ are all set to 1 during 4'5'6.
Table 11 indicates CSI/O Baud Rate Selection.
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢂ
ꢄ
ꢀ
6CDNG ꢁꢁꢆ %5+ꢃ1ꢄ$CWFꢄ4CVGꢄ5GNGEVKQP
6KOGTꢅ&CVC
55ꢇ
55ꢁ
55ꢂ
&KXKFGꢄ4CVKQ
(KIWTG ꢉꢋꢆ 6KOGTꢄ&CVCꢄ4GIKUVGTꢄ%JCPPGNꢄꢂꢄ*KIJ
ꢀ
ꢀ
ꢀ
ꢀ
ꢄ
ꢄ
ꢄ
ꢄ
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
÷ꢂꢀ
÷ꢎꢀ
÷ꢆꢀ
÷ꢄꢁꢀ
÷ꢍꢂꢀ
÷ꢁꢎꢀ
÷ꢄꢂꢆꢀ
6KOGTꢄ4GNQCFꢄ4GIKUVGTꢄ%JCPPGNꢄꢂꢄ.QY
/PGOQPKEꢄ4.&4ꢂ.
#FFTGUUꢄꢂ'*
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢂ
ꢄ
ꢀ
'ZVGTPCNꢅ%NQEMꢅ+PRWV
ꢈ.GUUꢅ6JCPꢅ÷ꢂꢀꢉ
6KOGTꢅ4GNQCFꢅ&CVC
After 4'5'6, the%-5 pin is configured as an external clock
input (55ꢂꢇꢅ55ꢄꢇꢅ55ꢀꢅꢐꢅꢄ). Changing these values causes
%-5tobecomeanoutputpinandtheselectedclockisoutput
when transmit or receive operations are enabled.
(KIWTG ꢉꢉꢆ 6KOGTꢄ4GNQCFꢄ4GIKUVGTꢄ.QY
6KOGTꢄ4GNQCFꢄ4GIKUVGTꢄ%JCPPGNꢄꢂꢄ*KIJ
%5+ꢃ1ꢄ6TCPUOKVꢃ4GEGKXGꢄ&CVCꢄ4GIKUVGT
/PGOQPKEꢄ4.&4ꢂ*
#FFTGUUꢄꢂ(*
/PGOQPKEꢄ64&4
#FFTGUUꢄꢂ$*
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢂ
ꢄ
ꢀ
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢂ
ꢄ
ꢀ
6KOGTꢅ4GNQCFꢅ&CVC
(KIWTG ꢉꢑꢆ 6KOGTꢄ4GNQCFꢄ4GIKUVGTꢄ%JCPPGNꢄꢂꢄ*KIJ
%5+ꢌ1ꢅ6ꢌ4ꢅ&CVC
(KIWTG ꢉꢁꢆ %5+ꢃ1ꢄ6TCPUOKVꢃ4GEGKXGꢄ&CVCꢄ4GIKUVGTꢄ
6KOGTꢄ&CVCꢄ4GIKUVGTꢄ%JCPPGNꢄꢂꢄ.QY
/PGOQPKEꢄ6/&4ꢂ.
#FFTGUUꢄꢂ%*
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢂ
ꢄ
ꢀ
#5%+ꢅ4GEGKXGꢅ&CVC
(KIWTG ꢉꢇꢆ 6KOGTꢄ4GIKUVGTꢄ%JCPPGNꢄꢂꢄ.QY
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢎꢊ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
6+/'4ꢄ%10641.ꢄ4')+56'4
The Timer Control Register (6%4) monitors both channels
(246ꢀꢇꢅ246ꢄ) 6/&4 status. It also controls the enabling
anddisablingofdown-countingandinterrupts, andcontrols
the output pin #ꢄꢆꢌ6
for 246ꢄ.
ꢍ
$KV
ꢊ
ꢁ
ꢏ
ꢎ
ꢂ
ꢄ
ꢀ
6+(ꢀ
4
6+'ꢄ
4ꢌ9
6+'ꢀ
4ꢌ9
61%ꢄ
4ꢌ9
61%ꢀ
4ꢌ9
6&'ꢄ
4ꢌ9
6&'ꢀ
4ꢌ9
ꢅ6+(ꢄ
4
(KIWTG ꢉꢈꢆ 6KOGTꢄ%QPVTQNꢄ4GIKUVGTꢄꢌ6%4ꢅꢄ+ꢃ1ꢄ#FFTGUUꢄꢒꢄꢁꢂ*ꢍ
6+(ꢁꢅꢄ6KOGTꢄ+PVGTTWRVꢄ(NCIꢄꢁꢄꢌ$KVꢄꢐꢍꢄꢆꢄWhen 6/&4ꢄ dec-
rements toꢅ0, 6+(ꢄ is set to 1. This condition generates an
interrupt request if enabled by 6+'ꢄꢅꢐ 1. 6+(ꢄ is reset toꢅ0
when 6%4 is read and the higher or lower byte of 6/&4ꢄ
is read. During 4'5'6, 6+(ꢄ is cleared to 0.
61%ꢄ and 61%ꢀ, the #ꢄꢆꢌ6
Low, or toggled when 6/&4ꢄ decrements to 0.
pin can be forced High,
6CDNG ꢁꢇꢆ 6KOGTꢄ1WVRWVꢄ%QPVTQN
61%ꢁ 61%ꢂ
1WVRWV
6+(ꢂꢅꢄ6KOGTꢄ+PVGTTWRVꢄ(NCIꢄꢂꢄꢌ$KVꢄꢈꢍꢆꢄWhen 6/&4ꢀ dec-
rements toꢅ0, 6+(ꢀ is set to 1. This condition generates an
interrupt request if enabled by 6+'ꢀꢅꢐ 1. 6+(ꢀ is reset toꢅ0
when 6%4 is read and the higher or lower byte of 6/&4ꢀ
is read. During 4'5'6, 6+(ꢀ is cleared to 0.
ꢀ
ꢀ
+PJKDKVGF 6JGꢅ#ꢄꢆꢌ6
ꢅRKPꢅKUꢅPQVꢅ
CHHGEVGFꢅD[ꢅVJGꢅ246
ꢀ
ꢄ
ꢄ
ꢄ
ꢀ
ꢄ
6QIINGF +HꢅDKVꢅꢍꢅQHꢅ+#4ꢄ$ꢅKUꢅꢄꢇꢅVJGꢅ
#ꢄꢆꢌ6
ꢅRKPꢅKUꢅVQIINGFꢅQTꢅ
ꢀ
ꢄ
UGVꢅ.QYꢅQTꢅ*KIJꢅCUꢅ
KPFKECVGF
6+'ꢁꢅꢄ6KOGTꢄ+PVGTTWRVꢄ'PCDNGꢄꢁꢄꢌ$KVꢄꢑꢍꢆꢄWhen 6+'ꢀ is set
to 1, 6+(ꢄꢅꢐ 1 generates a CPU interrupt request. When
6+'ꢀ is reset toꢅ0, the interrupt request is inhibited. During
4'5'6, 6+'ꢀ is cleared to 0.
6&'ꢁꢎꢄꢂꢅꢄ6KOGTꢄ&QYPꢄ%QWPVꢄ'PCDNGꢄꢌ$KVUꢄꢁꢎꢄꢂꢍꢆꢄ6&'ꢄ
and 6&'ꢀ enable and disable down-counting for 6/&4ꢄ
and 6/&4ꢀ, respectively. When 6&'P (Pꢅꢐ ꢀ,ꢄ) is set to
1, down-counting is stopped and 6/&4P is freely read or
written. 6&'ꢄ and 6&'ꢀ are cleared toꢅ0during 4'5'6 and
6/&4P does not decrement until 6&'P is set to ꢄ.
61%ꢁꢎꢄꢂꢅꢄ6KOGTꢄ1WVRWVꢄ%QPVTQNꢄꢌ$KVUꢄꢋꢎꢄꢇꢍꢆꢄ61%ꢄ and
61%ꢀ control the output of 246ꢄ using the multiplexed
#ꢄꢆꢌ6
pin as indicated in Table 12. During 4'5'6,
61%ꢄ and 61%ꢀ are cleared to 0. If bit 3 of the +#4ꢄ$ reg-
ister is 1, the 6
function is selected. By programming
ꢎꢆ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
#5%+ꢄ':6'05+10ꢄ%10641.ꢄ4')+56'4ꢄ%*#00'.ꢄꢂꢄ#0&ꢄ%*#00'.ꢄꢁ
The ASCI Extension Control Registers (#5':6ꢀ and
#5':6ꢄ) control functions that have been added to the
ASCIs in the Z8S180/Z8L180 family. All bits in this
register reset to 0.
#5%+ꢅ'ZVGPUKQPꢅ%QPVTQNꢅ4GIKUVGTꢅꢀꢅꢈ#5':6ꢀꢅ+ꢌ1ꢅ#FFTGUUꢅꢐꢅꢄꢂ*ꢉ
ꢍ
$KV
ꢊ
ꢁ
ꢏ
ꢎ
ꢂ
ꢄ
ꢀ
&%&ꢀ
%65ꢀ
$4)ꢀ
/QFG
$TGCM
'PCDNG
5GPF
$TGCM
4GUGTXGF
$TGCM
:ꢄ
&KUCDNG &KUCDNG
#5%+ꢅ'ZVGPUKQPꢅ%QPVTQNꢅ4GIKUVGTꢅꢄꢅꢈ#5':6ꢄꢅ+ꢌ1ꢅ#FFTGUUꢅꢐꢅꢄꢍ*ꢉ
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢂ
ꢄ
ꢀ
$KV
5GPF
$TGCM
$4)ꢄ
/QFG
$TGCM
'PCDNG
4GUGTXGF 4GUGTXGF
:ꢄ
4GUGTXGF
$TGCM
(KIWTG ꢉꢐꢆ #5%+ꢄ'ZVGPUKQPꢄ%QPVTQNꢄ4GIKUVGTUꢎꢄ%JCPPGNUꢄꢂꢄCPFꢄꢁ
&%&ꢂꢄ&KUCDNGꢄꢌ$KVꢄꢈꢎꢄ#5%+ꢂꢄ1PN[ꢍꢆꢄIf this bit isꢅ0, then
the &%&ꢀ pin auto-enables the ASCI0 receiver, such that
when the pin is negated/High, the Receiver is held in a 4'ꢃ
5'6 state. If this bit is 1, the state of the &%&-pin has no
effect on receiver operation. In either state of this bit, soft-
ware can read the state of the &%&ꢀ pin in the 56#6ꢀ reg-
ister, and the receiver interrupts on a rising edge of &%&ꢀ.
divides 2*+ by 10 or 30, depending on the 25 bit in %06.$,
andfactoredbyapoweroftwo(selectedbythe55ꢂ ꢀ bits),
to obtain the clock that is presented to the transmitter and
receiver and output on the %-# pin. If 55ꢂ ꢀ are not ꢄꢄꢄ,
and this bit is 1, the Baud Rate Generator divides 2*+ by
twice the sum of the 16-bit value (programmed into the
Time Constant registers) and 2. This mode is identical to
the operation of the baud rate generator in the '5%%.
%65ꢂꢄ&KUCDNGꢄꢌ$KVꢄꢑꢎꢄ#5%+ꢂꢄ1PN[ꢍꢆꢄIf this bitisꢅ0,thenthe
%65ꢀ pin auto-enables the #5%+1 transmitter, in that when
the pin is negated/High, the 6&4' bit in the 56#6ꢀ register
is forced to 0. If this bit is 1, the state of the %65ꢀ pin has
no effect on the transmitter. Regardless of the state of this
bit, software can read the state of the %65ꢀ pin the %06.$ꢀ
register.
$TGCMꢄ'PCDNGꢄꢌ$KVꢄꢇꢍꢆꢄIf this bit is 1, the receiver detects
$4'#- conditions and report them in bit 1, and the trans-
mitter sends $4'#-s under the control of bit 0.
$TGCMꢄ&GVGEVꢄꢌ$KVꢄꢁꢍꢆꢄThe receiver sets this read-only bit to
1 when an all-zero character with a Framing Error becomes
the oldest character in the 4Zꢅ(+(1. The bit is cleared when
software writes aꢅ0to the '(4 bit in %06.# register, also
by 4'5'6, by +15612 mode, and for #5%+ꢀ, if the &%&ꢀ
pin is auto-enabled and is negated (High).
:ꢁꢄꢌ$KVꢄꢉꢍꢆꢄIf this bit is 1, the clock from the Baud Rate
Generator or %-# pin is taken as a 1X-bit clock (sometimes
called isochronous mode). In this mode, receive data on the
4:# pin must be synchronized to the clock on the %-# pin,
regardless of whether %-# is an input or an output. If this
bit isꢅ0, the clock from the Baud Rate Generator or %-#
pin is divided by 16 or 64 per the &4 bit in the %06.$ reg-
ister, to obtain the actual bit rate. In this mode, receive data
onthe4:# pin isnot required tobe synchronized to a clock.
5GPFꢄ$TGCMꢄꢌ$KVꢄꢂꢍꢆꢄIf thisbit and bit 2 are both1, the trans-
mitter holds the 6:# pin Low to send a $4'#- condition.
The duration of the $4'#- is under software control (one
of the PRTs or CTCs can be used to time it). This bit resets
toꢅ0, inwhichstate6:# carriesthe serialoutputofthetrans-
mitter.
$4)ꢄ/QFGꢄꢌ$KVꢄꢋꢍꢆꢄIf the 55ꢂ ꢀ bits in the %06.$ register
are not ꢄꢄꢄ, and this bit isꢅ0, the ASCI Baud Rate Generator
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢎꢋ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
#5%+ꢄ':6'05+10ꢄ%10641.ꢄ4')+56'4ꢄ%*#00'.ꢄꢂꢄ#0&ꢄ%*#00'.ꢄꢁꢄꢈ%QPVKPWGFꢉ
6KOGTꢄ&CVCꢄ4GIKUVGTꢄ%JCPPGNꢄꢁꢄ.QY
6KOGTꢄ4GNQCFꢄ4GIKUVGTꢄ%JCPPGNꢄꢁꢄ*KIJ
/PGOQPKEꢄ6/&4ꢁ.
#FFTGUUꢄꢁꢉ*
/PGOQPKEꢄ4.&4ꢁ*
#FFTGUUꢄꢁꢐ*
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢂ
ꢄꢅ
ꢀ
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢂ
ꢄꢅ
ꢀ
4GNQCFꢅ&CVC
6KOGTꢅ&CVC
(KIWTG ꢉꢀꢆ 6KOGTꢄ&CVCꢄ4GIKUVGTꢄꢁꢄ.QY
(KIWTG ꢑꢁꢆ 6KOGTꢄ4GNQCFꢄ4GIKUVGTꢄ%JCPPGNꢄꢁꢄ*KIJ
6KOGTꢄ&CVCꢄ4GIKUVGTꢄ%JCPPGNꢄꢁꢄ*KIJ
(TGGꢄ4WPPKPIꢄ%QWPVGTꢄꢌ4GCFꢄ1PN[ꢍ
/PGOQPKEꢄ6/&4ꢁ*
#FFTGUUꢄꢁꢑ*
/PGOQPKEꢄ(4%
#FFTGUUꢄꢁꢀ*
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢂ
ꢄꢅ
ꢀ
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢂ
ꢄꢅ
ꢀ
%QWPVKPIꢅ&CVC
(KIWTG ꢑꢇꢆ (TGGꢄ4WPPKPIꢄ%QWPVGT
6KOGTꢅ&CVC
(KIWTG ꢉꢏꢆ 6KOGTꢄ&CVCꢄ4GIKUVGTꢄꢁꢄ*KIJ
6KOGTꢄ4GNQCFꢄ4GIKUVGTꢄ%JCPPGNꢄꢁꢄ.QY
/PGOQPKEꢄ4.&4ꢁ.
#FFTGUUꢄꢁꢈ
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢂ
ꢄꢅ
ꢀ
4GNQCFꢅ&CVC
(KIWTG ꢑꢂꢆ 6KOGTꢄ4GNQCFꢄ%JCPPGNꢄꢁꢄ.QY
ꢏꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
#5%+ꢄ6+/'ꢄ%1056#06ꢄ4')+56'45
DKVUꢌUGEQPFꢅꢐꢅH ꢌꢈꢂꢕꢈ6%ꢔꢂꢉꢅZꢅUCORNKPIꢅTCVGꢉ
If the 55ꢂ ꢀ bits of the %06.$ register are not ꢄꢄꢄ, and
the $4) mode bit in the #5':6 register is 1, the #5%+ di-
vides the 2*+ clock by two times the registers’ 16-bit value,
plustwo.Asaresult, theclockispresentedtothetransmitter
and receiver for division by 1, 16, or 64, and is output on
the %-# pin.
where 6% is the 16-bit value programmed into the ASCI
Time Constant High and Low registers. If the ASCI multi-
plexed %-# pin is selected for the %-# function, it outputs
the clock before the final division by the sampling rate, as
follows:
If the 55ꢂ ꢀ bits in an ASCI %06.$ register are not 111,
and the $4) mode bit in its Extension Control Register is
1, itsnew baudrate generatordivides2*+ forserial clocking,
as follows:
H
ꢅꢐꢅH ꢌꢈꢂꢕꢈ6%ꢔꢂꢉꢉ
Find the 6% value for a particular serial bit rate as follows:
6%ꢅꢐꢅꢈH ꢌꢈꢂꢅZꢅDKVUꢌUGEQPFꢅZꢅUCORNKPIꢅTCVGꢉꢉꢅ ꢅꢂ
#5%+ꢅ6KOGꢅ%QPUVCPVꢅ4GIKUVGTꢅꢀꢅ.QYꢅꢈ#56%ꢀ.ꢇꢅ+ꢌ1ꢅ#FFTGUUꢅꢄ#*ꢉ
#5%+ꢅ6KOGꢅ%QPUVCPVꢅ4GIKUVGTꢅꢄꢅ.QYꢅꢈ#56%ꢄ.ꢇꢅ+ꢌ1ꢅ#FFTGUUꢅꢄ%*ꢉ
ꢏ
ꢎ
ꢍ
ꢂ
ꢄ
ꢀ
ꢀ
ꢊ
ꢊ
ꢁ
$KV
$KV
.5ꢅꢆꢅ$KVUꢅQHꢅ6KOGꢅ%QPUVCPV
#5%+ꢅ6KOGꢅ%QPUVCPVꢅ4GIKUVGTꢅꢀꢅ*KIJꢅꢈ#56%ꢀ*ꢇꢅ+ꢌ1ꢅ#FFTGUUꢅꢄ$*ꢉ
#5%+ꢅ6KOGꢅ%QPUVCPVꢅ4GIKUVGTꢅꢄꢅ*KIJꢅꢈ#56%ꢄ*ꢇꢅ+ꢌ1ꢅ#FFTGUUꢅꢄ&*ꢉ
ꢏ
ꢎ
ꢍ
ꢂ
ꢄ
ꢁ
/5ꢅꢆꢅ$KVUꢅQHꢅ6KOGꢅ%QPUVCPV
(KIWTG ꢑꢋꢆ #5%+ꢄ6KOGꢄ%QPUVCPVꢄ4GIKUVGTU
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢏꢄ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
%.1%-ꢄ/7.6+2.+'4ꢄ4')+56'4
ꢌ<ꢁꢀꢂꢄ/27ꢄ#FFTGUUꢄꢁ'*ꢍꢄ
$KVꢄꢈꢆꢄ.QYꢄ0QKUGꢄ%T[UVCNꢄ1RVKQPꢆꢄSetting this bit to 1 en-
ables the low-noise option for the ':6#. and :6#. pins.
This option reduces the gain in addition to reducing the out-
put drive capability to 30% of its original drive capability.
The Low Noise Crystal Option is recommended in the use
of crystalsforPCMCIA applications, where the crystal may
be driven too hard by the oscillator. Setting this bit toꢅ0is
selected for normal operation of the ':6#. and :6#. pins.
The default for this bit is 0.
ꢊ
ꢀ
ꢁ
ꢀ
ꢏ
ꢄ
ꢎ
ꢄ
ꢍ
ꢄ
ꢂ
ꢄ
ꢄ
ꢄ
ꢀ
ꢄꢅ
4'5'48'&
.19ꢅ01+5'ꢅ%4;56#.
:ꢂꢅ%.1%-ꢅ/7.6+2.+'4
0QVGꢅ Operating restrictions for device operation are listed be-
low. If a low-noise option is required, and normal device
operation is required, use the clock multiplier feature.
(KIWTG ꢑꢉꢆ %NQEMꢄ/WNVKRNKGTꢄ4GIKUVGT
6CDNG ꢁꢋꢆ .QYꢄ0QKUGꢄ1RVKQP
$KVꢄꢐꢆꢄ:ꢇꢄ%NQEMꢄ/WNVKRNKGTꢄ/QFGꢆꢄWhen this bit is set to 1,
the programmer can double the internal clock speed from
the speed of the external clock. This feature only operates
effectively withfrequenciesof10–16MHz(20–32MHzin-
ternal). When this bit is set toꢅ0, the Z8S180/Z8L180 device
operates in normal mode. At power-up, this feature is dis-
abled.
.QYꢄ0QKUG
#&&4ꢄꢁ'ꢎꢄDKVꢄꢈꢄꢒꢄꢁ
0QTOCN
#&&4ꢄꢁ'ꢎꢄDKVꢄꢈꢄꢒꢄꢂ
ꢂꢀꢅ/*\ꢅ"ꢅꢎꢑꢏ8ꢇꢅꢄꢀꢀu% ꢍꢍꢅ/*\ꢅ"ꢅꢎꢑꢏ8ꢇꢅꢄꢀꢀu%
ꢄꢀꢅ/*\ꢅ"ꢅꢍꢑꢀ8ꢇꢅꢄꢀꢀu% ꢂꢀꢅ/*\ꢅ"ꢅꢍꢑꢀ8ꢇꢅꢄꢀꢀu%
ꢏꢂ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
&/#ꢄ5174%'ꢄ#&&4'55ꢄ4')+56'4ꢄ%*#00'.ꢄꢂ
The DMA Source Address Register Channel 0 specifies the
physical source address for channel 0 transfers. The register
contains 20 bits and can specify up to 1024 KB memory ad-
dresses or up to 64-KB I/O addresses. Channel 0 source can
be memory, I/O, or memory mapped I/O. For I/O, bits
ꢄꢊ ꢄꢁ of this register identify the Request Handshake sig-
nal.
&/#ꢄ5QWTEGꢄ#FFTGUUꢄ4GIKUVGTꢄ%JCPPGNꢄꢂ$
/PGOQPKEꢄ5#4ꢂ$
#FFTGUUꢄꢇꢇ*
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢂ
ꢄꢅ
ꢀ
&/#ꢄ5QWTEGꢄ#FFTGUUꢄ4GIKUVGTꢎꢄ%JCPPGNꢄꢂꢄ.QY
/PGOQPKEꢄ5#4ꢂ.
#FFTGUUꢄꢇꢂ*
&/#ꢅ%JCPPGNꢅꢀꢅ#FFTGUU
4GUGTXGF
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢂ
ꢄꢅ
ꢀ
(KIWTG ꢑꢐꢆ &/#ꢄ5QWTEGꢄ#FFTGUUꢄ4GIKUVGTꢄꢂ$
If the source is in I/O space, bits ꢄ ꢀ of this register select
the DMA request signal for DMA0, as follows:
&/#ꢅ%JCPPGNꢅꢀꢅ#FFTGUU
(KIWTG ꢑꢑꢆ &/#ꢄ5QWTEGꢄ#FFTGUUꢄ4GIKUVGTꢄꢂꢄ.QY
$KVꢄꢁ
$KVꢄꢂ
ꢌ#ꢁꢐꢍ
ꢌ#ꢁꢈꢍ &/#ꢄ6TCPUHGTꢄ4GSWGUV
&/#ꢄ5QWTEGꢄ#FFTGUUꢄ4GIKUVGTꢎꢄ%JCPPGNꢄꢂꢄ
*KIJ
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
&4'3ꢀꢅꢈGZVGTPCNꢉ
4&4(ꢅꢈ#5%+ꢀꢉ
4&4(ꢅꢈ#5%+ꢄꢉ
4GUGTXGF
/PGOQPKEꢄ5#4ꢂ*
#FFTGUUꢄꢇꢁ*
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢂ
ꢄꢅ
ꢀ
&/#ꢅ%JCPPGNꢅꢀꢅ#FFTGUU
(KIWTG ꢑꢈꢆ &/#ꢄ5QWTEGꢄ#FFTGUUꢄ4GIKUVGTꢄꢂꢄ*KIJ
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢏꢍ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
&/#ꢄ&'56+0#6+10ꢄ#&&4'55ꢄ4')+56'4ꢄ%*#00'.ꢄꢂ
The DMA Destination Address Register Channel 0
specifies the physical destination address for channel 0
transfers. The register contains 20 bits and can specify up
to 1024-KB memory addresses or up to 64-KB I/O
addresses. Channel 0 destination can be memory, I/O, or
memory mapped I/O. For I/O, the /5 bits of this register
identify the Request Handshake signal for channel 0.
&/#ꢄ&GUVKPCVKQPꢄ#FFTGUUꢄ4GIKUVGTꢄ
%JCPPGN ꢂ$
/PGOQPKEꢄꢂ$
#FFTGUUꢄꢇꢑ*
#ꢄꢋ #ꢄꢁ
4GUGTXGF
&/#ꢄ&GUVKPCVKQPꢄ#FFTGUUꢄ4GIKUVGTꢄ%JCPPGN ꢂꢄ
.QY
(KIWTG ꢈꢂꢆ &/#ꢄ&GUVKPCVKQPꢄ#FFTGUUꢄ4GIKUVGTꢄ%JCPPGNꢄ
ꢂ$
/PGOQPKEꢄꢂ.
#FFTGUUꢄꢇꢋ*
If the DMA destination is in I/O space, bits ꢄ ꢀ of this reg-
ister select the DMA request signal for DMA0, as follows:
(KIWTG ꢑꢀꢆ &/#ꢄ&GUVKPCVKQPꢄ#FFTGUUꢄ4GIKUVGTꢄ%JCPPGNꢄ
ꢂꢄ.QY
$KVꢄꢁ
$KVꢄꢂ
ꢌ#ꢁꢐꢍ
ꢌ#ꢁꢈꢍ &/#ꢄ6TCPUHGTꢄ4GSWGUVꢄ
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
&4'3ꢀꢅꢈGZVGTPCNꢉ
6&4ꢀꢅꢈ#5%+ꢀꢉ
6&4ꢄꢅꢈ#5%+ꢄꢉ
0QVꢅ7UGF
&/#ꢄ&GUVKPCVKQPꢄ#FFTGUUꢄ4GIKUVGTꢄ%JCPPGN ꢂꢄ
*KIJ
/PGOQPKEꢄꢂ*
#FFTGUUꢄꢇꢉ*
(KIWTG ꢑꢏꢆ &/#ꢄ&GUVKPCVKQPꢄ#FFTGUUꢄ4GIKUVGTꢄ%JCPPGNꢄ
ꢂꢄ*KIJ
ꢏꢎ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
&/#ꢄ$;6'ꢄ%1706ꢄ4')+56'4ꢄ%*#00'.ꢄꢂꢄ
The DMA Byte Count Register Channel 0 specifies the
number of bytes to be transferred. This register contains 16
bits and may specify up to 64-KB transfers. When one byte
is transferred, the register is decremented by one. If P bytes
should be transferred, P must be stored before the DMA op-
eration.
&/#ꢄ$[VGꢄ%QWPVꢄ4GIKUVGTꢄ%JCPPGNꢄꢂꢄ*KIJ
/PGOQPKEꢄ$%4ꢂ*
#FFTGUUꢄꢇꢐ*
0QVGꢅ All DMA Count Register channels are undefined during
4'5'6.
(KIWTG ꢈꢇꢆ &/#ꢄ$[VGꢄ%QWPVꢄ4GIKUVGTꢄꢂꢄ*KIJ
&/#ꢄ$[VGꢄ%QWPVꢄ4GIKUVGTꢄ%JCPPGNꢄꢁꢄ.QY
&/#ꢄ$[VGꢄ%QWPVꢄ4GIKUVGTꢄ%JCPPGNꢄꢂꢄ.QY
/PGOQPKEꢄ$%4ꢁ.
#FFTGUUꢄꢇ'*
/PGOQPKEꢄ$%4ꢂ.
#FFTGUUꢄꢇꢈ*
(KIWTG ꢈꢋꢆ &/#ꢄ$[VGꢄ%QWPVꢄ4GIKUVGTꢄꢁꢄ.QY
(KIWTG ꢈꢁꢆ &/#ꢄ$[VGꢄ%QWPVꢄ4GIKUVGTꢄꢂꢄ.QY
&/#ꢄ$[VGꢄ%QWPVꢄ4GIKUVGTꢄ%JCPPGNꢄꢁꢄ*KIJ
/PGOQPKEꢄ$%4ꢁ*
#FFTGUUꢄꢇ(*
(KIWTG ꢈꢉꢆ &/#ꢄ$[VGꢄ%QWPVꢄ4GIKUVGTꢄꢁꢄ*KIJ
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢏꢏ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
&/#ꢄ/'/14;ꢄ#&&4'55ꢄ4')+56'4ꢄ%*#00'.ꢄꢁ
The DMA Memory Address Register Channel 1 specifies
the physical memory address for channel 1 transfers. The
address may be a destination or a source memory location.
Theregistercontains20bitsandmayspecifyupto1024 KB
memory addresses.
&/#ꢄ/GOQT[ꢄ#FFTGUUꢄ4GIKUVGTꢎꢄ%JCPPGNꢄꢁ*
/PGOQPKEꢄ/#4ꢁ*
#FFTGUUꢄꢇꢏ*
&/#ꢄ/GOQT[ꢄ#FFTGUUꢄ4GIKUVGTꢎꢄ%JCPPGNꢄꢁ.
(KIWTG ꢈꢈꢆ &/#ꢄ/GOQT[ꢄ#FFTGUUꢄ4GIKUVGTꢎꢄ
%JCPPGNꢄꢁ*
/PGOQPKEꢄ/#4ꢁ.
#FFTGUUꢄꢇꢀ*
&/#ꢄ/GOQT[ꢄ#FFTGUUꢄ4GIKUVGTꢎꢄ%JCPPGNꢄꢁ$
/PGOQPKEꢄ/#4ꢁ$
#FFTGUUꢄꢇ#*
(KIWTG ꢈꢑꢆ &/#ꢄ/GOQT[ꢄ#FFTGUUꢄ4GIKUVGTꢎꢄ
%JCPPGNꢄꢁ.
#ꢄꢋ #ꢄꢁ
4GUGTXGF
(KIWTG ꢈꢐꢆ &/#ꢄ/GOQT[ꢄ#FFTGUUꢄ4GIKUVGTꢎꢄ
%JCPPGNꢄꢁ$
ꢏꢁ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
&/#ꢄ+ꢃ1ꢄ#&&4'55ꢄ4')+56'4
#NV'ꢆꢄThe #NV' bit should be set only when both DMA
channels are programmed for the same I/O source or I/O
destination. In this case, a channel end condition (byte count
= 0) on channel 0 sets bit 6 (#NV%), which subsequently
enables the channel 1 request and blocks the channel 0
request. Similarly, a channel end condition on channel 1
clears bit 6 (#NV%), which then enables the channel 0 request
and blocks the channel 1 request. For external requests, the
request from the device must be routed or connected to both
the &4'3ꢀ and &4'3ꢄ pins.
The DMA I/O Address Register specifies the I/O device for
channel 1 transfers. This address may be a destination or
source I/O device. +#4ꢄ. and +#4ꢄ* each contain 8 address
bits. The most significant byte identifies the Request Hand-
shake signal and controls the Alternating Channel feature.
&/#ꢄ+ꢃ1ꢄ#FFTGUUꢄ4GIKUVGTꢄ%JCPPGNꢄꢁꢄ.QY
/PGOQPKEꢄ+#4ꢁ.
#FFTGUUꢄꢇ$*
#NV%ꢆꢄIf bit (#NV') isꢅ0, the #NV% bit has no effect. When bit
7(#NV') is 1 andthe #NV% bit isꢅ0, the request signal selected
bybitsꢂ ꢀisnotpresentedtochannel1;however, thechan-
nel 0 request operates normally. When #NV' is 1 and #NV%
is 1, the request selected by 5#4ꢄꢆ ꢄꢁ or ꢄꢆ ꢄꢁ is
not presented to channel 0; however, the channel 1 request
operates normally. The #NV% bit can be written by software
to select which channel should operate first; however, this
operation should be executed only when both channels are
stopped (both &'ꢄ and &'ꢀ are ꢀ).
(KIWTG ꢈꢀꢆ &/#ꢄ+ꢃ1ꢄ#FFTGUUꢄ4GIKUVGTꢄ%JCPPGNꢄꢁꢄ.QY
&/#ꢄ+ꢃ1ꢄ#FFTGUUꢄ4GIKUVGTꢄ%JCPPGNꢄꢁꢄ*KIJ
/PGOQPKEꢄ+#4ꢁ*
#FFTGUUꢄꢇ%*
4GSꢁ5GNꢆꢄIf bit &+/ꢄ in the &%06. register is 1, indicating
an I/O source, the following bits select which source hand-
shake signal should control the transfer:
(KIWTG ꢈꢏꢆ &/#ꢄ+ꢃ1ꢄ#FFTGUUꢄ4GIKUVGTꢄ%JCPPGNꢄꢁꢄ*KIJ
ꢀꢀꢀ
ꢀꢀꢄ
ꢀꢄꢀ
1VJGT
&4'3ꢄꢅRKP
#5%+ꢀꢅ4&4(
#5%+ꢄꢅ4&4(
4GUGTXGFꢇꢅFQꢅPQVꢅRTQITCO
&/#ꢄ+ꢃ1ꢄ#FFTGUUꢄ4GIKUVGTꢄ%JCPPGNꢄꢁꢄ$
/PGOQPKEꢄ+#4ꢁ$
#FFTGUUꢄꢇ&*
If &+/ꢄ isꢅ0, indicating an I/O destination, the following
bits select which destination handshake signal should con-
trol the transfer:
$KV
ꢊ
ꢍ
ꢂ
ꢄ
ꢀ
ꢁ
ꢏ
ꢎ
#NV%
#NV'
4GSꢅꢄꢅ5GN
ꢀꢀꢀ
ꢀꢀꢄ
ꢀꢄꢀ
1VJGT
&4'3ꢄꢅRKP
#5%+ꢀꢅ6&4'
#5%+ꢄꢅ6&4'
4GUGTXGFꢇꢅFQꢅPQVꢅRTQITCO
(KIWTG ꢐꢂꢆ &/#ꢄ+ꢃ1ꢄ#FFTGUUꢄ4GIKUVGTꢄ%JCPPGNꢄꢁꢄ$
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢏꢊ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
&/#ꢄ56#675ꢄ4')+56'4
The DMA Status Register (&56#6) is used to enable and
&56#6 also indicates DMA transfer status, Completed or
disable DMA transfer and DMA termination interrupts.
In Progress.
&/#ꢄ5VCVWUꢄ4GIKUVGT
/PGOQPKEꢄ&56#6
#FFTGUUꢄꢋꢂ*
ꢎ
ꢄ
ꢏ
ꢍ
$KV
ꢊ
ꢁ
ꢂ
ꢀ
&'ꢄ
4ꢌ9
&'ꢀ
4ꢌ9
&+'ꢀ
4ꢌ9
&/'
4
&9'ꢄ &9'ꢀ &+'ꢄ
4ꢌ9
9
9
(KIWTG ꢐꢁꢆ &/#ꢄ5VCVWUꢄ4GIKUVGTꢄꢌ&56#6ꢅꢄ+ꢃ1ꢄ#FFTGUUꢄꢒꢄꢋꢂ*ꢍ
&'ꢁꢅꢄ&/#ꢄ'PCDNGꢄ%JCPPGNꢄꢁꢄꢌ$KVꢄꢐꢍꢆꢄWhen &'ꢄꢅꢐ 1
&+'ꢁꢅꢄ&/#ꢄ+PVGTTWRVꢄ'PCDNGꢄ%JCPPGNꢄꢁꢄꢌ$KVꢄꢋꢍꢆꢄWhen
&+'ꢀ is set to 1, the termination channel 1 DMA transfer
(indicated when &'ꢄꢅꢐꢅ0) causes a CPU interrupt request
to be generated. When &+'ꢀꢅꢐꢅ0, the channel 0 DMA ter-
mination interrupt is disabled. &+'ꢀ is cleared toꢅ0during
4'5'6.
and &/'ꢅꢐ 1, channel 1 DMA is enabled. When a DMA
transfer terminates ($%4ꢄꢅꢐꢅꢀ), &'ꢄ is reset toꢅ0by the
DMAC. When &'ꢄꢅꢐꢅ0and the DMA interrupt is enabled
(&+'ꢄ ꢐ 1), a DMA interrupt request is made to the CPU.
To perform a software 94+6' to &'ꢄ, &9'ꢄ should be
written withꢅaꢅ0during the same register 94+6' access.
Writing &'ꢄ toꢅ0disables channel 1 DMA, but DMA is re-
startable. Writing &'ꢄ to 1 enables channel 1 DMA and
automatically sets DMA Main Enable (&/') to 1. &'ꢄ is
cleared toꢅ0during 4'5'6.
&+'ꢂꢅꢄ&/#ꢄ+PVGTTWRVꢄ'PCDNGꢄ%JCPPGNꢄꢂꢄꢌ$KVꢄꢇꢍꢆꢄWhen
&+'ꢀ is set to 1, the termination channel 0 of DMA transfer
(indicated when &'ꢀꢅꢐꢅꢀ) causes a CPU interrupt request
to be generated. When &+'ꢀꢅꢐꢅ0, the channel 0 DMA ter-
mination interrupt is disabled. &+'ꢀ is cleared toꢅ0during
4'5'6.
&'ꢂꢅꢄ&/#ꢄ'PCDNGꢄ%JCPPGNꢄꢂꢄꢌ$KVꢄꢈꢍꢆꢄWhen &'ꢀꢅꢐ 1
and &/'ꢅꢐ 1, channel 0 DMA is enabled. When a DMA
transfer terminates ($%4ꢀꢅꢐꢅꢀ), &'ꢀ is reset toꢅ0by the
DMAC. When &'ꢀꢅꢐꢅ0and the DMA interrupt is enabled
(&+'ꢀ ꢐ 1), a DMA interrupt request is made to the CPU.
&/'ꢅꢄ&/#ꢄ/CKPꢄ'PCDNGꢄꢌ$KVꢄꢂꢍꢆꢄA DMA operation is
only enabled when its &' bit (&'ꢀ for channelꢅ0, &'ꢄ for
channel 1) and the &/'ꢅbit is set to ꢄ.
When 0/+ occurs, &/' is reset toꢅ0, thus disabling DMA
activity during the 0/+ interrupt service routine. To restart
DMA, &' and/or &'ꢄ should be written with a 1 (even
if the contents are already ꢄ). This condition automatically
sets &/' to 1, allowing DMA operations to continue.
To perform a software 94+6' to &'ꢀ, &9'ꢀ should be
written withꢅ0duringthe same register94+6' access. Writ-
ing &'ꢀ toꢅ0disables channel 0 DMA. Writing &'ꢀ to 1
enables channel 0 DMA and automatically sets DMA Main
Enable (&/') to 1. &'ꢀ is cleared toꢅ0during 4'5'6.
0QVGꢅ &/' cannot be directly written. The bit is cleared to 0
by 0/+ or indirectly set to 1 by setting &'ꢀ and/or &'ꢄ
to 1. &/' is cleared to 0during 4'5'6.
&9'ꢁꢅꢄ&'ꢁꢄ$KVꢄ9TKVGꢄ'PCDNGꢄꢌ$KVꢄꢑꢍꢆꢄWhen performing
any software 94+6' to &'ꢄ, this bit should be written with
0during the same access. &9'ꢄ always reads as ꢄ.
&9'ꢂꢅꢄ&'ꢂꢄ$KVꢄ9TKVGꢄ'PCDNGꢄꢌ$KVꢄꢉꢍꢆꢄWhen performing
any software 94+6' to &'ꢀ, this bit should be written with
0during the same access. &9'ꢀ always reads as ꢄ.
ꢏꢆ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
&/#ꢄ/1&'ꢄ4')+56'4
The DMA Mode Register (&/1&') is used to set the ad-
dressing and transfer mode for channel 0.
&/#ꢄ/QFGꢄ4GIKUVGT
/PGOQPKEꢄ&/1&'
#FFTGUUꢄꢋꢁ*
ꢎ
ꢄ
$KV
ꢊ
ꢁ
ꢏ
ꢍ
ꢂ
ꢀ
&/ꢄ
&/ꢀ
4ꢌ9
5/ꢄ
4ꢌ9
5/ꢀ //1&
4ꢌ9
4ꢌ9
4ꢌ9
(KIWTG ꢐꢇꢆ &/#ꢄ/QFGꢄ4GIKUVGTꢄꢌ&/1&'ꢅꢄ+ꢃ1ꢄ#FFTGUUꢄꢒꢄꢋꢁ*ꢍ
&/ꢁꢎꢄ&/ꢂꢅꢄ&GUVKPCVKQPꢄ/QFGꢄ%JCPPGNꢄꢂꢄꢌ$KVUꢄꢑꢎꢉꢍꢆꢄThis
5/ꢁꢎꢄ5/ꢂꢅꢄ5QWTEGꢄ/QFGꢄ%JCPPGNꢄꢂꢄꢌ$KVUꢄꢋꢎꢄꢇꢍꢄꢆꢄThis
mode specifies whether the source for channel 0 transfers
is memory or I/O, and whether the address should be incre-
mented or decremented for each byte transferred.
mode specifies whetherthe destination for channel 0 transfers
is memory or I/O, and whether the address should be incre-
mented or decremented for each byte transferred. &/ꢄ and
&/ꢀ are cleared toꢅ0during 4'5'6
.
6CDNG ꢁꢑꢆ %JCPPGNꢄꢂꢄ5QWTEG
/GOQT[ꢄ
6CDNG ꢁꢉꢆ %JCPPGNꢄꢂꢄ&GUVKPCVKQP
/GOQT[ꢄ
5/ꢁ 5/ꢂ /GOQT[ꢄ+ꢃ1
+PETGOGPVꢃ&GETGOGPV
&/ꢁ &/ꢂ /GOQT[ꢄ+ꢃ1
+PETGOGPVꢃ&GETGOGPV
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
/GOQT[
/GOQT[
/GOQT[
+ꢌ1
ꢔꢄ
ꢄ
HKZGF
HKZGF
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
/GOQT[
/GOQT[
/GOQT[
+ꢌ1
ꢔꢄ
ꢄ
HKZGF
HKZGF
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢏꢋ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
Table 16 indicates all DMA transfer mode combinations of
&/ꢀ, &/ꢄ, 5/ꢀ, and 5/ꢄ. Because I/O to/from I/O trans-
fers are not implemented, 12 combinations are available.
6CDNG ꢁꢈꢆ 6TCPUHGTꢄ/QFGꢄ%QODKPCVKQPU
5/ꢂ 6TCPUHGTꢄ/QFG #FFTGUUꢄ+PETGOGPVꢃ&GETGOGPV
&/ꢁ
&/ꢂ
5/ꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢄ
ꢀ
ꢀ
ꢀ
ꢀ
ꢄ
ꢄ
ꢄ
ꢄ
ꢀ
ꢀ
ꢀ
ꢀ
ꢄ
ꢄ
ꢄ
ꢄ
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
/GOQT[→/GOQT[
/GOQT[→/GOQT[
/GOQT[ꢕ→/GOQT[
+ꢌ1→/GOQT[
/GOQT[→/GOQT[
/GOQT[→/GOQT[
/GOQT[ꢕ→/GOQT[
+ꢌ1→/GOQT[
/GOQT[→/GOQT[ꢕ
/GOQT[→/GOQT[ꢕ
4GUGTXGF
4GUGTXGF
/GOQT[→+ꢌ1
5#4ꢀꢔꢄꢇꢅꢀꢔꢄ
5#4ꢀ ꢄꢇꢅꢀꢔꢄ
5#4ꢀꢅHKZGFꢇꢅꢀꢔꢄ
5#4ꢀꢅHKZGFꢇꢅꢀꢔꢄ
5#4ꢀꢔꢄꢇꢅꢀ ꢄ
5#4ꢀ ꢄꢇꢅꢀ ꢄ
5#4ꢀꢅHKZGFꢇꢅꢀ ꢄ
5#4ꢀꢅHKZGFꢇꢅꢀ ꢄ
5#4ꢀꢔꢄꢇꢅꢀꢅHKZGF
5#4ꢀ ꢄꢇꢅꢀꢅHKZGF
5#4ꢀꢔꢄꢇꢅꢀꢅHKZGF
5#4ꢀ ꢄꢇꢅꢀꢅHKZGF
/GOQT[→+ꢌ1
4GUGTXGF
4GUGTXGF
0QVGꢅꢄ* Includes memory mapped I/O.
//1&ꢅꢄ/GOQT[ꢄ/QFGꢄ%JCPPGNꢄꢂꢄꢌ$KVꢄꢁꢍꢆꢄWhen chan-
nel 0 is configured for memory to/from memory transfers
there is no Request Handshake signal to control the transfer
timing. Instead, twoautomatictransfertimingmodesarese-
lectable: burst (//1&ꢅꢐꢅꢄ) and cycle steal (//1&ꢅꢐꢅꢀ).
For burst memory to/from memory transfers, the DMAC
takescontrolofthebuscontinuouslyuntiltheDMAtransfer
completes (as indicated by the byte count register = ꢀ). In
cyclestealmode, theCPUisprovidedacycleforeachDMA
byte transfer cycle until the transfer is completed.
For channel 0 DMA with I/O source or destination, the se-
lected Request signal times the transfer ignoring //1&.
//1& is cleared toꢅ0during 4'5'6.
ꢁꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
&/#ꢃ9#+6ꢄ%10641.ꢄ4')+56'4
The DMA/WAIT Control Register (&%06.) controls the
insertion of wait states into DMAC (and CPU) accesses of
memory or I/O. Also, the register defines the Request signal
for each channel as level or edge sense. &%06. also sets
the DMA transfer mode for channel 1, which is limited to
memory to/from I/O transfers.
ꢏ
ꢎ
ꢍ
ꢄ
$KV
ꢊ
ꢁ
ꢂ
ꢀ
/9+ꢄ
4ꢌ9
/9+ꢀ
4ꢌ9
+9+ꢀ
4ꢌ9
&/5ꢀ
4ꢌ9
&+/ꢀ
4ꢌ9
+9+ꢄ
4ꢌ9
&/5ꢄ
4ꢌ9
&+/ꢄ
4ꢌ9
(KIWTG ꢐꢋꢆ &/#ꢃ9#+6ꢄ%QPVTQNꢄ4GIKUVGTꢄꢌ&%06.ꢅꢄ+ꢃ1ꢄ#FFTGUUꢄꢒꢄꢋꢇ*ꢍ
/9+ꢁꢎꢄ/9+ꢂꢅꢄ/GOQT[ꢄ9CKVꢄ+PUGTVKQPꢄꢌ$KVUꢄꢐ ꢈꢍꢆꢄThis
&/5K
5GPUG
bit specifies the number of wait states introduced into CPU
or DMAC memory access cycles. /9+ꢄ and /9+ꢀ are set
to 1 during 4'5'6.
ꢄ
ꢀ
'FIGꢅ5GPUG
.GXGNꢅ5GPUG
Typically, for an input/source device, the associated &/5
bit should be programmed asꢅ0for level sense. The device
takes a relatively long time to update its Request signal after
the DMA channel reads data (in the first of the two machine
cycles involved in transferring a byte).
/9+ꢁ
/9+ꢂ
9CKVꢄ5VCVG
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢂ
ꢍ
Anoutput/destinationdevice takesmuchlesstimetoupdate
its Request signal after the DMA channel starts a 94+6'
operation to it (the second machine cycle of the two cycles
involvedintransferringabyte). Withzero-wait stateI/Ocy-
cles, a devicecannotupdateitsrequest signalin the required
time, so edge sensing must be used.
+9+ꢁꢎꢄ+9+ꢂꢅꢄ+ꢃ1ꢄ9CKVꢄ+PUGTVKQPꢄꢌ$KVUꢄꢑ ꢉꢍꢆꢄThis bit speci-
fies the number of wait states introduced into CPU or DMAC
I/Oaccess cycles. +9+ꢄ and +9+ꢀ are set to
1
during 4'5'6.
+9+ꢁ
+9+ꢂ
9CKVꢄ5VCVG
A one-wait-state I/O cycle also does not provide sufficient
time for updating, so edge sensing is again required.
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢄ
ꢂ
ꢍ
ꢎ
&+/ꢁꢎꢄ&+/ꢂꢅꢄ&/#ꢄ%JCPPGNꢄꢁꢄ+ꢃ1ꢄCPFꢄ/GOQT[ꢄ/QFG
ꢌ$KVUꢄꢁ ꢂꢍꢆꢄSpecifies the source/destination and address
modifier for channel 1 memory to/from I/O transfer modes.
&+/ꢄ and &+/ꢀ are cleared toꢅ0during 4'5'6.
0QVGꢅ These wait states are added to the 3-clock I/O cycle that
is used to access the on-chip I/O registers. It is equally
valid to regard these as 0 to 3 wait states added to a 4-
clock external I/O cycle.
6CDNG ꢁꢐꢆ %JCPPGNꢄꢁꢄ6TCPUHGTꢄ/QFG
#FFTGUUꢄ
&+/ꢁ &/+ꢂ 6TCPUHGTꢄ/QFG +PETGOGPVꢃ&GETGOGPV
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
/GOQT[→+ꢌ1 /#4ꢄꢅꢔꢄꢇꢅ+#4ꢄꢅHKZGF
/GOQT[→+ꢌ1 /#4ꢄꢅ ꢄꢇꢅ+#4ꢄꢅHKZGF
+ꢌ1→/GOQT[ +#4ꢄꢅHKZGFꢇꢅ/#4ꢄꢅꢔꢄ
+ꢌ1→/GOQT[ +#4ꢄꢅHKZGFꢇꢅ/#4ꢄꢅ ꢄ
&/5ꢁꢎꢄ&/5ꢂꢅꢄ&/#ꢄ4GSWGUVꢄ5GPUGꢄꢌ$KVUꢄꢋ ꢇꢍꢆꢄ&/5ꢄ
and&/5ꢀ specifytheDMArequestsenseforchannel 0and
channel 1 respectively. When reset toꢅ0, the input is level
sense. When set to 1, the input is edge sense. &/5ꢄ and
&/5ꢀ are cleared toꢅ0during 4'5'6.
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢁꢄ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
+06'44726ꢄ8'%614ꢄ.19ꢄ4')+56'4
Bits ꢊ ꢏ of the Interrupt Vector Low Register (+ ) are used
as bits ꢊ ꢏ of the synthesized interrupt vector during inter-
rupts for the +06ꢄ and +06ꢂ pins and for the DMAs, ASCIs,
PRTs, and CSI/O. These three bits are cleared toꢅ0during
4'5'6 (Figure 74).
+PVGTTWRVꢄ8GEVQTꢄ.QYꢄ4GIKUVGT
/PGOQPKEꢅꢄ+.
#FFTGUUꢄꢋꢋ*
ꢎ
ꢄ
ꢊ
ꢁ
ꢂ
ꢀ
ꢏ
ꢍ
$KV
+.ꢅꢁ
+.ꢅꢊ
4ꢌ9
+.ꢅꢏ
4ꢌ9
4ꢌ9
2TQITCOOCDNG
+PVGTTWRVꢅ5QWTEGꢅ&GRGPFGPVꢅ%QFG
(KIWTG ꢐꢉꢆ +PVGTTWRVꢄ8GEVQTꢄ.QYꢄ4GIKUVGTꢄꢌ+.ꢅꢄ+ꢃ1ꢄ#FFTGUUꢄꢒꢄꢋꢋ*ꢍ
+06ꢃ64#2ꢄ%10641.ꢄ4')+56'4
This register is used in handling 64#2 interrupts and to en-
able or disable Maskable Interrupt Levelꢅꢀꢅand the +06ꢄ
and +06ꢂ pins.
+06ꢂ and +06ꢄ, respectively. +6'ꢀ enables and disables in-
terrupts from:
'5%%
%6%U
• Bidirectional Centronics controller
+06ꢃ64#2ꢄ%QPVTQNꢄ4GIKUVGT
/PGOQPKEUꢄ+6%
#FFTGUUꢄꢋꢉ*
• External interrupt input +06ꢀ
A 1 in a bit enables the corresponding interrupt level while
aꢅ0disables it. A 4'5'6 sets +6'ꢀ to 1 and clears +6'ꢄ
and +6'ꢂ to 0.
ꢎ
ꢊ
ꢁ
ꢂ
ꢄ
ꢀ
ꢏ
ꢍ
$KV
64#2
7(1
+6'ꢂ +6'ꢄ
+6'ꢀ
64#2ꢄ+PVGTTWRVꢆꢄThe Z8S180/Z8L180 generates a 64#2
sequence when an undefined opcode fetch occurs. This fea-
ture can be used to increase software reliability, implement
an extended instruction set, or both. 64#2 may occur during
opcode fetch cycles and also if an undefined opcode is
fetched during the interrupt acknowledge cycle for +06ꢀ
when Modeꢅꢀꢅis used.
4ꢌ9
4
4ꢌ9 4ꢌ9 4ꢌ9
64#2ꢄꢌ$KVꢄꢐꢍꢆꢄThis bit is set to 1 when an undefined op-
code is fetched. 64#2 can be reset under program control
bywritingitwithaꢀ;however,64#2cannotbewrittenwith
1 under program control. 64#2 is reset toꢅ0during 4'5'6.
When a 64#2 sequence occurs, the Z8S180/Z8L180:
7(1ꢅꢄ7PFGHKPGFꢄ(GVEJꢄ1DLGEVꢄꢌ$KVꢄꢈꢍꢆꢄWhen a 64#2 in-
terrupt occurs, the contents of 7(1 allow the starting ad-
dress of the undefined instruction to be determined. This in-
terrupt is necessary because the 64#2 may occur on either
the second or third byte of the opcode. 7(1 allows the
stacked PC value to be correctly adjusted. If 7(1ꢅꢐꢅ0, the
first opcode should be interpreted as the stacked 2%ꢃꢄ. If
7(1ꢅꢐ 1, the first opcode address is stacked 2%ꢃꢂ. 7(1 is
Read-Only.
1. Sets the 64#2 bit in the Interrupt 64#2/Control (+6%)
register to 1.
2. Saves the current Program Counter (PC) value,
reflecting the location of the undefined opcode, on the
stack.
3. Resumes execution at logical address 0.
0QVGꢅ If logical address 0000His mapped to physical address
00000H, the vector is the same as for 4'5'6. In this
case, testing the 64#2 bit in +6% reveals whether the re-
start at physical address 00000Hwas caused by 4'5'6
or 64#2.
+6'ꢇꢎꢄꢁꢎꢄꢂꢅꢄ+PVGTTWRVꢄ'PCDNGꢄꢇꢎꢄꢁꢎꢄꢂꢄꢌ$KVUꢄꢇ ꢂꢍꢆꢄ+6'ꢂ
and +6'ꢄ enable and disable the external interrupt inputs
ꢁꢂ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
All64#2U occur after fetchinganundefined secondopcode
byte following one of the prefix opcodes (CBH, DDH, EDH,
or FDH) or after fetching an undefined third opcode byte
following one of the double-prefix opcodes (DDCBH or
FDCBH).
The state of the Undefined Fetch Object (7(1) bit in +6%
allows 64#2 softwaretocorrectlyadjust thestackedPC, de-
pending on whether the second or third byte of the opcode
generated the 64#2. If 7(1ꢅꢐꢅ0, the starting address of
the invalid instruction is the stacked 2% ꢄ. If 7(1ꢅꢐ 1, the
starting address of the invalid instruction is equal to the
stacked 2% ꢂ.
4GUVCTVꢅ
HTQOꢅꢀꢀꢀꢀ*
1REQFG
(GVEJꢅ%[ENG
ꢂPFꢅ1REQFG
(GVEJꢅ%[ENG
2%ꢅ5VCEMKPI
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
2*+
ꢅꢈ#
#
#
ꢉ
ꢀꢀꢀꢀ*
2%
52ꢃꢄ
2%
52ꢃꢂ
2%
&
&
7PFGHKPGF
1REQFG
/ꢄ
/4'3
4&
94
(KIWTG ꢐꢑꢆ 64#2ꢄ6KOKPI
ꢇ
ꢄ1REQFGꢄ7PFGHKPGF
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢁꢍ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
4GUVCTV
(TQOꢅꢀꢀꢀꢀ*
1REQFG
(GVEJꢅ%[ENG
ꢍTFꢅ1REQFG
(GVEJꢅ%[ENG
/GOQT[
4GCFꢅ%[ENG
2%ꢅ5VCEMKPI
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
2*+
ꢉ
#
#
ꢅꢈ#
2%
+:ꢅꢔꢅFꢇꢅ+;ꢅꢔꢅF
52ꢃꢄ
2%ꢃꢄ
ꢀꢀꢀꢀ*
52ꢃꢂ
2%ꢃꢄ
&
&
7PFGHKPGF
1REQFG
/ꢄ
/4'3
4&
94
(KIWTG ꢐꢈꢆ 64#2ꢄ6KOKPI ꢋ ꢄ1REQFGꢄ7PFGHKPGF
ꢁꢎ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
4'(4'5*ꢄ%10641.ꢄ4')+56'4
/PGOQPKEꢄ4%4
#FFTGUUꢄꢋꢈ*ꢄ
4'('ꢅꢄ4GHTGUJꢄ'PCDNGꢄꢌ$KVꢄꢐꢍꢆꢄ4'('ꢅꢐꢅ0disables the re-
fresh controller, while 4'('ꢅꢐ 1 enables refresh cycle in-
sertion. 4'(' is set to 1 during 4'5'6.
ꢀ
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢂ
ꢄ
ꢃ
4'(9ꢅꢄ4GHTGUJꢄ9CKVꢄꢌ$KVꢄꢈꢍꢆꢄ4'(9 ꢐ 0 causes the re-
fresh cycle to be two clocks in duration. 4'(9ꢅꢐ 1 causes
the refresh cycle to be three clocks in duration by adding a
refresh wait cycle (649). 4'(9 is set to 1 during 4'5'6.
4'('
4'(9
%[Eꢀ
%[Eꢄ
%;%ꢁꢎꢄꢂꢅꢄ%[ENGꢄ+PVGTXCNꢄꢌ$KVꢄꢁꢎꢂꢍꢆꢄ%;%ꢄ and %;%ꢀ
specifytheinterval(inclockcycles)betweenrefreshcycles.
When dynamic RAM requires 128 refresh cycles every 2
ms (or 256 cycles in every 4 ms), the required refresh in-
terval is lessthan or equalto15.625µs. Thus, theunderlined
values indicate the best refresh interval depending on CPU
clock frequency. %;%ꢀ and %;%ꢄ are cleared toꢅ0during
4'5'6 (see Table 18).
4GUGTXGF
(KIWTG ꢐꢐꢆ 4GHTGUJꢄ%QPVTQNꢄ4GIKUVGTꢄ
ꢌ4%4ꢅꢄ+ꢃ1ꢄ#FFTGUUꢄꢒꢄꢋꢈ*ꢍ
The Refresh Control Registerꢅ(4%4) specifies the interval
and length of refresh cycles, while enabling or disabling the
refresh function.
6CDNG ꢁꢀꢆ &4#/ꢄ4GHTGUJꢄ+PVGTXCNU
6KOGꢄ+PVGTXCN
ꢈꢄ/*\
%;%ꢁ
%;%ꢂ
+PUGTVKQPꢄ+PVGTXCN 2*+ꢅꢄꢁꢂꢄ/*\
ꢀꢄ/*\
ꢉꢄ/*\
ꢇꢆꢑꢄ/*\
ꢀ
ꢀ
ꢄ
ꢄ
ꢀ
ꢄ
ꢀ
ꢄ
ꢄꢀꢅUVCVGU
ꢂꢀꢅUVCVGU
ꢎꢀꢅUVCVGU
ꢆꢀꢅUVCVGU
ꢈꢄꢑꢀꢅzUꢉꢕ
ꢈꢂꢑꢀꢅzUꢉꢕ
ꢈꢎꢑꢀꢅzUꢉꢕ
ꢈꢆꢑꢀꢅzUꢉꢕ
ꢈꢄꢑꢂꢏꢅzUꢉꢕ
ꢈꢂꢑꢏꢅzUꢉꢕ
ꢈꢏꢑꢀꢅzUꢉꢕ
ꢈꢄꢀꢑꢀꢅzUꢉꢕ
ꢄꢑꢁꢁꢅzU
ꢍꢑꢍꢅzU
ꢁꢑꢁꢅzU
ꢂꢑꢏꢅzU
ꢏꢑꢀꢅzU
ꢄꢀꢑꢀꢅzU
ꢂꢀꢑꢀꢅzU
ꢎꢑꢀꢅzU
ꢆꢑꢀꢅzU
ꢄꢁꢑꢀꢅzU
ꢍꢂꢑꢀꢅzU
ꢄꢍꢑꢍꢅzU
0QVGꢅꢄ*calculated interval.
4GHTGUJꢄ%QPVTQNꢄCPFꢄ4GUGVꢆꢄAfter 4'5'6, based on the
initialized value of 4%4, refresh cycles occur with an inter-
val of 10 clock cycles and be 3 clock cycles in duration.
3. Refresh cycles are suppressed during 5.''2 mode. If
a refresh cycle is requested during 5.''2 mode, the
refresh cycle request is internally latched (until
replaced with the next refresh request). The latched
refresh cycle is inserted at the end of the first machine
cycle after 5.''2 mode is exited. After this initial
cycle, the time at which the next refresh cycle occurs
depends on the refresh time and offers no relationship
with the exit from 5.''2 mode.
&[PCOKEꢄ4#/ꢄ4GHTGUJꢄ1RGTCVKQP
1. Refresh Cycle insertion is stopped when the CPU is in
the following states:
a. During 4'5'6
b. When the bus is released in response to $754'3
c. During 5.''2 mode
4. The refresh address is incremented by one for each
successful refresh cycle, not for each refresh. Thus,
independent of the number of missed refresh requests,
each refresh bus cycle uses a refresh address
incremented by one from that of the previous refresh
bus cycles.
d. During 9#+6 states
2. Refresh cycles are suppressed when the bus is released
in response to $754'3. However, the refresh timer
continues to operate. The time at which the first
refresh cycle occurs after the Z8S180/Z8L180
reacquires the bus depends on the refresh timer. This
cycle offers no timing relationship with the bus
exchange.
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢁꢏ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
//7ꢄ%1//10ꢄ$#5'ꢄ4')+56'4
The Common Base Register (%$4) specifies the base ad-
dress (on 4-KB boundaries) used to generate a 20-bit phys-
ical address for Common Area 1 accesses. All bits of %$4
are reset toꢅ0during 4'5'6.
//7ꢄ%QOOQPꢄ$CUGꢄ4GIKUVGT
/PGOQPKEꢄ%$4
#FFTGUUꢄꢋꢀ*
ꢏ
ꢎ
ꢍ
ꢂ
ꢄ
ꢀ
ꢊ
ꢁ
$KV
ꢅ%$ꢊ
4ꢌ9
%$ꢁ
4ꢌ9
%$ꢏ
4ꢌ9
%$ꢎ
4ꢌ9
%$ꢍ
4ꢌ9
%$ꢂ
4ꢌ9
%$ꢄ
4ꢌ9
%$ꢀ
4ꢌ9
(KIWTG ꢐꢀꢆ //7ꢄ%QOOQPꢄ$CUGꢄ4GIKUVGTꢄꢌ%$4ꢅꢄ+ꢃ1ꢄ#FFTGUUꢄꢒꢄꢋꢀ*ꢍ
//7ꢄ$#0-ꢄ$#5'ꢄ4')+56'4
The Bank Base Register ($$4) specifies the base address
(on 4-KB boundaries) used to generate a 20-bit physical ad-
dress for Bank Area accesses. All bits of $$4 are reset to
0during 4'5'6.
//7ꢄ$CPMꢄ$CUGꢄ4GIKUVGT
/PGOQPKEꢄ$$4
#FFTGUUꢄꢋꢏ*
ꢏ
ꢍ
ꢊ
ꢅ$$ꢊ
4ꢌ9
ꢁ
ꢎ
ꢂ
ꢄ
ꢀ
$KV
$$ꢁ
4ꢌ9
$$ꢏ
4ꢌ9
$$ꢎ
4ꢌ9
$$ꢍ
4ꢌ9
$$ꢀ
4ꢌ9
$$ꢂ
4ꢌ9
$$ꢄ
4ꢌ9
(KIWTG ꢐꢏꢆ //7ꢄ$CPMꢄ$CUGꢄ4GIKUVGTꢄꢌ$$4ꢅꢄ+ꢃ1ꢄ#FFTGUUꢄꢒꢄꢋꢏ*ꢍ
//7ꢄ%1//10ꢃ$#0-ꢄ#4'#ꢄ4')+56'4
TheCommon/BankAreaRegister(%$#4)specifiesbound-
aries within the Z8S180/Z8L180 64-KB logical address
space for up to three areas; Common Area), Bank Area and
Common Area 1.
//7ꢄ%QOOQPꢃ$CPMꢄ#TGCꢄ4GIKUVGT
/PGOQPKEꢄ%$#4
#FFTGUUꢄꢋ#*
ꢏ
ꢎ
ꢍ
ꢂ
ꢄ
ꢀ
ꢊ
ꢁ
$KV
ꢅ%#ꢍ
4ꢌ9
%#ꢂ
4ꢌ9
%#ꢄ
4ꢌ9
%#ꢀ
4ꢌ9
$#ꢍ
4ꢌ9
$#ꢂ
4ꢌ9
$#ꢄ
4ꢌ9
$#ꢀ
4ꢌ9
(KIWTG ꢀꢂꢆ //7ꢄ%QOOQPꢃ$CPMꢄ#TGCꢄ4GIKUVGTꢄꢌ%$#4ꢅꢄ+ꢃ1ꢄ#FFTGUUꢄꢒꢄꢋ#*ꢍ
ꢁꢁ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
%#ꢋ %#ꢂꢅ%#ꢄꢌ$KVUꢄꢐ ꢉꢍꢆꢄ%#specifiesthestart(Low)ad-
dress (on 4-KB boundaries) for Common Area 1. This con-
dition also determines the most recent address of the Bank
Area. All bits of %# are set to 1 during 4'5'6.
$#ꢋ $#ꢂꢄꢌ$KVUꢄꢋ ꢂꢍꢆꢄ$# specifiesthe start (Low)address
(on 4-KB boundaries) for the Bank Area. This condition
also determines the most recent address of Common Area
0. All bits of $# are set to 1 during 4'5'6.
12'4#6+10ꢄ/1&'ꢄ%10641.ꢄ4')+56'4
/ꢁ'ꢄꢌ/ꢁꢄ'PCDNGꢍꢆꢄThis bit controls the /ꢄ output and is
set to a 1 during reset.
The Z8S180/Z8L180 is descended from two different an-
cestor processors, ZiLOG’s original Z80 and the Hitachi
64180. The Operating Mode Control Register (1/%4) can
be programmed to select between certain differences be-
tween the Z80 and the 64180.
When /ꢄ'ꢅꢐ 1, the /ꢄ output is asserted Low during the
opcode fetch cycle, the +06ꢀ acknowledge cycle, and the
first machine cycle of the 0/+ acknowledge.
1RGTCVKQPꢄ/QFGꢄ%QPVTQNꢄ4GIKUVGT
On the Z8S180/Z8L180, this choice makes the processor
fetch one4'6+ instruction. When fetching a4'6+ fromzero-
wait-state memory, the processor uses three clock machine
cycles that are not fully Z80-timing-compatible.
/PGOQPKEꢄ1/%4
#FFTGUUꢄꢋ'*
When /ꢄ'ꢅꢐꢅ0, the processor does not drive /ꢄ Low dur-
inginstruction fetchcycles. Afterfetchingone4'6+instruc-
tion with normal timing, the processor returns and refetches
the instruction using Z80-compatible cycles that drive /ꢄ
Low. Thistimingcompatibilitymayberequiredbyexternal
Z80 peripherals to properly decode the 4'6+ instruction.
&ꢊ &ꢁ &ꢏ
4GUGTXGF
+1%ꢅꢈ4ꢌ9ꢉ
/ꢄ6'ꢅꢈ9ꢉ
/ꢄ'ꢅꢈ4ꢌ9ꢉ
(KIWTG ꢀꢁꢆ 1RGTCVKPIꢄ%QPVTQNꢄ4GIKUVGT
ꢌ1/%4ꢅꢄ+ꢃ1ꢄ#FFTGUUꢄꢒꢄꢋ'*ꢍ
T1 T2 T3 T1 T2 T3
TI
TI
TI T1 T2 T3
TI T1 T2 T3
TI
2*+
A0–A18 (A19)
PC+1
PC
EDH
PC+1
PC
EDH
4DH
4DH
D0–D7
M1
MREQ
RD
ST
(KIWTG ꢀꢇꢆ 4'6+ꢄ+PUVTWEVKQPꢄ5GSWGPEGꢄYKVJꢄ/ꢁ'ꢄꢒꢄꢂ
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢁꢊ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
+ꢃ1ꢄ%10641.ꢄ4')+56'4
The I/O Control Register (+%4) allows relocation of the in-
ternal I/O addresses. +%4 also controls the enabling and dis-
abling of +15612 mode (Figure 83).
$KV
ꢊ
ꢁ
ꢏ
ꢎ
ꢍ
ꢂ
ꢄ
ꢀ
+1#ꢊ
+1#ꢁ
+1562
4ꢌ9
4ꢌ9
4ꢌ9
(KIWTG ꢀꢋꢆ +ꢃ1ꢄ%QPVTQNꢄ4GIKUVGTꢄꢌ+%4ꢅꢄ+ꢃ1ꢄ#FFTGUUꢄꢒꢄꢋ(*ꢍ
+1#ꢐꢎꢄꢈꢅꢄ+ꢃ1ꢄ#FFTGUUꢄ4GNQECVKQPꢄꢌ$KVUꢄꢐꢎꢈꢍꢆꢄ+1#ꢊ and
+1#ꢁ relocate internal I/O as indicated in Figure 84.
0QVGꢅ The high-order 8 bits of 16-bit internal I/O address are al-
ways 0. +1#ꢊ and +1#ꢁ are cleared toꢅ0ꢅduring 4'5'6
.
ꢀꢀ((*
+1#ꢊ +1#ꢁꢅꢐꢅꢄꢅꢄ
+1#ꢊ +1#ꢁꢅꢐꢅꢄꢅꢀ
+1#ꢊ +1#ꢁꢅꢐꢅꢀꢅꢄ
+1#ꢊ +1#ꢁꢅꢐꢅꢀꢅꢀ
ꢀꢀ%ꢀ*
ꢀꢀ$(*
ꢀꢀꢆꢀ*
ꢀꢀꢊ(*
ꢀꢀꢎꢀ*
ꢀꢀꢍ(*
ꢀꢀꢀꢀ*
(KIWTG ꢀꢉꢆ +ꢃ1ꢄ#FFTGUUꢄ4GNQECVKQP
+1562ꢅꢄ+15612ꢄ/QFGꢄꢌ$KVꢄꢑꢍꢆꢄꢄ+15612 mode is enabled
when +1562 isset to1. NormalI/Ooperationresumeswhen
+1562 is reprogrammed or 4'5'6 to 0.
ꢁꢆ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
2#%-#)'ꢄ+0(14/#6+10
(KIWTG ꢀꢑꢆ ꢈꢉꢊ2KPꢄ&+2ꢄ2CEMCIGꢄ&KCITCO
(KIWTG ꢀꢈꢆ ꢀꢂꢊ2KPꢄ3(2ꢄ2CEMCIGꢄ&KCITCO
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢁꢋ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
(KIWTG ꢀꢐꢆ ꢈꢀꢊ2KPꢄ2.%%ꢄ2CEMCIGꢄ&KCITCO
ꢊꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ
'PJCPEGFꢄ<ꢁꢀꢂꢄ/KETQRTQEGUUQT
ZiLOG
14&'4+0)ꢄ+0(14/#6+10
For fast results, contact your local ZiLOG sales office for
assistance in ordering the part(s) required.
%QFGU
5RGGF
ꢄꢀꢅꢐꢅꢄꢀꢅ/*\
ꢂꢀꢅꢐꢅꢂꢀꢅ/*\
ꢍꢍꢅꢐꢅꢍꢍꢅ/*\
2CEMCIG
2ꢅꢐꢅꢁꢀꢃ2KPꢅ2NCUVKEꢅ&+2
8ꢅꢐꢅꢁꢆꢃ2KPꢅ2.%%
(ꢅꢐꢅꢆꢀꢃ2KPꢅ3(2
6GORGTCVWTG
5ꢅꢐꢅꢀu%ꢅVQꢅꢔꢊꢀu%
'ꢅꢐꢅ ꢎꢀu%ꢅVQꢅꢔꢆꢏu%
%ꢅꢐꢅ2NCUVKEꢅ5VCPFCTF
'PXKTQPOGPVCN
'ZCORNGꢓ
<ꢅꢅꢆ5ꢄꢆꢀꢅꢄꢀ 2 5 %ꢅ
KUꢅCꢅ<ꢆ5ꢄꢆꢀꢅꢄꢀꢃ/*\ꢅꢁꢀꢃ2KPꢅ&+2ꢇꢅꢀꢅVQꢅꢔꢊꢀ%ꢇꢅ2NCUVKEꢅ5VCPFCTFꢅ(NQY
'PXKTQPOGPVCNꢅ(NQY
6GORGTCVWTG
2CEMCIG
5RGGF
2TQFWEVꢅ0WODGT
<K.1)ꢅ2TGHKZ
2TGꢊ%JCTCEVGTK\CVKQPꢄ2TQFWEV
The product represented by this document is newly introduced
and ZiLOG has not completed the full characterization of the
product. The document states what ZiLOG knows about this
product at this time, but additional features or non-conformance
with some aspects of the document may be found, either by
ZiLOG or its customers in the course of further application and
characterization work. In addition, ZiLOG cautions that delivery
may be uncertain at times, due to start-up yield issues.
©2000 by ZiLOG, Inc. All rights reserved. Information in this
publication concerning the devices, applications, or technology
described is intended to suggest possible uses and may be
superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY
FOR OR PROVIDE A REPRESENTATION OF ACCURACY
OF THE INFORMATION, DEVICES, OR TECHNOLOGY
DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES
NOT ASSUME LIABILITY FOR INTELLECTUAL
PROPERTY INFRINGEMENT RELATED IN ANY
MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE.
Except with the express written approval of ZiLOG, use of
information, devices, or technology as critical components of
life support systems is not authorized. No licenses are conveyed,
implicitly or otherwise, by this document under any intellectual
property rights.
ZiLOG, Inc.
910 East Hamilton Avenue, Suite 110
Campbell, CA 95008
Telephone (408) 558-8500
FAX (408) 558-8300
Internet: http://www.zilog.com
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
ꢊꢄ
相关型号：
©2020 ICPDF网 联系我们和版权申明