SF23C3200B [KB]

32 Mbit CMOS Mask Programmable ROM; 32兆位的CMOS掩模可编程ROM
SF23C3200B
型号: SF23C3200B
厂家: King blillion Electronics Co.,Ltd.    King blillion Electronics Co.,Ltd.
描述:

32 Mbit CMOS Mask Programmable ROM
32兆位的CMOS掩模可编程ROM

文件: 总7页 (文件大小:296K)
中文:  中文翻译
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King Billion Electronics Co., Ltd SF23C3200B  
駿 億 電 子 股 份 有 限 公 司  
- Table of Contents -  
1. General Description_______________________________________________________________2  
2. Features ________________________________________________________________________2  
3. Functional block diagram __________________________________________________________2  
4. Pin Description __________________________________________________________________3  
5. Pad Location ____________________________________________________________________5  
6. Absolute Maximum Rating _________________________________________________________6  
7. AC Electrical Characteristics _______________________________________________________6  
8. DC Electrical Characteristics _______________________________________________________7  
December 8, 2003  
Page 1 of 7  
V1.1  
This specification is subject to change without notice. Please contact sales person for the latest version before use.  
King Billion Electronics Co., Ltd SF23C3200B  
駿 億 電 子 股 份 有 限 公 司  
1. General Description  
The SF23C3200B is a fully static, 32 Mbit CMOS Mask Programmable ROM. This device operates in  
wide operating range. It requires no external clock for its operation and suitable for use with  
microprocessor program memory, and data memory (speech, graphic, etc).  
2. Features  
9 Operating range: 2.4V ~ 3.6V  
9 Organization  
-
Memory Cell Array: 4M x 8 or 2M x 16 selectable by BYTEB pin  
9 Low Operation Current (Typical)  
-
-
10 µA standby mode current.  
30 mA active read current at 100 ns cycle time.  
9 Fully static operation  
9 Tri-state outputs  
9 Package: bare chip  
3. Functional block diagram  
X BUFFER &  
DECODER  
MEMORY  
CELL  
ARRAY  
[A20..A-1]  
Y BUFFER &  
DECODER  
CEn  
CONTROL  
LOGIC  
OEn  
SENSE AMP.  
[Q15..Q0]  
BYTEB  
December 8, 2003  
Page 2 of 7  
V1.1  
This specification is subject to change without notice. Please contact sales person for the latest version before use.  
King Billion Electronics Co., Ltd SF23C3200B  
駿 億 電 子 股 份 有 限 公 司  
4. Pin Description  
1
2
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
A18  
A17  
A7  
A20  
A19  
A8  
3
4
A6  
A9  
5
A5  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
BYTE  
GND  
Q15/A-1  
Q7  
6
A4  
7
A3  
8
A2  
9
A1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
A0  
CE  
GND  
OE  
Q0  
Q8  
Q1  
Q9  
Q2  
Q10  
Q3  
Q11  
Q14  
Q6  
Q13  
Q5  
Q12  
Q4  
VCC  
SF23C3200  
Symbol Pin No. I/O  
Description  
A18, A17  
A7 ~ A0  
CEn  
1, 2  
3 ~ 10  
11  
I
I
I
Mask ROM Address input pins.  
Mask ROM Address input pins.  
The CEn (Chip Enable) input is the device selection and power control for  
internal Mask ROM array. Whenever CEn goes high, the internal Mask  
ROM will enter standby (power saving) mode. Otherwise, it is in active  
mode and the contents of the ROM can be accessed.  
GND  
OEn  
12  
13  
P
I
Negative power supply input pin.  
OEn (Output Enable) is the output control which gates ROM array data onto  
the data output pins Q7 ~ Q0 in Byte mode (BYTEB pin is at “low” state) or  
Q15A-1, Q14 ~ Q0 in Word mode (BYTEB pin is at “high” state).  
Q0,  
14,  
16,  
18,  
20,  
23,  
25,  
27,  
29  
15,  
17,  
19,  
21,  
24,  
26,  
28,  
30  
O, Mask ROM array Data lower byte outputs drive Q7 ~ Q0 pins during read  
Q1,  
O, operations (CEn and OEn are “low”). The Q7 ~ Q0 pins stay in high-Z when  
Q2,  
O, the chip is deselected (CEn high) or when the outputs are disabled (OEn  
Q3,  
O, high).  
Q4,  
O,  
Q5,  
O,  
Q6,  
O,  
Q7,  
O,  
Q8,  
O, Mask ROM data higher byte output pins when Word mode is selected  
Q9,  
O, (BYTEB is at “high” level) during read operations (CEn and OEn are  
Q10,  
Q11,  
Q12,  
Q13,  
Q14,  
Q15A-1,  
O, “low”). They will be tri-stated when Byte mode is selected (BYTEB at  
O, “low” level), the chip is deselected (CEn high), the outputs are disabled  
O, (OEn high).  
O,  
O,  
O/I, Q15A-1 is Mask ROM MSB Data output pin in Word mode and LSB  
address pin in Byte mode.  
VCC  
22  
P
Positive power supply input pin.  
December 8, 2003  
Page 3 of 7  
V1.1  
This specification is subject to change without notice. Please contact sales person for the latest version before use.  
King Billion Electronics Co., Ltd SF23C3200B  
駿 億 電 子 股 份 有 限 公 司  
GND  
31  
32  
P
I
Negative power supply input pin.  
BYTEB  
Byte/Word mode selection input pin. Byte mode is selected when it is at  
“low” state, otherwise Word mode is selected.  
Mask ROM Address input pins.  
A16 ~ A8 33 ~ 41  
A19, A20 42, 43  
I
I
Mask ROM Address input pins.  
December 8, 2003  
Page 4 of 7  
V1.1  
This specification is subject to change without notice. Please contact sales person for the latest version before use.  
King Billion Electronics Co., Ltd SF23C3200B  
駿 億 電 子 股 份 有 限 公 司  
5. Pad Location  
December 8, 2003  
Page 5 of 7  
V1.1  
This specification is subject to change without notice. Please contact sales person for the latest version before use.  
King Billion Electronics Co., Ltd SF23C3200B  
駿 億 電 子 股 份 有 限 公 司  
Pad No. Pad Name  
1 NC  
X Coord. Y Coord. Pad No.  
Pad Name  
X Coord. Y Coord.  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
-1941.5  
3231.86  
3008.86  
2785.86  
2562.86  
2339.86  
2116.86  
1893.86  
1670.86  
1447.86  
1224.86  
1001.86  
778.86  
31 GND  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
1941.5  
-3262.78  
-3039.78  
-2816.78  
-2593.78  
-2370.78  
-2140.78  
-1917.78  
-1687.78  
-1464.78  
-1234.78  
-1011.78  
-781.78  
-558.78  
-335.78  
-112.78  
110.22  
2 BYTEB  
3 A16  
32 GND  
33 GND  
34 OEN  
35 D0  
4 A15  
5 A14  
6 A13  
36 D8  
7 A12  
37 D1  
8 A11  
38 D9  
9 A10  
39 D2  
10 A9  
40 D10  
41 D3  
11 A8  
12 A19  
13 GND  
14 NC  
42 D11  
43 VDD  
44 GND  
45 VDD  
46 GND  
47 VDD  
48 GND  
49 D4  
555.86  
332.86  
-34.78  
15 GND  
16 NC  
-257.78  
-480.78  
-703.78  
-926.78  
-1149.78  
-1372.78  
-1595.78  
-1818.78  
-2041.78  
-2264.78  
-2487.78  
-2710.78  
-2931.48  
-3152.18  
-3372.88  
17 GND  
18 A20  
19 A18  
20 A17  
21 A7  
333.22  
712.16  
935.16  
50 D12  
51 D5  
1165.16  
1388.16  
1618.16  
1841.16  
2071.16  
2294.16  
2517.16  
2740.16  
2963.16  
3186.16  
22 A6  
52 D13  
53 D6  
23 A5  
24 A4  
54 D14  
55 D7  
25 A3  
26 A2  
56 D15A_1  
57 GND  
58 GND  
59 GND  
27 A1  
28 A0  
29 CEN  
30 NC  
6. Absolute Maximum Rating  
Items  
Symbol  
VCC  
Rating  
Supply Voltage  
2.4 to 3.6 V  
Input Voltage  
Operating Temperature  
Storage Temperature  
VIN  
-0.3 to Vdd+0.3 V  
-0 to 70 °C  
-55 to 125 °C  
TOPR  
TSTR  
7. AC Electrical Characteristics  
READ CYCLE:  
December 8, 2003  
Page 6 of 7  
V1.1  
This specification is subject to change without notice. Please contact sales person for the latest version before use.  
King Billion Electronics Co., Ltd SF23C3200B  
駿 億 電 子 股 份 有 限 公 司  
There are two ways of accessing the ROM data. The first one is to assert the valid address on the Address  
Bus, then assert CEn “low” to enable the ROM array. The access time in this mode is specified as tACE  
.
The advantage of this access mode is that power consumption can be lowered. The second access mode  
keeps the CEn “low” while changes the addresses to access the contents of ROM data. The access time in  
this way is specified as tAA.  
Item  
Symbol  
Min  
100  
120  
Max  
Unit  
Condition  
Read Cycle Time  
tRC  
ns VDD = 3.0 V, no load  
VDD = 2.4V, no load  
ns VDD = 3.0 V, no load  
VDD = 2.4V, no load  
ns VDD = 3.0 V, no load  
VDD = 2.4V, no load  
ns  
Chip Enable Access Time  
Address Access Time  
tACE  
tAA  
100  
120  
100  
120  
50  
Output Enable Time  
Output or Chip Disable to Output High-Z  
Output Hold from Address Change  
tOE  
tDF  
tOH  
20  
ns  
ns  
0
8. DC Electrical Characteristics  
(GND = 0V, VCC = 3.0 V, TOPR = 25°C unless otherwise noted)  
Parameter  
Symbol Min. Typical Max.  
Unit  
Condition  
Supply Voltage  
VCC  
ICC  
2.4  
-
-
30  
10  
-
3.6  
-
V
Operating Current  
Standby Current  
mA  
µA  
No load, tRC@ 100 ns  
No load  
ISTBY  
VIH  
VIL  
IIL  
-
-
2/3  
0
1
Input voltage  
VDD  
VDD = 2.4V ~ 3.6V  
-
1/3  
± 10  
-
Input current leakage  
-
2.4  
-
µA  
V
P0, P1 Output High Voltage  
P0, P1 Output Low Voltage  
D Output High Voltage  
D Output Low Voltage  
VOH  
VOL  
VOH  
VOL  
-
-
-
-
IOH = 0.4 mA  
IOL = 2.1 mA  
IOH = 1.4 mA  
IOL = 3 mA  
-
2.4  
-
0.4  
-
0.4  
V
V
V
December 8, 2003  
Page 7 of 7  
V1.1  
This specification is subject to change without notice. Please contact sales person for the latest version before use.  

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