C0805C151J1GACAUTO_技术文档

SurfaceꢀMountꢀMultilayerꢀCeramicꢀChipꢀCapacitorsꢀ(SMDꢀMLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Overview

KEMET’sꢀC0Gꢀdielectricꢀfeaturesꢀaꢀ125°Cꢀmaximumꢀ

operatingꢀtemperatureꢀandꢀisꢀconsideredꢀ“stable.”ꢀ

TheꢀElectronicsꢀComponents,ꢀAssembliesꢀ&ꢀMaterialsꢀ

Associationꢀ(EIA)ꢀcharacterizesꢀC0Gꢀdielectricꢀasꢀaꢀ

ClassꢀIꢀmaterial.ꢀComponentsꢀofꢀthisꢀclassiﬁcationꢀareꢀ

temperatureꢀcompensatingꢀandꢀareꢀsuitedꢀforꢀresonantꢀ

circuitꢀapplicationsꢀorꢀthoseꢀwhereꢀQꢀandꢀstabilityꢀofꢀ

capacitanceꢀcharacteristicsꢀareꢀrequired.ꢀC0Gꢀexhibitsꢀnoꢀ

changeꢀinꢀcapacitanceꢀwithꢀrespectꢀtoꢀtimeꢀandꢀvoltageꢀandꢀ

boastsꢀaꢀnegligibleꢀchangeꢀinꢀcapacitanceꢀwithꢀreferenceꢀtoꢀ

ambientꢀtemperature.ꢀCapacitanceꢀchangeꢀisꢀlimitedꢀto

±30ꢀppm/ºCꢀfromꢀ−55°Cꢀtoꢀ+125°C.ꢀ

Beneﬁts

•ꢀ −55°Cꢀtoꢀ+125°Cꢀoperatingꢀtemperatureꢀrange

• Lead (Pb)-free, RoHS, and REACH compliant

• EIA 0201, 0402, 0603, 0805, 1206, 1210, 1808, 1812, 1825,

2220, and 2225 case sizes

•ꢀ DCꢀvoltageꢀratingsꢀofꢀ10ꢀV,ꢀ16ꢀV,ꢀ25ꢀV,ꢀ50ꢀV,ꢀ100ꢀV,ꢀ200ꢀV,ꢀandꢀ

250ꢀV

•ꢀ Capacitanceꢀofferingsꢀrangingꢀfromꢀ0.5ꢀpFꢀupꢀtoꢀ0.47ꢀμFꢀ

•ꢀ Availableꢀcapacitanceꢀtolerancesꢀofꢀ±0.10ꢀpF,ꢀ±0.25ꢀpF,ꢀ

±0.5ꢀpF,ꢀ±1%,ꢀ±2%,ꢀ±5%,ꢀ±10%,ꢀandꢀ±20%ꢀꢀ

• No piezoelectric noise

• Extremely low ESR and ESL

•ꢀ Highꢀthermalꢀstability

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•ꢀ Highꢀrippleꢀcurrentꢀcapability

Ordering Information

C

1206

C

104

J

3

G

A

C

TU

Rated

Voltage Dielectric

(VDC)

Termination

Finish³

Case Size Speciﬁcation/

(L" x W")

Capacitance

Codeꢀ(pF)

Capacitance

Tolerance²

FailureꢀRate/

Design

Packaging/

Grade (C-Spec)

Ceramic

Series¹

0201

0402

0603

0805

1206

1210

1808

1812

1825

2220

2225

C =

Standard

Twoꢀsigniﬁcantꢀdigitsꢀ Bꢀ=ꢀ±0.10ꢀpF

andꢀnumberꢀofꢀzeros. Cꢀ=ꢀ±0.25ꢀpF

Useꢀ9ꢀforꢀ1.0ꢀ–ꢀ9.9ꢀpF Dꢀ=ꢀ±0.5ꢀpF

Useꢀ8ꢀforꢀ0.5ꢀ–ꢀ.99ꢀpF Fꢀ=ꢀ±1%

8 = 10

4 = 16

3 = 25

5 = 50

1 = 100

2 = 200

A = 250

G = C0G

A = N/A

Cꢀ=ꢀ100%ꢀMatteꢀSn

See

“Packagingꢀ

C-Spec

Orderingꢀ

Options

Table”

e.g.,ꢀ2.2ꢀpFꢀ=ꢀ229

e.g.,ꢀ0.5ꢀpFꢀ=ꢀ508

Gꢀ=ꢀ±2%

Jꢀ=ꢀ±5%

Kꢀ=ꢀ±10%

Mꢀ=ꢀ±20%

¹Flexible termination option is available. Please see FT-CAP product bulletin C1062_C0G_FT-CAP_SMD

²Additional capacitance tolerance offerings may be available. Contact KEMET for details.

³Additional termination ﬁnish options may be available. Contact KEMET for details.

One world. One KEMET

C1003_C0G • 6/7/2018

1

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Packaging C-Spec Ordering Options Table

Packaging/Grade

Packaging Type¹

Ordering Code (C-Spec)

BulkꢀBag/Unmarked

Notꢀrequiredꢀ(Blank)

7" Reel/Unmarked

TU

7411 (EIA 0603 and smaller case sizes)

13" Reel/Unmarked

7210ꢀ(EIAꢀ0805ꢀandꢀlargerꢀcaseꢀsizes)

7"ꢀReel/Unmarked/2ꢀmmꢀpitch²

13"ꢀReel/Unmarked/2ꢀmmꢀpitch²

7081

7082

¹Default packaging is “Bulk Bag”. An ordering code C-Spec is not required for “Bulk Bag” packaging.

¹The terms “Marked” and “Unmarked” pertain to laser marking option of capacitors. All packaging options labeled as “Unmarked” will contain

capacitors that have not been laser marked. The option to laser mark is not available on these devices. For more information see “Capacitor Marking”.

²The 2 mm pitch option allows for double the packaging quantity of capacitors on a given reel size. This option is limited to EIA 0603 (1608 metric) case

size devices. For more information regarding 2 mm pitch option see “Tape & Reel Packaging Information”.

Beneﬁts cont'd

•ꢀ PreferredꢀcapacitanceꢀsolutionꢀatꢀlineꢀfrequenciesꢀandꢀintoꢀtheꢀMHzꢀrange

•ꢀ NoꢀcapacitanceꢀchangeꢀwithꢀrespectꢀtoꢀappliedꢀratedꢀDCꢀvoltage

•ꢀ Negligibleꢀcapacitanceꢀchangeꢀwithꢀrespectꢀtoꢀtemperatureꢀfromꢀ−55°Cꢀtoꢀ+125°C

•ꢀ Noꢀcapacitanceꢀdecayꢀwithꢀtime

•ꢀ Non-polarꢀdevice,ꢀminimizingꢀinstallationꢀconcerns

•ꢀ 100%ꢀpureꢀmatteꢀtin-platedꢀterminationꢀﬁnishꢀallowingꢀforꢀexcellentꢀsolderability

•ꢀ SnPbꢀplatedꢀterminationꢀﬁnishꢀoptionꢀavailableꢀuponꢀrequestꢀ(5%ꢀPbꢀminimum)

Applications

Typicalꢀapplicationsꢀincludeꢀcriticalꢀtiming,ꢀtuning,ꢀcircuitsꢀrequiringꢀlowꢀloss,ꢀcircuitsꢀwithꢀpulse,ꢀhighꢀcurrent,ꢀdecoupling,ꢀ

bypass,ꢀﬁltering,ꢀtransientꢀvoltageꢀsuppression,ꢀblockingꢀandꢀenergyꢀstorage.

Qualiﬁcation/Certiﬁcation

CommercialꢀGradeꢀproductsꢀareꢀsubjectꢀtoꢀinternalꢀqualiﬁcation.ꢀDetailsꢀregardingꢀtestꢀmethodsꢀandꢀconditionsꢀareꢀ

referenced in Table 4, Performance and Reliability.

Environmental Compliance

Leadꢀ(Pb)-free,ꢀRoHS,ꢀandꢀREACHꢀcompliantꢀwithoutꢀexemptions.

C1003_C0G • 6/7/2018

2

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Dimensions – Millimeters (Inches)

L

W

T

B

S

EIA Size

Code

Metric Size

Code

L

W

Width

T

B

Mounting

Technique

Separation

Minimum

Length

Thickness

Bandwidth

0.60 (0.024)

±0.03 (0.001)

1.00 (0.040)

±0.05 (0.002)

1.60 (0.063)

±0.15 (0.006)

2.00 (0.079)

±0.20 (0.008)

3.20 (0.126)

±0.20 (0.008)

3.20 (0.126)

±0.20 (0.008)

4.70 (0.185)

±0.50 (0.020)

4.50 (0.177)

±0.30 (0.012)

4.50 (0.177)

±0.30 (0.012)

5.70 (0.224)

±0.40 (0.016)

5.60 (0.220)

±0.40 (0.016)

0.30 (0.012)

±0.03 (0.001)

0.50 (0.020)

±0.05 (0.002)

0.80 (0.032)

±0.15 (0.006)

1.25 (0.049)

±0.20 (0.008)

1.60 (0.063)

±0.20 (0.008)

2.50 (0.098)

±0.20 (0.008)

2.00 (0.079)

±0.20 (0.008)

3.20 (0.126)

±0.30 (0.012)

6.40 (0.252)

±0.40 (0.016)

5.00 (0.197)

±0.40 (0.016)

6.40 (0.248)

±0.40 (0.016)

0.15 (0.006)

±0.05 (0.002)

0.30 (0.012)

±0.10 (0.004)

0.35 (0.014)

±0.15 (0.006)

0.50 (0.02)

±0.25 (0.010)

0.50 (0.02)

±0.25 (0.010)

0.50 (0.02)

±0.25 (0.010)

0.60 (0.024)

±0.35 (0.014)

0.60 (0.024)

±0.35 (0.014)

0.60 (0.024)

±0.35 (0.014)

0.60 (0.024)

±0.35 (0.014)

0.60 (0.024)

±0.35 (0.014)

0201

0402

0603

0805

1206

1210

1808

1812

1825

2220

2225

0603

1005

1608

2012

3216

3225

4520

4532

4564

5650

5664

N/A

SolderꢀReﬂowꢀ

Only

0.30 (0.012)

0.70 (0.028)

0.75 (0.030)

Solder Wave or

SolderꢀReﬂow

See Table 2 for

Thickness

N/A

SolderꢀReﬂowꢀ

Only

C1003_C0G • 6/7/2018

3

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Electrical Parameters/Characteristics

Item

Parameters/Characteristics

OperatingꢀTemperatureꢀRange

−55°Cꢀtoꢀ+125°Cꢀꢀ

±30 ppm/ºC

0%

CapacitanceꢀChangeꢀwithꢀReferenceꢀto

+25°Cꢀandꢀ0ꢀVDCꢀAppliedꢀ(TCC)

AgingꢀRateꢀ(Maximumꢀ%ꢀCapacitanceꢀLoss/DecadeꢀHour)

¹DielectricꢀWithstandingꢀVoltageꢀ(DWV)

250%ꢀofꢀratedꢀvoltage

(5±1ꢀsecondsꢀandꢀcharge/dischargeꢀnotꢀexceedingꢀ50ꢀmA)

²DissipationꢀFactorꢀ(DF)ꢀMaximumꢀLimitꢀatꢀ25ºC

0.1%

1,000ꢀmegohmꢀmicrofaradsꢀorꢀ100ꢀGΩ

(Ratedꢀvoltageꢀappliedꢀforꢀ120±5ꢀsecondsꢀatꢀ25°C)

³InsulationꢀResistanceꢀ(IR)ꢀLimitꢀatꢀ25°C

¹DWV is the voltage a capacitor can withstand (survive) for a short period of time. It exceeds the nominal and continuous working voltage of the

capacitor.

²Capacitance and dissipation factor (DF) measured under the following conditions:

1 MHz ±100 kHz and 1.0 Vrms ±0.2 V if capacitance ≤ 1,000 pF

1 kHz ±50 Hz and 1.0 Vrms ±0.2 V if capacitance > 1,000 pF

³To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits.

Capacitance and Dissipation Factor (DF) measured under the following conditions:

Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 and Agilent E4980 have a feature known

as Automatic Level Control (ALC). The ALC feature should be switched to "ON."

Post Environmental Limits

High Temperature Life, Biased Humidity, Moisture Resistance

Rated DC

Capacitance DissipationꢀFactorꢀ Capacitance

Insulationꢀ

Dielectric

C0G

Voltage

Value

(Maximumꢀ%)ꢀ

Shiftꢀ

Resistance

10%ꢀofꢀInitialꢀ

All

0.5

0.3%ꢀorꢀ±0.25ꢀpFꢀ

Limit

C1003_C0G • 6/7/2018

4

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 1A – Capacitance Range/Selection Waterfall (0201 – 1206 Case Sizes)

Case Size/

Series

C0201C

C0402C

C0603C

C0805C

C1206C

Cap

Code

Voltage Code

8

4

3

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

Cap

Rated Voltage (VDC)

Capacitance

Tolerance

Product Availability and Chip Thickness Codes

See Table 2 for Chip Thickness Dimensions

0.50ꢀ&ꢀ0.75ꢀpF 508ꢀ&ꢀ758

0.75ꢀpF 758

1.0ꢀ–ꢀ9.1ꢀpF* 109ꢀ–ꢀ919* B

B

C

D

BB BB BB BB

CF CF CF CF CF CF CF DN DN DN DN DN DN DN

CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

CF CF CF CF CF CF CF DM DM DM DM DN DN DN EB EB EB EB EB EB EB

CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

1.1ꢀpF

1.2ꢀpF

1.3ꢀpF

1.5ꢀpF

1.6ꢀpF

1.8ꢀpF

2.0ꢀpF

2.2ꢀpF

2.4ꢀpF

2.7ꢀpF

3.0ꢀpF

3.3ꢀpF

3.6ꢀpF

3.9ꢀpF

4.3ꢀpF

4.7ꢀpF

5.1ꢀpF

5.6ꢀpF

6.2ꢀpF

6.8ꢀpF

7.5ꢀpF

8.2ꢀpF

9.1ꢀpF

10ꢀpF

11ꢀpF

12ꢀpF

13ꢀpF

15ꢀpF

16ꢀpF

18ꢀpF

20ꢀpF

22ꢀpF

24ꢀpF

27ꢀpF

30ꢀpF

33ꢀpF

36ꢀpF

39ꢀpF

43ꢀpF

47ꢀpF

51ꢀpF

56ꢀpF

62ꢀpF

68ꢀpF

75ꢀpF

82ꢀpF

91ꢀpF

100ꢀpF

119

129

139

159

169

189

209

229

249

279

309

339

369

399

439

479

519

569

629

689

759

829

919

100

110

120

130

150

160

180

200

220

240

270

300

330

360

390

430

470

510

560

620

680

750

820

910

101

B

F

G

J

K

M AB¹ AB¹ AB¹ BB BB BB BB

BB BB BB BB

M AB² AB² AB² BB BB BB BB

BB BB BB BB

M AB² AB² AB² BB BB BB BB

BB BB BB BB

M AB² AB² AB² BB BB BB BB

BB BB BB BB

M AB² AB² AB² BB BB BB BB

BB BB BB BB

M AB² AB² AB² BB BB BB BB

BB BB BB BB

M AB² AB² AB² BB BB BB BB

BB BB BB BB

M AB² AB² AB² BB BB BB BB

BB BB BB BB

M AB² AB² AB² BB BB BB BB

BB BB BB BB

M AB² AB² AB² BB BB BB BB

BB BB BB BB

M AB² AB² AB² BB BB BB BB

BB BB BB BB

M AB² AB² AB² BB BB BB BB

BB BB BB BB

M AB² AB² AB² BB BB BB BB BB BB BB CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

M

Rated Voltage (VDC)

Voltage Code

8

4

3

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

Cap

Cap Code

Case Size/Series

C0201C

C0402C

C0603C

C0805C

C1206C

*Capacitance range Includes E24 decade values only. (i.e., 10, 11, 12, 13, 15, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 43, 47, 51, 56, 62, 68, 75, 82, and 91).

xx¹ Available only in D, J, K, M tolerance

xx² Available only in J, K, M tolerance.

These products are protected under US Patents 7,172,985 & 7,670,981, other patents pending, and any foreign counterparts.

C1003_C0G • 6/7/2018

5

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 1A – Capacitance Range/Selection Waterfall (0201 – 1206 Case Sizes) cont'd

Case Size/

Series

C0201C

C0402C

C0603C

C0805C

C1206C

Cap

Code

Voltage Code

8

4

3

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

Cap

Rated Voltage (VDC)

Capacitance

Tolerance

Product Availability and Chip Thickness Codes

See Table 2 for Chip Thickness Dimensions

110ꢀ–ꢀ180ꢀpF* 111ꢀ–ꢀ181*

200ꢀ–ꢀ270ꢀpF* 201ꢀ–ꢀ271*

F

G

J

K

M

BB BB BB BB BB BB BB CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

BB BB BB BB BB BD BD CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

300ꢀpF

330ꢀpF

301

331

361

391

431

471

511

561

621

681

751

821

911

102

112

122

132

152

162

182

202

222

242

272

302

332

362

392

432

472

512

562

622

682

752

822

912

103

123

153

183

223

273

333

393

473

563

683

823

104

360ꢀpF

390ꢀpF

430ꢀpF

470ꢀpF

BB BB BB BB BB

BB BB BB BB

BB BB BB

CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

CF CF CF CF CF CF CF DN DN DN DN DN DP DP EB EB EB EB EB EB EB

CF CF CF CF CF CF CF DN DN DN DN DN DN DN EB EB EB EB EB EB EB

CF CF CF CF CF CF CF DN DN DN DN DP DP DP EB EB EB EB EB EB EB

CF CF CF CF CF CH CH DN DN DN DN DN DN DN EB EB EB EB EB EB EB

CF CF CF CF CF CH CH DP DP DP DP DP DN DN EB EB EB EB EC EC EC

CF CF CF CF CF CH CH DP DP DP DP DP DN DN EB EB EB EB ED EC EC

CF CF CF CF CF CH CH DP DP DP DP DP DN DN EB EB EB EB ED ED ED

CF CF CF CF CF CH CH DN DN DN DN DN DN DN EB EB EB EB ED ED ED

CF CF CF CF CF CH CH DN DN DN DN DN DN DN EB EB EB EB EE EE EE

510ꢀpF

560ꢀpF

620ꢀpF

680ꢀpF

750ꢀpF

820ꢀpF

910ꢀpF

1,000ꢀpF

1,100ꢀpF

1,200ꢀpF

1,300ꢀpF

1,500ꢀpF

1,600ꢀpF

1,800ꢀpF

2,000ꢀpF

2,200ꢀpF

2,400ꢀpF

2,700ꢀpF

3,000ꢀpF

3,300ꢀpF

3,600ꢀpF

3,900ꢀpF

4,300ꢀpF

4,700ꢀpF

5,100ꢀpF

5,600ꢀpF

6,200ꢀpF

6,800ꢀpF

7,500ꢀpF

8,200ꢀpF

9,100ꢀpF

10,000ꢀpF

12,000ꢀpF

15,000ꢀpF

18,000ꢀpF

22,000ꢀpF

27,000ꢀpF

33,000ꢀpF

39,000ꢀpF

47,000ꢀpF

56,000ꢀpF

68,000ꢀpF

82,000ꢀpF

0.10ꢀµF

CF CF CF CF CF

CF CF CF CF

CF CF CF

DN DN DN DN DN DN DN EB EB EB EB EC EC EC

DP DP DP DP DN DN DN EC EC EC EC EC EB EB

DP DP DP DP DN DN DN EC EC EC EC EE EB EB

DP DP DP DP DN DP DP EC EC EC EC EE EB EB

DE DE DE DE DN DP DP EC EC EC EC EF EB EB

DE DE DE DE DN DP DP EC EC EC EC EC EB EB

DE DE DE DE DN DP DP ED ED ED ED ED EB EB

DN DN DN DN DN DP DP ED ED ED ED ED EB EB

DN DN DN DN DN DG DG EB EB EB EB EB EB EB

DN DN DN DN DN DG DG EC EC EC EC EB EC EC

CF CF CF

DN DN DN DN DN

DN DN DN DN DP

DN DN DN DN DE

DN DN DN DP DG

DN DN DN DP

DP DP DP DF

DF DF DF

EC EC EC EC EB EC EC

ED ED ED ED EB EC EC

EB EB EB EB EB ED ED

EB EB EB EB EB EF EF

EB EB EB EB EB EH EH

EB EB EB EB EC EH EH

EB EB EB EB EE

DG DG DG

EB EB EB EB EE

DG DG DG

EC EC EC EE EH

DG DG DG

EC EC EC EE EH

ED ED ED EF

EF EF EF EH

EH EH EH EH

EH EH EH

Rated Voltage (VDC)

Voltage Code

8

4

3

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

Cap

Cap Code

Case Size/Series

C0201C

C0402C

C0603C

C0805C

C1206C

*Capacitance range Includes E24 decade values only. (i.e., 10, 11, 12, 13, 15, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 43, 47, 51, 56, 62, 68, 75, 82, and 91).

xx¹ Available only in D, J, K, M tolerance

xx² Available only in J, K, M tolerance.

These products are protected under US Patents 7,172,985 & 7,670,981, other patents pending, and any foreign counterparts.

C1003_C0G • 6/7/2018

6

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 1B – Capacitance Range/Selection Waterfall (1210 – 2225 Case Sizes)

Case Size/

Series

C1210C

C1808C

C1812C

C1825C

C2220C

C2225C

Cap

Code

Voltage Code

8

4

3

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

Cap

Rated Voltage (VDC)

Capacitance

Tolerance

B C D

Product Availability and Chip Thickness Codes

See Table 2 for Chip Thickness Dimensions

1.0ꢀ–ꢀ9.1ꢀpF*

10ꢀ–ꢀ91ꢀpF*

100ꢀ–ꢀ300ꢀpF*

330ꢀ–ꢀ430ꢀpF*

470ꢀ–ꢀ910ꢀpF*

1,000ꢀpF

1,100ꢀpF

109ꢀ–ꢀ919*

100ꢀ–ꢀ910*

101ꢀ–ꢀ301*

331ꢀ–ꢀ431*

471ꢀ–ꢀ911*

102

FB FB FB FB FB FB FB

F

G

J

K M FB FB FB FB FB FB FB

K M FB FB FB FB FB FB FB LF LF LF LF

K M FB FB FB FB FB FB FB LF LF LF LF GB GB GB GB

K M FB FB FB FB FB FC FC LF LF LF LF GB GB GB GB

K M FB FB FB FB FB FE FE LF LF LF LF GB GB GB GB

K M FB FB FB FB FC FE FE LF LF LF LF GB GB GB GB

K M FB FB FB FB FC FG FG LF LF LF LF GB GB GB GB

K M FB FB FB FB FC FC FC LF LF LF LF

112

122

132

152

162

182

202

222

242

272

302

332

362

392

432

472

512

562

622

682

752

822

912

103

123

153

183

223

273

333

393

473

1,200ꢀpF

1,300ꢀpF

1,500ꢀpF

1,600ꢀpF

1,800ꢀpF

2,000ꢀpF

2,200ꢀpF

2,400ꢀpF

2,700ꢀpF

3,000ꢀpF

3,300ꢀpF

3,600ꢀpF

3,900ꢀpF

4,300ꢀpF

4,700ꢀpF

5,100ꢀpF

5,600ꢀpF

6,200ꢀpF

6,800ꢀpF

7,500ꢀpF

8,200ꢀpF

9,100ꢀpF

10,000ꢀpF

12,000ꢀpF

15,000ꢀpF

18,000ꢀpF

22,000ꢀpF

27,000ꢀpF

33,000ꢀpF

39,000ꢀpF

47,000ꢀpF

56,000ꢀpF

68,000ꢀpF

82,000ꢀpF

0.10ꢀµF

K M FB FB FB FB FC FC FC LF LF LF LF GB GB GB GB

K M FB FB FB FB FC FF FF LF LF

K M FB FB FB FB FF FF FF LF LF

K M FF FF FF FF FG FG FG LF LF

K M FB FB FB FB FG FG FG

K M FB FB FB FB FG FB FB

K M FC FC FC FC FC FB FB

K M FE FE FE FE FE FB FB

K M FF FF FF FF FF FB FB

K M FG FG FG FG FB FB FB

K M FG FG FG FG FB FC FC

K M FB FB FB FB FB FC FC

K M FB FB FB FB FB FF FF

K M FB FB FB FB FB FG FG

K M FB FB FB FB FB FH FH

K M FB FB FB FB FE FH FH

K M FB FB FB FB FE FJ FJ

K M FB FB FB FB FF

GB GB GB GB

GB GB GB GB HB HB HB HB

GB GB GD GD HB HB HB HB

GB GB GH GH HB HB HB HB

KE KE KE KE

KE KE

GB GB GJ GJ HB HB HB HB JE JE JB

GB GH GB GB HB HB HB HB JE JE JB

GB GH GB GB HB HB HE HE JE JE JB

GB GG GB GB HB HB HE HE JE JE JB

GB GB GB GB HB HB

GB GB GB GB HB HE

GB GB GB GB HB HG

GB GB GB GB

GB GB GD GD

GB GB GK GK

GB GB GM GM

GB GD GM GM

GB GH

JE JE JB

JE JB JB

JB JB JB

JB JB JD

JB JB JG

JB JD JG

JB JD JL

JB JF

KE KE

KE

F G

563

683

823

104

124

154

184

224

274

334

394

474

F

G

K M FB FB FB FC FG

K M FC FC FC FF FH

K M FE FE FE FG FM

K M FG FG FG FH

K M FH FH FH FM

K M FJ FJ FJ

K M FK FK FK

K M

0.12ꢀµF

0.15ꢀµF

0.18ꢀµF

0.22ꢀµF

0.27ꢀµF

0.33ꢀµF

0.39ꢀµF

0.47ꢀµF

GD GN

GH

GK

K M

JD JG

JG

Rated Voltage (VDC)

Voltage Code

Cap

Code

8

4

3

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

Cap

Case Size/Series

C1210C

C1808C

C1812C

C1825C

C2220C

C2225C

*Capacitance range Includes E24 decade values only. (i.e., 10, 11, 12, 13, 15, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 43, 47, 51, 56, 62, 68, 75, 82, and 91).

These products are protected under US Patents 7,172,985 & 7,670,981, other patents pending, and any foreign counterparts.

C1003_C0G • 6/7/2018

7

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 2A – Chip Thickness/Tape & Reel Packaging Quantities

Paper Quantity¹

7" Reel 13" Reel

Plastic Quantity

Thickness Case Thickness ±

Code

Size¹Range (mm)

7" Reel

13" Reel

AB

BB

BD

CF

CH

DM

DN

DP

DE

DF

DG

EB

EC

ED

EE

EF

0201

0402

0603

0805

1206

1210

1706

1808

1812

1825

2220

2225

0.30±0.03

0.50±0.05

0.55±0.05

0.80±0.07

0.85±0.07

0.70±0.20

0.78±0.10

0.90±0.10

1.00±0.10

1.10±0.10

1.25±0.15

0.78±0.10

0.90±0.10

1.00±0.10

1.10±0.10

1.20±0.15

1.60±0.20

0.78±0.10

0.90±0.10

1.00±0.10

1.10±0.10

1.25±0.15

1.55±0.15

1.70±0.20

1.85±0.20

2.10±0.20

1.00±0.15

1.00±0.10

1.25±0.15

1.40±0.15

1.55±0.10

1.60±0.20

1.70±0.15

1.70±0.20

2.00±0.20

1.10±0.15

1.40±0.15

1.60±0.20

1.00±0.15

1.30±0.15

1.40±0.15

1.50±0.15

1.70±0.15

2.00±0.20

1.40±0.15

15,000

10,000

4,000

0

50,000

15,000

10,000

15,000

0

2,500

4,000

2,500

2,000

4,000

2,500

2,000

4,000

2,500

1,000

500

10,000

8,000

10,000

8,000

10,000

4,000

2,000

4,000

2,000

4,000

0

4,000

0

10,000

0

EH

FB

FC

FE

FF

FG

FH

FM

FJ

FK

NC

LF

GB

GD

GH

GG

GK

GJ

GN

GM

HB

HE

HG

JB

JD

JE

1,000

500

JF

JG

JL

0

KE

1,000

7" Reel

13" Reel

7" Reel

13" Reel

Thickness

Code

Case

Size¹

Thickness ±

Range (mm)

Paper Quantity¹

Plastic Quantity

Package quantity based on ﬁnished chip thickness speciﬁcations.

¹If ordering using the 2 mm Tape and Reel pitch option, the packaging quantity outlined in the table above will be doubled. This option is limited to EIA

0603 (1608 metric) case size devices. For more information regarding 2 mm pitch option see “Tape & Reel Packaging Information”.

C1003_C0G • 6/7/2018

8

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 2B – Bulk Packaging Quantities

Loose Packaging

BulkꢀBagꢀ(default)

N/A²

Packaging Type

PackagingꢀC-Spec¹

Case Size

Packaging Quantities (pieces/unit packaging)

EIA (in)

Metric (mm)

Minimum

Maximum

0402

0603

0805

1206

1210

1808

1812

1825

2220

2225

1005

1608

2012

3216

3225

4520

4532

4564

5650

5664

50,000

1

20,000

¹The "Packaging C-Spec" is a 4 to 8 digit code which identiﬁes the packaging type and/or product grade. When ordering, the proper code must be

included in the 15th through 22nd character positions of the ordering code. See "Ordering Information" section of this document for further details.

Commercial Grade product ordered without a packaging C-Spec will default to our standard "Bulk Bag" packaging. Contact KEMET if you require a bulk

bag packaging option for Automotive Grade products.

²A packaging C-Spec (see note 1 above) is not required for "Bulk Bag" packaging (excluding Anti-Static Bulk Bag and Automotive Grade products). The

15th through 22nd character positions of the ordering code should be left blank. All product ordered without a packaging C-Spec will default to our

standard "Bulk Bag" packaging.

C1003_C0G • 6/7/2018

9

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 3 – Chip Capacitor Land Pattern Design Recommendations per IPC–7351

Density Level A:

Maximum (Most)

Land Protrusion (mm)

Density Level B:

Median (Nominal)

Land Protrusion (mm)

Density Level C:

Minimum (Least)

Land Protrusion (mm)

EIA

Size

Code

Metric

Size

Code

C

Y

X

V1

V2

C

Y

X

V1

V2

C

Y

X

V1

V2

0201

0402

0603

0805

1206

1210

1210¹

1808

1812

1825

2220

2225

0603

1005

1608

2012

3216

3225

4520

4532

4564

5650

5664

0.38

0.56

0.52

1.80

1.00

0.33

0.46

0.42

1.50

0.80

0.28

0.36

0.32

1.20

0.60

0.50

0.90

1.00

1.60

1.50

2.30

2.15

2.75

2.70

0.72

1.15

1.35

1.60

1.75

1.60

1.70

0.72

1.10

1.55

1.90

2.80

2.90

2.30

3.60

6.90

5.50

6.90

2.20

4.00

4.40

5.60

5.65

5.60

7.40

6.90

8.20

8.10

1.20

2.10

2.60

2.90

3.80

3.90

3.30

4.60

7.90

6.50

7.90

0.45

0.80

0.90

1.50

1.40

2.20

2.05

2.65

2.60

0.62

0.95

1.15

1.40

1.55

1.40

1.50

0.62

1.00

1.45

1.80

2.70

2.80

2.20

3.50

6.80

5.40

6.80

1.90

3.10

3.50

4.70

6.50

6.00

7.30

7.20

1.00

1.50

2.00

2.30

3.20

3.30

2.70

4.00

7.30

5.90

7.30

0.40

0.60

0.75

1.40

1.30

2.10

1.95

2.55

2.50

0.52

0.75

0.95

1.20

1.35

1.20

1.30

0.52

0.90

1.35

1.70

2.60

2.70

2.10

3.40

6.70

5.30

6.70

1.60

2.40

2.80

4.00

5.80

5.30

6.60

6.50

0.80

1.20

1.70

2.00

2.90

3.00

2.40

3.70

7.00

5.60

7.00

¹Only for capacitance values ≥ 22 µF

Density Level A: For low-density product applications. Recommended for wave solder applications and provides a wider process window for reﬂow

solder processes. KEMET only recommends wave soldering of EIA 0603, 0805 and 1206 case sizes.

Density Level B: For products with a moderate level of component density. Provides a robust solder attachment condition for reﬂow solder processes.

Density Level C: For high component density product applications. Before adapting the minimum land pattern variations the user should perform

qualiﬁcation testing based on the conditions outlined in IPC Standard 7351 (IPC–7351).

Image below based on Density Level B for an EIA 1210 case size.

V1

Y

V2

X

C

Grid Placement Courtyard

C1003_C0G • 6/7/2018

10

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Soldering Process

Recommended Soldering Technique:

ꢀ •ꢀSolderꢀwaveꢀorꢀsolderꢀreﬂowꢀforꢀEIAꢀcaseꢀsizesꢀ0603,ꢀ0805ꢀandꢀ1206

ꢀ •ꢀAllꢀotherꢀEIAꢀcaseꢀsizesꢀareꢀlimitedꢀtoꢀsolderꢀreﬂowꢀonly

Recommended Reﬂow Soldering Proﬁle:

KEMET’sꢀfamiliesꢀofꢀsurfaceꢀmountꢀmultilayerꢀceramicꢀcapacitorsꢀ(SMDꢀMLCCs)ꢀareꢀcompatibleꢀwithꢀwaveꢀ(singleꢀorꢀdual),ꢀ

convection,ꢀIRꢀorꢀvaporꢀphaseꢀreﬂowꢀtechniques.ꢀPreheatingꢀofꢀtheseꢀcomponentsꢀisꢀrecommendedꢀtoꢀavoidꢀextremeꢀthermalꢀ

stress.ꢀKEMET’sꢀrecommendedꢀproﬁleꢀconditionsꢀforꢀconvectionꢀandꢀIRꢀreﬂowꢀreﬂectꢀtheꢀproﬁleꢀconditionsꢀofꢀtheꢀIPC/

J-STD-020ꢀstandardꢀforꢀmoistureꢀsensitivityꢀtesting.ꢀTheseꢀdevicesꢀcanꢀsafelyꢀwithstandꢀaꢀmaximumꢀofꢀthreeꢀreﬂowꢀpassesꢀ

atꢀtheseꢀconditions.

Termination Finish

ꢀ_ꢂ

ꢀ_L

t_ꢂ

Proﬁle Feature

Maꢁimum ꢃamp ꢄp ꢃate ꢅ ꢆꢇCꢈsecond

Maꢁimum ꢃamp Doꢉn ꢃate ꢅ ꢊꢇCꢈsecond

SnPb

100%ꢀMatteꢀSn

t_L

Preheat/Soak

TemperatureꢀMinimumꢀ(T_Smin

)

100°C

150°C

200°C

ꢀ_smaꢁ

ꢀ_smin

TemperatureꢀMaximumꢀ(T_Smax

)

Time (t_S) from T_Sminto T_Smax

60 – 120 seconds

3°C/secondꢀ

maximum

60 – 120 seconds

3°C/secondꢀ

maximum

t_s

Ramp-Up Rate (T_Lto T_P)

25

LiquidousꢀTemperatureꢀ(T_L)

TimeꢀAboveꢀLiquidousꢀ(t_L)

PeakꢀTemperatureꢀ(T_P)

183°C

60 – 150 seconds

235°C

217°C

60 – 150 seconds

260°C

25ꢇC to ꢂeaꢋ

Tiꢀe

TimeꢀWithinꢀ5°CꢀofꢀMaximumꢀ

20 seconds

maximum

30 seconds

maximum

PeakꢀTemperatureꢀ(t_P)

6°C/secondꢀ

maximum

6°C/secondꢀ

maximum

Ramp-Down Rate (T_Pto T_L)

Timeꢀ25°CꢀtoꢀPeakꢀ

Temperature

6ꢀminutes

maximum

8ꢀminutes

maximum

Note 1: All temperatures refer to the center of the package, measured on the

capacitor body surface that is facing up during assembly reﬂow.

C1003_C0G • 6/7/2018

11

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Table 4 – Performance & Reliability: Test Methods and Conditions

Stress

Reference

Test or Inspection Method

TerminalꢀStrength

JIS–C–6429

Appendixꢀ1,ꢀNote:ꢀForceꢀofꢀ1.8ꢀkgꢀforꢀ60ꢀseconds.

Appendixꢀ2,ꢀNote:ꢀStandardꢀterminationꢀsystemꢀ–ꢀ2.0ꢀmmꢀ(minimum)ꢀforꢀallꢀexceptꢀ3ꢀmmꢀ

forꢀC0G.ꢀFlexibleꢀterminationꢀsystemꢀ–ꢀ3.0ꢀmmꢀ(minimum).

BoardꢀFlex

JIS–C–6429

Magniﬁcationꢀ50ꢀX.ꢀConditions:

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀa)ꢀMethodꢀB,ꢀ4ꢀhoursꢀatꢀ155°C,ꢀdryꢀheatꢀatꢀ235°C

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀb)ꢀMethodꢀBꢀatꢀ215°Cꢀcategoryꢀ3

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀc)ꢀMethodꢀD,ꢀcategoryꢀ3ꢀatꢀ260°C

Solderability

J–STD–002

1,000ꢀCyclesꢀ(−55°Cꢀtoꢀ+125°C).ꢀMeasurementꢀatꢀ24ꢀhoursꢀ+/−ꢀ4ꢀhoursꢀafterꢀtestꢀ

conclusion.

LoadꢀHumidity:ꢀ1,000ꢀhoursꢀ85°C/85%ꢀRHꢀandꢀratedꢀvoltage.ꢀAddꢀ100ꢀKꢀohmꢀresistor.ꢀ

Measurementꢀatꢀ24ꢀhoursꢀ+/−ꢀ4ꢀhoursꢀafterꢀtestꢀconclusion.

LowꢀVoltꢀHumidity:ꢀ1,000ꢀhoursꢀ85°C/85%ꢀRHꢀandꢀ1.5ꢀV.ꢀAddꢀ100ꢀKꢀohmꢀresistor.ꢀ

Measurementꢀatꢀ24ꢀhoursꢀ+/−ꢀ4ꢀhoursꢀafterꢀtestꢀconclusion.

TemperatureꢀCycling

BiasedꢀHumidity

JESD22ꢀMethodꢀJA–104

MIL–STD–202ꢀMethodꢀ

103

MIL–STD–202ꢀMethodꢀ

tꢀ=ꢀ24ꢀhours/cycle.ꢀStepsꢀ7aꢀandꢀ7bꢀnotꢀrequired.ꢀ

MoistureꢀResistance

ThermalꢀShock

Measurementꢀatꢀ24ꢀhoursꢀ+/−ꢀ4ꢀhoursꢀafterꢀtestꢀconclusion.

106

MIL–STD–202ꢀMethodꢀ

−55°C/+125°C.ꢀNote:ꢀNumberꢀofꢀcyclesꢀrequiredꢀ–ꢀ300,ꢀmaximumꢀtransferꢀtimeꢀ–ꢀ20ꢀ

seconds,ꢀdwellꢀtimeꢀ–ꢀ15ꢀminutes.ꢀAirꢀ–ꢀAir.

107

MIL–STD–202ꢀMethodꢀ

108

HighꢀTemperatureꢀLife

1,000ꢀhoursꢀatꢀ125°Cꢀ(85°CꢀforꢀX5R,ꢀZ5UꢀandꢀY5V)ꢀwithꢀ2ꢀXꢀratedꢀvoltageꢀapplied.

/EIA–198

MIL–STD–202ꢀMethodꢀ

108

StorageꢀLife

Vibration

150°C,ꢀ0ꢀVDCꢀforꢀ1,000ꢀhours.

5ꢀg'sꢀforꢀ20ꢀminutes,ꢀ12ꢀcyclesꢀeachꢀofꢀ3ꢀorientations.ꢀNote:ꢀUseꢀ8"ꢀXꢀ5"ꢀPCBꢀ0.031"ꢀthickꢀ

7ꢀsecureꢀpointsꢀonꢀoneꢀlongꢀsideꢀandꢀ2ꢀsecureꢀpointsꢀatꢀcornersꢀofꢀoppositeꢀsides.ꢀPartsꢀ

mountedꢀwithinꢀ2"ꢀfromꢀanyꢀsecureꢀpoint.ꢀTestꢀfromꢀ10ꢀ–ꢀ2,000ꢀHz

MIL–STD–202ꢀMethodꢀ

204

MIL–STD–202ꢀMethodꢀ

MechanicalꢀShock

Figureꢀ1ꢀofꢀMethodꢀ213,ꢀConditionꢀF.

213

MIL–STD–202ꢀMethodꢀ

215

Resistance to Solvents

Addꢀaqueousꢀwashꢀchemical,ꢀOKEMꢀCleanꢀorꢀequivalent.

Storage and Handling

Ceramicꢀchipꢀcapacitorsꢀshouldꢀbeꢀstoredꢀinꢀnormalꢀworkingꢀenvironments.ꢀWhileꢀtheꢀchipsꢀthemselvesꢀareꢀquiteꢀrobustꢀinꢀ

otherꢀenvironments,ꢀsolderabilityꢀwillꢀbeꢀdegradedꢀbyꢀexposureꢀtoꢀhighꢀtemperatures,ꢀhighꢀhumidity,ꢀcorrosiveꢀatmospheres,ꢀ

andꢀlongꢀtermꢀstorage.ꢀInꢀaddition,ꢀpackagingꢀmaterialsꢀwillꢀbeꢀdegradedꢀbyꢀhighꢀtemperature–reelsꢀmayꢀsoftenꢀorꢀwarpꢀ

andꢀtapeꢀpeelꢀforceꢀmayꢀincrease.ꢀKEMETꢀrecommendsꢀthatꢀmaximumꢀstorageꢀtemperatureꢀnotꢀexceedꢀ40ºCꢀandꢀmaximumꢀ

storageꢀhumidityꢀnotꢀexceedꢀ70%ꢀrelativeꢀhumidity.ꢀTemperatureꢀﬂuctuationsꢀshouldꢀbeꢀminimizedꢀtoꢀavoidꢀcondensationꢀonꢀ

theꢀpartsꢀandꢀatmospheresꢀshouldꢀbeꢀfreeꢀofꢀchlorineꢀandꢀsulfurꢀbearingꢀcompounds.ꢀForꢀoptimizedꢀsolderabilityꢀchipꢀstockꢀ

shouldꢀbeꢀusedꢀpromptly,ꢀpreferablyꢀwithinꢀ1.5ꢀyearsꢀofꢀreceipt.

C1003_C0G • 6/7/2018

12

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Construction

Detailed Cross Section

Dielectric Material

(CaZrO₃)

Barrier Layer

(Ni)

Dielectric

Material (CaZrO₃)

End Termination/

External Electrode

(Cu)

Termination Finish

(100% Matte Sn)

Inner Electrodes

(Ni)

End Termination/

External Electrode

(Cu)

Barrier Layer

(Ni)

Termination Finish

(100% Matte Sn)

Inner Electrodes

(Ni)

Capacitor Marking (Optional):

Laserꢀmarkingꢀoptionꢀisꢀnotꢀavailableꢀon:

•ꢀ C0G,ꢀUltraꢀStableꢀX8RꢀandꢀY5Vꢀdielectricꢀdevices

• EIA 0402 case size devices

•ꢀ EIAꢀ0603ꢀcaseꢀsizeꢀdevicesꢀwithꢀFlexibleꢀTerminationꢀoption.

•ꢀ KPSꢀCommercialꢀandꢀAutomotiveꢀgradeꢀstackedꢀdevices.

Theseꢀcapacitorsꢀareꢀsuppliedꢀunmarkedꢀonly.

C1003_C0G • 6/7/2018

13

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Tape & Reel Packaging Information

KEMETꢀoffersꢀmultilayerꢀceramicꢀchipꢀcapacitorsꢀpackagedꢀinꢀ8,ꢀ12ꢀandꢀ16ꢀmmꢀtapeꢀonꢀ7"ꢀandꢀ13"ꢀreelsꢀinꢀaccordanceꢀwithꢀ

EIAꢀStandardꢀ481.ꢀThisꢀpackagingꢀsystemꢀisꢀcompatibleꢀwithꢀallꢀtape-fedꢀautomaticꢀpickꢀandꢀplaceꢀsystems.ꢀSeeꢀTableꢀ2ꢀforꢀ

detailsꢀonꢀreelingꢀquantitiesꢀforꢀcommercialꢀchips.

ꢓar code laꢉel

ꢆntiꢇstatic reel

®

ꢈmꢉossed plasticꢊ or

punched paper carrierꢃ

Chip and ꢏꢐS orientation in pocꢎet

(eꢍcept 1ꢀ25 commercial, and 1ꢀ25 and 2225 Military)

KEMET

Sprocꢎet holes

ꢈmꢉossment or punched caꢋity

ꢀ mm, 12 mm

or 1ꢁ mm carrier tape

ꢆntiꢇstatic coꢋer tape

(0ꢃ10 mm (0ꢃ00ꢌꢄ) maꢍimum thicꢎness)

1ꢀ0 mm (ꢂꢃ00ꢄ)

or

ꢅꢅ0 mm (1ꢅꢃ00ꢄ)

ꢊꢈꢑꢆ 01005, 0201, 0ꢌ02 and 0ꢁ0ꢅ case siꢒes aꢋailaꢉle on punched paper carrier onlyꢃ

Table 5 – Carrier Tape Conﬁguration, Embossed Plastic & Punched Paper (mm)

New 2 mm Pitch Reel Options*

Embossed Plastic Punched Paper

Tape

Packaging

Ordering Code

(C-Spec)

C-3190

7" Reel 13" Reel 7" Reel 13" Reel

EIA Case Size Size

(W)*

Packaging Type/Options

Pitchꢀ(P₁)* Pitchꢀ(P₁)*

01005 – 0402

0603

8

2

2/4

4

Automotiveꢀgradeꢀ7"ꢀreelꢀunmarked

Automotiveꢀgradeꢀ13"ꢀreelꢀunmarked

Commercialꢀgradeꢀ7"ꢀreelꢀunmarked

Commercialꢀgradeꢀ13"ꢀreelꢀunmarked

C-3191

2/4

4

C-7081

0805

8

4

C-7082

1206 – 1210

1805 – 1808

≥ꢀ1812

8

4

* 2 mm pitch reel only available for 0603 EIA case size.

2 mm pitch reel for 0805 EIA case size under development.

12

16

8

4

8

Beneﬁts of Changing from 4 mm to 2 mm Pitching Spacing

• Lower placement costs.

•ꢀ Doubleꢀtheꢀpartsꢀonꢀeachꢀreelꢀresultsꢀinꢀfewerꢀreelꢀ

changesꢀandꢀincreasedꢀe ꢀꢀciency.

•ꢀ Fewerꢀreelsꢀresultꢀinꢀlowerꢀpackaging,ꢀshippingꢀandꢀ

storageꢀcosts,ꢀreducingꢀwaste.

KPS 1210

8

KPS 1812

and 2220

12

4

12

4

Array 0612

*Refer to Figures 1 and 2 for W and P₁carrier tape reference locations.

*Refer to Tables 6 and 7 for tolerance speciﬁcations.

C1003_C0G • 6/7/2018

14

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Figure 1 – Embossed (Plastic) Carrier Tape Dimensions

ꢁ

ꢁ₂

ꢀ₂

(10 pitches cumulatiꢄe

tolerance on tape ꢐ0ꢊ2 mm)

ꢌ₁

ꢀ₀

ꢋD₀

ꢅ₀

ꢂ

ꢇ₀

ꢃ

ꢌ₂

ꢆ₁

ꢆ₀

S₁

ꢀ₁

ꢁ₁

Coꢄer ꢁape

ꢌmꢉossment

ꢂor caꢄity siꢍe,

see ꢎote 1 ꢁaꢉle ꢏ

Center Lines of Caꢄity

ꢋD₁

ꢆ₁is for tape feeder reference only,

includinꢈ draft concentric aꢉout ꢆ₀ꢊ

Uꢀer ꢁireꢂꢃiꢄꢅ ꢄꢆ Uꢅreeꢇiꢅꢈ

Table 6 – Embossed (Plastic) Carrier Tape Dimensions

Metricꢀwillꢀgovern

Constant Dimensions — Millimeters (Inches)

D₁ꢀMinimum

Note 1

1.0

(0.039)

R Reference S₁ꢀMinimum

T

T₁

Tape Size

8 mm

D₀

E₁

P₀

P₂

Note 2

Note 3

Maximum Maximum

25.0

(0.984)

1.5ꢀ+0.10/−0.0ꢀ

(0.059ꢀ+0.004/−0.0)

1.75 ±0.10

4.0 ±0.10

2.0 ±0.05

0.600

(0.024)

0.600

(0.024)

0.100

(0.004)

12 mm

16 mm

(0.069 ±0.004) (0.157 ±0.004) (0.079 ±0.002)

1.5

(0.059)

30

(1.181)

Variable Dimensions — Millimeters (Inches)

B₁ꢀMaximum

E₂

T₂

W

Tape Size

8 mm

Pitchꢀ

Fꢀ

P₁

A₀,B₀ꢀ&ꢀK₀

Note 4

4.35

(0.171)

Minimum

6.25

(0.246)

Maximum Maximum

2.5

(0.098)

3.5 ±0.05

(0.138 ±0.002) (0.157 ±0.004)

4.0 ±0.10

8.3

(0.327)

Singleꢀ(4ꢀmm)

8.2

10.25

5.5 ±0.05

8.0 ±0.10

4.6

12.3

12 mm

16 mm

Note 5

andꢀdoubleꢀ(8ꢀmm)

(0.323)

(0.404)

(0.217 ±0.002) (0.315 ±0.004)

(0.181)

(0.484)

12.1

(0.476)

14.25

(0.561)

7.5 ±0.05 12.0 ±0.10

(0.138 ±0.002) (0.157 ±0.004)

4.6

(0.181)

16.3

(0.642)

Triple (12 mm)

1. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. Dimensions of the embossment

location and the hole location shall be applied independently of each other.

2. The tape with or without components shall pass around R without damage (see Figure 6.)

3. If S₁< 1.0 mm, there may not be enough area for a cover tape to be properly applied (see EIA Standard 481, paragraph 4.3, section b.)

4. B₁dimension is a reference dimension for tape feeder clearance only.

5. The cavity deﬁned by A₀, B₀and K₀shall surround the component with suﬃcient clearance that:

(a) the component does not protrude above the top surface of the carrier tape.

(b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been

removed.

(c) rotation of the component is limited to 20° maximum for 8 and 12 mm tapes and 10° maximum for 16 mm tapes (see Figure 3.)

(d) lateral movement of the component is restricted to 0.5 mm maximum for 8 and 12 mm wide tape and to 1.0 mm maximum for 16 mm tape

(see Figure 4.)

(e) for KPS product, A₀and B₀are measured on a plane 0.3 mm above the bottom of the pocket.

(f) see addendum in EIA Standard 481 for standards relating to more precise taping requirements.

C1003_C0G • 6/7/2018

15

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Figure 2 – Punched (Paper) Carrier Tape Dimensions

ꢀ

(10 pitches cumulatiꢁe

tolerance on tape ꢍ0ꢎ2 mm)

ꢄ₁

ꢂo

ꢃDo

ꢇ₀

ꢅ

ꢆ

ꢄ₂

ꢈ₀

ꢂ¹

ꢈottom Coꢁer ꢀape

G

Caꢁity Siꢉe,

See

ꢀ¹

Center Lines of Caꢁity

ꢀop Coꢁer ꢀape

ꢊote 1, ꢀaꢋle ꢌ

ꢈottom Coꢁer ꢀape

Uꢀer ꢁireꢂꢃiꢄꢅ ꢄꢆ Uꢅreeꢇiꢅꢈ

Table 7 – Punched (Paper) Carrier Tape Dimensions

Metricꢀwillꢀgovern

Constant Dimensions — Millimeters (Inches)

R Reference

Note 2

Tape Size

8 mm

D₀

E₁

P₀

P₂

T₁Maximum

GꢀMinimum

0.10

1.5ꢀ+0.10ꢀ-0.0ꢀ

(0.059ꢀ+0.004ꢀ-0.0)

1.75 ±0.10

(0.069 ±0.004)

4.0 ±0.10

(0.157 ±0.004)

2.0 ±0.05

(0.079 ±0.002)

0.75

(0.030)

25

(0.984)

(0.004)

maximum

Variable Dimensions — Millimeters (Inches)

Tape Size

8 mm

Pitch

E2ꢀMinimum

Fꢀ

P₁

TꢀMaximum

WꢀMaximum

A₀B₀

2.0 ±0.05

(0.079 ±0.002)

4.0 ±0.10

(0.157 ±0.004)

8.3

(0.327)

8.3

(0.327)

Half (2 mm)

Singleꢀ(4ꢀmm)

6.25

(0.246)

3.5 ±0.05

(0.138 ±0.002)

1.1

(0.098)

Note 1

8 mm

1. The cavity deﬁned by A₀, B₀and T shall surround the component with suﬃcient clearance that:

a) the component does not protrude beyond either surface of the carrier tape.

b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been

removed.

c) rotation of the component is limited to 20° maximum (see Figure 3.)

d) lateral movement of the component is restricted to 0.5 mm maximum (see Figure 4.)

e) see addendum in EIA Standard 481 for standards relating to more precise taping requirements.

2. The tape with or without components shall pass around R without damage (see Figure 6.)

C1003_C0G • 6/7/2018

16

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Packaging Information Performance Notes

1. Cover Tape Break Force:ꢀ1.0ꢀkgꢀminimum.

2. Cover Tape Peel Strength: Theꢀtotalꢀpeelꢀstrengthꢀofꢀtheꢀcoverꢀtapeꢀfromꢀtheꢀcarrierꢀtapeꢀshallꢀbe:ꢀ

Tape Width

8 mm

Peel Strength

0.1ꢀtoꢀ1.0ꢀnewtonꢀ(10ꢀtoꢀ100ꢀgf)

0.1ꢀtoꢀ1.3ꢀnewtonꢀ(10ꢀtoꢀ130ꢀgf)

12 and 16 mm

Theꢀdirectionꢀofꢀtheꢀpullꢀshallꢀbeꢀoppositeꢀtheꢀdirectionꢀofꢀtheꢀcarrierꢀtapeꢀtravel.ꢀTheꢀpullꢀangleꢀofꢀtheꢀcarrierꢀtapeꢀshallꢀbeꢀ

165°ꢀtoꢀ180°ꢀfromꢀtheꢀplaneꢀofꢀtheꢀcarrierꢀtape.ꢀDuringꢀpeeling,ꢀtheꢀcarrierꢀand/orꢀcoverꢀtapeꢀshallꢀbeꢀpulledꢀatꢀaꢀvelocityꢀofꢀ

300ꢀ±10ꢀmm/minute.

3. Labeling:ꢀBarꢀcodeꢀlabelingꢀ(standardꢀorꢀcustom)ꢀshallꢀbeꢀonꢀtheꢀsideꢀofꢀtheꢀreelꢀoppositeꢀtheꢀsprocketꢀholes.ꢀRefer to EIA

Standards 556 and 624.

Figure 3 – Maximum Component Rotation

°

T

Maximum Component Rotation

Top View

Maximum Component Rotation

Side View

Typical Pocket Centerline

Tape

Maximum

°

T

s

Width (mm) Rotation (

)

8,12

16 – 200

20

10

Bo

Tape

Maximum

°

S

Width (mm) Rotation (

)

8,12

16 – 56

72 – 200

20

10

5

Typical Component Centerline

Ao

Figure 4 – Maximum Lateral Movement

Figure 5 – Bending Radius

Embossed

Carrier

Punched

Carrier

8 mm & 12 mm Tape

16 mm Tape

0.5 mm maximum

1.0 mm maximum

R

Bending

Radius

R

C1003_C0G • 6/7/2018

17

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Figure 6 – Reel Dimensions

ꢂull ꢃadius,

ꢍ_ꢎ(ꢈncludes

flanꢏe distortion

at outer edꢏe)

ꢀccess ꢅole at

Slot Location

(ꢆ ꢇ0 mm minimum)

See ꢁote

ꢍ₂(Measured at huꢐ)

D

(See ꢁote)

ꢀ

ꢁ

C

(ꢀrꢐor hole

ꢍ₁(Measured at huꢐ)

diameter)

ꢈf present,

tape slot in core

for tape startꢉ

2ꢊ5 mm minimum ꢋidth ꢌ

10ꢊ0 mm minimum depth

ꢄ

(see ꢁote)

ꢁoteꢉ Driꢑe spoꢒes optionalꢓ if used, dimensions ꢄ and D shall applyꢊ

Table 8 – Reel Dimensions

Metricꢀwillꢀgovern

Constant Dimensions — Millimeters (Inches)

Tape Size

8 mm

A

BꢀMinimum

C

DꢀMinimum

178 ±0.20

(7.008 ±0.008)

or

1.5

(0.059)

13.0ꢀ+0.5/−0.2ꢀ

(0.521ꢀ+0.02/−0.008)

20.2

(0.795)

12 mm

16 mm

330 ±0.20

(13.000 ±0.008)

Variable Dimensions — Millimeters (Inches)

Tape Size

8 mm

NꢀMinimum

W₁

W₂ꢀMaximum

W₃

8.4ꢀ+1.5/−0.0

(0.331ꢀ+0.059/−0.0)

14.4

(0.567)

50

(1.969)

12.4ꢀ+2.0/−0.0

18.4

Shallꢀaccommodateꢀtapeꢀ

widthꢀwithoutꢀinterference

12 mm

16 mm

(0.488ꢀ+0.078/−0.0)ꢀꢀ

(0.724)

16.4ꢀ+2.0/−0.0

(0.646ꢀ+0.078/−0.0)

22.4

(0.882)

C1003_C0G • 6/7/2018

18

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

Figure 7 – Tape Leader & Trailer Dimensions

ꢅmꢍossed Carrier

Carrier ꢀape

ꢊunched Carrier

ꢋ mm ꢌ 12 mm only

ꢂound Sprocꢃet ꢄoles

ꢃTAꢄT

ꢀꢁꢂ

ꢀop Coꢉer ꢀape

ꢅlonꢆated Sprocꢃet ꢄoles

(ꢇ2 mm tape and ꢈider)

100 mm

minimum leader

ꢎ00 mm minimum

ꢀrailer

Components

1ꢁ0 mm minimum

ꢀop Coꢉer ꢀape

Figure 8 – Maximum Camber

ꢆlonꢅated Sprocꢂet ꢃoles

(ꢇ2 mm ꢈ ꢉider tapes)

Carrier ꢀape

ꢁound Sprocꢂet ꢃoles

1 mm maꢄimum, either direction

Straiꢅht ꢆdꢅe

250 mm

C1003_C0G • 6/7/2018

19

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10 – 250 VDC (Commercial Grade)

KEMET Electronics Corporation Sales Oﬃces

Forꢀaꢀcompleteꢀlistꢀofꢀourꢀglobalꢀsalesꢀo ꢀꢀces,ꢀpleaseꢀvisitꢀwww.kemet.com/sales.

Disclaimer

Allꢀproductꢀspeci ꢀcations,ꢀstatements,ꢀinformationꢀandꢀdataꢀ(collectively,ꢀtheꢀ“Information”)ꢀinꢀthisꢀdatasheetꢀareꢀsubjectꢀtoꢀchange.ꢀTheꢀcustomerꢀisꢀresponsibleꢀforꢀ

checkingꢀandꢀverifyingꢀtheꢀextentꢀtoꢀwhichꢀtheꢀInformationꢀcontainedꢀinꢀthisꢀpublicationꢀisꢀapplicableꢀtoꢀanꢀorderꢀatꢀtheꢀtimeꢀtheꢀorderꢀisꢀplaced.

AllꢀInformationꢀgivenꢀhereinꢀisꢀbelievedꢀtoꢀbeꢀaccurateꢀandꢀreliable,ꢀbutꢀitꢀisꢀpresentedꢀwithoutꢀguarantee,ꢀwarranty,ꢀorꢀresponsibilityꢀofꢀanyꢀkind,ꢀexpressedꢀorꢀimplied.

StatementsꢀofꢀsuitabilityꢀforꢀcertainꢀapplicationsꢀareꢀbasedꢀonꢀKEMETꢀElectronicsꢀCorporation’sꢀ(“KEMET”)ꢀknowledgeꢀofꢀtypicalꢀoperatingꢀconditionsꢀforꢀsuchꢀ

applications,ꢀbutꢀareꢀnotꢀintendedꢀtoꢀconstituteꢀ–ꢀandꢀKEMETꢀspeci ꢀcallyꢀdisclaimsꢀ–ꢀanyꢀwarrantyꢀconcerningꢀsuitabilityꢀforꢀaꢀspeci ꢀcꢀcustomerꢀapplicationꢀorꢀuse.ꢀ

TheꢀInformationꢀisꢀintendedꢀforꢀuseꢀonlyꢀbyꢀcustomersꢀwhoꢀhaveꢀtheꢀrequisiteꢀexperienceꢀandꢀcapabilityꢀtoꢀdetermineꢀtheꢀcorrectꢀproductsꢀforꢀtheirꢀapplication.ꢀAnyꢀ

technicalꢀadviceꢀinferredꢀfromꢀthisꢀInformationꢀorꢀotherwiseꢀprovidedꢀbyꢀKEMETꢀwithꢀreferenceꢀtoꢀtheꢀuseꢀofꢀKEMET’sꢀproductsꢀisꢀgivenꢀgratis,ꢀandꢀKEMETꢀassumesꢀnoꢀ

obligationꢀorꢀliabilityꢀforꢀtheꢀadviceꢀgivenꢀorꢀresultsꢀobtained.

AlthoughꢀKEMETꢀdesignsꢀandꢀmanufacturesꢀitsꢀproductsꢀtoꢀtheꢀmostꢀstringentꢀqualityꢀandꢀsafetyꢀstandards,ꢀgivenꢀtheꢀcurrentꢀstateꢀofꢀtheꢀart,ꢀisolatedꢀcomponentꢀ

failuresꢀmayꢀstillꢀoccur.ꢀAccordingly,ꢀcustomerꢀapplicationsꢀwhichꢀrequireꢀaꢀhighꢀdegreeꢀofꢀreliabilityꢀorꢀsafetyꢀshouldꢀemployꢀsuitableꢀdesignsꢀorꢀotherꢀsafeguardsꢀ

(suchꢀasꢀinstallationꢀofꢀprotectiveꢀcircuitryꢀorꢀredundancies)ꢀinꢀorderꢀtoꢀensureꢀthatꢀtheꢀfailureꢀofꢀanꢀelectricalꢀcomponentꢀdoesꢀnotꢀresultꢀinꢀaꢀriskꢀofꢀpersonalꢀinjuryꢀorꢀ

propertyꢀdamage.

Althoughꢀallꢀproduct–relatedꢀwarnings,ꢀcautionsꢀandꢀnotesꢀmustꢀbeꢀobserved,ꢀtheꢀcustomerꢀshouldꢀnotꢀassumeꢀthatꢀallꢀsafetyꢀmeasuresꢀareꢀindictedꢀorꢀthatꢀotherꢀ

measuresꢀmayꢀnotꢀbeꢀrequired.

KEMET is a registered trademark of KEMET Electronics Corporation.

C1003_C0G • 6/7/2018

20


型号：	C0805C151J1GACAUTO
厂家：	KEMET CORPORATION
描述：	Capacitor, Ceramic, Chip, General Purpose, 150pF, 100V, ±5%, C0G/NP0, 0805 (2012 mm), -55º ~ +125ºC, Bulk 电容器
文件：	总20页 (文件大小：1342K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

C0805C151J1GACAUTO [KEMET]

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