C1210C106MAR2C7168_技术文档

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)

Overview

KEMET Power Solutions (KPS) Commercial Series stacked

capacitors utilize a proprietary lead-frame technology

to vertically stack one or two multilayer ceramic chip

capacitors into a single compact surface mount package.

The attached lead-frame mechanically isolates the

capacitor/s from the printed circuit board, therefore offering

advanced mechanical and thermal stress performance.

Isolation also addresses concerns for audible, microphonic

noise that may occur when a bias voltage is applied. A

two chip stack offers up to double the capacitance in

the same or smaller design footprint when compared to

traditional surface mount MLCCs devices. Providing up

to 10 mm of board ﬂex capability, KPS Series capacitors

are environmentally friendly and in compliance with RoHS

legislation. Available in X7R dielectric, these devices are

capable of Pb-Free reﬂow proﬁles and provide lower ESR, ESL

and higher ripple current capability when compared to other

dielectric solutions.

Combined with the stability of an X7R dielectric, KEMET’s

KPS Series devices exhibit a predictable change in

capacitance with respect to time and voltage and boast a

minimal change in capacitance with reference to ambient

temperature. Capacitance change is limited to ±15% from

−55°C to +125°C.

Beneﬁts

• −55°C to +125°C operating temperature range

• Reliable and robust termination system

• EIA 1210, 1812, and 2220 case sizes

• DC voltage ratings of 10 V, 16 V, 25 V, 50 V, 100 V,

and 250 V

• Capacitance offerings ranging from 0.1 μF up to 47 μF

• Available capacitance tolerances of ±10% and ±20%

• Higher capacitance in the same footprint

• Potential board space savings

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Ordering Information

C

2220

C

106

M

5

R

2

C

7186

Rated

Packaging/

Grade

(C-Spec)

Case Size Speciﬁcation/ Capacitance Capacitance

Ceramic

Voltage Dielectric Failure Rate/Design Leadframe Finish²

(VDC)

(L" x W")

Series

Code (pF)

Tolerance¹

1210

1812

2220

C = Standard

Two

signiﬁcant

digits +

number of

zeros

K = ±10%

M = ±20%

8 = 10

4 = 16

3 = 25

5 = 50

1 = 100

A = 250

R = X7R 1 = KPS Single

Chip Stack

C = 100% Matte Sn

See

“Packaging

C-Spec

Ordering

Options Table”

below

2 = KPS Double

Chip Stack

¹Double chip stacks ("2" in the 13th character position of the ordering code) are only available in M (±20%) capacitance tolerance. Single chip stacks

("1" in the 13th character position of the ordering code) are available in K (±10%) or M (±20%) tolerances.

²Additional leadframe ﬁnish options may be available. Contact KEMET for details.

One world. One KEMET

C1020_X7R_KPS_SMD • 8/11/2016

1

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)

Packaging C-Spec Ordering Options Table

Packaging/Grade

Packaging Type¹

Ordering Code (C-Spec)²

7" Reel (Embossed Plastic Tape)/Unmarked

13" Reel (Embossed Plastic Tape)/Unmarked

7186

7289

¹The terms "Marked" and "Unmarked" pertain to laser marking option of capacitors. All packaging options labeled as "Unmarked" will contain capacitors

that have not been laser marked. The option to laser mark is not available on these devices. For more information see "Capacitor Marking".

Beneﬁts cont'd

• Advanced protection against thermal

and mechanical stress

• Lead (Pb)-free, RoHS and REACH compliant

• Capable of Pb-free reﬂow proﬁles

• Provides up to 10 mm of board ﬂex capability

• Reduces audible, microphonic noise

• Extremely low ESR and ESL

• Non-polar device, minimizing installation concerns

• Tantalum and electrolytic alternative

Applications

Typical applications include smoothing circuits, DC/DC converters, power supplies (input/output ﬁlters), noise reduction

(piezoelectric/mechanical), circuits with a direct battery or power source connection, critical and safety relevant circuits

without (integrated) current limitation and any application that is subject to high levels of board ﬂexure or temperature

cycling. Markets include industrial, military, automotive and telecom.

Qualiﬁcation/Certiﬁcation

Commercial Grade products are subject to internal qualiﬁcation. Details regarding test methods and conditions are

referenced in Table 4, Performance & Reliability.

Environmental Compliance

Lead (Pb)-free, RoHS, and REACH compliant without exemptions.

C1020_X7R_KPS_SMD • 8/11/2016

2

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)

Dimensions – Millimeters (Inches)

Single or Double ꢀhip Stack

Double ꢀhip Stack

Single ꢀhip Stack

L

ꢄ

ꢆ

Lꢄ

Number

of Chips

EIA

Size Code

Metric

Size Code

Mounting

Technique

L Length

W Width

H Height LW Lead Width

3.50 (0.138)

±0.30 (.012)

5.00 (0.197)

±0.50 (.020)

6.00 (0.236)

±0.50 (.020)

3.50 (0.138)

±0.30 (0.012)

5.00 (0.197)

±0.50 (0.020)

6.00 (0.236)

±0.50 (.020)

2.60 (0.102)

±0.30 (.012)

3.50 (0.138)

±0.50 (.020)

5.00 (0.197)

±0.50 (.020)

2.60 (0.102)

±0.30 (.012)

3.50 (0.138)

±0.50 (0.020)

5.00 (0.197)

±0.50 (0.020)

3.35 (0.132)

±0.10 (.004)

2.65 (0.104)

±0.35 (0.014)

3.50 (0.138)

±0.30 (0.012)

6.15 (0.242)

±0.15 (0.006)

5.00 (0.197)

±0.50 (0.020)

5.00 (0.197)

±0.50 (0.020)

0.80 (0.032)

±0.15 (0.006)

1.10 (0.043)

±0.30 (0.012)

1.60 (0.063)

±0.30 (0.012)

0.80 (0.031)

±0.15 (0.006)

1.10 (0.043)

±0.30 (0.012)

1.60 (0.063)

±0.30 (0.012)

1210

3225

4532

5650

3225

4532

5650

Single

1812

2220

1210

1812

2220

Solder Reﬂow

Only

Double

Electrical Parameters/Characteristics

Item

Parameters/Characteristics

Operating Temperature Range

−55°C to +125°C

±15%

Capacitance Change with Reference to

+25°C and 0 Vdc Applied (TCC)

¹Aging Rate (Maximum % Capacitance Loss/Decade Hour)

3.0%

250% of rated voltage

(5±1 seconds and charge/discharge not exceeding 50mA)

²Dielectric Withstanding Voltage (DWV)

³Dissipation Factor (DF) Maximum Limit at 25°C

⁴Insulation Resistance (IR) Minimum Limit at 25°C

5%(10V), 3.5%(16V & 25V) and 2.5%(50V to 250V)

See Insulation Resistance Limit Table

(Rated voltage applied for 120±5 seconds at 25°C)

¹Regarding Aging Rate: Capacitance measurements (including tolerance) are indexed to a referee time of 48 or 1,000 hours. Please refer to a part

number speciﬁc datasheet for referee time details.

²DWV is the voltage a capacitor can withstand (survive) for a short period of time. It exceeds the nominal and continuous working voltage of the

capacitor.

³Capacitance and dissipation factor (DF) measured under the following conditions:

1 kHz ±50 Hz and 1.0 ±0.2 Vrms if capacitance ≤ 10 µF

120 Hz ±10 Hz and 0.5 ±0.1 Vrms if capacitance > 10 µF

⁴To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits.

Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 and Agilent E4980 have a feature known

as Automatic Level Control (ALC). The ALC feature should be switched to "ON."

C1020_X7R_KPS_SMD • 8/11/2016

3

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)

Post Environmental Limits

High Temperature Life, Biased Humidity, Moisture Resistance

Rated DC

Voltage

Capacitance Dissipation Factor Capacitance

Insulation

Dielectric

X7R

Value

(Maximum %)

Shift

Resistance

> 25

16/25

< 16

3.0

10% of Initial

Limit

All

5.0

7.5

±20%

Insulation Resistance Limit Table

1,000 Megohm

Microfarads or 100 GΩ

500 Megohm

Microfarads or 10 GΩ

EIA Case Size

1210

1812

2220

< 0.39 µF

< 2.2 µF

< 10 µF

≥ 0.39 µF

≥ 2.2 µF

≥ 10 µF

Electrical Characteristics

Z and ESR C2220C225MAR2C

Z and ESR C1210C475M5R1C

10^ꢀ

10²

10¹

10⁰

10^ꢀ1

10^ꢀ2

10^ꢀꢁ

10^ꢀ

10²

10¹

10⁰

10^ꢀ1

10^ꢀ2

10^ꢀꢁ

ꢀSR

ꢀ

10⁰

10²

10^ꢀ

10¹⁰

10⁰

10²

10^ꢀ

10¹⁰

ꢀreꢁuency (ꢂꢃ)

C1020_X7R_KPS_SMD • 8/11/2016

4

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)

Electrical Characteristics cont'd

ESR – 1812, .10 µF, 50 V X7R

Z and ESR C2220C476M3R2C

10^ꢀ

ESR vs. Frequency

ꢀSR

10

1

ꢀ

C1812C104K5R2C (2 Chip Stack)

C1812C104K5R1C (1 Chip Stack)

10²

10⁰

10^ꢀ2

10^ꢀꢁ

0.1

0.01

10⁰

10²

10^ꢀ

10¹⁰

ꢀreꢁuency (ꢂꢃ)

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

Frequency (Hz)

Impedance – 1812, .10 µF, 50 V X7R

ESR – 1210, .22 µF, 50 V X7R

ESR vs. Frequency

Impedance vs. Frequency

10

1

10000

1000

100

10

C1210C224K5R2C (2 Chip Stack)

C1210C224K5R1C (1 Chip Stack)

C1812C104K5R2C (2 Chip Stack)

C1812C104K5R1C (1 Chip Stack)

0.1

1

0.1

0.01

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

Frequency (Hz)

Impedance – 1210, .22 µF, 50 V X7R

Impedance vs. Frequency

1000

100

10

C1210C224K5R2C (2 Chip Stack)

C1210C224K5R1C (1 Chip Stack)

1

0.1

0.01

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

Frequency (Hz)

C1020_X7R_KPS_SMD • 8/11/2016

5

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)

Electrical Characteristics cont'd

Microphonics – 2220, 22 µF, 50 V, X7R

Microphonics – 1210, 4.7 µF, 50 V, X7R

60

50

40

30

20

50

40

30

20

10

0

Standard SMD MLCC

KPS - 2 Chip Stack

Standard SMD MLCC

KPS - 1 Chip Stack

10

0

2

4

6

0

5

10

15

Vp-p

Microphonics – 2220, 47 µF, 25 V, X7R

Microphonics – 1210, 22 µF, 25 V, X7R

50

40

30

20

10

0

50

40

30

20

10

0

Standard SMD MLCC

KPS - 2 Chip Stack

Standard SMD MLCC

KPS - 2 Chip Stack

0

5

10

15

20

0

2

4

6

Vp-p

Competitive Comparision

Microphonics – 1210, 4.7 µF, 50 V, X7R

Ripple Current (Arms) 2220, 22 µF, 50 V

120

60

100

80

60

40

20

0

50

40

30

20

10

0

KEMET KPS, 2220, 22µF, 50V rated (2 Chip Stack)

Competitor 2220, 22µF, 50V rated (2 Chip Stack)

Competitor

KEMET - KPS

0

10

20

30

0

5

10

15

Ripple Current (Arms)

Vp-p

Note: Refer to Table 4 for test method.

6

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)

Electrical Characteristics cont'd

Board Flex vs. Termination Type

ꢆeiꢇull

X7R 1210 10 uꢈ – (22uꢈ KPS Stacꢉed)

X7R 2220 22uꢈ 25V – (ꢄ7uꢈ KPS Stacꢉed)

2

Standard ꢊermination

KPS – 2 Chip Stacꢉ

ꢁ0

Standard ꢊermination

KPS – 2 Chip Stacꢉ

ꢁ0

ꢂ0

70

ꢃ0

50

ꢂ0

70

ꢃ0

50

ꢄ0

ꢅ0

20

10

20

10

0

5

0

ꢀ

0

ꢀ

1

2

ꢅ

ꢄ

5

ꢃ

7

ꢂ

ꢁ

1

Board ꢀleꢁure (mm)

Board Flexure to 10 mm

ꢅeiꢆull

X7R 1ꢁ12 ꢃ7uꢇ 1ꢂV

ꢆeiꢇull

X7R 1210 ꢄꢀ7 uꢈ 50V

2

ꢀ0

ꢁ0

ꢂ0

70

ꢃ0

50

ꢄ0

ꢁ0

70

ꢂ0

50

ꢃ0

ꢅ0

ꢄ0

20

10

1

10

Board ꢀleꢁure (mm)

C1020_X7R_KPS_SMD • 8/11/2016

7

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)

Table 1 – Capacitance Range/Selection Waterfall (1210 – 2220 Case Sizes)

Case Size/Series

Voltage Code

C1210C

C1812C

C2220C

8

4

3

5

1

A

4

3

5

1

A

4

3

5

1

A

Cap

Code

Capacitance

Rated Voltage (VDC)

10

16

25

50

100

250

16

25

50

100

250

16

25

50

100

250

Product Availability and Chip Thickness Codes

See Table 2 for Chip Thickness Dimensions

Capacitance Tolerance

Single Chip Stack

0.10 µF

0.22 µF

0.47 µF

1.0 µF

2.2 µF

3.3 µF

4.7 µF

10 µF

104

224

474

105

225

335

475

106

156

226

K

M

FV

GP

JP

15 µF

22 µF

Double Chip Stack

0.10 µF

0.22 µF

0.47 µF

1.0 µF

2.2 µF

3.3 µF

4.7 µF

10 µF

104

224

474

105

225

335

475

106

226

336

476

M

FW

GR

JR

22 µF

33 µF

47 µF

Rated Voltage (VDC)

Voltage Code

10

8

16

4

25

3

50

5

100

1

250

A

16

4

25

3

50

5

100

1

250

A

16

4

25

3

50

5

100

1

250

A

Cap

Code

Capacitance

Case Size/Series

C1210C

C1812C

C2220C

These products are protected under US Patent 8,331,078 other patents pending, and any foreign counterparts.

Table 2 – Chip Thickness/Tape & Reel Packaging Quantities

Paper Quantity

7" Reel 13" Reel

Plastic Quantity

7" Reel 13" Reel

Thickness Case Thickness ±

Code

Size

Range (mm)

FV

FW

GP

GR

JP

JR

1210

1812

2220

3.35 ± 0.10

6.15 ± 0.15

2.65 ± 0.35

5.00 ± 0.50

3.50 ± 0.30

5.00 ± 0.50

0

600

2,000

0

300

500

400

300

200

1,000

2,000

1,700

1,300

800

7" Reel

13" Reel

7" Reel

13" Reel

Thickness

Code

Case

Size

Thickness ±

Range (mm)

Paper Quantity

Plastic Quantity

Package quantity based on ﬁnished chip thickness speciﬁcations.

C1020_X7R_KPS_SMD • 8/11/2016

8

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)

Table 3 – KPS Land Pattern Design Recommendations (mm)

V1

Median (Nominal) Land

Protrusion

METRIC

SIZE

CODE

EIA SIZE

CODE

ꢀ

C

Y

X

V1

V2

1210

1812

2220

3225

4532

5650

1.50

1.14

1.75

5.05

3.40

V2

X

2.20

2.69

1.35

2.08

2.87

4.78

6.70

7.70

4.50

6.00

Image at right based on an EIA 1210 case size.

C

Grid Placement Courtyard

Soldering Process

KEMET’s KPS Series devices are compatible with IR

reﬂow techniques. Preheating of these components is

recommended to avoid extreme thermal stress. KEMET's

recommended proﬁle conditions for IR reﬂow reﬂect the

proﬁle conditions of the IPC/J–STD–020D standard for

moisture sensitivity testing.

Proﬁle Feature

Preheat/Soak

SnPb Assembly Pb-Free Assembly

Temperature Minimum (T_Smin

)

100°C

150°C

200°C

Temperature Maximum (T_Smax

)

Time (t_s) from T_sminto T_smax

Ramp-up Rate (T_Lto T_P)

)

60 – 120 seconds

3°C/seconds maximum 3°C/seconds maximum

To prevent degradation of temperature cycling capability,

care must be taken to prevent solder from ﬂowing into

the inner side of the lead frames (inner side of "J" lead in

contact with the circuit board).

Liquidous Temperature (T_L)

Time Above Liquidous (t_L)

Peak Temperature (T_P)

183°C

60 – 150 seconds

235°C

217°C

60 – 150 seconds

250°C

Time within 5°C of Maximum

20 seconds maximum 10 seconds maximum

Peak Temperature (t_P)

After soldering, the capacitors should be air cooled to

room temperature before further processing. Forced air

cooling is not recommended.

Ramp-down Rate (T_Pto T_L) 6°C/seconds maximum 6°C/seconds maximum

Time 25°C to Peak

6 minutes maximum

8 minutes maximum

Temperature

Note: All temperatures refer to the center of the package, measured on the

package body surface that is facing up during assembly reﬂow.

Hand soldering should be performed with care due to the

difﬁculty in process control. If performed, care should be

taken to avoid contact of the soldering iron to the capacitor

body. The iron should be used to heat the solder pad,

applying solder between the pad and the lead, until reﬂow

occurs. Once reﬂow occurs, the iron should be removed

immediately. (Preheating is required when hand soldering to

avoid thermal shock.)

ꢀ_P

t_P

Maꢁimum Ramp ꢂp Rate ꢃ ꢄꢅCꢆsec

Maꢁimum Ramp Doꢇn Rate ꢃ ꢈꢅCꢆsec

ꢀ_L

t_L

ꢀ_smaꢁ

ꢀ_smin

t_s

25

25ꢅC to Peaꢉ

Time

C1020_X7R_KPS_SMD • 8/11/2016

9

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)

Table 4 – Performance & Reliability: Test Methods and Conditions

Stress

Terminal Strength

Board Flex

Reference

JIS–C–6429

Test or Inspection Method

Appendix 1, Note: Force of 1.8 kg for 60 seconds.

Appendix 2, Note: 5.0 mm minimum

Magniﬁcation 50 X. Conditions:

a) Method B, 4 hours at 155°C, dry heat at 235°C

b) Method B at 215°C category 3

Solderability

J–STD–002

c) Method D, category 3 at 250°C

Temperature Cycling

Biased Humidity

JESD22 Method JA–104 1,000 cycles (−55°C to +125°C). Measurement at 24 hours +/− 4 hours after test conclusion.

Load Humidity: 1,000 hours 85°C/85% RH and rated voltage. Add 100 K ohm resistor.

Measurement at 24 hours +/− 4 hours after test conclusion.

Low Volt Humidity: 1,000 hours 85°C/85% RH and 1.5 V. Add 100 K ohm resistor.

Measurement at 24 hours +/− 4 hours after test conclusion.

t = 24 hours/cycle. Steps 7a and 7b not required.

Measurement at 24 hours +/− 4 hours after test conclusion.

−55°C/+125°C. Note: Number of cycles required – 300. Maximum transfer time – 20

seconds. Dwell time – 15 minutes. Air-Air.

MIL–STD–202 Method

103

MIL–STD–202 Method

106

MIL–STD–202 Method

107

MIL–STD–202 Method

108

Moisture Resistance

Thermal Shock

High Temperature Life

Storage Life

1,000 hours at 125°C with 1.5X rated voltage applied.

MIL–STD–202 Method

108

150°C, 0 VDC for 1,000 hours.

5 g's for 20 minutes, 12 cycles each of 3 orientations. Note: Use 8" X 5" PCB .031" thick,

7 secure points on one long side and 2 secure points at corners of opposite sides. Parts

mounted within 2" from any secure point. Test from 10 – 2,000 Hz.

MIL–STD–202 Method

204

Vibration

MIL–STD–202 Method

Mechanical Shock

Figure 1 of Method 213, Condition F.

213

MIL–STD–202 Method

215

Resistance to Solvents

Add aqueous wash chemical, OKEM Clean or equivalent.

Storage & Handling

Ceramic chip capacitors should be stored in normal working environments. While the chips themselves are quite robust in

other environments, solderability will be degraded by exposure to high temperatures, high humidity, corrosive atmospheres,

and long term storage. In addition, packaging materials will be degraded by high temperature–reels may soften or warp

and tape peel force may increase. KEMET recommends that maximum storage temperature not exceed 40ºC and maximum

storage humidity not exceed 70% relative humidity. Temperature ﬂuctuations should be minimized to avoid condensation on

the parts and atmospheres should be free of chlorine and sulfur bearing compounds. For optimized solderability chip stock

should be used promptly, preferably within 1.5 years of receipt.

C1020_X7R_KPS_SMD • 8/11/2016 10

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)

Construction (Typical)

Detailed Cross Section

Dielectric Material

(ꢀaꢁiꢂ_ꢃ)

Leadframe

(Phosphor ꢀronꢋe ꢌ ꢈlloy 510)

Leadframe ꢈttach

(ꢉiꢊh Meltinꢊ Point Solder)

ꢅnner ꢆlectrodes

(ꢄi)

ꢆnd ꢁerminationꢍ

ꢆꢎternal ꢆlectrode

(Cu)

ꢀarrier Layer

(ꢄi)

Dielectric Material

(ꢀaꢁiꢂ_ꢃ)

ꢁermination ꢇinish

(Sn)

ꢁermination ꢇinish

(Sn)

ꢅnner ꢆlectrodes

ꢀarrier Layer

(ꢄi)

ꢆnd ꢁerminationꢍ

ꢆꢎternal ꢆlectrode

(Cu)

Product Marking

Laser marking option is not available on:

• C0G, Ultra Stable X8R and Y5V dielectric devices

• EIA 0402 case size devices

• EIA 0603 case size devices with Flexible Termination option.

• KPS Commercial and Automotive grade stacked devices.

These capacitors are supplied unmarked only.

C1020_X7R_KPS_SMD • 8/11/2016 11

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)

Tape & Reel Packaging Information

KEMET offers multilayer ceramic chip capacitors packaged in 8, 12 and 16 mm tape on 7" and 13" reels in accordance with

EIA Standard 481. This packaging system is compatible with all tape-fed automatic pick and place systems. See Table 2 for

details on reeling quantities for commercial chips.

Table 5 – Carrier Tape Conﬁguration – Embossed Plastic (mm)

EIA Case Size

01005 – 0402

0603 – 1210

1805 – 1808

≥ 1812

Tape Size (W)*

Pitch (P₁)*

8

2

4

12

16

8

4

8

KPS 1210

8

KPS 1812 & 2220

Array 0508 & 0612

12

4

*Refer to Figure 1 for W and P₁carrier tape reference locations.

*Refer to Table 5 for tolerance speciﬁcations.

C1020_X7R_KPS_SMD • 8/11/2016 12

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)

Figure 1 – Embossed (Plastic) Carrier Tape Dimensions

ꢀ

P 2

ꢍ10 pitches cumulatiꢃe

tolerance on tape ꢎ 0ꢏ2 mmꢐ

2

ꢉ

1

Po

ꢈDo

ꢄo

ꢁ

Ko

ꢂ

ꢉ

2

ꢅ

1

ꢅo

S

1

P

1

ꢀ

1

ꢉmꢇossment

ꢁor caꢃity siꢊe,

see ꢋote 1 ꢀaꢇle ꢌ

Center Lines of Caꢃity

ꢈD

1

Coꢃer ꢀape

is for tape feeder reference only,

includinꢆ draft concentric aꢇout ꢅ

ꢅ

1

o

.

ꢀser Direction of ꢀnreeling

Table 6 – Embossed (Plastic) Carrier Tape Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

D₁Minimum

Note 1

R Reference

Note 2

S₁Minimum

Note 3

T

T₁

Tape Size

D₀

E₁

P₀

P₂

Maximum Maximim

1.0

25.0

8 mm

12 mm

16 mm

(0.039)

(0.984)

1.5+0.10/0.0−0.0

(0.059+0.004/−0.0)

1.75±0.10

4.0±0.10

2.0±0.05

0.600

(0.024)

0.600

(0.024)

0.100

(0.004)

(0.069±0.004) (0.157±0.004) (0.079±0.002)

1.5

(0.059)

30

(1.181)

Variable Dimensions — Millimeters (Inches)

B₁Maximum

Note 4

T₂

W

Tape Size

8 mm

Pitch

E₂Minimum

F

P₁

A₀, B₀& K₀

Maximum

2.5

(0.098)

Maximum

8.3

(0.327)

4.35

(0.171)

6.25

(0.246)

3.5±0.05

(0.138±0.002) (0.157±0.004)

4.0±0.10

Single (4 mm)

Single (4 mm) &

Double (8 mm)

8.2

10.25

5.5±0.05

(0.217±0.002) (0.315±0.004)

7.5±0.05 12.0±0.10

(0.138±0.002) (0.157±0.004)

8.0±0.10

4.6

12.3

12 mm

16 mm

Note 5

(0.323)

(0.404)

(0.181)

(0.484)

12.1

(0.476)

14.25

(0.561)

4.6

(0.181)

16.3

(0.642)

Triple (12 mm)

1. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. Dimensions of embossment

location and hole location shall be applied independent of each other.

2. The tape with or without components shall pass around R without damage (see Figure 5).

3. If S₁< 1.0 mm, there may not be enough area for cover tape to be properly applied (see EIA Standard 481 paragraph 4.3 section b).

4. B₁dimension is a reference dimension for tape feeder clearance only.

5. The cavity deﬁned by A₀, B₀and K₀shall surround the component with sufﬁcient clearance that:

(a) the component does not protrude above the top surface of the carrier tape.

(b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.

(c) rotation of the component is limited to 20° maximum for 8 and 12 mm tapes and 10° maximum for 16 mm tapes (see Figure 2).

(d) lateral movement of the component is restricted to 0.5 mm maximum for 8 and 12 mm wide tape and to 1.0 mm maximum for 16 mm tape (see

Figure 3).

(e) for KPS Series product, A₀and B₀are measured on a plane 0.3 mm above the bottom of the pocket.

(f) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.

C1020_X7R_KPS_SMD • 8/11/2016 13

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)

Packaging Information Performance Notes

1. Cover Tape Break Force: 1.0 Kg minimum.

2. Cover Tape Peel Strength: The total peel strength of the cover tape from the carrier tape shall be:

Tape Width

8 mm

Peel Strength

0.1 to 1.0 Newton (10 to 100 gf)

0.1 to 1.3 Newton (10 to 130 gf)

12 and 16 mm

The direction of the pull shall be opposite the direction of the carrier tape travel. The pull angle of the carrier tape shall be

165° to 180° from the plane of the carrier tape. During peeling, the carrier and/or cover tape shall be pulled at a velocity of

300 ±10 mm/minute.

3. Labeling: Bar code labeling (standard or custom) shall be on the side of the reel opposite the sprocket holes. Refer to EIA

Standards 556 and 624.

Figure 2 – Maximum Component Rotation

°

ꢂ

Maꢀimum Component Rotation

Top View

Maꢀimum Component Rotation

Side View

ꢂypical Pocꢅet Centerline

Tape

Maꢀimum

°

ꢂ

s

Width (mm) Rotation (

)

ꢃ,12

1ꢄ – 200

20

10

ꢁo

Tape

Maꢀimum

°

S

Width (mm) Rotation (

)

ꢃ,12

1ꢄ – 5ꢄ

72 – 200

20

10

5

ꢂypical Component Centerline

ꢀo

Figure 3 – Maximum Lateral Movement

Figure 4 – Bending Radius

ꢂmꢃossed

Carrier

Punched

Carrier

ꢂ mm ꢃ 12 mm ꢄape

1ꢅ mm ꢄape

0ꢀ5 mm maꢁimum

1ꢀ0 mm maꢁimum

R

ꢀendinꢁ

Radius

R

C1020_X7R_KPS_SMD • 8/11/2016 14

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)

Figure 5 – Reel Dimensions

ꢂull Radius,

ꢌꢍ (ꢇncludes

flanꢎe distortion

at outer edꢎe)

ꢀccess ꢄole at

Slot Location

(ꢅ ꢆ0 mm minimum)

See ꢁote

ꢌ2 (Measured at huꢏ)

D

(See ꢁote)

ꢀ

ꢁ

C

(ꢀrꢏor hole

ꢌ1 (Measured at huꢏ)

diameter)

ꢇf present,

tape slot in core

for tape startꢈ

2ꢉ5 mm minimum ꢊidth ꢋ

10ꢉ0 mm minimum depth

ꢃ

(see ꢁote)

ꢁoteꢈ Driꢐe spoꢑes optionalꢒ if used, dimensions ꢃ and D shall applyꢉ

Table 7 – Reel Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

Tape Size

8 mm

A

B Minimum

C

D Minimum

178 ±0.20

(7.008 ±0.008)

or

1.5

(0.059)

13.0 +0.5/-0.2

(0.521 +0.02/-0.008)

20.2

(0.795)

12 mm

16 mm

330 ±0.20

(13.000 ±0.008)

Variable Dimensions — Millimeters (Inches)

Tape Size

8 mm

N Minimum

W₁

W₂Maximum

W₃

8.4 +1.5/-0.0

(0.331 +0.059/-0.0)

14.4

(0.567)

50

(1.969)

12.4 +2.0/-0.0

18.4

Shall accommodate tape

width without interference

12 mm

16 mm

(0.488 +0.078/-0.0)

(0.724)

16.4 +2.0/-0.0

(0.646 +0.078/-0.0)

22.4

(0.882)

C1020_X7R_KPS_SMD • 8/11/2016 15

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)

Figure 6 – Tape Leader & Trailer Dimensions

ꢄmꢋossed Carrier

Carrier ꢀape

Punched Carrier

ꢉ mm ꢊ 12 mm only

Round Sprocꢂet ꢃoles

START

END

ꢀop Coꢈer ꢀape

ꢄlonꢅated Sprocꢂet ꢃoles

(ꢆ2 mm tape and ꢇider)

100 mm

Minimum Leader

ꢌ00 mm Minimum

ꢀrailer

Components

1ꢁ0 mm Minimum

ꢀop Coꢈer ꢀape

Figure 7 – Maximum Camber

ꢅlonꢄated sprocꢁet holes

(ꢆ2 mm ꢇ ꢈider tapes)

Carrier ꢀape

Round Sprocꢁet ꢂoles

1 mm Maꢃimum, either direction

Straiꢄht ꢅdꢄe

250 mm

C1020_X7R_KPS_SMD • 8/11/2016 16

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

KPS Series, X7R Dielectric, 10 – 250 VDC (Commercial Grade)

KEMET Electronic Corporation Sales Ofﬁces

For a complete list of our global sales ofﬁces, please visit www.kemet.com/sales.

Disclaimer

All product speciﬁcations, statements, information and data (collectively, the “Information”) in this datasheet are subject to change. The customer is responsible for

checking and verifying the extent to which the Information contained in this publication is applicable to an order at the time the order is placed.

All Information given herein is believed to be accurate and reliable, but it is presented without guarantee, warranty, or responsibility of any kind, expressed or implied.

Statements of suitability for certain applications are based on KEMET Electronics Corporation’s (“KEMET”) knowledge of typical operating conditions for such

applications, but are not intended to constitute – and KEMET speciﬁcally disclaims – any warranty concerning suitability for a speciﬁc customer application or use.

The Information is intended for use only by customers who have the requisite experience and capability to determine the correct products for their application. Any

technical advice inferred from this Information or otherwise provided by KEMET with reference to the use of KEMET’s products is given gratis, and KEMET assumes no

obligation or liability for the advice given or results obtained.

Although KEMET designs and manufactures its products to the most stringent quality and safety standards, given the current state of the art, isolated component

failures may still occur. Accordingly, customer applications which require a high degree of reliability or safety should employ suitable designs or other safeguards

(such as installation of protective circuitry or redundancies) in order to ensure that the failure of an electrical component does not result in a risk of personal injury or

property damage.

Although all product–related warnings, cautions and notes must be observed, the customer should not assume that all safety measures are indicted or that other

measures may not be required.

KEMET is a registered trademark of KEMET Electronics Corporation.

C1020_X7R_KPS_SMD • 8/11/2016 17


型号：	C1210C106MAR2C7168
厂家：	KEMET CORPORATION
描述：	KPS Series, X7R Dielectric, 10 - 250 VDC (Commercial Grade)
文件：	总17页 (文件大小：3883K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

C1210C106MAR2C7168 [KEMET]

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