C1812H154J1GAC7800_技术文档

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature 200°C, C0G Dielectric, 10 – 200 VDC

(Industrial Grade)

Overview

KEMET’s High Temperature surface mount C0G Multilayer

Ceramic Capacitors (MLCCs) are constructed of a robust

and proprietary C0G/NP0 base metal electrode (BME)

dielectric system that offers industry-leading performance

at extreme temperatures up to 200°C. These devices are

speciﬁcally designed to withstand the demands of harsh

industrial environments such as down-hole oil exploration

and automotive/avionics engine compartment circuitry.

elevated temperatures up to 200°C. They also exhibit low ESR

at high frequencies and offer greater volumetric efﬁciency

over competitive high temperature precious metal electrode

(PME) and BME ceramic capacitor devices.

These devices are Lead (Pb)-Free, RoHS and REACH

compliant without the need of any exemptions.

KEMET’s High Temperature C0G capacitors are temperature

compensating and are well suited for resonant circuit

applications or those where Q and stability of capacitance

characteristics are required. They exhibit no change in

capacitance with respect to time and voltage and boast a

negligible change in capacitance with reference to ambient

temperature. Capacitance change is limited to ±30ppm/ºC

from −55°C to +200°C. In addition, these capacitors exhibit

high insulation resistance with low dissipation factor at

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Ordering Information

C

1210

H

124

J

5

G

A

C

TU

Case Size Speciﬁcation/

Capacitance

Code (pF)

Capacitance

Tolerance¹

Failure Rate/

Design

Packaging/

Ceramic

Voltage

Dielectric

G = C0G

Termination Finish²

(L" x W")

Series

Grade (C-Spec)

0402

0603

0805

1206

1210

1812

2220

H = High

Temperature

(200°C)

Two signiﬁcant digits + B = ±0.10 pF

number of zeros.

Use 9 for 1.0 – 9.9 pF

Use 8 for 0.5 – 0.99 pF F = ±1%

e.g., 2.2 pF = 229

e.g., 0.5 pF = 508

8 = 10 V

A = N/A

C = 100% Matte Sn

See

“Packaging

C-Spec

Ordering

Options

Table”

C = ±0.25 pF 4 = 16 V

D = ±0.5 pF

L = SnPb (5% Pb minimum)

E = Gold (Au) 1.97 – 11.8 µin

F = Gold (Au) 30 – 50 µin

G = Gold (Au) 100 µin

minimum

3 = 25 V

5 = 50 V

1 = 100 V

2 = 200 V

G = ±2%

J = ±5%

K = ±10%

M = ±20%

below

¹Additional capacitance tolerance offerings may be available. Contact KEMET for details.

²Additional termination ﬁnish options may be available. Contact KEMET for details.

One world. One KEMET

C1001_C0G_200C_SMD • 7/29/2016

1

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Beneﬁts

• −55°C to +200°C operating temperature range

• Lead (Pb)-free, RoHS and REACH compliant

• EIA 0402, 0603, 0805, 1206, 1210, 1812, and 2220

case sizes

• DC voltage ratings of 10 V, 16 V, 25 V, 50 V, 100 V,

and 200 V

• Preferred capacitance solution at line frequencies and into

the MHz range

• No capacitance change with respect to applied rated DC

voltage

• Negligible capacitance change with respect to temperature

from −55°C to +200°C

• Capacitance offerings ranging from 0.5 pF up to 470 nF

• Available capacitance tolerances of ±0.10 pF, ±0.25 pF,

±0.5 pF, ±1%, ±2%, ±5%, ±10% or ±20%

• No piezoelectric noise

• No capacitance decay with time

• Non-polar device, minimizing installation concerns

• 100% pure matte tin-plated termination ﬁnish allowing for

excellent solderability

• Extremely low ESR and ESL

• Gold (Au), Tin/Lead (Sn/Pb) and 100% pure matte Tin (Sn)

• High thermal stability

• High ripple current capability

termination ﬁnishes available

Applications

Typical applications include critical timing, tuning, circuits requiring low loss, circuits with pulse, high current, decoupling,

bypass, ﬁltering, transient voltage suppression, blocking and energy storage for use in extreme environments such as down-

hole exploration, aerospace engine compartments and geophysical probes.

C1001_C0G_200C_SMD • 7/29/2016

2

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Packaging C-Spec Ordering Options Table

Packaging

Ordering Code (C-Spec)

Termination Finish Options

Packaging Type/Options

Standard Packaging – Unmarked³

Bulk Bag

Wafﬂe Tray²

Blank¹

7292

TU

7" Tape & Reel

7411 (EIA 0603 and smaller case sizes)

7210 (EIA 0805 and larger case sizes)

13" Reel

C = 100% Matte Sn

7” Tape & Reel/2 mm pitch⁴

7" Tape & Reel – 50 pieces

7" Tape & Reel – 100 pieces

7" Tape & Reel – 250 pieces

7" Tape & Reel – 500 pieces

7" Tape & Reel – 1,000 pieces

7081

T050

T100

T250

T500

T1K0

L = SnPb (5% Pb min.)

F = Gold (Au) 30 – 50 µin

G = Gold (Au) 100 µin minimum

Moisture Sensitive Packaging⁵– Unmarked³

Wafﬂe Tray²

7282

7130

7" Tape & Reel

7" Tape & Reel – 50 pieces

7" Tape & Reel – 100 pieces

7" Tape & Reel – 250 pieces

7" Tape & Reel – 500 pieces

7" Tape & Reel – 1,000 pieces

E = Gold (Au) 1.97 – 11.8 µin

F = Gold (Au) 30 – 50 µin

G = Gold (Au) 100 µin minimum

Contact KEMET⁶

¹Default packaging is “Bulk Bag”. An ordering code C-Spec is not required for “Bulk Bag” packaging.

¹“Bulk Bag” packaging option is not available for Gold (Au) termination ﬁnish options and case sizes larger than 2225 (5664 Metric).

²“Wafﬂe Tray” packaging option is not available for case sizes larger than 2225 (5664 Metric).

³The terms “Marked” and “Unmarked” pertain to laser marking option of components. All packaging options labeled as “Unmarked” will contain

capacitors that have not been laser marked. The option to laser mark is not available on these devices.

³Reeling quantities are dependent upon chip size and thickness dimension. When ordering using the “T1K0” packaging option, 1812 through 2225 case

size devices with chip thickness of ≥ 1.9 mm (nominal) may be shipped on multiple 7” reels or a single 13” reel. Additional reeling or packaging options

may be available. Contact KEMET for details.

⁴The 2 mm pitch option allows for double the packaging quantity of capacitors on a given reel size. This option is limited to EIA 0603 (1608 metric) case

size devices. For more information regarding 2 mm pitch option see “Tape & Reel Packaging Information”.

⁵Moisture sensitive packaging is required for Gold (Au) termination option “E” (1.97 – 11.8 µin)

⁶Additional reeling or packaging options may be available. Contact KEMET for details.

C1001_C0G_200C_SMD • 7/29/2016

3

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Dimensions – Millimeters (Inches)

L

ꢁ

T

ꢀ

S

EIA Size

Code

Metric Size

Code

L

W

Width

T

B

Mounting

Technique

Separation

Minimum

Length

Thickness

Bandwidth

1.00 (0.040)

0.50 (0.020)

0.30 (0.012)

±0.10 (0.004)

0.35 (0.014)

±0.15 (0.006)

0.50 (0.02)

±0.25 (0.010)

0.50 (0.02)

±0.25 (0.010)

0.50 (0.02)

±0.25 (0.010)

Solder Reﬂow

0402

0603

0805

1206

1210

1812

2220

1005

1608

2012

3216

3225

4532

5650

0.30 (0.012)

0.70 (0.028)

0.75 (0.030)

±0.05 (0.002)

Only

1.60 (0.063)

±0.15 (0.006)

2.00 (0.079)

±0.20 (0.008)

3.20 (0.126)

±0.20 (0.008)

3.20 (0.126)

±0.20 (0.008)

4.50 (0.177)

±0.30 (0.012)

5.70 (0.224)

±0.40 (0.016)

0.80 (0.032)

±0.15 (0.006)

1.25 (0.049)

±0.20 (0.008)

1.60 (0.063)

±0.20 (0.008)

2.50 (0.098)

±0.20 (0.008)

3.20 (0.126)

±0.30 (0.012)

5.00 (0.197)

±0.40 (0.016)

Solder Wave or

Solder Reﬂow

See Table 2 for

Thickness

N/A

0.60 (0.024)

±0.35 (0.014)

0.60 (0.024)

±0.35 (0.014)

Solder Reﬂow

Only

Qualiﬁcation/Certiﬁcation

High temperature (200ºC) Industrial grade products meet or exceed the requirements outlined in Table 4, Performance &

Reliability. Qualiﬁcation packages are available for review and download on our website at www.kemet.com/hightemp

Environmental Compliance

Lead (Pb)-free, RoHS, and REACH compliant without exemptions (excluding SnPb termination ﬁnish option).

C1001_C0G_200C_SMD • 7/29/2016

4

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Electrical Parameters/Characteristics

Item

Parameters/Characteristics

Operating Temperature Range

−55°C to +200°C

Capacitance Change with Reference to

±30 ppm/ºC (up to 200ºC)

+25°C and 0 VDC Applied (TCC)

Aging Rate (Maximum % Capacitance Loss/Decade Hour)

¹Dielectric Withstanding Voltage (DWV)

0%

250% of rated voltage

(5±1 seconds and charge/discharge not exceeding 50 mA)

²Dissipation Factor (DF) Maximum Limit at 25ºC

0.1%

1,000 megohm microfarads or 100 GΩ

(Rated voltage applied for 120±5 seconds at 25°C)

³Insulation Resistance (IR) Minimum Limit at 25°C

¹DWV is the voltage a capacitor can withstand (survive) for a short period of time. It exceeds the nominal and continuous working voltage of the

capacitor.

²Capacitance and dissipation factor (DF) measured under the following conditions:

1 MHz ±100 kHz and 1.0 ±0.2 Vrms if capacitance ≤ 1,000 pF

1 kHz ±50 Hz and 1.0 ±0.2 Vrms if capacitance > 1,000 pF

³To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits.

Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 & Agilent E4980 have a feature known as

Automatic Level Control (ALC). The ALC feature should be switched to “ON.”

Post Environmental Limits

High Temperature Life, Biased Humidity, Moisture Resistance

Rated DC

Voltage

Capacitance Dissipation Factor Capacitance

Insulation

Resistance

Dielectric

C0G

Value

(Maximum %)

Shift

10% of Initial

All

0.5

0.3% or ±0.25 pF

Limit

C1001_C0G_200C_SMD • 7/29/2016

5

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Electrical Characteristics

C1210H104J1GAC - Life Test IR Distribution (Lognormal)

Delta Cap vs. Temperature (Typical)

20

1ꢀ

10

ꢀ

ꢁꢁ

0 hrs

2000 hrs

ꢁꢂ

ꢁ0

ꢃ0

ꢄ0

ꢅ0

ꢂ0

ꢆ0

ꢇ0

0

−ꢀ

20

10

ꢂ

−10

0 Vr

−1ꢀ

100ꢄ Vr

1

−20

0ꢀ1

1ꢀ0

10ꢀ0

100ꢀ0

25°C IR (GOhms)

Capacitance vs. Temperature with 25 V DC Bias

(Rated Voltage)

DF vs. Temperature without DC Bias.

1ꢀ00

200

200ꢄC C0G 100nꢅ no DC

200ꢅC C0G MLCC 100nꢆ

200ꢄC C0G 100nꢅ 2ꢀV DC

0ꢀꢁ0

1ꢀ0

0ꢀ00

100

ꢀ0

−0ꢀꢁ0

−1ꢀ00

0

Temperature (°C)

BME vs. PME/IR vs. Temperature with 25 V DC Bias

IR vs. Temperature with 25 V DC Bias (Rated Voltage)

(Rated Voltage)

1ꢀꢁꢂ0ꢈ

1ꢀꢁꢂ0ꢇ

1ꢀꢁꢂ0ꢆ

1ꢀꢁꢂ0ꢅ

1ꢀꢁꢂ0ꢄ

1ꢀꢁꢂ0ꢈ

1ꢀꢁꢂ0ꢇ

1ꢀꢁꢂ0ꢆ

1ꢀꢁꢂ0ꢅ

1ꢀꢁꢂ0ꢄ

1ꢀꢁꢂ0ꢃ

1ꢀꢁꢂ02

1ꢀꢁꢂ0ꢃ

ꢉMꢁ C0G MLCC 120ꢆꢊ10nꢋ

1ꢀꢁꢂ02

1ꢀꢁꢂ01

1ꢀꢁꢂ00

200ꢉC C0G MLCC 100nꢊ

ꢌMꢁ C0G MLCC 120ꢆꢊ10nꢋ

1ꢀꢁꢂ01

Temperature (°C)

C1001_C0G_200C_SMD • 7/29/2016

6

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Table 1A – Capacitance Range/Selection Waterfall (0402 – 1206 Case Sizes)

Case Size / Series

Voltage Code

C0402H

C0603H

C0805H

C1206H

8

4

3

5

1

8

4

3

5

1

2

8

4

3

5

1

2

8

4

3

5

1

2

Cap

Code

Capacitance

Rated Voltage (VDC)

Product Availability and Chip Thickness Codes

See Table 2 for Chip Thickness Dimensions

CF CF CF CF CF CF DN DN DN DN DN DN

CF CF CF CF CF CF DN DN DN DN DN DN EB EB EB EB EB EB

Capacitance Tolerance

0.5 & 0.75 pF

1.0 - 9.0 pF*

10 - 91 pF*

100 - 180 pF*

200 - 430 pF*

470 pF

510 pF

560 pF

620 pF

680 pF

508 & 758

109 - 919*

100 - 910*

101 - 181*

201 - 431*

471

511

561

621

681

751

821

911

102

112

122

132

152

162

182

202

222

242

272

302

332

362

392

432

472

512

562

622

682

752

822

912

103

123

153

183

223

273

333

393

473

563

683

823

104

B

C

D

BB BB BB BB

F

G

J

K

M

BB BB BB BB BB CF CF CF CF CF CF DN DN DN DN DN DN EB EB EB EB EB EB

BB BB BB BB BB CF CF CF CF CF

DN DN DN DN DN DN EB EB EB EB EB EB

DN DN DN DN DN DP EB EB EB EB EB EB

DN DN DN DN DN DN EB EB EB EB EB EB

DN DN DN DN DP DP EB EB EB EB EB EB

DN DN DN DN DP DP EB EB EB EB EB EE

750 pF

820 pF

910 pF

1,000 pF

1,100 pF

1,200 pF

1,300 pF

1,500 pF

1,600 pF

1,800 pF

2,000 pF

2,200 pF

2,400 pF

2,700 pF

3,000 pF

3,300 pF

3,600 pF

3,900 pF

4,300 pF

4,700 pF

5,100 pF

5,600 pF

6,200 pF

6,800 pF

7,500 pF

8,200 pF

9,100 pF

10,000 pF

12,000 pF

15,000 pF

18,000 pF

22,000 pF

27,000 pF

33,000 pF

39,000 pF

47,000 pF

56,000 pF

68,000 pF

82,000 pF

0.10 µF

BB BB BB BB

CF CF CF CF CF

CF CF CF CF

CF CF CF

DN DN DN DN DN

DP DP DP DP DP

DN DN DN DN DN

DP DP DP DP DN

DE DE DE DE DN

DN DN DN DN DN

DN DN DN DN DP

DN DN DN DN DE

DN DN DN DP DG

DN DN DN DP

EB EB EB EB EB EB

EB EB EB EB EC EC

EB EB EB EB ED EC

EB EB EB EB ED ED

EB EB EB EB EE EE

EB EB EB EB EC EC

EC EC EC EC EC

EC EC EC EC EE

EC EC EC EC EF

EC EC EC EC EC

ED ED ED ED ED

EB EB EB EB EB

EC EC EC EC EB

ED ED ED ED EB

EB EB EB EB EB

EB EB EB EB EC

EB EB EB EB EE

EC EC EC EE EH

ED ED ED EF

DP DP DP DF

DF DF DF

DG DG DG

EF EF EF EH

EH EH EH EH

EH EH EH

Rated Voltage (VDC)

Voltage Code

8

4

3

5

1

8

4

3

5

1

2

8

4

3

5

1

2

8

4

3

5

1

2

Capacitance

Cap Code

Case Size / Series

C0402H

C0603H

C0805H

C1206H

*Capacitance range Includes E24 decade values only. (i.e., 10, 11, 12, 13, 15, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 43, 47, 51, 56, 62, 68, 75, 82, and 91)

KEMET reserves the right to substitute product with an improved temperature characteristic, tighter capacitance tolerance and/or higher voltage

capability within the same form factor (conﬁguration and dimensions).

These products are protected under US Patents 7,172,985 and 7,670,981, other patents pending, and any foreign counterparts.

C1001_C0G_200C_SMD • 7/29/2016

7

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Table 1B – Capacitance Range/Selection Waterfall (1210 – 2220 Case Sizes)

Case Size / Series

Voltage Code

C1210H

C1812H

C2220H

8

4

3

5

1

2

8

4

3

5

1

2

8

4

3

5

1

2

Cap

Code

Capacitance

Rated Voltage (VDC)

Product Availability and Chip Thickness Codes

See Table 2 for Chip Thickness Dimensions

Capacitance Tolerance

0.5 & 0.75 pF

1.0 - 9.1 pF*

10 - 91 pF*

100 - 910 pF*

1,000 pF

1,100 pF

1,200 pF

1,300 pF

1,500 pF

1,600 pF

1,800 pF

2,000 pF

2,200 pF

2,400 pF

2,700 pF

3,000 pF

3,300 pF

3,600 pF

3,900 pF

4,300 pF

4,700 pF

5,100 pF

5,600 pF

6,200 pF

6,800 pF

7,500 pF

8,200 pF

9,100 pF

10,000 pF

12,000 pF

15,000 pF

18,000 pF

22,000 pF

27,000 pF

33,000 pF

39,000 pF

47,000 pF

56,000 pF

68,000 pF

82,000 pF

0.10 µF

508 & 758

109 - 919*

100 - 910*

101 - 911*

102

112

122

132

152

162

182

202

222

242

272

302

332

362

392

432

472

512

562

622

682

752

822

912

103

123

153

183

223

B

C

D

FB FB FB FB FB FB

FB FB FB FB FB FC

FB FB FB FB FB FE

FB FB FB FB FC FE

FB FB FB FB FC FG

FB FB FB FB FC FC

FB FB FB FB FC FF

FB FB FB FB FF FF

FF FF FF FF FG FG

FB FB FB FB FG FG

FB FB FB FB FG

FC FC FC FC FC

FE FE FE FE FE

FF FF FF FF FF

FG FG FG FG FB

FB FB FB FB FB

FB FB FB FB FE

FB FB FB FB FF

FB FB FB FC FG

FC FC FC FF FH

F

G

J

K

M

GB GB GB GB GB

GB GB GB GB GD

GB GB GB GB GH

GD GD GD GD GN

GH GH GH GH

273

333

393

473

563

683

823

104

124

154

184

224

FE FE FE FG FM

FG FG FG FH

FH FH FH FM

0.12 µF

0.15 µF

0.18 µF

0.22 µF

GK GK GK GK

0.47 µF

474

JJ JJ JJ JJ

Rated Voltage (VDC)

Voltage Code

8

4

3

5

1

2

8

4

3

5

1

2

8

4

3

5

1

2

Capacitance

Cap Code

Case Size / Series

C1210H

C1812H

C2220H

*Capacitance range Includes E24 decade values only. (i.e., 10, 11, 12, 13, 15, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 43, 47, 51, 56, 62, 68, 75, 82, and 91)

KEMET reserves the right to substitute product with an improved temperature characteristic, tighter capacitance tolerance and/or higher voltage

capability within the same form factor (conﬁguration and dimensions).

These products are protected under US Patents 7,172,985 and 7,670,981, other patents pending, and any foreign counterparts.

C1001_C0G_200C_SMD • 7/29/2016

8

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Table 2A – Chip Thickness/Tape & Reel Packaging Quantities

Paper Quantity¹

Plastic Quantity

Thickness

Code

Case Thickness ±

Size¹Range (mm)

7" Reel

13" Reel

7" Reel

13" Reel

BB

CF

DN

DP

DE

DF

DG

EB

EC

ED

EE

EF

0402

0603

0805

1206

1210

1812

2220

0.50±0.05

0.80±0.07

0.78±0.10

0.90±0.10

1.00±0.10

1.10±0.10

1.25±0.15

0.78±0.10

0.90±0.10

1.00±0.10

1.10±0.10

1.20±0.15

1.60±0.20

0.78±0.10

0.90±0.10

1.00±0.10

1.10±0.10

1.25±0.15

1.55±0.15

1.70±0.20

1.00±0.10

1.25±0.15

1.40±0.15

1.60±0.20

1.70±0.20

2.20±0.15

10,000

4,000

50,000

15,000

0

2,500

4,000

2,500

2,000

4,000

2,500

2,000

1,000

500

10,000

8,000

10,000

8,000

4,000

2,000

4,000

10,000

0

EH

FB

FC

FE

FF

FG

FH

FM

GB

GD

GH

GK

GN

JJ

7" Reel

13" Reel

7" Reel

13" Reel

Thickness

Code

Case

Size¹

Thickness ±

Range (mm)

Paper Quantity¹

Plastic Quantity

Package quantity based on ﬁnished chip thickness speciﬁcations.

¹If ordering using the 2mm Tape and Reel pitch option, the packaging quantity outlined in the table above will be doubled. This option is limited to EIA

0603 (1608 metric) case size devices. For more information regarding 2mm pitch option see “Tape & Reel Packaging Information”.

C1001_C0G_200C_SMD • 7/29/2016

9

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Table 2B – Bulk Packaging Quantities

Loose Packaging

Secure Packaging

Packaging Type

2” x 2” Wafﬂe Pack/

Bulk Bag (default)

Tray³

Packaging C-Spec¹

N/A²

7282/7292

Case Size

Packaging Quantities (pieces/unit packaging)

Chip Thickness

(mm)

EIA (in)

Metric (mm)

Minimum

Maximum

Minimum

Maximum

0402

0603

0805

1206

1210

1808

1812

1825

2220

2225

1005

1608

2012

3216

3225

4520

4532

4564

5650

5664

368

100

126

50

All

50,000

≤ 1.25 (nominal)

> 1.25 (nominal)

1

80

50

42

All

20,000

20

¹The "Packaging C-Spec" is a 4-digit code which identiﬁes the packaging type. When ordering, the proper code must be included in the 15th through

18th character positions of the ordering code. See "Ordering Information" section of this document for further details. Product ordered without a

packaging C-Spec will default to our standard "Bulk Bag" packaging.

²A packaging C-Spec (see note 1 above) is not required For "Bulk Bag" packaging (excluding Anti-Static Bulk Bag). The 15th through 18th character

positions of the ordering code should be left blank. All product ordered without a packaging C-Spec will default to our standard "Bulk Bag" packaging.

³Also commonly referred to as “Chip Carrier” or “Molded Tray”. All tray packaging options offer static protection.

C1001_C0G_200C_SMD • 7/29/2016

10

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Table 3 – Chip Capacitor Land Pattern Design Recommendations per IPC–7351

Density Level A:

Maximum (Most)

Land Protrusion (mm)

Density Level B:

Median (Nominal)

Land Protrusion (mm)

Density Level C:

Minimum (Least)

Land Protrusion (mm)

EIA

Size

Code

Metric

Size

Code

C

Y

X

V1

V2

C

Y

X

V1

V2

C

Y

X

V1

V2

0402

0603

0805

1206

1210

1210¹

1812

2220

1005

1608

2012

3216

3225

4532

5650

0.50

0.72

2.20

1.20

0.45

0.62

1.90

1.00

0.40

0.52

1.60

0.80

0.90

1.00

1.60

1.50

2.15

2.75

1.15

1.35

1.60

1.70

1.10

1.55

1.90

2.80

2.90

3.60

5.50

4.00

4.40

5.60

5.65

5.60

6.90

8.20

2.10

2.60

2.90

3.80

3.90

4.60

6.50

0.80

0.90

1.50

1.40

2.05

2.65

0.95

1.15

1.40

1.50

1.00

1.45

1.80

2.70

2.80

3.50

5.40

3.10

3.50

4.70

6.00

7.30

1.50

2.00

2.30

3.20

3.30

4.00

5.90

0.60

0.75

1.40

1.30

1.95

2.55

0.75

0.95

1.20

1.30

0.90

1.35

1.70

2.60

2.70

3.40

5.30

2.40

2.80

4.00

5.30

6.60

1.20

1.70

2.00

2.90

3.00

3.70

5.60

¹Only for capacitance values ≥ 22 µF

Density Level A: For low-density product applications. Recommended for wave solder applications and provides a wider process window for reﬂow

solder processes. KEMET only recommends wave soldering of EIA 0603, 0805 and 1206 case sizes.

Density Level B: For products with a moderate level of component density. Provides a robust solder attachment condition for reﬂow solder processes.

Density Level C: For high component density product applications. Before adapting the minimum land pattern variations the user should perform

qualiﬁcation testing based on the conditions outlined in IPC Standard 7351 (IPC–7351).

Image below based on Density Level B for an EIA 1210 case size.

V1

ꢀ

V2

ꢁ

C

Grid ꢂlacement Courtyard

C1001_C0G_200C_SMD • 7/29/2016

11

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Soldering Process

Recommended Soldering Technique:

• Solder wave or solder reﬂow for EIA case sizes 0603, 0805 and 1206

• All other EIA case sizes are limited to solder reﬂow only

Recommended Reﬂow Soldering Proﬁle:

KEMET’s families of surface mount multilayer ceramic capacitors (SMD MLCCs) are compatible with wave (single or dual),

convection, IR or vapor phase reﬂow techniques. Preheating of these components is recommended to avoid extreme thermal

stress. KEMET’s recommended proﬁle conditions for convection and IR reﬂow reﬂect the proﬁle conditions of the IPC/

J-STD-020 standard for moisture sensitivity testing. These devices can safely withstand a maximum of three reﬂow passes

at these conditions.

Termination Finish

T_ꢂ

T_L

t_ꢂ

Proﬁle Feature

Maꢁimum ꢃamp ꢄp ꢃate ꢅ ꢆꢇCꢈsec

Maꢁimum ꢃamp Doꢉn ꢃate ꢅ ꢊꢇCꢈsec

SnPb

100% Matte Sn

t_L

Preheat/Soak

Temperature Minimum (T_Smin

)

100°C

150°C

200°C

T_smaꢁ

T_smin

Temperature Maximum (T_Smax

Time (t_S) from T_Sminto T_Smax

)

60 – 120 seconds

t_s

3°C/second

maximum

3°C/second

maximum

Ramp-Up Rate (T_Lto T_P)

Liquidous Temperature (T_L)

Time Above Liquidous (t_L)

Peak Temperature (T_P)

2ꢀ

183°C

60 – 150 seconds

235°C

217°C

60 – 150 seconds

260°C

2ꢀꢇC to ꢂeaꢋ

Time

Time Within 5°C of Maximum

Peak Temperature (t_P)

20 seconds

maximum

30 seconds

maximum

6°C/second

maximum

6°C/second

maximum

Ramp-Down Rate (T_Pto T_L)

Time 25°C to Peak

Temperature

6 minutes

maximum

8 minutes

maximum

Note 1: All temperatures refer to the center of the package, measured on the

capacitor body surface that is facing up during assembly reﬂow.

C1001_C0G_200C_SMD • 7/29/2016

12

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Table 4 – Performance & Reliability: Test Methods and Conditions

Product Qualiﬁcation Test Plan

Reliability/Environmental Tests per MIL–STD–202//JESD22

High Temperature Life

Load Humidity

200°C rated voltage 1,000 hours

85°C/85%RH rated voltage 1,000 hours

85°C/85%RH, 1.5 V, 1,000 hours

Low Voltage Humidity

Temperature Cycling

Thermal Shock

−55°C to +200°C, 50 Cycles

−55°C to +150°C, 20 seconds transfer, 15 minute dwell, 300 cycles

Cycled Temp/RH 0 V, 10 cycles at 24 hours each

Moisture Resistance

Physical, Mechanical & Process Tests per MIL–STD 202/JIS–C–6429

Resistance to Solvents

Include Aqueous wash chemical, OKEM Clean or equivalent

Method 213: Figure 1, Condition F Method 204: 5 gs for 20 minutes 12 cycles

Condition B, no per-heat of samples, Single Wave Solder

Force of 1.8 kg for 60 seconds

Mechanical Shock and Vibration

Resistance to Soldering Heat

Terminal Strength

Board Flex

Appendix 2, Note: 3.0 mm (minimum)

Storage and Handling

Ceramic chip capacitors should be stored in normal working environments. While the chips themselves are quite robust in

other environments, solderability will be degraded by exposure to high temperatures, high humidity, corrosive atmospheres,

and long term storage. In addition, packaging materials will be degraded by high temperature–reels may soften or warp

and tape peel force may increase. KEMET recommends that maximum storage temperature not exceed 40°C and maximum

storage humidity not exceed 70% relative humidity. In addition, temperature ﬂuctuations should be minimized to avoid

condensation on the parts and atmospheres should be free of chlorine and sulfur bearing compounds. For optimized

solderability chip stock should be used promptly, preferably within the time frame outlined in the table below:

Termination Finish

Termination Finish Ordering Code¹

Storage Life

100% Matte Tin (Sn)

SnPb (5% Pb min.)

C

L

1.5 years upon receipt

6 months upon receipt²

1.5 years upon receipt

Gold (Au) 1.97 – 11.8 µin²

Gold (Au) 30 – 50 µin

Gold (Au) 100 µin min.

E

F

G

¹The fourteenth (14th) character position of the KEMET part number is assigned to identify and/or deﬁne the termination ﬁnish.

For more information, see “Ordering Information” section of this document.

²Gold plating option “E” devices should remain in its factory sealed moisture sensitive packaging during storage. If the factory sealed packaging is

disturbed please store any remaining packaged components in a dry box container to prevent oxidation of the termination ﬁnish.

C1001_C0G_200C_SMD • 7/29/2016

13

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Construction

Detailed Cross Section

Termination ꢆinishꢇ

C ꢈ 100ꢉ Matte Sn

L ꢈ Snꢊꢋ ꢌ ꢍꢉ ꢊꢋ min

Dielectric Material

(Caꢀrꢁ_ꢂ)

ꢅ ꢈ Gold (ꢎu) 1ꢏꢐꢑ ꢌ 11ꢏꢒ ꢓin

Dielectric

ꢆ ꢈ Gold (ꢎu) ꢂ0 ꢌ ꢍ0 ꢓin

Material (Caꢀrꢁ_ꢂ)

G ꢈ Gold (ꢎu) 100 ꢓin min

ꢃarrier Layer ꢅnd Terminationꢔ

(ꢄi)

ꢅꢕternal ꢅlectrode

(Cu)

Inner ꢅlectrodes

(ꢄi)

ꢅnd Terminationꢔ

ꢅꢕternal ꢅlectrode

(Cu)

ꢃarrier Layer

(ꢄi)

Termination ꢆinish

(See options at left)

Inner ꢅlectrodes

(ꢄi)

Capacitor Marking (Optional):

Laser marking option is not available on:

• C0G, Ultra Stable X8R and Y5V dielectric devices

• EIA 0402 case size devices

• EIA 0603 case size devices with Flexible Termination option.

• KPS Commercial and Automotive grade stacked devices.

These capacitors are supplied unmarked only.

C1001_C0G_200C_SMD • 7/29/2016

14

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Tape & Reel Packaging Information

KEMET offers multilayer ceramic chip capacitors packaged in 8, 12 and 16 mm tape on 7" and 13" reels in accordance with

EIA Standard 481. This packaging system is compatible with all tape-fed automatic pick and place systems. See Table 2 for

details on reeling quantities for commercial chips.

ꢕar Code Laꢊel

ꢆntiꢇStatic ꢈeel

®

ꢉmꢊossed ꢋlasticꢌ or

ꢋunched ꢋaper Carrierꢃ

Chip and ꢑꢋS ꢒrientation in ꢋocꢐet

(eꢏcept 1ꢀ2ꢓ Commercial, and 1ꢀ2ꢓ and 222ꢓ Military)

KEMET

Sprocꢐet Holes

ꢉmꢊossment or ꢋunched Caꢍity

ꢀ mm, 12 mm

or 1ꢁ mm Carrier Tape

ꢆntiꢇStatic Coꢍer Tape

(ꢃ10 mm (ꢃ00ꢎꢄ) Maꢏimum Thicꢐness)

1ꢂꢀ mm (ꢂꢃ00ꢄ)

or

ꢅꢅ0 mm (1ꢅꢃ00ꢄ)

ꢌꢉIꢆ 0100ꢓ, 0201, 0ꢎ02 and 0ꢁ0ꢅ case siꢔes aꢍailaꢊle on punched paper carrier onlyꢃ

Table 5 – Carrier Tape Conﬁguration, Embossed Plastic & Punched Paper (mm)

New 2 mm Pitch Reel Options*

Embossed Plastic Punched Paper

Tape

Packaging

Ordering Code

(C-Spec)

C-3190

7" Reel 13" Reel 7" Reel 13" Reel

EIA Case Size Size

(W)*

Packaging Type/Options

Pitch (P₁)* Pitch (P₁)*

01005 – 0402

0603

8

2

2/4

4

Automotive grade 7" reel unmarked

Automotive grade 13" reel unmarked

Commercial grade 7" reel unmarked

Commercial grade 13" reel unmarked

C-3191

2/4

4

C-7081

0805

8

4

C-7082

1206 – 1210

1805 – 1808

≥ 1812

8

4

* 2 mm pitch reel only available for 0603 EIA case size.

2 mm pitch reel for 0805 EIA case size under development.

12

16

8

4

8

Beneﬁts of Changing from 4 mm to 2 mm Pitching Spacing

• Lower placement costs

• Double the parts on each reel results in fewer reel

changes and increased efﬁciency

• Fewer reels result in lower packaging, shipping and

storage costs, reducing waste

KPS 1210

8

KPS 1812 & 2220

Array 0508 & 0612

12

4

12

4

*Refer to Figures 1 & 2 for W and P₁carrier tape reference locations.

*Refer to Tables 6 & 7 for tolerance speciﬁcations.

C1001_C0G_200C_SMD • 7/29/2016

15

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Figure 1 – Embossed (Plastic) Carrier Tape Dimensions

T

ꢀ 2

ꢍ10 pitches cumulatiꢃe

tolerance on tape ꢎ 0ꢏ2 mmꢐ

2

ꢉ

1

ꢀo

ꢈDo

ꢄo

ꢁ

ꢆo

ꢂ

ꢉ

2

ꢅ

1

ꢅo

S

1

ꢀ

1

T

1

ꢉmꢇossment

ꢁor caꢃity siꢊe,

see ꢋote 1 Taꢇle ꢌ

Center Lines of Caꢃity

ꢈD

1

Coꢃer Tape

is for tape feeder reference only,

including draft concentric aꢇout ꢅ

ꢅ

1

o

.

User Direction of Unreeling

Table 6 – Embossed (Plastic) Carrier Tape Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

D₁Minimum

Note 1

R ReferenceS₁Minimum

T

T₁

Tape Size

8 mm

D₀

E₁

P₀

P₂

Note 2

Note 3

Maximum Maximum

1.0

(0.039)

25.0

(0.984)

1.5+0.10 −0.0

(0.059+0.004 −0.0)

1.75±0.10

4.0±0.10

2.0±0.05

0.600

(0.024)

0.600

(0.024)

0.100

(0.004)

12 mm

16 mm

(0.069±0.004) (0.157±0.004) (0.079±0.002)

1.5

(0.059)

30

(1.181)

Variable Dimensions — Millimeters (Inches)

B₁Maximum

Note 4

E₂

T₂

W

Tape Size

8 mm

Pitch

F

P₁

A₀,B₀& K₀

Minimum

6.25

(0.246)

Maximum Maximum

4.35

(0.171)

3.5±0.05

4.0±0.10

2.5

8.3

(0.327)

Single (4 mm)

(0.138±0.002) (0.157±0.004) (0.098)

Single (4 mm) &

Double (8 mm)

8.2

10.25

5.5±0.05

8.0±0.10

4.6

12.3

12 mm

16 mm

Note 5

(0.323)

(0.404)

(0.217±0.002) (0.315±0.004) (0.181)

(0.484)

12.1

(0.476)

14.25

(0.561)

7.5±0.05 12.0±0.10 4.6

(0.138±0.002) (0.157±0.004) (0.181)

16.3

(0.642)

Triple (12 mm)

1. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. Dimensions of embossment

location and hole location shall be applied independent of each other.

2. The tape with or without components shall pass around R without damage (see Figure 6).

3. If S₁< 1.0 mm, there may not be enough area for cover tape to be properly applied (see EIA Standard 481 paragraph 4.3 section b).

4. B₁dimension is a reference dimension for tape feeder clearance only.

5. The cavity deﬁned by A₀, B₀and K₀shall surround the component with sufﬁcient clearance that:

(a) the component does not protrude above the top surface of the carrier tape.

(b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.

(c) rotation of the component is limited to 20° maximum for 8 and 12 mm tapes and 10° maximum for 16 mm tapes (see Figure 3).

(d) lateral movement of the component is restricted to 0.5 mm maximum for 8 and 12 mm wide tape and to 1.0 mm maximum for 16 mm tape

(See Figure 4).

(e) for KPS Series product, A₀and B₀are measured on a plane 0.3 mm above the bottom of the pocket.

(f) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.

C1001_C0G_200C_SMD • 7/29/2016

16

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Figure 2 – Punched (Paper) Carrier Tape Dimensions

T

ꢌ10 pitches cumulatiꢀe

tolerance on tape ꢍ 0ꢎ2 mmꢏ

ꢃ¹

ꢁo

ꢂDo

ꢆ⁰

ꢄ

ꢅ

ꢃ²

ꢇ⁰

ꢇottom Coꢀer Tape

ꢁ¹

G

Caꢀity Siꢈe,

See

T¹

Center Lines of Caꢀity

Top Coꢀer Tape

ꢉote 1, Taꢊle ꢋ

ꢇottom Coꢀer Tape

User Direction of Unreeling

Table 7 – Punched (Paper) Carrier Tape Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

R Reference

Note 2

Tape Size

8 mm

D₀

E₁

P₀

P₂

T₁Maximum

G Minimum

0.10

1.5 +0.10 -0.0

(0.059 +0.004 -0.0)

1.75 ±0.10

(0.069 ±0.004)

4.0 ±0.10

(0.157 ±0.004)

2.0 ±0.05

(0.079 ±0.002)

0.75

(0.030)

25

(0.984)

(0.004)

Maximum

Variable Dimensions — Millimeters (Inches)

Tape Size

8 mm

Pitch

E2 Minimum

F

P₁

T Maximum

W Maximum

A₀B₀

2.0 ±0.05

(0.079 ±0.002)

4.0 ±0.10

8.3

(0.327)

8.3

Half (2 mm)

Single (4 mm)

6.25

(0.246)

3.5 ±0.05

(0.138 ±0.002)

1.1

(0.098)

Note 1

8 mm

(0.157 ±0.004)

(0.327)

1. The cavity deﬁned by A₀, B₀and T shall surround the component with sufﬁcient clearance that:

a) the component does not protrude beyond either surface of the carrier tape.

b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.

c) rotation of the component is limited to 20° maximum (see Figure 3).

d) lateral movement of the component is restricted to 0.5 mm maximum (see Figure 4).

e) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.

2. The tape with or without components shall pass around R without damage (see Figure 6).

C1001_C0G_200C_SMD • 7/29/2016

17

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Packaging Information Performance Notes

1. Cover Tape Break Force: 1.0 Kg minimum.

2. Cover Tape Peel Strength: The total peel strength of the cover tape from the carrier tape shall be:

Tape Width

8 mm

Peel Strength

0.1 to 1.0 Newton (10 to 100 gf)

0.1 to 1.3 Newton (10 to 130 gf)

12 and 16 mm

The direction of the pull shall be opposite the direction of the carrier tape travel. The pull angle of the carrier tape shall be

165° to 180° from the plane of the carrier tape. During peeling, the carrier and/or cover tape shall be pulled at a velocity of

300 ±10 mm/minute.

3. Labeling: Bar code labeling (standard or custom) shall be on the side of the reel opposite the sprocket holes. Refer to EIA

Standards 556 and 624.

Figure 3 – Maximum Component Rotation

°

T

Maximum Component Rotation

Top View

Maximum Component Rotation

Side View

Typical ꢆocꢇet Centerline

Tape

Maximum

°

T

s

Width (mm) Rotation (

)

ꢂ,12

1ꢃ – 200

20

10

ꢁo

Tape

Maximum

°

S

Width (mm) Rotation (

)

ꢂ,12

1ꢃ – ꢄꢃ

ꢅ2 – 200

20

10

ꢄ

Typical Component Centerline

ꢀo

Figure 4 – Maximum Lateral Movement

Figure 5 – Bending Radius

ꢂmꢃossed

Carrier

ꢄunched

Carrier

ꢃ mm ꢄ 12 mm Tape

1ꢅ mm Tape

0ꢀꢁ mm maꢂimum

1ꢀ0 mm maꢂimum

ꢀ

ꢁending

ꢀadius

ꢀ

C1001_C0G_200C_SMD • 7/29/2016

18

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Figure 6 – Reel Dimensions

ꢂull ꢃadius,

ꢌꢍ (Includes

flange distortion

at outer edge)

ꢀccess Hole at

Slot Location

(ꢅ ꢆ0 mm minimum)

See ꢁote

ꢌ2 (Measured at huꢎ)

D

(See ꢁote)

ꢀ

ꢁ

C

(ꢀrꢎor hole

ꢌ1 (Measured at huꢎ)

diameter)

If present,

tape slot in core

for tape startꢇ

2ꢈꢉ mm minimum ꢊidth ꢋ

10ꢈ0 mm minimum depth

ꢄ

(see ꢁote)

ꢁoteꢇ Driꢏe spoꢐes optionalꢑ if used, dimensions ꢄ and D shall applyꢈ

Table 8 – Reel Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

Tape Size

8 mm

A

B Minimum

C

D Minimum

178 ±0.20

(7.008 ±0.008)

or

1.5

(0.059)

13.0 +0.5/-0.2

(0.521 +0.02/-0.008)

20.2

(0.795)

12 mm

16 mm

330 ±0.20

(13.000 ±0.008)

Variable Dimensions — Millimeters (Inches)

Tape Size

8 mm

N Minimum

W₁

W₂Maximum

W₃

8.4 +1.5/-0.0

(0.331 +0.059/-0.0)

14.4

(0.567)

50

(1.969)

12.4 +2.0/-0.0

18.4

Shall accommodate tape

width without interference

12 mm

16 mm

(0.488 +0.078/-0.0)

(0.724)

16.4 +2.0/-0.0

(0.646 +0.078/-0.0)

22.4

(0.882)

C1001_C0G_200C_SMD • 7/29/2016

19

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Figure 7 – Tape Leader & Trailer Dimensions

ꢃmꢊossed Carrier

Carrier Tape

ꢇunched Carrier

ꢈ mm ꢉ 12 mm only

ꢁound Sprocꢂet Holes

START

END

Top Coꢆer Tape

ꢃlongated Sprocꢂet Holes

(ꢄ2 mm tape and ꢅider)

100 mm

Minimum Leader

ꢋ00 mm Minimum

Trailer

Components

1ꢀ0 mm Minimum

Top Coꢆer Tape

Figure 8 – Maximum Camber

ꢃlongated sprocꢁet holes

(ꢅ2 mm ꢆ ꢇider tapes)

Carrier Tape

ꢀound Sprocꢁet Holes

1 mm Maꢂimum, either direction

Straight ꢃdge

2ꢄ0 mm

C1001_C0G_200C_SMD • 7/29/2016

20

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Wafﬂe Tray Packaging Information – 2" x 2" w/ Static Protection

Figure 9 – Wafﬂe Tray Dimensions – Inches (Millimeters)

M

M3

0.10 (2.54) X 45°

M1

M2

Y

X

A

Z

0.098

(2.489)

0.156 +0.002/-0.003

(3.962 +0.051/-0.076)

0.086

(2.184)

0.004

90°

(0.102)

2.000 ±0.004 SQ

(50.800 ±0.102 SQ)

1.800 ±0.004 SQ

(45.720 ±0.102 SQ)

1.812 ±0.004 SQ

(46.025 ±0.102 SQ)

STANDARD RIB MATRIX

C1001_C0G_200C_SMD • 7/29/2016

21

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

Table 9A – Wafﬂe Tray Dimensions – Inches

2" x 2" Wafﬂe Tray Dimensions – Inches

Packaging Quantity

(pcs/unit

Case Size

M

M1

M2

M3

X

Y

Z

A°

MATRIX

EIA (in) Metric (mm) ±0.003

±0.003

±0.002

±0.003

± 1/2°

7

5

7

10

5

(X x Y)

packaging)

0402

0504

0603

0805

1005

1206^1,2

1206^1,3

1210

1005

1210

1608

2012

2512

3216

3225

4520

4532

4564

5650

5664

0.175

0.235

0.175

0.232

0.230

0.194

0.250

0.217

0.271

0.318

0.153

0.226

0.153

0.186

0.240

0.228

0.250

0.244

0.285

0.362

0.077

0.172

0.077

0.181

0.190

0.193

0.375

0.215

0.286

0.424

0.110

0.170

0.110

0.171

0.140

0.124

0.167

0.174

0.243

0.34

0.073

0.080

0.073

0.062

0.060

0.067

0.100

0.110

0.150

0.24

0.042

0.090

0.042

0.092

0.110

0.130

0.200

0.145

0.200

0.32

0.041

0.055

0.041

0.036

0.075

0.065

0.070

0.080

0.075

0.032

16 X 23

10 X 10

16 X 23

10 X 10

12 X 9

14 X 9

10 X 5

10 X 8

7 X 6

5 X 4

368

100

368

100

108

126

50

80

42

20

1808

1812

5

1825

2220

2225

0.34

0.24

0.32

20

¹Packaging of 1206 (3216 metric) case size capacitors is dependent upon the nominal chip thickness of the device. See "Capacitance Range/Selection

Waterfall" and "Chip Thickness/Tape & Reel Packaging Quantities" to identify the nominal chip thickness of the capacitor.

²Assigned to 1206 (3216 metric) case size capacitors with nominal thickness of ≤ 1.25mm (0.049 inches).

³Assigned to 1206 (3216 metric) case size capacitors with nominal thickness of > 1.25mm (0.049 inches).

Table 9B – Wafﬂe Tray Dimensions – Millimeters

2" x 2" Wafﬂe Tray Dimensions – Millimeters

Packaging Quantity

(pcs/unit

Case Size

M

M1

M2

M3

X

Y

Z

A°

MATRIX

EIA (in) Metric (mm) ±0.08

±0.08

±0.05

±0.08

± 1/2°

7

5

7

10

5

(X x Y)

packaging)

0402

0504

0603

0805

1005

1206^1,2

1206^1,3

1210

1005

1210

1608

2012

2512

3216

3225

4520

4532

4564

5650

5664

4.45

5.97

4.45

5.89

5.84

4.93

6.35

5.51

6.88

8.08

3.89

5.74

3.89

4.72

6.10

5.79

6.35

6.20

7.24

9.19

1.96

4.37

1.96

4.60

4.83

4.90

9.53

5.46

7.26

2.79

4.32

2.79

4.34

3.56

3.15

4.24

4.42

6.17

8.64

1.85

2.03

1.85

1.57

1.52

1.70

2.54

2.79

3.81

6.10

1.07

2.29

1.07

2.34

2.79

3.30

5.08

3.68

5.08

8.13

1.04

1.40

1.04

0.91

1.91

1.65

1.78

2.03

1.91

0.81

16 X 23

10 X 10

16 X 23

10 X 10

12 X 9

14 X 9

10 X 5

10 X 8

7 X 6

5 X 4

368

100

368

100

108

126

50

80

42

20

1808

1812

7.26

5

1825

2220

2225

10.77

20

¹Packaging of 1206 (3216 metric) case size capacitors is dependent upon the nominal chip thickness of the device. See "Capacitance Range/Selection

Waterfall" and "Chip Thickness/Tape & Reel Packaging Quantities" to identify the nominal chip thickness of the capacitor.

²Assigned to 1206 (3216 metric) case size capacitors with nominal thickness of ≤ 1.25mm (0.049 inches).

³Assigned to 1206 (3216 metric) case size capacitors with nominal thickness of > 1.25mm (0.049 inches).

C1001_C0G_200C_SMD • 7/29/2016

22

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

High Temperature (200°C), C0G Dielectric, 10 – 200 VDC (Industrial Grade)

KEMET Electronic Corporation Sales Ofﬁces

For a complete list of our global sales ofﬁces, please visit www.kemet.com/sales.

Disclaimer

All product speciﬁcations, statements, information and data (collectively, the “Information”) in this datasheet are subject to change. The customer is responsible for

checking and verifying the extent to which the Information contained in this publication is applicable to an order at the time the order is placed.

All Information given herein is believed to be accurate and reliable, but it is presented without guarantee, warranty, or responsibility of any kind, expressed or implied.

Statements of suitability for certain applications are based on KEMET Electronics Corporation’s (“KEMET”) knowledge of typical operating conditions for such

applications, but are not intended to constitute – and KEMET speciﬁcally disclaims – any warranty concerning suitability for a speciﬁc customer application or use.

The Information is intended for use only by customers who have the requisite experience and capability to determine the correct products for their application. Any

technical advice inferred from this Information or otherwise provided by KEMET with reference to the use of KEMET’s products is given gratis, and KEMET assumes no

obligation or liability for the advice given or results obtained.

Although KEMET designs and manufactures its products to the most stringent quality and safety standards, given the current state of the art, isolated component

failures may still occur. Accordingly, customer applications which require a high degree of reliability or safety should employ suitable designs or other safeguards

(such as installation of protective circuitry or redundancies) in order to ensure that the failure of an electrical component does not result in a risk of personal injury or

property damage.

Although all product–related warnings, cautions and notes must be observed, the customer should not assume that all safety measures are indicted or that other

measures may not be required.

KEMET is a registered trademark of KEMET Electronics Corporation.

C1001_C0G_200C_SMD • 7/29/2016

23


型号：	C1812H154J1GAC7800
厂家：	KEMET CORPORATION
描述：	Ceramic Capacitor, Multilayer, Ceramic, 100V, 5% +Tol, 5% -Tol, C0G, 30ppm/Cel TC, 0.15uF, Surface Mount, 1812, CHIP
文件：	总23页 (文件大小：1700K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

C1812H154J1GAC7800 [KEMET]

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