M3102A-CH2 [KEYSIGHT]
PXIe Digitizers with Optional Real-Time Sequencing and FPGA Programming;
| 型号： | M3102A-CH2 |
| 厂家： | 
Keysight Technologies |
| 描述： | PXIe Digitizers with Optional Real-Time Sequencing and FPGA Programming |
| 文件： | 总9页 (文件大小：1004K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Keysight M3102A
PXIe Digitizers with Optional Real-Time
Sequencing and FPGA Programming
500 MSa/s, 14 Bits, 2/4 Channels
Data Sheet
02 | Keysight | M3102A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Improve Your Measurement Fidelity, Signal Integrity
and Measurement Throughput
The M3102A are high-performance, high-bandwidth digitizers with an advanced
data acquisition system (DAQ). Performance meets simplicity thanks to easy-to-use
programming libraries, real-time sequencing technology (Hard Virtual Instrumentation
or HVI), and graphical FPGA programming technology.
Features
500 MSa/s simultaneous sampling, 14 bits, 2/4 channels, 200 MHz BW
Advanced data acquisition system (DAQ)
– Flexible triggering (HW trigger, HVI trigger, SW trigger)
– Programmable cycles and data bursts to avoid PC saturation
Optional HW programming for high-performance applications
– Real-time sequencing (HVI technology)
– FPGA programming
– Xilinx Kintex-7, 325T or 410T FPGA
Up to 2 GB of onboard RAM (~ 1 Gsamples)
Mechanical/interface
– 1 slot 3U (PXIe)
– Up to 200 MB/s transfer BW with P2P capabilities
– Independent DMA channels for fast and efficient data transfer
Applications
General purpose digitizer
BB electronics designs and manufacturing in wireless devices
R&D/scientific research equipment
Aerospace & defense (A/D), angle of arrival (AoA)
03 | Keysight | M3102A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Programming technology and software tools
Software programming
– Easy-to-use native programming libraries for most common languages: C, C++, Visual
Studio, LabVIEW, MATLAB, Python, and more
Hardware programming (optional)
– Real-time sequencing ((Hard Virtual Instrumentation or HVI technology))
– Graphical flowchart-style M3601A design environment (-HV1 option required on HW)
– Ultra-fast, fully-parallelized hard real-time execution
– Ultra-fast, time-deterministic decision-making
– Off-the-shelf inter-module synchronization & data exchange
– FPGA programming
– Graphical M3602A FPGA design environment (-FP1 option required on HW)
– No FPGA know-how required
– Include high-level to low-level design elements: off-the-shelf DSP blocks, MATLAB/
Simulink designs, Xilinx CORE Generator IP cores, Xilinx VIVADO/ISE projects, VHDL
or Verilog code
– Ultra-fast, one-click compiling and on-the-fly programming
No programming
– Ready-to-use SD1 SPF (software front panels)
M31XX/M32XX/M33XX family product table
Outputs (AWGs)
Inputs (Digitizers)
Product
Type
Speed
Bits
Ch
BW
Speed
Bits
Ch
BW
(MSa/s)
(MHz)
(MSa/s)
(MHz)
M3202A
M3201A
M3102A
M3100A
M3302A
M3300A
AWG
1000
500
14
16
2/4
2/4
400
200
AWG
Digitizer
Digitizer
Combo
Combo
500
100
500
100
14
14
14
14
2/4
4/8
2
200
200
200
200
500
500
16
16
2
200
200
2/4
4/8
04 | Keysight | M3102A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Functional block diagram
Channel 1
Channel 1
output
Channel x
Input settings
Full scale, ꢀ,
coupling (as
available)
Prescaler
ꢁ
Data
acquisition
(DAQx)
Channel x
output
Analog
trigger
Channel n
Channel n
output
Figure 1. M3102A input functional block diagram, all channels have identical input structure
Ordering information
Product
Description
M3102A
PXIe digitizer: 500 MSa/s, 14 Bits
Options
Description
M3102A-CH2 / -CH4
M3102A-CLV / -CLF
M3102A-M01 / -M12 / -M20
HW programming options
M3102A-HVI
Two channels / four channels
Variable sampling clock / fixed sampling clock, low jitter
Memory 16 MB, 8 MSamples / 128 MB, 60 MSamples / 2 GB, 1 GSamples
Description
Enabled HVI programming, requires an HVI design environment license (M3601A)
Enabled FPGA programming, requires -K32 or -K41 option and an FPGA design environment license (M3602A)
FPGA, Xilinx 7K325T / 7K410T, required for -FP1 option only (needs memory option -M20)
M3102A-FP1
M3102A-K32 / -K41
All options must be selected at time of purchase and are not upgradable
These options represent the standard configuration
Related software
M3601A
Description
HVI design environment
FPGA design environment
M3602A
05 | Keysight | M3102A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Input specifications
Specifications summary
M3102A-CH2
M3102A-CH4
Typ
Parameter
Min
Typ
Max
Min
Max Units
Comments
Inputs and outputs
Channels
2
1
1
1
8
4
1
1
1
8
Out
Reference clock 1
Reference clock 2
Triggers/markers 1, 3
Triggers/markers 2, 3
Input channels overview
Sampling rate 4
Out
In
In/out
In/out
Reconfigurable
Reconfigurable
500
14
500
14
MSa/s
Bits
Voltage resolution
Input frequency
0
200
0
200 MHz
MHz
Real-time BW
200
200
Time skew
< 50
< 50
ps
Between channels
Built-in functionalities
Input conditioning blocks
Analog trigger processors
Data acquisition blocks
Onboard memory
RAM memory
2
2
2
4
4
4
1 per channel
1 per channel
1 per channel
16
2048
16
2048 MBytes
1. At front panel
2. At backplane
3. Markers available from firmware version v3.0 or later
4. 100 to 500 MSa/s (-CLV) option with variable sampling clock
Table 1. General specifications
06 | Keysight | M3102A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
I/O specifications
Analog input characteristics
Number of channels
Sampling rate
CH2 or CH4
500 MSa/s option CLF (Table 4)
variable rate option CLV (Table 4)
Configurable inputs: impedance
Configurable inputs: Coupling
Input voltage range (50Ω)
Input voltage range (HiZ)
50Ω or 1MΩ (HiZ)
AC or DC
125 mVpp to 8Vpp (7 scales: 0.125, 0.25, 0,5, 1, 2, 4, 8 Vpp)
200 mVpp to 16Vpp (7 scales: 0.2, 0.4, 0.8, 2, 4, 8, 16 Vpp)
200 MHz
Bandwidth limit filters
Effective number of bits (ENOB)1
Noise floor1
10.6 bits @ 95 MHz (typical)
-146 dBm/Hz
SINAD1
66 dB @ 95 MHz (typical)
Spurious free dynamic range (SFDR) + Total Harmonic Distorsion1
71 dBc @ 95 MHz (typical)
1. Measured at -1 DBFS input signal with 1 Vpp 50Ω
Table 2a.
M3102A
Parameter
Min
Typ
Max
Units
Comments
Reference clock output
Frequency
10 to 12.52
MHz
mVpp
dBm
Ω
Generated from the internal clock. User selectable
Voltage
800
2
On a 50 Ω load
On a 50 Ω load
AC coupled
Power
Source impedance
50
External I/O trigger/marker
VIH
2
0
5
V
VIL
0.8
3.3
0.25
V
VOH
2.4
0
V
On a high Z load
On a high Z load
VOL
V
Input impedance
Source impedance
Speed
10
K Ω
–
TTL
100
MHz
2.
CLF option is set to 10 MHz while with CLV option varies from 12.5 MHz to 10 MHz
Table 2b.
07 | Keysight | M3102A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Data acquisition blocks (DAQs) specifications
M3102A-CH2
M3102A-CH4
Typ
Parameter
Min
Typ
2
Max
Min
Max Units
Comments
General specifications
DAQs
4
5
1 per channel
Aggregated speed
Acquisition burst multiple
Acquisition RAM capacity
Acquisition RAM capacity effic.
Trigger
1000
2000 MSa/s
For all onboard DAQs combined
5
Samples Burst length must be a multiple of this value
957M Samples Maximum depends on onboard RAM
15
957M
15
93.5
93.5
%
Effic. = waveform size / waveform size in RAM
Selec.
Selec.
Hardware trigger (analog channels, input trigger,
backplane triggers), software trigger
DAQ specifications
Speed
500
500 MSa/s
Bits
Per DAQ
Resolution
14
14
Table 3. Data acquisition blocks (DAQs) specifications
Clock system specifications
M3102A
Parameter
Min
Max
Units
Comments
General specifications
Clock frequency (-CLF)
Clock frequency (-CLV)
500
100
500
500
MHz
MHz
Fixed clock
Variable clock
Table 4. Clock system specifications
System specifications
Environmental specifications (PXI Express)
M3102A-CH2
M3102A-CH4
Typ
Parameter
Min
Typ
Max
Min
Max Units
Comments
System bus
Slots
1
1
Slot
PXI Express (CompactPCI Express compatible)
Automatic gen negotiation, chassis dependent
Automatic lane negotiation, chassis dependent
PCI Express type
PCI Express link
Power dissipation
3.3V PXIe power supply
12V PXIe power supply
Gen 1
1
Gen 2 Gen 1
Gen 2
4
–
4
1
Lanes
1.5
2
1.5
2
A
A
~ 5 W
~ 24 W
Table 5. Environmental specifications (PXI Express)
08 | Keysight | M3102A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
Environmental
Temperature range
Operating
0 to +55°C (10,000 feet)
Non-operating
-40 to +70°C (up to 15,000 feet)
Max operative altitude
4000 m (10,000 feet)
10 to 95% at 40°C
5 to 95%
Operating Humidity range (%RH)
Non-operating Humidity range (%RH): 5 to 95
Calibration interval
1 year
EMC
Complies with European EMC Directive
– IEC/EN 61326-1
– CISPR Pub 11 Group 1, class A
This ISM device Compliace with Canadian ICES-001
Cet appareil ISM est conforme à la norme NMB-001 du Canada.
This ISM device Compliace with Australian and New Zealand RCM
This ISM device Compliace with South Korea EMC KCC
Table 6. Environmental
Samples of this product have been type tested in accordance with the Keysight Environmental Test Manual and verified to be robust
against the environmental stresses of Storage, Transportation and End-use; those stresses include but are not limited to temperature,
humidity, shock, vibration, altitude and power line conditions. Test Methods are aligned with IEC 60068-2 and levels are similar to
MIL-PRF-28800F Class 3.
09 | Keysight | M3102A PXIe Digitizer with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
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© Keysight Technologies, 2017
Published in USA, May 4, 2017
5992-1805EN
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