U4164A-016_技术文档

Keysight U4164A

Logic Analyzer Module

with Options up to 4 Gb/s State Mode and 10 GHz Timing Mode

Data Sheet

02 | Keysight | U4164A Logic Analyzer Module - Data Sheet

Table of Contents

Product Description ............................................................................................................................

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7

Dual-Sample State Mode....................................................................................................................

Quad-Sample State Mode ....................................................................................................................

State Mode Clock Inputs and Clock Qualiﬁers ..................................................................................

Timing Zoom ........................................................................................................................................

Deep Trace Captures ..........................................................................................................................

DDR Measurements Made Fast, Easy, and Powerful .......................................................................

Burst Trigger and Trigger Macros .......................................................................................................

Signal Integrity Insight Made Fast and Easy......................................................................................

Harness your Logic Analyzer and Scope for Powerful Insight..........................................................

Programmability...................................................................................................................................

Operating Modes .................................................................................................................................

Optional Hardware ..............................................................................................................................

Optional Software ...............................................................................................................................

Probe/Cables As Required to Connect to the Target System...........................................................

U4164A State Speed Option Requirements for DDR/LPDDR Data Rates ......................................

U4164A Includes .................................................................................................................................

U4164A Requires..................................................................................................................................

Minimal Hardware................................................................................................................................

Typical Conﬁgurations ........................................................................................................................

Related Products ................................................................................................................................

Technical Speciﬁcations and Characteristics.....................................................................................

Environmental and Physical ...............................................................................................................

Ordering................................................................................................................................................

Warranty and Calibration....................................................................................................................

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03 | Keysight | U4164A Logic Analyzer Module - Data Sheet

Product Description

The Keysight Technologies, Inc. U4164A logic analyzer system combines reliable data capture

with powerful analysis and validation tools to enable you to quickly and conﬁdently validate and

debug high-speed digital designs operating at speeds up to 4 Gb/s. The U4164A logic analyzer

module delivers the following unique capabilities that enable you to make measurements and

achieve levels of insight unavailable with other logic analyzers:

– Quad sample state mode provides four samples with two different threshold settings from

a single-touch connection to high-speed data signals under test ¹

– Dual sample, dual threshold state mode

– Clock hysteresis allows the user to deﬁne a hysteresis range about the clock threshold

– 10 GHz ¼ channel conventional and transitional timing mode ²

– Software tool for timing de-skew

– 400 Mb (sample) memory depth option

– Four speed options corresponding to the state clock rate, data rate, and timing mode

sample rates

Applications

– Functional validation of memory systems and other high-speed digital systems operating

up to 4 Gb/s

– Debug of hardware and software in high-speed digital systems operating up to 4 Gb/s

– Qualitative bus level signal integrity insight using eye scan or DDR eye scan

Features

– State capture up to 4 Gb/s on 68 channels, 2.5 Gb/s on 136 channels per module

– Reliable data capture on eye openings as small as 100 ps by 100 mV

– 12.5 GHz timing zoom with 256 K sample memory

– Memory depth up to 400 M samples

– Wide variety of probing solutions including BGA, interposer, mid-bus, and ﬂying leads

– Up to 10,880 channels in a system using Multiframe

User values

– Conﬁdence in state measurements with signal eye openings as small as 100 ps by 100 mV

– Rapidly view signal integrity information in a matter of minutes on all the buses in your

design under a wide variety of operating conditions

– Quickly and easily set up complex DDR and LPDDR measurements

– 350 MHz, 700 MHz, 1.4 GHz, and 2.5 GHz state speed options: Purchase the level of state

speed capture capability you need now and upgrade as your state speed needs increase.

The U4164A with the 2.5 GHz state speed option allows you to capture the highest speeds

(up to 4 Gb/s) for DDR/LPDDR memory systems

– Dual-sample state mode: set separate sample positions and thresholds for DDR/LPDDR

read/write captures for data rates less than 2500 Mb/s from one probe point

– Quad-sample state mode: set separate sample positions and thresholds for DDR/LPDDR

read/write and rising/falling edge captures for data rates greater than 2500 Mb/s from one

probe point

– Clock hysteresis: avoid false sampling on noisy clock inputs when differential clocks turn

off

– 10 GHz quarter channel conventional and transitional timing mode: Identify timing

problems in deep traces with high sample resolution

– 400 Mb (sample) memory depth option: Capture more system activity so you can debug

complex problems when the symptom and root cause are widely separated in time

1. Available in Option -02G

2. Available in Options -01G and -02G

04 | Keysight | U4164A Logic Analyzer Module - Data Sheet

Product Description (Continued)

Beyond being a powerful general purpose logic analysis system, the U4164A system includes

speciﬁc tools and features to enable powerful debug, validation and analysis of DDR and

LPDDR memory systems.

Figure 1A shows the Read DQ and DQS eyes associated with byte lane 0 on a DDR4 system

operating at 3300 Mb/s data rate. This screen shot is captured in signal trace mode with no

back-to-back bursts so that the eyes for the entire burst of eight are displayed. The trace was

captured using the FS2510AB DDR4 DIMM interposer providing double probe points of each

DDR4 DQ with the logic analyzer module in dual-sample state mode. The U4164A logic analyzer

uses its unique eye scan capability to automatically place the sampling point in both time and

voltage within the eye on each individual channel for optimal sampling reliability.

Figure 1A. DDR4 3300 Mb/s read DQ bursts for bits D2 – D7 and DQS0.

05 | Keysight | U4164A Logic Analyzer Module - Data Sheet

Product Description (Continued)

Figure 1B shows the trigger setup to capture a burst of eight DDR4 writes using the unique

Keysight burst trigger that captures precise sequences of two to eight patterns per burst

recognizer. (The U4164A has up to eight burst detectors.) The trigger sequencer operates up

to 2.5 GHz, enabling accurate and precise triggering on DDR4 read or write bursts of DQ up to

4 Gb/s with each DQ sampled simultaneously for both a rising edge and falling edge sample.

Notice that the exact write DQ burst in the trigger is at the trigger point in both the waveform

and listing displays. The trigger marker is red and is found at the last sample in the DDR4 write

burst. The green marker is for the start of the write burst and the yellow marker in the listing is

at the write command where the B4661A DDR4 decoder has assembled the DQ with the write

command and associated row and column addresses.

Figure 1B. DDR4 3300 Mb/s burst trigger for speciﬁc write DQ burst.

Figure 1C shows the state listing and Figure 1D shows the waveform for this capture using the

B4661A DDR decoder. Figure 1E shows the transaction decode option and trafﬁc overview of

the DDR4 3300 Mb/s trace using the B4661A performance analysis software.

Figure 1C. DDR4 3300 Mb/s listing.

06 | Keysight | U4164A Logic Analyzer Module - Data Sheet

Product Description (Continued)

Figure 1D. DDR4 3300 Mb/s state waveform.

Figure 1E. DDR4 3300 Mb/s state waveform.

There are two methods to capture DDR or LPDDR memory DQ (data) transactions over

2500 Mb/s using the U4164A logic analyzer system:

1. Using quad-sample state mode, the U4164A is sampled on one clock edge, a single

probe load is placed on each DQ, and quad-sample mode is used to provide separate

read rising, read falling, write rising, and write falling edge captures with sample

positions set independently. Read and write thresholds can be set independently. Read

rising, read falling, write rising, and write falling edge captures are given different labels

in the conﬁguration so that the sample positions can be set independently.

2. Using dual-sample state mode, the U4164A is sampled on one clock edge, double

probing of each DQ must be performed and provide separate read DQ and write DQ

samples, and dual-sample mode is used to provide a rising and falling edge sample for

each DQ, resulting in four samples taken for each DQ signal from two probe loads. Read

rising, read falling, write rising, and write falling edge captures are given different labels

so the sample positions can be set independently.

07 | Keysight | U4164A Logic Analyzer Module - Data Sheet

Dual-Sample State Mode

Dual-sample mode has multiple beneﬁts:

1. For non-DDR or LPDDR memory trace capture, dual-sample state mode allows

acquisition of state (synchronous) data at rates up to 4 Gb/s depending on the speed

state option purchased. When used in this mode, the data will appear in two labels. One

label for rising edge and another for falling edge captures. The logic analyzer will be

clocked with one edge of the system clock. Labels can be merged using the Keysight

B4602A signal extractor tool. When operated in dual-sample state mode on all pods,

the channel count is 68 channels for one U4164A 136 channels for two U4164As, or 204

channels for three U4164A modules combined. Dual-sample state mode can be selected

on a per-pod-pair basis, so if you have only a subset of signals that require dual-sample

mode, the channel count can be higher.

2. For DDR/LPDDR memory signals up to 2.5 Gb/s, dual-sample state mode allows

separation of read data samples from write data samples. The B4661A DDR2/3/4

decoder or the B4661A LPDDR/2/3/4 decoder reassembles the data to align with

the associated commands. (There’s no need for the B4602A tool for DDR and LPDDR

solutions.)

3. For DDR4 and LPDDR4 memory solutions over 2.5 Gb/s using dual-sample state mode,

double probing is required to capture read and write DQ signals and dual-sample state

mode is used to capture rising and falling edge DQ samples. Using this technique, a

maximum of 34 DDR4 or LPDDR4 DQ signals operating over 2.5 Gb/s can be captured

per U4164A module. Address, command, and control signals for DDR or LPDDR memory

do not require double probing above or below 2.5 Gb/s data rates, so modules with a

mixture of address, command and DQ signals may have higher signal count depending

on how the signals are routed into the U4164A.

Quad-Sample State Mode

Quad-sample state mode enables four samples with two different threshold settings from

a single-touch connection to high-speed data signals under test. This results in four unique

sample positions at two unique thresholds. Single-touch connection preserves probe routing

space and minimized probe load on high-speed digital systems. DDR4 and LPDDR4 probing for

data rates over 2.5 Gb/s are examples of where single-touch probing enables high-speed trace

capture using quad-sample mode to capture read and write DQ (data) at different thresholds

with rising and falling edge samples for both read and write data to sample, trigger, and display

DDR4 and LPDDR4 at data rates up to 4 Gb/s.

When operated in quad-sample state mode on all pods, the channel count is 34 channels

for one U4164A, 68 channels for two U4164As, or 102 channels for three U4164A modules

combined. Quad-sample state mode is only available with U4164A Option -02G. Quad-sample

state mode can be selected on a per-pod-pair basis, so if you have only a subset of signals that

require quad-sample mode, the channel count can be higher.

08 | Keysight | U4164A Logic Analyzer Module - Data Sheet

State Mode Clock Inputs and Clock Qualiﬁers

State mode support for bursty clock inputs allows you to take measurements that include

periods of in activity on the clock, such as power management transitions when the clock is

inactive. In state mode, the U4164A allows one clock input into pod 1 of the clocking module.

– Double module set - bottom module of set is clocking module

– Three card set - middle module is clocking module

There are ﬁve clock qualiﬁers available on the clocking module. The clock inputs to pods 2, 3, 4,

and 5 can be used as “AND” or “OR” clock qualiﬁers. The “RESET” clock qualiﬁer input on pod

7 is available as an “AND” input only when the other clock qualiﬁers are setup as “OR” inputs.

The most common use mode for this clock qualiﬁer is to capture “RESET” when the other clock

qualiﬁers are looking for clock enable (CKE) signals on DDR and LPDDR buses.

Clock hysteresis

The U4164A module has a unique clock hysteresis feature that allows the user to deﬁne a range

about the clock threshold. Using clock hysteresis enables the U4164A clock input in state mode

to avoid false sampling on noisy clock inputs that may ﬂoat to zero volts at the differential

clock input to the U4164A when the clock is turned off. Clock hysteresis improves state mode

captures from systems where a differential clock input turns off and ﬂoats to zero volts.

Clock hysteresis control is inside the threshold dialog for the clock. The “hysteresis on” check

box [x] is an on/off control. There is also an input for the amount of hysteresis setting in

millivolts around threshold between 0 and 1 volts.

Figure 2. Clock hysteresis selection and setting in clock thresholds window. The settings shown were used

to capture an LPDDR4 system initializing without the use of any clock qualiﬁers.

09 | Keysight | U4164A Logic Analyzer Module - Data Sheet

Timing Zoom

The 12.5 GHz timing zoom with 256 K sample memory gives you simultaneous state and high-

resolution timing measurements covering a time span of 20 us, which corresponds to 43680

clock cycles at a 2133 MHz clock rate. Timing zoom also provides simultaneous high-resolution

timing measurements with conventional and transitional timing modes of operation.

Figure 3. Timing zoom can be used to measure the time between the rising edge of the clock and the rising

edge of DQS in a DDR system.

10 | Keysight | U4164A Logic Analyzer Module - Data Sheet

Deep Trace Captures

Using memory depth options, transitional timing and state mode store

qualiﬁcation triggers

Available memory depth of up to 400 M samples allows you to debug very complex problems

where the cause and symptoms may be separated by several seconds. The amount of memory

can be upgraded after purchase; see “Upgrades” in “Ordering Information” section of this

document.

No need to sacriﬁce sampling resolution to view more system activity. In timing mode, if your

system has bursts of activity followed by times with little activity, you can use transitional

timing along with the logic analyzer’s deep memory to capture seconds to minutes of activity

at 400 ps (2.5 GHz), 200 ps (5 GHz), or 100 ps (10 GHz) sampling resolutions. You also have the

ﬂexibility to increase the amount of time captured by excluding certain buses or signals from

the transition detector, for example clock or strobe signals, that add little useful information to

a state mode measurement.

In state mode, use store qualiﬁcation to save only states of interest into memory. Figure 4

shows a store qualiﬁcation trigger for state mode that stores only valid mode register settings

for DDR memories, allowing deep capture of only the MRS commands. The MRS command is a

“favorite” trigger that can be “recalled” from any Keysight default probing conﬁguration for DDR

memory. Other “favorite” store qualiﬁcation triggers include “Filter NOP, trigger on ﬁrst valid

command,” which is where the valid commands and enough samples to capture the DQ bursts

for DDR memory transactions are stored and “Deselected” or “NOP” states are not stored,

conserving logic analyzer memory depth.

Figure 4. Mode register trigger allows you to capture key events during initialization without wasting

valuable memory.

11 | Keysight | U4164A Logic Analyzer Module - Data Sheet

DDR Measurements Made Fast, Easy, and Powerful

The DDR setup assistant simpliﬁes measurement setup and minimizes the time to make your

ﬁrst measurement. The DDR setup tool guides you through even the most complex state

mode DDR/LPDDR setup in minutes. DDR eye scan makes it easy to determine the optimum

acquisition sample point without requiring an oscilloscope. Keysight-qualiﬁed scans place

the sample position at the center of the eye on every individual channel for maximum data

capture reliability, including separate sampling positions for read and write data. The DDR

setup assistant includes a variety of powerful, time-saving trigger features optimized for DDR

measurements.

The DDR setup assistant tool is available at no charge as part of the Keysight B4661A memory

analysis software package that can be downloaded from www.keysight.com/ﬁnd/B4661A

Figure 5. DDR setup assistant, with 10 simple steps, simpliﬁes the setup of state mode measurements.

12 | Keysight | U4164A Logic Analyzer Module - Data Sheet

Burst Trigger and Trigger Macros

Burst trigger captures an entire data burst of eight on DDR or LPDDR memory systems from

one sequence level in the trigger menu. Burst trigger is used in state mode. Up to four back-

to-back bursts of eight sequential patterns can be captured. This enables capture of up to 32

sequential patterns at up to 4 Gb/s data rates from any high-speed digital system.

Intuitive trigger macros with diagrams provide visualization of triggering options and simplify

the process of creating triggers.

Figure 6. Burse recognizer trigger makes it easy to trigger on events in a burst read or write.

13 | Keysight | U4164A Logic Analyzer Module - Data Sheet

Signal Integrity Insight Made Fast and Easy

As timing and voltage margins continue to shrink, conﬁdence in signal integrity becomes

an increasingly vital requirement in the design validation process. Eye scan lets you acquire

qualitative signal integrity information in a matter of minutes on all the buses in your design

under a wide variety of operating conditions.

– Identify problem signals quickly for further investigation with an oscilloscope.

– Results can be viewed for each individual signal or as a composite of multiple signals or

buses.

The ability to qualify scans of any signal from any combination of other signals, full triggering

capabilities for scan qualiﬁcation, and customizable viewing windows allow you to sample

only when the qualifying signal is active and see speciﬁc system activity of interest. Eye scan

technology in the U4154B provides insights that can’t be achieved as easily with any other test

method. DDR eye scan automatically groups signals so you can quickly spot byte lane related

signal integrity problems. Scans can be qualiﬁed based on state trigger criteria, providing

unique insight. For example, read and write scans can be separated. Signal trace mode scan

allows you to gather signal integrity information on two read or write cycles separated by only

one cycle.

DDR eye scan is available at no charge as part of the Keysight B4661A memory analysis

software package that can be downloaded from:

www.keysight.com/ﬁnd/B4661A

Figure 7 shows a scan using signal trace mode where the samples in a DDR/LPDDR data

burst are displayed in sequence. Figure 8 shows DDR3 DQ (data bits) scanned in overlay mode

where the samples in the burst are scanned so that they overlay. Overlay mode provides the

worst case eye, which allows for the most accurate sample position for the state mode sample

positions.

Figure 7. Burst qualiﬁed eye scan allows you to view the activity on the signals only when a burst is taking

place. The screenshot above shows DDR4 2400 Mb/s read DQS 0-3 scanned in signal trace mode with no

back-to-back bursts, allowing the user to view the DDR4 read strobes relative to each other, including the

strobe pre-embles.

14 | Keysight | U4164A Logic Analyzer Module - Data Sheet

Signal Integrity Insight Made Fast and Easy (Continued)

Figure 8. Eye scan clearly indicates the DDR3 byte lane shift caused by ﬂy-by routing.

15 | Keysight | U4164A Logic Analyzer Module - Data Sheet

Harness your Logic Analyzer and Scope for Powerful Insight

Combine the powerful triggering and protocol analysis of a logic analyzer with the signal

integrity insight of a scope to solve tough design problems. Keysight View Scope allows

you to easily make time-correlated measurements between Keysight logic analyzers and

oscilloscopes. The time-correlated logic analyzer and oscilloscope waveforms are integrated

into a single logic analyzer waveform display for easy viewing and analysis. You can also trigger

the oscilloscope from the logic analyzer (or vice versa), and automatically de-skew the two

instruments. View Scope enables you to perform the following tasks more easily, quickly, and

effectively:

– Validate signal integrity

– Track down problems caused by signal integrity

– Validate correct operation of A/D and D/A converters

– Validate correct logical and timing relationships between the analog and digital portions of

a design

Figure 9. DQS0, DQ6 and CK0 from a DDR4 system probed by an Inﬁniium scope and displayed in the logic

analyzer waveform using View Scope.

Programmability

You can write programs to control the logic analyzer application from remote computers on

the local area network using COM. The COM automation server is part of the logic analyzer

application. This software allows you to write programs to control loading, running, and storing

conﬁgurations on the logic analyzer.

16 | Keysight | U4164A Logic Analyzer Module - Data Sheet

Operating Modes ¹

State operating

modes

Conventional state sampling on both edges Dual sample state sampling on one clock

Quad sample state sampling on

one clock edge and using quad

sample mode to capture rising

and falling edge samples of both

read and write DQ (data bits) on

DDR4 or LPDDR4 (synchronous)

Option -02G

of the clock (synchronous)

edge and using dual sample mode to

capture rising and falling edge samples

(synchronous)

Option

-02G

Option

-01G

Option

-700

350 MHz

(standard) -02G

Option Option

-01G

Option

-700

350 MHz

(standard)

Maximum

acquisition rate

Number of

available channels

in one module

Number of

available channels

in a two module set

Number of

2.5 Gb/s 2.5 Gb/s 1.4 Mb/s 700 Mb/s 4 Gb/s 2.8 Gb/s 1.4 Gb/s 700 Mb/s

4 Gb/s

34

136

272

408

136

272

408

136

272

408

136

272

408

68

136

204

136

204

136

204

136

204

68

102

available channels

in a three module

set

Timing operating modes

Conventional or transitional timing

Full channel

Half channel

Quarter channel

All channels

Option -02G / -01G

Maximum acquisition rate

Number of available channels in one module

2.5 GHz

136

5 GHz

68

10 GHz

34

12.5 GHz

136

Number of available channels in a two module set

Number of available channels in a three module set

272

408

136

204

68

102

272

408

State modes (synchronous)

Conventional and transitional timing modes (asynchronous)

Timing zoom

Memory depth

(samples)

Conventional and dual-sample (all

state speed options); Quad-sample

(available with Option 02G only)

Full channel

Half channel

Quarter channel

(requires Option 01G or 02G)

All options

Standard (base) memory 2 M

2 M

4 M

8 M

16 M

32 M

64 M

128 M

200 M

400 M

4 M

8 M

16 M

256 K

U4164A-004

U4164A-008

U4164A-016

U4164A-032

U4164A-064

U4164A-128

U4164A-200

U4164A-400

4 M

8 M

16 M

32 M

64 M

128 M

200 M

400 M

800 M

32 M

64 M

128 M

200 M

400 M

800 M

1.6 G

16 M

32 M

64 M

128 M

200 M

400 M

Contact Keysight Technologies for information on additional conﬁgurations.

Note: Memory can be upgraded after purchase. See “Upgrades” in “Ordering Information.”

1. Deﬁned for general purpose use models. For DDR/LPDDR memory applications, either dual-sample or quad-sample modes are used for read/write

separation. Quad-sample mode is used to capture rising and falling edge samples of both read and write DDR/LPDDR DQ signals for data rates up to

4 Gb/s from a single probe point. Dual-sample mode is used to capture read and write data instead of higher data rates. Using dual sample mode instead of

quad sample mode requires, double probing of DDR/LPDDR data (DQ) to capture data rates over 2.5 Gb/s.

17 | Keysight | U4164A Logic Analyzer Module - Data Sheet

Optional Hardware

When you need more channels or more functions

Multiframe allows you to combine 16 AXIe chassis. ¹

One or more Y1223A Multiframe cables to connect multiple frames. Order one fewer Y1223A

cables than the total number of frames/chassis to be combined.

1. One PC host is recommended for each AXIe chassis.

Optional Software

B4661A memory analysis software

The Keysight B4661A memory analysis software offers a suite of tools that include the

industry’s ﬁrst protocol compliance violation testing capability across speed changes, a

condensed trafﬁc overview for rapid navigation to areas of interest in the logic analyzer

trace, powerful performance analysis graphics, and DDR and LPDDR decoders. With the

B4661A memory analysis software and a Keysight logic analyzer, users can monitor DDR3/4

or LPDDR2/3/4 systems to debug, improve performance, and validate protocol compliance.

Powerful trafﬁc overviews, multiple viewing choices, and real-time compliance violation

triggering help identify elusive DDR/LPDDR system violations.

The Keysight B4661A memory analysis software provides four standard software features and

four licensed memory analysis options.

B4661A standard software features

– Default conﬁgurations for DDR and LPDDR probing solutions for Keysight logic analyzers

– DDR setup assistant

– DDR eye ﬁnder/eye scan

– DDR conﬁguration creator

B4661A licensed software options

– DDR decoder with physical address trigger tool (B4661A-1xx)

– LPDDR decoder (B4661A-2xx)

– DDR and LPDDR compliance violation analysis (B4661A-3xx)

– Post-process compliance violation analysis real-time compliance violation analysis

– DDR3/4 and LPDDR2/3/4 performance analysis (B4661A-4xx)

18 | Keysight | U4164A Logic Analyzer Module - Data Sheet

Optional Software (Continued)

Figure 10. Trafﬁc overview example: Graphing command activity by commands and banks across the

captured trace from the Keysight logic analyzer.

Figure 11. Transaction decode in the performance analysis option, provides a high-level view that is

time-correlated to the listing window where each state is viewed using the DDR bus decoder. (The

transaction decode also includes a details window to see the data associated with each read or write

transaction.)

19 | Keysight | U4164A Logic Analyzer Module - Data Sheet

Optional Software (Continued)

Figure 12. The post-process compliance tool includes hyperlinks to quickly jump to and/or mark violations

and worst-case violations in the logic analyzer traces, transaction overview, and listing windows.

20 | Keysight | U4164A Logic Analyzer Module - Data Sheet

Probe/Cables As Required to Connect to the Target System

Direct connect probes – Probes that connect directly between a connector or footprint on the

device under test and the front panel connector of the logic analyzer.

Probe type

Model

Channels Maximum Supported signal

Comments

number

data rate

4 Gb/s

types

Single-ended data, Compatible with the U4164A

Differential or only. Requires one U4206A

Connectorless, U4206A 34

Soft Touch Pro

single-ended clock per U4164A module. Use only

for U4164A quad-sample

state or quarter channel

timing modes. Refer to

U4206A user guide for

example that allows for mixed

modes of operation (e.g.

quad-sample is selectable by

pod pair)

Connectorless, U4204A 34

Soft Touch Pro

4 Gb/s

Differential or

single-ended data,

Differential or

single-ended clock

Flying lead

Mictor

U4203A 34

U4205A 34

1.5 Gb/s

Single-ended data,

Differential or

single-ended clock

600 Mb/s Single-ended data,

Single-ended clock

Model number Description

Maximum data rate Comments

U4208A

Probe/cable, 61-pin 3.2 Gb/s typical

Compatible with the U4164A only. For

ZIF, left wing, no

RC, 160-pin direct

connect to U4164A

use with W4631A or W4636A DDR4 BGA

interposers that include RC network to

provide proper signal termination to the logic

analyzer. Uses quad-sample state mode to

capture DQ signals.

U4209A

Probe/cable, 61-pin 3.2 Gb/s typical

ZIF, right wing, no

RC, 160-pin direct

Compatible with the U4164A only. For

use with W4631A or W4636A DDR4 BGA

interposers. Includes RC network to provide

proper signal termination to the logic

analyzer. Uses quad-sample state mode to

capture DQ signals.

connect to U4164A

21 | Keysight | U4164A Logic Analyzer Module - Data Sheet

Probe/Cables As Required to Connect to the Target System (Continued)

General purpose probes as required to connect to the target system. (Probes in this chart require

U4201A cables.)

Probe type

Model

number

Channels

Maximum

data rate

Supported signal types

Number of U4201A

required per probe

Soft Touch Connectorless Pro E5406A

Series

34 (32 data, 2 clock)

17 (16 data, 1 clock)

34 (32 data, 2 clock)

17 (16 data, 1 clock)

34 (32 data, 2 clock)

17 (16 data, 1 clock)

4 Gb/s