KK0065 [KODENSHI]
40 Channel Segment / Common Driver For Dot Matrix LCD; 40通道段/通用驱动程序对于点阵LCD
| 型号： | KK0065 |
| 厂家： | 
KODENSHI KOREA CORP. |
| 描述： | 40 Channel Segment / Common Driver For Dot Matrix LCD |
| 文件： | 总6页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL DATA
KK0065
40 Channel Segment / Common Driver
For Dot Matrix LCD
The KK0065 is a LCD driver LSI which is fabricated by low power CMOS technology. Basically this LSI consists of
20 × 2 bit bi-directional shift register, 20 × 2 bit data latch and 20 × 2 bit driver. This LSI can be used a common or
segment driver.
FEATURES
FUNCTIONS
•Dot matrix LCD driver with 40-channel output.
•Display driving bias: static -1/5
•Power supply voltage: +5V ± 10%, +3V ± 10%
•Supply voltage for display: 0 ~ -5V(VEE)
•Interface
•Selectable function to use common/segment drivers
simultaneously.
•Input / Output signal
- output: 20 × 2 channel waveform for LCD driving
- input: - Serial display data and control pulse from
the controller LSI.
• Bias voltage (V1-V6)
driver(cascade connection)
controller
Other KK0065
IZ0066
KS0066
HD44780
SED1278
•CMOS Process
•Bare chip available
ABSOLUTE MAXIMUM RATING (Ta = 25oC)
Characteristic
Operating Voltage
Symbol
Value
Unit
VDD
VLCD
VIN1
VIN2
TOPR
TSTG
V
V
-0.3 ~ 7.0
VDD - 13.5 ~ VDD + 0.3
- 0.3 ~ VDD + 0.3
VDD + 0.3 ~ VEE - 0.3
-30 ~ +85
Driver Supply Voltage
Input Voltage 1
V
Input Voltage 2 (V1-V6)
Operating Temperature
Storage Temperature
V
oC
oC
-55 ~ +125
Voltage greater than above may damage to then circuit.
VEE: connect protection resistor (220Ω ± 5%)
1
KK0065
ELECTRICAL CHARACTERISTICS
DC characteristics (VDD=2.7~5.5V, VDD - VEE =3~13V, VSS=0V, Ta=-30 ~ +85OC )
Characteristic
Symbol
Test Condition
Min
Max
Unit
Applicable pin
Operating Current *
Supply Current *
Input High Voltage
IDD
IEE
fCL2=400KHz
fCL1=1KHz
-
-
-
1
mA
µA
V
-
10
VIH
0.7VDD
VDD
CL1, CL2, DL1,
DL2,
Input Low Voltage
VIL
0
0.3VDD
5
DR1, DR2,
Input Leakage Current
ILKG
VIN =0-VDD
IOH = -0.4mA
IOL = +0.4mA
-5
SHL1, SHL2, M,
FCS
µA
Output High Voltage
VOH
VDD
0.4
-
-
DL1, DL2, DR1,
DR2
Output Low Voltage
Voltage Descending
VOL
VD1
-
-
0.4
1.1
V
ION=0.1mA for one of
SC1-SC40
V(V1-V6),
SC(SC1-SC40)
VD2
IV
ION=0.5mA for each
SC1-SC40
-
1.5
10
Leakage Current
* VDD-VEE=4V
VIH= VDD~ VEE
-10
V1-V6
µA
(Output SC1-
SC40:floating)
AC characteristics (VDD=2.7~5.5V, VDD - VEE =3~13V, VSS=0V, Ta=-30 ~ +85OC )
Characteristic
Symbol
Test Condition
Min
Max
Unit
Applicable pin
Data Shift Frequency
Clock High Level Width
Clock Low Level Width
Clock Set-up Time
fCL
tWCKH
tWCKL
tLS
-
-
400
KHz
CL2
CL1, CL2
CL2
-
800
800
500
500
-
-
-
-
from CL2 to CL1
-
-
tLS
from CL1 to CL2
ns
CL1, CL2
Clock Rise/Fall Time
Data Set-up Time
tR/tF
tSU
-
-
200
-
300
DL1, DL2, DR1,
DR2,
Data Hold Time
Data Delay Time
tDH
tD
-
300
-
-
FLM
CL=15pF
500
DL1, DL2, DR1,
DR2
Input/Output current excluded; When input is at the intermediate level with CMOS, excessive current flows through the
input circuit to the power supply,To avoid this, input level must be fixed at «H» or «L».
2
KK0065
BLOCK DIAGRAM
S
C
1
S
C
2
S
C
1
S
C
2
S
C
2
S
C
2
S
C
3
S
C
4
9
0
1
2
9
0
PART 2
PART 1
V1
V2
V1
V2
V3
V4
LCD DRIVER
LCD DRIVER
V5
V6
DATA LATCH
DATA LATCH
)
)
(20 bit
(20 bit
VDD
Vss
VEE
BIDIRECTIONAL
SHIFT REGISTER
(20bit)
BIDIRECTIONAL
SHIFT REGISTER
(20bit)
M
SW
CL1
CONTR
LOGIC
CL2
F
C
S
D
L
1
S
H
L
1
D
R
1
D
L
2
S
H
L
2
D
R
2
3
KK0065
PIN DESCRIPTION
PIN №
INP/
OUTP
NAME
DESCRIPTION
INTER-
FACE
Power
Operating Voltage
VDD (24)
GND (34)
VEE (31)
For logical circuit (+5 V ± 10%, +3 V ± 10%)
0 V (GND)
Power
Input
Supply
Negative Supply
Voltage
Bias Voltage
For LCD driver circuit (-5 V)
Bias voltage level for LCD drive (select level)
Power
V1 V2
(44,45)
SC1÷SC20
V3 V4
Output
Input
LCD driver
LCD driver output
Bias voltage level for LCD drive (nonselect level)
LCD
Power
Bias Voltage
PART 1
(46,47)
Input
Data interface Selection of the shift direction of Part 1 shift register
VDD
or
VSS
SHL1
(41)
SHL1
VDD
DL1
out
in
DR1
in
VSS
out
Input/
Output
Data input/output of Part 1 shift register
Controller
or
DL1,DR1
(35,36)
KK0065
Output
Input
LCD driver
LCD driver output
SC21÷
SC40
V5 V6
(48,49)
SHL2
(42)
Bias Voltage
Bias voltage level for LCD drive (nonselect level)
Power
PART 2
Input
Data interface Selection of the shift direction of Part 2 shift register
VDD
or
VSS
SHL2
VDD
DL2
out
in
DR2
in
out
VSS
Input/
Output
Data input/output of Part 2 shift register
Controller
or
DL2,DR2
(37,38)
KK0065
Input
Alternated
M
signal for LCD
Controller
(40)
PART FCS
CL1
CL2
M
polarity
driver output
1
2
VSS
VDD
VSS
VDD
latch clock shift clock
M
Input Data shift / latch clock
Input Mode selection
(
)
(
)
CL1,CL2
(32,33)
FCS
shift clock latch clock
_
M
(
)
(
)
(43)
Shift/latch clock of display data and polarity of M signal
are changed by FCS signal.
By setting FCS to VDD level , user can select the function
that use Part 1 as segment driver and Part 2 as common
driver simultaneously.
No connection pin
N.C
NC(39)
4
KK0065
APPLICATION CIRCUIT
To MPU
VLC D (1/5 bias)
5
KK0065
PAD DIAGRAM
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
48
49
50
51
52
53
54
55
56
57
58
59
1
30
KK0065 (CHIP)
29
28
27
26
25
24
23
22
Y
X
(0,0)
Chip size:3240×2740
Pad size:100×100
Unit
:µm
21
20
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
PAD LOCATION
Pad
№
1
Pad
X
Y
Pad
№
21
22
23
Pad
Name
SC38
SC37
SC36
X
Y
Pad
№
41
42
43
Pad
Name
SC18
SC17
SC16
X
Y
Name
VEE -1384
CL1 -1344
CL2 -1190
-840
-1140
-1140
1381
1381
1381
-627.5
-477.5
-327.5
-185
-335
-485
1135
1135
1135
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VSS -1002
-1140
-1140
-1140
-1140
-1140
-1140
-1140
-1140
-1140
-1140
-1140
-1140
-1140
-1140
-1140
-1140
-777.5
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SC35
SC30
SC31
SC32
SC33
SC34
SC29
SC28
SC27
SC26
SC25
SC24
SC23
SC22
SC21
SC20
SC19
1381
1381
1381
1381
1381
1381
1381
1380
1232
1082
932
782
632
482
332
115
-35
-177.5
-29.5
120.5
270.5
420.5
570.5
720.5
1135
1135
1135
1135
1135
1135
1135
1135
1135
1135
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
SC15
SC14
SC13
SC12
SC9
SC10
SC11
SC8
SC7
VDD
SC6
SC5
SC4
-635
-785
1135
1135
1135
1135
970
820
670
520
370
220
70
-80
-230
-380
-528
-678
DL1
DR1
DL2
DR2
M
-852
-702
-552
-402
-252
-1033
-1183
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
-1384
SHL1 -102
SHL2
FCS
V1
V2
V3
V4
V5
V6
48
198
482
632
782
932
1082
1232
SC3
SC2
SC1
SC40 1382
SC39 1381
6
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