概述
数据手册KK74ACT04 概述
Hex Inverter High-Speed Silicon-Gate CMOS 六反相器高速硅栅CMOS
KK74ACT04 数据手册
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PDF下载TECHNICAL DATA
KK74ACT04
Hex Inverter
High-Speed Silicon-Gate CMOS
The KK74ACT04 is identical in pinout to the LS/ALS04, HC/HCT04.
The KK74ACT04 may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
•
•
•
•
•
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA; 0.1 µA @ 25°C
Outputs Source/Sink 24 mA
ORDERING INFORMATION
KK74ACT04N Plastic
KK74ACT04D SOIC
TA = -40° to 85° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
Output
A
L
Y
H
L
H
PIN 14 =VCC
PIN 7 = GND
1
KK74ACT04
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 to +7.0
-0.5 to VCC +0.5
-0.5 to VCC +0.5
±20
Unit
V
VCC
VIN
VOUT
IIN
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
V
V
mA
mA
mA
mW
IOUT
ICC
DC Output Sink/Source Current, per Pin
DC Supply Current, VCC and GND Pins
±50
±50
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Junction Temperature (PDIP)
Min
4.5
0
Max
Unit
V
5.5
VCC
140
+85
-24
24
VIN, VOUT
TJ
V
°C
TA
Operating Temperature, All Package Types
Output Current - High
-40
°C
IOH
mA
mA
ns/V
IOL
Output Current - Low
tr, tf
Input Rise and Fall Time *
(except Schmitt Inputs)
VCC =4.5 V
VCC =5.5 V
0
0
10
8.0
* VIN from 0.8 V to 2.0 V
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
V
OUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
KK74ACT04
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
V
Guaranteed Limits
Symbol
VIH
Parameter
Test Conditions
VOUT=0.1 V
Unit
V
25 °C
-40°C to
85°C
Minimum High-
Level Input Voltage
4.5
5.5
2.0
2.0
2.0
2.0
VIL
Maximum Low -
Level Input Voltage
VOUT= VCC-0.1 V
4.5
5.5
0.8
0.8
0.8
0.8
V
VOH
Minimum High-
Level Output Voltage
4.5
5.5
4.4
5.4
4.4
5.4
V
IOUT ≤ -50 µA
*VIN= VIL
IOH=-24 mA
IOH=-24 mA
4.5
5.5
3.86
4.86
3.76
4.76
VOL
Maximum Low-
Level Output Voltage
4.5
5.5
0.1
0.1
0.1
0.1
V
IOUT ≤ 50 µA
*VIN=VIH
IOL=24 mA
IOL=24 mA
4.5
5.5
0.36
0.36
0.44
0.44
IIN
∆ICCT
IOLD
IOHD
ICC
Maximum Input
Leakage Current
VIN=VCC or GND
5.5
5.5
5.5
5.5
5.5
±0.1
±1.0
1.5
75
µA
mA
mA
mA
µA
Additional Max
ICC/Input
VIN=VCC - 2.1 V
+Minimum Dynamic VOLD=1.65 V Max
Output Current
+Minimum Dynamic VOHD=3.85 V Min
Output Current
-75
40
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
4.0
* All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
3
KK74ACT04
AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)
Guaranteed Limits
Symbol
Parameter
Unit
25 °C
-40°C to
85°C
Min Max
Min
Max
9.0
tPLH
tPHL
CIN
Propagation Delay, Input A to Output Y (Figure 1)
Propagation Delay, Input A to Output Y (Figure 1)
Maximum Input Capacitance
1.5
1.5
8.5
8.0
1.0
1.0
ns
ns
pF
8.5
4.5
4.5
Typical @25°C,VCC=5.0 V
CPD
Power Dissipation Capacitance
30
pF
Figure 1. Switching Waveforms
4
KK74ACT04
N SUFFIX PLASTIC DIP
(MS - 001AA)
A
Dimension, mm
Symbol
MIN
18.67
6.1
MAX
19.69
7.11
8
7
14
1
B
A
B
C
D
F
5.33
0.36
1.14
0.56
F
L
1.78
C
2.54
7.62
G
H
J
-T-
SEATING
PLANE
N
0
°
10
°
M
J
G
K
H
D
2.92
7.62
0.2
3.81
8.26
0.36
K
L
M
N
0.25 (0.010) M
T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
0.38
D SUFFIX SOIC
(MS - 012AB)
Dimension, mm
A
14
8
Symbol
MIN
8.55
3.8
MAX
8.75
4
A
B
C
D
F
H
B
P
1.35
0.33
0.4
1.75
0.51
1.27
1
7
G
R x 45
C
1.27
5.27
G
H
J
-T-
SEATING
PLANE
K
M
D
J
F
0°
8°
0.25 (0.010) M
T
M
C
0.1
0.25
0.25
6.2
K
M
P
NOTES:
0.19
5.8
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
0.25
0.5
R
for A; for B 0.25 mm (0.010) per side.
‑
5
KK74ACT04 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| KK74ACT04D | KODENSHI | Hex Inverter High-Speed Silicon-Gate CMOS | 获取价格 |
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| KK74ACT04N | KODENSHI | Hex Inverter High-Speed Silicon-Gate CMOS | 获取价格 |
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| KK74ACT08 | KODENSHI | Quad 2-Input AND Gate High-Speed Silicon-Gate CMOS | 获取价格 |
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| KK74ACT08D | KODENSHI | Quad 2-Input AND Gate High-Speed Silicon-Gate CMOS | 获取价格 |
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| KK74ACT08N | KODENSHI | Quad 2-Input AND Gate High-Speed Silicon-Gate CMOS | 获取价格 |
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| KK74ACT10 | KODENSHI | Triple 3-Input NAND Gate High-Speed Silicon-Gate CMOS | 获取价格 |
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| KK74ACT109 | KODENSHI | Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS | 获取价格 |
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| KK74ACT109D | KODENSHI | Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS | 获取价格 |
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| KK74ACT109N | KODENSHI | Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS | 获取价格 |
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| KK74ACT10D | KODENSHI | Triple 3-Input NAND Gate High-Speed Silicon-Gate CMOS | 获取价格 |
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