KK74ACT193N [KODENSHI]
Presettable 4-Bit Binary UP/DOWN Counter High-Speed Silicon-Gate CMOS; 可预置4位二进制加/减计数器高速硅栅CMOS
| 型号： | KK74ACT193N |
| 厂家： | 
KODENSHI KOREA CORP. |
| 描述： | Presettable 4-Bit Binary UP/DOWN Counter High-Speed Silicon-Gate CMOS |
| 文件： | 总8页 (文件大小：598K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL DATA
KK74ACT193
Presettable 4-Bit Binary UP/DOWN Counter
High-Speed Silicon-Gate CMOS
The KK74ACT193 is identical in pinout to the LS/ALS192,
HC/HCT192. The KK74ACT193 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
The counter has two separate clock inputs, a Count Up Clock and
Count Down Clock inputs. The direction of counting is determined by
which input is clocked. The outputs change state synchronous with the
LOW-to-HIGH transitions on the clock inputs. This counter may be
preset by entering the desired data on the P0, P1, P2, P3 input. When the
Parallel Load input is taken low the data is loaded independently of either
clock input. This feature allows the counters to be used as devide-by-n by
modifying the count lenght with the preset inputs. In addition the counter
can also be cleared. This is accomplished by inputting a high on the
Master Reset input. All 4 internal stages are set to low independently of
either clock input.Both a Terminal Count Down (TCD) and Terminal
Count Up (TCU) Outputs are provided to enable cascading of both up and
down counting functions. The TCD output produces a negative going
pulse when the counter underflows and TCU outputs a pulse when the
counter overflows. The counter can be cascaded by connecting the TCU
and TCD outputs of one device to the Count Up Clock and Count Down
Clock inputs, respectively, of the next device.
ORDERING INFORMATION
KK74ACT193N Plastic
KK74ACT193D SOIC
TA = -40° to 85° C for all packages
PIN ASSIGNMENT
•
•
•
•
•
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA; 0.1 µA @ 25°C
Outputs Source/Sink 24 mA
LOGIC DIAGRAM
PIN 16 =VCC
PIN 8 = GND
1
KK74ACT193
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 to +7.0
-0.5 to VCC +0.5
-0.5 to VCC +0.5
±20
Unit
V
VCC
VIN
VOUT
IIN
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
V
V
mA
mA
mA
mW
IOUT
ICC
DC Output Sink/Source Current, per Pin
DC Supply Current, VCC and GND Pins
±50
±50
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Junction Temperature (PDIP)
Min
4.5
0
Max
Unit
V
5.5
VCC
140
+85
-24
24
VIN, VOUT
TJ
V
°C
TA
Operating Temperature, All Package Types
Output Current - High
-40
°C
IOH
mA
mA
ns/V
IOL
Output Current - Low
tr, tf
Input Rise and Fall Time *
(except Schmitt Inputs)
VCC =4.5 V
VCC =5.5 V
0
0
10
8.0
* VIN from 0.8 V to 2.0 V
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
V
OUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
KK74ACT193
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
V
Guaranteed Limits
Symbol
VIH
Parameter
Test Conditions
VOUT=0.1 V or VCC-0.1 V
VOUT=0.1 V or VCC-0.1 V
IOUT ≤ -50 µA
Unit
V
25 °C
-40°C to
85°C
Minimum High-
Level Input Voltage
4.5
5.5
2.0
2.0
2.0
2.0
VIL
Maximum Low -
Level Input Voltage
4.5
5.5
0.8
0.8
0.8
0.8
V
VOH
Minimum High-
Level Output Voltage
4.5
5.5
4.4
5.4
4.4
5.4
V
*VIN=VIH or VIL
IOH=-24 mA
IOH=-24 mA
4.5
5.5
3.86
4.86
3.76
4.76
VOL
Maximum Low-
Level Output Voltage
4.5
5.5
0.1
0.1
0.1
0.1
V
IOUT ≤ 50 µA
*VIN=VIH
IOL=24 mA
IOL=24 mA
4.5
5.5
0.36
0.36
0.44
0.44
IIN
IOLD
IOHD
ICC
Maximum Input
Leakage Current
VIN=VCC or GND
5.5
5.5
5.5
5.5
±0.1
±1.0
µA
mA
mA
µA
+Minimum Dynamic VOLD=1.65 V Max
Output Current
75
+Minimum Dynamic VOHD=3.85 V Min
Output Current
-75
80
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
8.0
* All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
FUNCTION TABLE
Inputs
CPU
Mode
MR PL
CPD
X
H
L
L
L
L
L
X
L
X
X
Reset(Asyn.)
Preset(Asyn.)
No Count
X
The KK74ACT193 is an UP/DOWN MODULO-
16 Binary Counter.
H
H
H
H
H
Logic equations
For Terminal Count:
H
Count Up
H
H
Count Down
No Count
TCU = Q0 • Q1 • Q2 • Q3 • CPU
TCD = Q0 • Q1 • Q2 • Q3 • CPD
X = don’t care
3
KK74ACT193
AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)
Guaranteed Limits
25 °C -40°C to
Symbol
Parameter
Unit
85°C
Min
100
Max Min
80
Max
fmax
tPLH
Maximum Clock Frequency (Figure 1)
MHz
ns
Propagation Delay, CPU or CPD to TCU or TCD
(Figure 2)
15
16.5
15.5
tPHL
Propagation Delay, CPU or CPD to TCU or TCD
(Figure 2)
14
ns
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
CIN
Propagation Delay, CPU or CPD to Qn (Figure 1)
Propagation Delay, CPU or CPD to Qn (Figure 1)
Propagation Delay, Pn to Qn (Figure 3)
12
12
12
12
12
15
15
14
14
15
11
15
15
13.5
13.5
13.5
13.5
13.5
16.5
16.5
15.5
15.5
16.5
12.5
16.5
16.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
Propagation Delay, Pn to Qn (Figure 3)
Propagation Delay, PL to Qn (Figure 4)
Propagation Delay, PL to Qn (Figure 4)
Propagation Delay, MR to Qn (Figure 5)
Propagation Delay, MR to TCU (Figure 6)
Propagation Delay, MR to TCD (Figure 6)
Propagation Delay, PL to TCU or TCD (Figure 6)
Propagation Delay, PL to TCU or TCD (Figure 6)
Propagation Delay, Pn to TCU or TCD (Figure 6)
Propagation Delay, Pn to TCU or TCD (Figure 6)
Maximum Input Capacitance
4.5
4.5
Typical @25°C,VCC=5.0 V
CPD
Power Dissipation Capacitance
45
pF
4
KK74ACT193
TIMING REQUIREMENTS (CL=50pF, Input tr=tf=3.0 ns, VCC=5.0 V ± 10%)
Guaranteed Limits
Symbol
Parameter
Unit
25 °C
-40°C to
85°C
tsu
th
Minimum Setup Time, Pn to PL (Figure 7)
Minimum Hold Time, PL to Pn (Figure 7)
Minimum Pulse Width, PL (Figure 4)
8
9
ns
ns
ns
ns
-1.0
14
-1.0
15
tw
tw
Minimum Pulse Width, CPU or CPD
(Figure 1)
10
11
tw
Minimum Pulse Width, MR (Figure 5)
12
8
14
9
ns
ns
trec
Minimum Recovery Time, PL to CPU or CPD (Figure
5)
trec
Minimum Recovery Time, MR to CPU or CPD
(Figure 5)
14
16
ns
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
5
KK74ACT193
Figure 5. Switching Waveforms
Figure 6. Switching Waveforms
Figure 7. Switching Waveforms
TIMING DIAGRAM
6
KK74ACT193
EXPANDED LOGIC DIAGRAM
7
KK74ACT193
N SUFFIX PLASTIC DIP
(MS - 001BB)
A
Dimension, mm
9
8
16
1
Symbol
MIN
18.67
6.1
MAX
19.69
7.11
B
A
B
C
D
F
5.33
0.36
1.14
0.56
F
L
1.78
C
2.54
7.62
G
H
J
SEATING
PLANE
-T-
N
M
0
°
10
°
J
G
K
H
D
2.92
7.62
0.2
3.81
8.26
0.36
K
L
M
N
0.25 (0.010) M
T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
0.38
D SUFFIX SOIC
(MS - 012AC)
Dimension, mm
A
16
Symbol
MIN
9.8
MAX
10
9
A
B
C
D
F
H
B
P
3.8
4
1.35
0.33
0.4
1.75
0.51
1.27
1
8
G
R x 45
C
1.27
5.72
G
H
J
-T-
SEATING
PLANE
K
M
D
J
F
0.25 (0.010) M T C
M
0
°
8
°
0.1
0.19
5.8
0.25
0.25
6.2
K
M
P
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
0.25
0.5
R
for A; for B 0.25 mm (0.010) per side.
‑
8
相关型号：
KK74ACT240
Octal 3-State Inverting Buffer/Line Driver/Line Receiver High-Speed Silicon-Gate CMOS
KODENSHI
KK74ACT240DW
Octal 3-State Inverting Buffer/Line Driver/Line Receiver High-Speed Silicon-Gate CMOS
KODENSHI
KK74ACT240N
Octal 3-State Inverting Buffer/Line Driver/Line Receiver High-Speed Silicon-Gate CMOS
KODENSHI
KK74ACT241
Octal 3-State Noninverting Buffer/Line Driver/Line Receiver High-Speed Silicon-Gate CMOS
KODENSHI
KK74ACT241DW
Octal 3-State Noninverting Buffer/Line Driver/Line Receiver High-Speed Silicon-Gate CMOS
KODENSHI
KK74ACT241N
Octal 3-State Noninverting Buffer/Line Driver/Line Receiver High-Speed Silicon-Gate CMOS
KODENSHI
©2020 ICPDF网 联系我们和版权申明