KK74HC193A [KODENSHI]
Presettable 4-Bit Binary UP/DOWN Counter High-Performance Silicon-Gate CMOS; 可预置4位二进制加/减计数器高性能硅栅CMOS
| 型号： | KK74HC193A |
| 厂家： | 
KODENSHI KOREA CORP. |
| 描述： | Presettable 4-Bit Binary UP/DOWN Counter High-Performance Silicon-Gate CMOS |
| 文件： | 总8页 (文件大小：520K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL DATA
KK74HC193A
Presettable 4-Bit Binary UP/DOWN Counter
High-Performance Silicon-Gate CMOS
The KK74HC193A is identical in pinout to the LS/ALS193. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
The counter has two separate clock inputs, a Count Up Clock and
Count Down Clock inputs. The direction of counting is determined by
which input is clocked. The outputs change state synchronous with the
LOW-to-HIGH transitions on the clock inputs. This counter may be
preset by entering the desired data on the P0, P1, P2, P3 input. When the
Parallel Load input is taken low the data is loaded independently of either
clock input. This feature allows the counters to be used as devide-by-n by
modifying the count lenght with the preset inputs. In addition the counter
can also be cleared. This is accomplished by inputting a high on the
Master Reset input. All 4 internal stages are set to low independently of
either clock input.Both a Terminal Count Down (TCD) and Terminal
Count Up (TCU) Outputs are provided to enable cascading of both up and
down counting functions. The TCD output produces a negative going
pulse when the counter underflows and TCU outputs a pulse when the
counter overflows. The counter can be cascaded by connecting the TCU
and TCD outputs of one device to the Count Up Clock and Count Down
Clock inputs, respectively, of the next device.
ORDERING INFORMATION
KK74HC193AN Plastic
KK74HC193AD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
•
•
•
•
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
PIN 16 =VCC
PIN 8 = GND
1
KK74HC193A
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 to +7.0
-1.5 to VCC +1.5
-0.5 to VCC +0.5
±20
Unit
V
VCC
VIN
VOUT
IIN
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
V
V
mA
mA
mA
mW
IOUT
ICC
DC Output Current, per Pin
±25
DC Supply Current, VCC and GND Pins
±50
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
2.0
0
Max
Unit
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
VCC
VIN, VOUT
TA
V
-55
+125
°C
ns
tr, tf
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
V
OUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
KK74HC193A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
VIH
Parameter
Test Conditions
Unit
V
25 °C
to
≤85 ≤125
°C
°C
-55°C
Minimum High-
Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢≤ 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
VIL
Maximum Low -
Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH
Minimum High-
Level Output Voltage
VIN=VIH or VIL
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN=VIH or VIL
⎢IOUT⎢ ≤ 4.0 mA
⎢IOUT⎢ ≤ 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOL
Maximum Low-
Level Output Voltage
VIN=VIH or VIL
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN=VIH or VIL
⎢IOUT⎢ ≤ 4.0 mA
⎢IOUT⎢ ≤ 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
6.0
±0.1
±1.0 ±1.0
µA
µA
ICC
Maximum Quiescent VIN=VCC or GND
Supply Current
(per Package)
6.0
8.0
80 160
I
OUT=0µA
FUNCTION TABLE
Inputs
Mode
The IN74HC193 is an UP/DOWN MODULO-
16 Binary Counter.
MR PL
CPU
X
CPD
X
Logic equations
For Terminal Count:
TCU = Q0 • Q1 • Q2 • Q3 • CPU
TCD = Q0 • Q1 • Q2 • Q3 • CPD
H
L
L
L
L
L
X
L
Reset(Asyn.)
Preset(Asyn.)
No Count
X
X
H
H
H
H
H
H
Count Up
H
H
Count Down
No Count
X = don’t care
3
KK74HC193A
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns)
VCC
V
Guaranteed Limit
Symbol
fmax
Parameter
Unit
25 °C to ≤85°C ≤125°C
-55°C
Minimum Clock Frequency (50% Duty Cycle)
(Figures 1 and 6)
2.0
4.5
6.0
12
36
43
3.2
16
19
2.6
13
15
MHz
tPLH, tPHL Maximum Propagation Delay, Clock to Q
(Figures 1 and 6)
2.0
4.5
6.0
215
43
37
270
54
46
325
65
55
ns
ns
ns
ns
pF
tPLH, tPHL Maximum Propagation Delay, PL to Q
(Figures 3 and 6)
2.0
4.5
6.0
215
43
37
270
54
46
325
65
55
tPLH, tPHL Maximum Propagation Delay, Clock to Terminal
Count (Figures 2 and 6)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
tTLH, tTHL Maximum Output Transition Time,Any Output
(Figures 1 and 6)
2.0
4.5
6.0
75
15
13
95
20
18
110
23
20
CIN
Maximum Input Capacitance
-
10
10
10
Power Dissipation Capacitance (Per Package)
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC
60
pF
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
tsu
Parameter
V
Unit
ns
25 °C to -55°C
≤85°C
≤125°C
Minimum Setup Time, Pn to PL
(Figure 4)
2.0
4.5
6.0
100
20
18
125
35
22
150
30
26
th
Minimum Hold Time, Pn to PL
(Figure 4)
2.0
4.5
6.0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
tw
Minimum Pulse Width, PL
(Figure 3)
2.0
4.5
6.0
100
20
17
125
25
26
150
30
26
tw
Minimum Pulse Width, MR
(Figure 5)
2.0
4.5
6.0
100
20
17
125
25
26
150
30
26
tr, tf
Minimum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
100
500
400
100
500
400
100
500
400
4
KK74HC193A
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
Figure 5. Switching Waveforms
Figure 6. Test Circuit
5
KK74HC193A
TIMING DIAGRAM
6
KK74HC193A
EXPANDED LOGIC DIAGRAM
7
KK74HC193A
N SUFFIX PLASTIC DIP
(MS - 001BB)
A
Dimension, mm
9
8
16
1
Symbol
MIN
18.67
6.1
MAX
19.69
7.11
B
A
B
C
D
F
5.33
0.36
1.14
0.56
F
L
1.78
C
2.54
7.62
G
H
J
SEATING
PLANE
-T-
N
M
0
°
10
°
J
G
K
H
D
2.92
7.62
0.2
3.81
8.26
0.36
K
L
M
N
0.25 (0.010) M
T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
0.38
D SUFFIX SOIC
(MS - 012AC)
Dimension, mm
A
16
Symbol
MIN
9.8
MAX
10
9
A
B
C
D
F
H
B
P
3.8
4
1.35
0.33
0.4
1.75
0.51
1.27
1
8
G
R x 45
C
1.27
5.72
G
H
J
-T-
SEATING
PLANE
K
M
D
J
F
0.25 (0.010) M T C
M
0
°
8
°
0.1
0.19
5.8
0.25
0.25
6.2
K
M
P
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
0.25
0.5
R
for A; for B 0.25 mm (0.010) per side.
‑
8
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