KK74HC573AN [KODENSHI]
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| 型号： | KK74HC573AN |
| 厂家： | 
KODENSHI KOREA CORP. |
| 描述： | 暂无描述 锁存器 |
| 文件： | 总6页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL DATA
KK74HC573A
Octal 3-State Noninverting
Transparent Latch
High-Performance Silicon-Gate CMOS
N SUFFIX
PLASTIC DIP
The KK74HC573A is identical in pinout to the LS/ALS573. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LS/ALSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when LE is high. When LE goes low, data meeting the
setup and hold time becomes latched.
20
1
DW SUFFIX
SOIC
20
1
•
•
•
•
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
ORDERING INFORMATION
KK74HC573AN
KK74HC573ADW
Plastic DIP
SOIC
High Noise Immunity Characteristic of CMOS Devices
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
OE
D0
1
20
19
18
17
16
15
14
13
12
11
V
CC
2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
19
D1
3
2
Q0
Q1
D0
18
17
16
15
14
13
12
3
4
5
D2
4
D1
D2
D3
5
D3
Q2
Q3
D4
6
DATA
NONINVERTING
OUTPUTS
INPUTS
6
D4
Q4
Q5
D5
7
7
8
D5
D6
D7
D6
8
Q6
Q7
9
D7
9
10
GND
11
LE
FUNCTION TABLE
1
OE
Inputs
Output
OE
L
LE
H
D
H
L
Q
PIN 20=VCC
PIN 10 = GND
H
L
H
L
no change
Z
L
L
X
X
H
X
H= high level
L = low level
X = don’t care
Z = high impedance
1
KK74HC573A
MAXIMUM RATINGS*
Symbol
Parameter
Value
-0.5 to +7.0
-1.5 to VCC +1.5
-0.5 to VCC +0.5
±20
Unit
V
VCC
VIN
VOUT
IIN
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
V
V
mA
mA
mA
mW
IOUT
ICC
DC Output Current, per Pin
±35
DC Supply Current, VCC and GND Pins
±75
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1.5 mm from Case for 4 Seconds
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
2.0
0
Max
6.0
Unit
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
VIN, VOUT
TA
VCC
+125
V
-55
°C
ns
tr, tf
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
V
OUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
KK74HC573A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VC
Guaranteed Limit
C
Symbol
Parameter
Test Conditions
VOUT ≥ VCC-0.1 V
V
Unit
25 °C to
-55°C
≤85
°C
≤125
°C
VIH
Minimum High-Level
Input Voltage
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
⎢IOUT⎢≤ 20 µA
VIL
Maximum Low -Level
Input Voltage
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
VOUT⎢ ≤ 0.1 V
⎢IOUT⎢ ≤ 20 µA
VOH
Minimum High-Level
Output Voltage
VIN=VIH
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
VIN=VIH
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
⎢IOUT⎢ ≤ 6.0 mA
⎢IOUT⎢ ≤ 7.8 mA
VOL
Maximum Low-Level
Output Voltage
VIN= VIL
⎢IOUT⎢ ≤ 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
VIN= VIL
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
⎢IOUT⎢ ≤ 6.0 mA
⎢IOUT⎢ ≤7.8 mA
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
6.0
±0.1
±1.0
±1.0
µA
µA
IOZ
Maximum Three State
Leakage Current
Output in High-Impedance
State
6.0
±0.5
±5.0
±10
VIN =VIH
VOUT= VCC or GND
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
6.0
4.0
40
160
µA
I
OUT=0µA
3
KK74HC573A
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC
V
Guaranteed Limit
Symbol
Parameter
Unit
25 °C to
-55°C
≤85°C
≤125°C
tPLH, tPHL Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tPLH, tPHL Maximum Propagation Delay, LE to Q
(Figures 2 and 5)
2.0
4.5
6.0
160
32
27
200
40
34
240
48
41
ns
ns
ns
ns
tPLZ, tPHZ Maximum Propagation Delay, OE to Q
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
tPZH, tPZL Maximum Propagation Delay, OE to Q
(Figures 3 and 6)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
CIN
Maximum Input Capacitance
-
-
10
15
10
15
10
15
pF
pF
COUT
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Enabled
Output)
Typical @25°C,VCC=5.0 V
CPD
Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC
23
pF
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
tSU
Parameter
V
Unit
ns
25 °C to
-55°C
≤85°C
≤125°C
Minimum Setup Time, Input D to
Latch Enable
2.0
4.5
6.0
50
10
9
65
13
11
75
15
13
(Figure 4)
th
Minimum Hold Time, Latch Enable
to Input D
(Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
ns
ns
tw
Minimum Pulse Width, Latch
Enable (Figure 2)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
tr, tf
Maximum Input Rise and Fall
Times (Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
4
KK74HC573A
VCC
t
t
f
LE
Q
50%
r
0 В
VCC
90%
50%
10%
D
Q
tw
0 В
tPLH
tPHL
tPLH
tPHL
90%
50%
10%
50%
tTLH
tTHL
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
VCC
0 В
50%
OE
VCC
tPZL
tPLZ
D
50%
HIGH
IMPEDANCE
0 В
50%
50%
Q
Q
tsu
th
10%
90%
VOL
VCC
tPHZ
tPZH
50%
LE
VOH
0 В
HIGH
IMPEDANCE
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
TEST POINT
TEST POINT
Connect to V when
CC
DEVICE
UNDER
TEST
OUTPUT
1 k
testing t
and t
OUTPUT
PLZ
PZL
DEVICE
UNDER
TEST
Connect to GND when
testing t and t
*
L
*
PHZ
PZH
C
C
L
Figure 5. Test Circuit
Figure 6. Test Circuit
EXPANDED LOGIC DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
LE
LE
LE
LE
LE
LE
LE
LE
LE
OE
Q0
Q1
Q2
Q4
Q3
Q5
Q6
Q7
5
KK74HC573A
N SUFFIX PLASTIC DIP
(MS - 001AD)
A
Dimension, mm
11
10
20
1
Symbol MIN
MAX
26.92
7.11
B
24.89
6.1
A
B
C
D
F
5.33
0.36
1.14
0.56
F
L
1.78
2.54
7.62
G
H
J
C
SEATING
PLANE
-T-
K
N
0
10
°
°
M
J
G
H
D
2.92
7.62
0.2
3.81
8.26
0.36
K
L
M
N
0.25 (0.010) M
T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
0.38
D SUFFIX SOIC
(MS - 013AC)
A
20
11
Dimension, mm
Symbol MIN
MAX
13
H
B
P
12.6
7.4
A
B
C
D
F
7.6
2.35
0.33
0.4
2.65
0.51
1.27
1
10
G
R x 45
C
-T-
SEATING
PLANE
1.27
9.53
G
H
J
K
M
D
J
F
M
0.25 (0.010) M T C
0
°
8
°
NOTES:
0.1
0.23
10
0.3
0.32
10.65
0.75
K
M
P
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B 0.25 mm (0.010) per side.
‑
0.25
R
6
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