MC12179D [LANSDALE]
500-2800 MHz Single Channel Frequency Synthesizer; 500-2800 MHz单信道频率合成器
| 型号： | MC12179D |
| 厂家： | 
LANSDALE SEMICONDUCTOR INC. |
| 描述： | 500-2800 MHz Single Channel Frequency Synthesizer |
| 文件： | 总11页 (文件大小：582K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ML12179
500-2800 MHz Single Channel
Frequency Synthesizer
Legacy Device: Motorola MC12179
The ML12179 is a monolithic Bipolar synthesizer integrating
the high frequency prescaler, phase/frequency detector, charge
pump, and reference oscillator/buffer functions. When combined
with an external loop filter and VCO, the ML12179 serves as a
complete PLL subsystem. The device is designed for operation up
to 2.8 GHz for high frequency applications such as CATV down
converters and satellite receiver tuners.
8
1
• 2.8 GHz Maximum Operating Frequency
• Low Power Supply Current of 3.5 mA Typical,
SO 8 = -5P
PLASTIC PACKAGE
CASE 751
Including I
and I Current
CC
P
• Supply Voltage of 5.0 V Typical
(SO–8)
• Integrated Divide by 256 Prescaler
• On–Chip Reference Oscillator/Buffer
– 2.0 to 11 MHz Operation When Driven
From Reference Source
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
SO 8
MOTOROLA
MC12179D
LANSDALE
ML12179-5P
– 5.0 to 11 MHz Operation when used with a Crystal
• Digital Phase/Frequency Detector with Linear
Transfer Function
• Balanced Charge Pump Output
• Space Efficient 8–Lead SOIC
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
• Operating Temperature Range T = –40° to +85°C
A
MAXIMUM RATINGS (Note 1)
Parameter
Symbol
Value
Unit
Vdc
Vdc
°C
PIN CONNECTIONS
Power Supply Voltage, Pin 2
Power Supply Voltage, Pin 7
Storage Temperature Range
V
CC
–0.5 to 6.0
V
P
V
to 6.0
CC
–65 to 150
Tstg
OSC
V
OSC
1
2
3
4
8
7
6
5
in
out
NOTES: 1. Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation should be restricted to the Recommended
Operating Conditions as identified in the Electrical Characteristics table.
V
P
CC
Gnd
PD
out
Block Diagram
F
GndP
in
OSC
in
Crystal
Oscillator
(Top View)
f
f
r
OSC
out
Phase/Frequency
Detector
Charge
Pump
PD
out
Prescaler
÷256
v
F
in
Page 1 of 11
www.lansdale.com
Issue A
ML12179
LANSDALE Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS (V
CC
= 4.5 to 5.5 V; V = V
to 5.5 V; T = –40 to 85 C, unless otherwise noted.)
P
CC
A
Characteristic
Symbol
Min
–
Ty p
Max
5.6
Unit
mA
Condition
Note 1
Supply Current for V
I
3.1
0.4
CC
P
CC
Supply Current for V
I
P
–
1.3
mA
Note 1
Note 2
Operating Frequency
f
max
F
IN
2800
–
–
–
–
500
MHz
IN
f
min
IN
Operating Frequency
Crystal Mode
F
5
2
–
–
11
11
MHz
Note 3
Note 4
OSC
External Oscillator OSC
F
in
in
in
Input Sensitivity
V
200
500
–2.8
–
–
1000
2200
–1.6
mV
Note 2
Note 4
IN
P–P
Input Sensitivity
External Oscillator OSC
V
mV
OSC
P–P
5
Output Source Current
(PD
(PD
(PD
)
)
)
I
–2.2
mA
V = 4.5 V, V
P
out
out
out
OH
PDout
PDout
PDout
= V /2
P
5
Output Sink Current
I
1.6
–
2.2
0.5
2.8
15
mA
nA
V = 4.5 V, V
P
OL
OZ
= V /2
P
Output Leakage Current
I
V = 5.0 V, V
P
= V /2
P
NOTES: 1. V
CC
and V = 5.5 V; F = 2.56 GHz; F
IN OSC
= 10 MHz crystal; PD open.
out
P
2. AC coupling, F measured with a 1000 pF capacitor.
IN
3. Assumes C and C (Figure 1) limited to 30 pF each including stray and parasitic capacitances.
4. AC coupling to OSC
5. Refer to Figure 15 and Figure 16 for typical performance curves over temperature and power supply voltage.
1
2
in
.
PIN FUNCTION DESCRIPTION
Pin
Symbol
I/O
Function
1
OSCin
I
Oscillator Input – An external parallel–resonant, fundamental crystal is connected between OSC
in
to form an internal reference oscillator (crystal mode). External capacitors C1 and C2, as
and OSC
out
shown in Figure 1, are required to set the proper crystal load capacitance and oscillator frequency.
For an external reference oscillator, an external signal is AC–coupled to the OSC pin with a
in
1000 pF coupling capacitor, with no connection to OSC . In either mode, a resistor with a nominal
out
value of 50 kΩ MUST be placed across the OSC and OSC
pins for proper operation.
in
out
2
V
CC
–
Positive Power Supply. Bypass capacitors should be placed as close as possible to the pin and be
connected directly to the ground plane.
3
4
5
6
Gnd
–
I
Ground.
F
in
Prescaler Input – The VCO signal is AC coupled into the F pin.
in
GndP
–
O
Ground – For charge pump circuitry .
PD
Single ended phase/frequency detector output (charge pump output). Three–state current
sink/source output for use as a loop error signal when combined with an external low pass filter. The
phase/frequency detector is characterized by a linear transfer function.
out
P
7
8
V
–
Positive power supply for charge pump. V MUST be equal or greater than V . Bypass capacitors
P CC
should be placed as close as possible to the pin and be connected directly to the ground plane.
OSCout
O
Oscillator output, for use with an external crystal as shown in Figure 1.
Page 2 of 11
www.lansdale.com
Issue A
ML12179
LANSDALE Semiconductor, Inc.
Figure 1. ML12179 Expanded Block Diagram
+5.0 V
+5.0 V
2
1
8
V
V
7
6
CC
P
C1
OSC
in
Crystal
Oscillator
OSC
f
out
r
Phase/Frequency
Detector
Charge
Pump
C2
To Loop Filter
NOTE: External 50 k
Ω
resistor
PD
out
across Pins 1 and 8 is necessary in
either crystal or driven mode.
f
v
F
4
Prescaler
÷256
in
VCO
1000 pF
GND
3
GNDP
5
PHASE CHARACTERISTICS
The phase comparator in the ML12179 is a high speed digital
fr leads fv in phase OR fv<fr in frequency
When the phase of fr leads that of fv or the frequency of fv is
phase/frequency detector circuit. The circuit determines the “lead” less than fr, the Do output will source current. The pulse width
or “lag” phase relationship and time difference between the lead-
ing edges of the VCO (fv) signal and the reference (fr) input. The
detector can cover a range of 2π radian of fv/fr phase difference.
The operation of the charge pump output is shown in Figure 2.
will be determined by the time difference between the two rising
edges.
fr = fv in phase and frequency
When the phase and frequency of fr and fv are equal, the charge
pump will be in a quiet state, except for current spikes when sig-
nals are in phase. This situation indicates that the loop is in lock
and the phase comparator will maintain the loop in its locked
state.
fr lags fv in phase OR fv>fr in frequency
When the phase of fr lags that of fv or the frequency of fv is
greater than fr, the Do output will sink current. The pulse width
will be determined by the time difference between the two rising
edges.
Figure 2. Phase/Frequency Detector and Charge Pump Waveforms
H
L
f
r
(OSC
)
in
H
L
f
v
(F ÷256)
in
Sourcing Current Pulse
Z
PD
out
Sinking Current Pulse
H = High voltage level; L = Low voltage level; Z = High impedance
NOTES: Phase difference detection range: –2 to 2
∼
π
π
|I
|
|I
sink
|
|2.2|
|–2.2|
+
source
+
1.1 mA
=
=
K –Charge Pump Gain
p
≈
4π
4π
πradian
Page 3 of 11
www.lansdale.com
Issue A
ML12179
LANSDALE Semiconductor, Inc.
Legacy Applications Information
The ML12179 is intended for applications where a fixed local
oscillator is required to be synthesized. The prescaler on the
ML12179 operates up to 2.8GHz which makes the part ideal for
many satellite receiver applications as well as applications in the
2nd ISM (Industrial, Scientific, and Medical) band which covers
the frequency range of 2400MHz to 2483MHz. The part is also
intended for MMDS (Multi–channel Multi–point Distribution
Since the ML12179 is realized with an all–bipolar ECL style
design, the internal oscillator circuitry is different from more tradi-
tional CMOS oscillator designs which realize the crystal oscillator
with a modified inverter topology. These CMOS designs typically
excite the crystal with a rail–to–rail signal which may overdrive the
crystal resulting in damage or unstable operation. The ML12179
design does not exhibit these phenomena because the swing out of
System) block downconverter applications. Below is a typical block the OSC
diagram of the complete PLL.
pin is less than 600mV. This has the added advantage
out
of minimizing EMI and switching noise which can be generated by
rail–to–rail CMOS outputs. The OSC
to drive other circuitry.
The oscillator buffer in the ML12179 is a single stage, high
speed, differential input/output amplifier; it may be considered to
be a form of the Pierce oscillator. A simplified circuit diagram is
seen in Figure 4.
output should not be used
out
Figure 3. Typical Block Diagram of Complete PLL
ML12179 PLL
External Ref
VCO
φ
/Freq
Det
Charge
Pump
Loop
Filter
10.0 MHz
2560.00 MHz
Figure 4. Simplified Crystal Oscillator/Buffer Circuit
V
CC
P
256
As can be seen from the block diagram, with the addition of a
VCO, a loop filter, and either an external oscillator or crystal, a
complete PLL sub–system can be realized. Since most of the PLL
function is integrated into the ML12179, the user's primary focus is
on the loop filter design and the crystal reference circuit. Figure 13
and Figure 14 illustrate typical VCO spectrum and phase noise
characteristics. Figure 17 and Figure 18 illustrate the typical input
impedance versus frequency for the prescaler input.
OSC
out
To Phase/
Frequency
Detector
OSC
in
Bias
Source
Crystal Oscillator Design
OSC drives the base of one input of an NPN transistor differ-
in
The ML12179 is used as a multiply–by–256 PLL circuit which
transfers the high stability characteristic of a low frequency refer-
ence source to the high frequency VCO in the PLL loop. To facili-
tate this, the device contains an input circuit which can be config-
ential pair. The non–inverting input of the differential pair is inter-
nally biased. OSC
an emitter follower with a 70 µA pull–down current and has a volt-
is the inverted input signal and is buffered by
out
age swing of about 600 mVpp. Open loop output impedance is
ured as a crystal oscillator or a buffer for accepting an external sig- about 425Ω. The opposite side of the differential amplifier output
nal source.
is used internally to drive another buffer stage which drives the
phase/frequency detector. With the 50 kΩ feedback resistor in
In the external reference mode, the reference source is AC–cou-
pled into the OSC input pin. The input level signal should be
place, OSC and OSC
are biased to approximately 1.1V below
in
in
out
between 500–2200 mVpp. When configured with an external refer-
ence, the device can operate with input frequencies down to 2
MHz, thus allowing the circuit to control the VCO down to 512
MHz. To optimize the phase noise of the PLL when used in this
mode, the input signal amplitude should be closer to the upper
V
CC
. The amplifier has a voltage gain of about 15 dB and a band-
width in excess of 150 MHz. Adherence to good RF design and
layout techniques, including power supply pin decoupling, is
strongly recommended.
A typical crystal oscillator application is shown in Figure 1. The
specification limit. This maximizes the slew rate of the input signal crystal and the feedback resistor are connected directly between
as it switches against the internal voltage reference.
In the crystal mode, an external parallel–resonant fundamental
OSC and OSC , while the loading capacitors, C1and C2, are
in out
connected between OSC and ground, and OSC and ground
in out
mode crystal is connected between the OSC and OSC
pins.
respectively. It is important to understand that as far as the crystal
is concerned, the two loading capacitors are in series (albeit
through ground). So when the crystal specification defines a spe-
in
out
This crystal must be between 5.0 MHz and 11 MHz. External
capacitors, C1 and C2 as shown in Figure 1, are required to set the
proper crystal load capacitance and oscillator frequency. The values cific loading capacitance, this refers to the total external (to the
of the capacitors are dependent on the crystal chosen and the input
capacitance of the device and any stray board capacitance.
In either mode, a 50kΩ resistor must be connected between the
crystal) capacitance seen across its two pins.
This capacitance consists of the capacitance contributed by the
amplifier (IC and packaging), layout capacitance, and the series
OSC and the OSC
of this resistor is not critical so a 47kΩ or 51kΩ 10ꢀ resistor is
pins for proper device operation. The value combination of the two loading capacitors. This is illustrated in the
in
out
equation below:
acceptable.
Page 4 of 11
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Issue A
ML12179
LANSDALE Semiconductor, Inc.
Legacy Applications Information
C1 C2
C = C
I
+ C
+
STRAY
AMP
+
C1 C2
Component
Guideline
Provided the crystal and associated components are located
immediately next to the IC, thus minimizing the stray capacitance,
C
a
R
x
C
x
<0.1 x C
o
>10 x R
o
the combined value of C
5pF. Note that the location of the OSC and OSC
in
and C
is approximately
pins at the
AMP
STRAY
<0.1 x C
o
out
end of the package, facilitates placing the crystal, resistor and the
C1 and C2 capacitors very close to the device. Usually, one of the
capacitors is in parallel with an adjustable capacitor used to trim
the frequency of oscillation. It is important that the total external
(to the IC) capacitance seen by either OSC or OSC , be no
tools can be used.
The focus of the design effort is to determine what the loop's
natural frequency, ωo, should be. This is determined by R , C ,
o
o
K , K , and N. Because K , K , and N are given, it is only neces-
p
v
p
v
in
out
sary to calculate values for R and C . There are 3 considerations
greater than 30pF.
o
o
in selecting the loop bandwidth:
In operation, the crystal oscillator will start up with the applica-
tion of power. If the crystal is in a can that is not grounded it is
often possible to monitor the frequency of oscillation by connect-
ing an oscilloscope probe to the can; this technique minimizes
any disturbance to the circuit. If a malfunction is indicated, a high
impedance, low capacitance, FET probe may be connected to
1) Maximum loop bandwidth for minimum tuning speed
2) Optimum loop bandwidth for best phase noise performance
3)Minimum loop bandwidth for greatest reference sideband
suppression
Usually a compromise is struck between these 3 cases, however,
for the fixed frequency application, minimizing the tuning speed
is not a critical parameter.
either OSC or OSC . Signals typically seen at those points
in out
will be very nearly sinusoidal with amplitudes of roughly 300 to
600 mVpp. Some distortion is inevitable and has little bearing on
the accuracy of the signal going to the phase detector.
Loop Filter Design
To specify the loop bandwidth for optimal phase noise perform-
ance, an understanding of the sources of phase noise in the sys-
tem and the effect of the loop filter on them is required. There are
3 major sources of phase noise in the phase–locked loop – the
crystal reference, the VCO, and the loop contribution. The loop
filter acts as a low–pass filter to the crystal reference and the loop
contribution equal to the total divide–by–N ratio. This is mathe-
matically described in Figure 10. The loop filter acts as a
high–pass filter to the VCO with an in–band gain equal to unity.
This is described in Figure 11. The loop contribution includes the
PLL IC, as well as noise in the system; supply noise, switching
noise, etc. For this example, a loop contribution of 15 dB has
been selected, which corresponds to data in Figure 14.
The crystal reference and the VCO are characterized as
high–order 1/f noise sources. Graphical analysis is used to deter-
mine the optimum loop bandwidth. It is necessary to have noise
plots from the manufacturer. This method provides a straightfor-
ward approximation suitable for quickly estimating the optimal
bandwidth. The loop contribution is characterized as white–noise
or low–order 1/f noise given in the form of a noise factor which
combines all the noise effects into a single value. The phase noise
of the Crystal References increased by the noise factor of the PLL
IC and related circuitry. It is further increased by the total
divide–by–N ratio of the loop. This is illustrated in Figure 6.
The point at which the VCO phase noise crosses the amplified
phase noise of the Crystal Reference is the point of the optimum
loop bandwidth. In the example of Figure 6, the optimum band-
width is approximately 15 KHz.
Because the device is designed for a non–frequency agile syn-
thesizer (i.e., how fast it tunes is not critical) the loop filter design
is very straight forward. The current output of the charge pump
allows the loop filter to be realized without the need of any active
components. The preferred topology for the filter is illustrated
below in Figure 5.
Figure 5. Loop Filter
Xtl
Osc
Ph/Frq
Det
Chrg
Pump
VCO
R
x
R
C
o
K
K
v
p
C
C
x
o
a
256
N
ML12179
The R /C components realize the primary loop filter. C is
o
o
a
added to the loop filter to provide for reference sideband suppres-
sion. If additional suppression is needed, the R /C realizes an
x
x
additional filter. In most applications, this will not be necessary.
If all components are used, this results in a 4th order PLL, which
makes analysis difficult. To simplify this, the loop design will be
treated as a 2nd order loop (R /C ) and additional guidelines are
o
o
provided to minimize the influence of the other components. If
more rigorous analysis is needed, mathematical/system simulation
Page 5 of 11
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Issue A
ML12179
LANSDALE Semiconductor, Inc.
Legacy Applications Information
Figure 6. Graphical Analysis of Optimum Bandwidth
damping coefficient, ζ ≈ 1. T(s) is the transfer function of the
–60
loop filter.
Optimum Bandwidth
–70
Figure 8. Design Equations for the 2nd Order System
–80
VCO
–90
2
ζ
+
s
1
(
(
(
+
ω
R C s
o o
1
o
=
=
T(s)
2
ζ
NC
1
o
2
+
+
1
2
s
R C s
o o
+
+
1
s
s
(
–100
(
(
(
(
ω
ω 2
K K
p
o
o
v
20*log(256)
–110
–120
K K
p v
NC
K K
p v
K K
p v
1
o
C
→
=
→ ω
o =
o
(
(
(
(
(
(
ω 2
2
–130
Nω
NC
o
o
o
15dB NF of the Noise
Contribution from Loop
–140
Crystal Reference
–150
2ζ
2ζ
R C
o o o
2
R C
o o =
R
o =
→ ζ =
→
ω
10
100
1k
10k
100k
1M
(
(
(
(
(
(
ω
C
o o
o
Hz
Figure 7. Closed Loop Frequency Response for ζ = 1
In summary, follow the steps given below:
Natural Frequency
Step 1: Plot the phase noise of crystal reference and the VCO
on the same graph.
Step 2: Increase the phase noise of the crystal reference by the
noise contribution of the loop.
10
3dB Bandwidth
0
–10
–20
–30
–40
–50
–60
Step 3: Convert the divide–by–N to dB (20log 256 – 48 dB) and
increase the phase noise of the crystal reference by
that amount.
Step 4: The point at which the VCO phase noise crosses the
amplified phase noise of the Crystal Reference is the
point of the optimum loop bandwidth. This is
approximately 15 kHz in Figure 6.
Step 5: Correlate this loop bandwidth to the loop natural
frequency and select components per Figure 8. In this
case the 3.0 dB bandwidth for a damping coefficient of 1
is 2.5 times the loop's natural frequency. The relationship
between the 3.0 dB loop bandwidth and the loop's
“natural” frequency will vary for different values of ζ.
Making use of the equations defined above in a math tool
or spreadsheet is useful. To aid in the use of such a tool
the equations are summarized in Figures 9 through 11.
0.1
1
10
Hz
100
1k
To simplify analysis further a damping factor of 1 will be
selected. The normalized closed loop response is illustrated in
Figure 7 where the loop bandwidth is 2.5 times the loop natural
frequency (the loop natural frequency is the frequency at which
the loop would oscillate if it were unstable). Therefore the opti-
mum loop bandwidth is15kHz/2.5 or 6kHz (37.7krads) with a
Figure 9. Loop Parameter Relations
NC
2ζ
o
o
1
Let:
Let:
=
, R C =
o o
ω
K K
p v
ω 2
o
=
=
x
=
+
=
+
+
a b
C
aC , C
o
bC , A
o
1
a , and B
1
a
1
3
1
4
1
5
Let: R C
o o
=
=
, R C
x x
=
, R (C
o
C ) =
a +
x
ω
ω
ω
Let: K ω
3 3
ω
, K ω
ω
, K ω
ω
=
=
o
4 4
o
5 5
o
Page 6 of 11
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Issue A
ML12179
LANSDALE Semiconductor, Inc.
Legacy Applications Information
Figure 10. Transfer Function for the Crystal Noise in the Frequency Plane
ω
1 + j (2ζωo
– Bωω2 + j 2ζ ω – (AK + K ) ωω3
3
o
)
T(jω) = N•
4
ω
1 + K K
(
(
(
(
3 4 ω
ω
4
5
o
4
2
o
o
Figure 11. Transfer Function for the VCO Noise in the Frequency Plane
4
2
3
ω
ω
ω
ω
K K
– B ω
– j (AK + K )
(
(
(
(
3 4ωo
4
5
4
2
3
o
o
T(jω) =
– B ωωo2 + j 2ζ ω – (AK + K ) ω3
(
3
4
ω
1 + K K
(
(
(
ω
3 4 ωo
4
5
ω
o
4
2
o
Appendix: Derivation of Loop Filter Transfer Function
function of the loop filter. To use these equations in determining
the overall transfer function of a PLL multiply the filter's imped-
ance by the gain constant of the phase detector then multiply that
by the filter's transfer function (which is unity in the 2nd and 3rd
order cases below).
The purpose of the loop filter is to convert the current from the
phase detector to a tuning voltage for the VCO. The total transfer
function is derived in two steps. Step 1 is to find the voltage gen-
erated by the impedance of the loop filter. Step 2 is to find the
transfer function from the input of the loop filter to its output.
The “voltage” times the “transfer function” is the overall transfer
Figure 12. Overall Transfer Function of the PLL
V
p
V
t
For the 2nd Order PLL:
R
C
R C s
1
+
o
o o
C s
=
(s)
Z
T
LF
LF
o
o
V (s)
t
(s) =
= 1 , V (s) = K (s)Z (s)
p
p
LF
V (s)
p
V
p
V
t
For the 3rd Order PLL:
R
C
C
a
R C s + 1
o o
o
Z
T
(s)
=
LF
LF
2
C R C s + (C + C )s
o o a
o
a
o
V (s)
t
(s) =
= 1 , V (s) = K (s)Z (s)
LF
p
p
V (s)
p
V
V
t
For the 4th Order PLL:
p
R
x
R
C
C
a
C
o
x
o
(R C s + 1) (R C s + 1)
o o x x
Z
T
(s) =
(s) =
LF
LF
3
2
+
+ [
+
+
+
]
+
+
C )s
a
C R C R C s
o o a x x
(C
C )R C
C R (C
C )
s
(C
C
o
a
x x o o
x
a
o
x
V (s)
t
1
=
, V (s) = K (s)Z (s)
LF
p
p
V (s) (R C s + 1)
p
x x
Page 7 of 11
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Issue A
ML12179
LANSDALE Semiconductor, Inc.
Legacy Applications Information
Figure 13. VCO Output Spectrum with ML12179, V
= 5.0 V
CC
(ECLiPTEK 8.9 MHz Crystal and ZCOM 2500 VCO)
NOTE: Spurs can be reduced further by narrowing the loop bandwidth of the PLL loop filter and/or
adding an extra filter (R /C )
x
x
Figure 14. Typical Phase Noise Plot, 2200 MHz VCO
(With the ML12179 in a Closed Loop)
HP 3048A
CARRIER
2200MHz
0
25
50
75
100
125
150
170
1k
10k
100k
(f) [dBc/Hz] vs f[Hz]
1M
10M
40M
Page 8 of 11
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Issue A
ML12179
LANSDALE Semiconductor, Inc.
Legacy Applications Information
Figure 15. Typical Charge Pump Current versus Temperature
(V = V = 5.0 V)
CC
pp
2.5
2.0
SINK
1.5
1.0
–40°C
+25°C
+85°C
0.5
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
SOURCE
0.5
0
1.0
1.5
2.0
2.5
Voltage at PD
3.0
3.5
4.0
4.5
5.0
(V)
out
Figure 16. Typical Charge Pump Current versus Voltage
(T = 25°C)
2.5
2.0
SINK
1.5
4.5V V /V
CC PP
1.0
5.0V V
5.5V V /V
V
CC/ PP
CC PP
0.5
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
SOURCE
0.5
0
1.0
1.5
2.0
2.5
3.0
out
3.5
4.0
4.5
5.0
5.5
Voltage at PD
(V)
Page 9 of 11
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Issue A
ML12179
LANSDALE Semiconductor, Inc.
Legacy Applications Information
Figure 17. Typical Real Input Impedance versus Input Frequency
(For the F Input)
in
100
80
60
40
20
0
250
500
750
1000
1250
1500
1750
2000
2250
2500
2750
Frequency (MHz)
Figure 18. Typical Imaginary Input Impedance versus Input Frequency
(For the F Input)
in
50
25
0
–25
–50
–75
–100
–125
–150
–175
–200
–225
–250
250
500
750
1000
1250
1500
1750
2000
2250
2500
2750
Frequency (MHz)
Page 10 of 11
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Issue A
ML12179
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
SO 8 = -5P
PLASTIC PACKAGE
CASE 751-06
(ML12179-5P)
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
D
A
C
8
1
5
4
M
M
0.25
B
H
E
MILLIMETERS
h X 45
θ
DIM
A
A1
B
C
D
MIN
1.35
0.10
0.35
0.19
4.80
3.80
MAX
1.75
0.25
0.49
0.25
5.00
4.00
B
e
A
C
SEATING
PLANE
E
e
H
h
L
1.27 BSC
L
5.80
0.25
0.40
0°
6.20
0.50
1.25
7°
0.10
A1
B
θ
M
S
S
0.25
C
B
A
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili-
ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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Issue A
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