MC145159P1 [LANSDALE]
Serial-Input PLL Frequency Synthesizer with Analog Phase Detector;
| 型号： | MC145159P1 |
| 厂家： | 
LANSDALE SEMICONDUCTOR INC. |
| 描述： | Serial-Input PLL Frequency Synthesizer with Analog Phase Detector 输入元件 光电二极管 |
| 文件： | 总10页 (文件大小：434K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ML145159
Serial-Input PLL Frequency
Synthesizer with Analog Phase
Detector
INTERFACES WITH DUAL–MODULUS PRESCALERS
Legacy Device: Motorola MC145159-1
The ML145159 has a programmable 14–bit reference
counter, as well as fully programmable
divide–by–N/divide–by–A counters. The counters are pro-
grammed serially through a common data input and
latched into the appropriate counter latch, according to the
last data bit (control bit) entered.
When combined with a loop filter and VCO, this device can
provide all the remaining functions for a PLL frequency syn-
thesizer operating up to the device's frequency limit. For high-
er VCO frequency operations, a down mixer or a dual–modu-
lus prescaler can be used between the VCO and the PLL.
• Operating Temperature Range: T – 40° to 85°C
A
• Low Power Consumption Through Use of CMOS
Technology
• 3.0 to 9.0 V Supply Range
• On– or Off–Chip Reference Oscillator Operation
• Compatible with the Serial Peripheral Interface (SPI)
on CMOS MCUs
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
• ÷ R Range = 3 to 16383
• ÷ N Range = 16 to 1023, P A Range = 0 to 127
• High–Gain Analog Phase Detector
• See Application Note AN969
Page 1 of 10
www.lansdale.com
Issue A
ML145159
LANSDALE Semiconductor, Inc.
BLOCK DIAGRAM
÷
′
′
÷
÷
* FSO is not and cannot be used as a digital phase detector output.
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised that
normal precautions be taken to avoid applica-
tions of any voltage higher than maximum rated
voltages to this high–impedance circuit. For
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
DD
– 0.5 to + 10
V
V , V
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
in out
I , I
Input or Output Current (DC or Transient),
per Pin
10
mA
in out
proper operation it is recommended that V and
in
V
be constrained to the range V
≤ (V or
in
out
SS
I
, I
Supply Current, V
DD
or V
SS
Pins
30
500
mA
mW
°C
DD SS
V
) ≤ V
.
out DD
P
D
Power Dissipation, per Package
Storage Temperature
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V
SS
T
stg
– 65 to + 150
260
or V ).
DD
T
L
Lead Temperature (8–Second Soldering)
°C
* Maximum Ratings are those values beyond which damage to the device may occur.
Page 2 of 10
www.lansdale.com
Issue A
ML145159
LANSDALE Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
except I
and I
APD
which are referenced to V ′)
SS
CR
– 40°C
25°C
85°C
Characteristic
Power Supply Voltage Range
Output Voltage
Symbol
V
Unit
V
Min
Max
Min
Max
Min
Max
DD
V
DD
—
3
9
3
9
3
9
0 Level
1 Level
0 Level
1 Level
V
OL
3
5
9
—
—
—
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
V
V
= 0 V or V
= 0 µA
in
DD
I
out
(Except OSC
and APD
)
V
OH
3
5
9
2.95
4.95
8.95
—
—
—
2.95
4.95
8.95
—
—
—
2.95
4.95
8.95
—
—
—
out
out
Output Voltage
V
OL
3
5
9
—
—
—
0.9
1.5
2.7
—
—
—
0.9
1.5
2.7
—
—
—
0.9
1.5
2.7
V
OSC
out
= 0 V or V
V
in
DD
V
OH
3
5
9
2.1
3.5
6.3
—
—
—
2.1
3.5
6.3
—
—
—
2.1
3.5
6.3
—
—
—
∆Voltage, V
CH
– V
, I
≈ 0 µA
∆V
—
—
—
—
1.05
—
—
V
V
APDout APDout
Input Voltage
0 Level
1 Level
V
IL
3
5
9
—
—
—
0.9
1.5
2.7
—
—
—
0.9
1.5
2.7
—
—
—
0.9
1.5
2.7
V
= 0.5 V or V
– 0.5 V
out
DD
(All Outputs Except OSC
)
out
V
IH
3
5
9
2.1
3.5
6.3
—
—
—
2.1
3.5
6.3
—
—
—
2.1
3.5
6.3
—
—
—
Input Voltage* — OSC
V
V
V
in
IL
IH
V
O
V
O
V
O
= 2.1 V or 0.9 V
= 3.5 V or 1.5 V
= 6.3 V or 2.7 V
0 Level
1 Level
3
5
9
—
—
—
0
0
0
—
—
—
0
0
0
—
—
—
0
0
0
V
V
O
V
O
V
O
= 0.9 V or 2.1 V
= 1.5 V or 3.5 V
= 2.7 V or 6.3 V
3
5
9
3.0
5.0
9.0
—
—
—
3.0
5.0
9.0
—
—
—
3.0
5.0
9.0
—
—
—
Output Current — MC
I
mA
OH
V
= 2.7 V
= 4.6 V
= 8.5 V
Source
Sink
3
5
9
– 0.60
– 0.90
– 1.50
—
—
—
– 0.50
– 0.75
– 1.25
—
—
—
– 0.30
– 0.50
– 0.80
—
—
—
out
V
V
out
out
V
= 0.3 V
= 0.4 V
= 0.5 V
I
3
5
9
1.30
1.90
3.80
—
—
—
1.10
1.70
3.30
—
—
—
0.66
1.08
2.10
—
—
—
out
OL
V
V
out
out
Output Current, C , V
= 4.5 V, R = 240 k
I
9
9
—
—
—
—
– 90
170
– 110
350
—
—
—
—
µA
µA
R
CR
R
CR
Output Current, APD
out
I
APD
R
= 240 k, V
CH
= 0 V, V = 4.5 V
APDout
O
Output Current — Other Outputs
I
mA
OH
V
= 2.7 V
= 4.6 V
= 8.5 V
Source
Sink
3
5
9
– 0.44
– 0.64
– 1.30
—
—
—
– 0.35
– 0.51
– 1.00
—
—
—
– 0.22
– 0.36
– 0.70
—
—
—
out
V
V
out
out
V
= 0.3 V
= 0.4 V
= 0.5 V
I
3
5
9
0.44
0.64
1.30
—
—
—
0.35
0.51
1.00
—
—
—
0.22
0.36
0.70
—
—
—
out
OL
V
V
out
out
Input Current — Data, CLK, ENB
I
I
9
9
—
2
0.3
50
—
2
0.1
25
—
2
1.0
22
µA
µA
pF
pF
µA
in
Input Current — f , OSC
in
in
in
Input Capacitance
C
—
—
—
—
10
—
—
10
—
—
10
in
Three–State Output Capacitance — FSO
C
10
10
10
out
DD
Quiescent Current
I
3
5
9
—
—
—
800
1200
1600
—
—
—
800
1200
1600
—
—
—
1600
2400
3200
V
= 0 V or V
= 0 µA
in
DD
I
out
Three–State Leakage Current, V
= 0 V or 9 V
I
9
—
0.3
—
0.1
—
3.0
µA
out
OZ
* DC coupled square wave.
Page 3 of 10
www.lansdale.com
Issue A
ML145159
LANSDALE Semiconductor, Inc.
SWITCHING CHARACTERISTICS (T = 25°C, C = 50 pF)
A
L
Figure
No.
Characteristic
Symbol
V
DD
Min
Max
Unit
Output Rise Time — MC
4, 9
4, 9
4, 9
5, 9
6
t
3
5
9
—
—
—
115
60
40
ns
TLH
Output Fall Time — MC
t
3
5
9
—
—
—
60
34
30
ns
ns
ns
ns
THL
Output Rise and Fall Time — LD and SR
out
t
t
,
3
5
9
—
—
—
140
80
60
TLH
THL
Propagation Delay Time — f to MC
in
t
t
,
3
5
9
—
—
—
125
80
50
PLH
PHL
Setup Times — Data to CLK
CLK to ENB
t
su
3
5
9
30
20
18
—
—
—
3
5
9
70
32
25
—
—
—
Hold Time — CLK to Data
Recovery Time — ENB to CLK
6
6
7
8
t
3
5
9
12
12
15
—
—
—
ns
ns
µs
ns
h
t
3
5
9
5
10
20
—
—
—
rec
Input Rise and Fall Times — CLK, OSC , f
in in
t , t
r f
3
5
9
—
—
—
5
2
0.5
Input Pulse Width — ENB and CLK
t
w
3
5
9
40
35
25
—
—
—
NOTE: Refer to the graphs and text in application note AN969 for maximum frequency information.
Page 4 of 10
www.lansdale.com
Issue A
ML145159
LANSDALE Semiconductor, Inc.
PIN DESCRIPTIONS
COMPONENT PINS
INPUT PINS
C
R
OSC , OSC
in out
Ramp Capacitor (PDIP, SOG – Pin 15, SSOP – Pin 20)
Oscillator Input and Oscillator Output (PDIP, SOG –
Pins 2, 3; SSOP – Pins 7, 8)
The capacitor connected from this pin to V ’ is charged lin-
SS
early, at a rate determined by R . The voltage on this capacitor
R
is proportional to the phase difference of the frequencies pres-
ent at the internal phase detector inputs. A polystyrene or
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel–resonant crystal.
Frequency–setting capacitors of appropriate value must be con- mylar capacitor is recommended.
nected from OSC to V and OSC toV . OSC may
in SS out SS in
also serve as input for an externally–generated reference sig-
R
R
Ramp Current Bias Resistor (PDIP, SOG – Pin 20,
SSOP – Pin 5)
nal. This signal will typically be AC coupled to OSC , but for
larger amplitude signals (standard CMOS logic levels), DC
coupling may also be used. In the external reference mode, no
in
A resistor connected from this pin to V ’ determines the
SS
rate at which the ramp capacitor is charged, thereby affecting
the phase detector gain (see Figure 2).
connection is required to OSC
.
out
f
in
C
H
Frequency Input (PDIP, SOG – Pin 10, SSOP – Pin 15)
Hold Capacitor (PDIP, SOG – Pin 18, SSOP – Pin 3)
Input to the positive edge triggered divide–by–N and di-
The charge stored on the ramp capacitor is transferred to the
vide–by–A counters. f is typically derived from a dual–mod-
in
capacitor connected from this pin to either V ’ or V ’. The
DD SS
ulus prescaler and is AC coupled. This input has an inverter
biased in the linear region to allow use with AC coupled sig-
nals as low as 500 mV peak–to–peak or direct coupled signals
ratio of C to C should be large enough to have no effect on
R
H
the phase detector gain (C > 10 C ). A low–leakage capaci-
R
H
tor should be used.
swinging from V
to V .
DD
SS
R
O
DATA
Output Bias Current Resistor (PDIP, SOG – Pin 1,
SSOP – Pin 6)
Serial Data Input (PDIP, SOG – Pin 12, SSOP – Pin 17)
Counter and control information is shifted into this input.
The last data bit entered goes into the one–bit control shift reg-
ister. A logic 1 allows the reference counter information to be
loaded into its 14–bit latch when ENB goes high. A logic 0
entered as the control bit disables the reference counter latch.
The divide–by–A/divide–by–N counter latch is loaded, regard-
less of the contents of the control register, when ENB goes
high. The data entry format is shown in Figure 1.
A resistor connected from this pin to V ’ biases the output
SS
N–Channel transistor, thereby setting a current sink on the ana-
log phase detector output. This resistor adjusts the APD
current (see Figure 3).
bias
out
OUTPUT PINS
APD
out
Analog Phase Detector Output (PDIP, SOG – Pin 17,
SSOP – Pin 2)
ENB
Transparent Latch Enable (PDIP, SOG – Pin 13,
SSOP – Pin 18)
This output produces a voltage that controls an external
VCO. The voltage range of this output (V
= + 9 V) is from
A logic high on this input allows data to be entered into the
divide–by–A/divide–by–N latch and, if the control bit is high,
into the reference counter latch. Counter programming is unaf-
fected when ENB is low. ENB should be kept normally low
and pulsed high to transfer data to the latches.
DD
below + 0.5 V to + 8 V or more. The source impedance of this
output is the equivalent of a source follower with an externally
variable source resistor. The source resistor depends upon the
output bias current controlled by the output bias current resis-
tor, R . The bias current is adjustable from 0.01 mA to 0.5
O
CLK
mA. The output voltage is not more than 1.05 V below the
sampled point on the ramp. With a constant sample of the
ramp voltage at 9 V and the hold capacitor of 50 pF, the instan-
taneous output ripple is about 5 mV peak–to–peak.
Shift Register Clock (PDIP, SOG – Pin 11, SSOP – Pin 16)
A low–to–high transition on this input shifts data from the
serial data input into the shift registers.
Figure 1. Data Entry Format
Page 5 of 10
www.lansdale.com
Issue A
ML145159
LANSDALE Semiconductor, Inc.
CHARGE
represent the dual modulus prescaler divide values respectively
for high and low modulus control levels, N is the number pro-
grammed into the divide–by–N counter, and A is the number
programmed into the divide–by–A counter.
Ramp Charge Indicator (PDIP, SOG – Pin 4,
SSOP – Pin 9)
This output is high from the time f goes high to the time
R
f goes high (f and f are the frequencies at the phase detec-
SRout
V
R
V
tor inputs). This high voltage indicates that the ramp capacitor,
Shift Register Output (PDIP, SOG – Pin 14,
SSOP – Pin 19)
C , is being charged.
R
FSO
This pin is the non–inverted output of the last stage of the
32–bit serial data shift register. It is not latched by the ENB
Three–State Frequency Steering Output (PDIP,
SOG –Pin 6, SSOP – Pin 11)
line. If unused, SR
should be floated.
out
If the counted down input frequency on f is higher than the
in
POWER SUPPLY
counted down reference frequency of OSC , this output goes
in
low. If the counted down VCO frequency is lower than that of
V
DD
the counted down OSC , this output goes high.
in
Positive Power Supply (PDIP, SOG – Pin 5, SSOP – Pin 10)
The repetition rate of the frequency steering output pulses is
approximately equal to the difference of the frequencies of the
Positive power supply input for all sections of the device
except the analog phase detector. V
and V ’ should be
DD
DD
two counted down inputs from the VCO and OSC . See
in
powered up at the same time to avoid damage to the
ML145159. V must be tied to the same potential asV ’.
Application Note AN969 for further information.
DD DD
LD
V
SS
Lock Detector Indicator (PDIP, SOG – Pin 9,
SSOP – Pin 14)
Negative Power Supply (PDIP, SOG – Pin 7,
SSOP – Pin 12)
This output is high during lock and goes low to indicate a
non–lock condition. The frequency and duration of the
non–lock pulses will be the same as either polarity of the fre-
quency steering output.
Circuit ground for all sections of the ML145159 except the
analog phase detector. V must be tied to the same potential
as V ’.
SS
SS
V
’
SS
MC
Analog Phase Detector Circuit Ground (PDIP, SOG –
Pin 16, SSOP – Pin 1)
Dual Modulus Prescaler Control (PDIP, SOG – Pin 8,
SSOP – Pin 13)
Separate power supply and ground inputs are provided to
help reduce the effects in the analog section of noise coming
from the digital sections of this device and the surrounding cir-
cuitry.
The modulus control level is low at the beginning of a count
cycle and remains low until the divide–by–A counter has
counted down from its programmed value. At that time, the
modulus control goes high and remains high until the di-
vide–by–N counter has counted the rest of the way down from
its programmed value (N – A additional counts since both
divide–by–N and divide–by–A are counting down during the
first portion of the cycle). Modulus control is then set back
low, the counters preset to their respective programmed values,
and the above sequence repeated. This provides for a total pro-
grammable divide value of NT = N • P + A, where P and P + 1
V
DD
’
Analog Power Supply (PDIP, SOG – Pin 19, SSOP – Pin 4)
Separate power supply and ground inputs are provided to
help reduce the effects in the analog section of noise coming
from the digital sections of this device and the surrounding cir-
cuitry.
Page 6 of 10
www.lansdale.com
Issue A
ML145159
LANSDALE Semiconductor, Inc.
′
′
′
µ
Ω
Figure 2. Charge Current vs Ramp Resistance
Figure 3. APD
Bias Current vs Output Resistance
out
DESIGN EQUATION
I
CHARGE
K
φ
=
2π f C
R R
where
K
= phase detector gain, I
= reference frequency
= ramp capacitor (in farads)
is from Figure 2
CHARGE
φ
f
R
C
R
SWITCHING WAVEFORMS
Figure 4.
Figure 5.
Figure 7.
Figure 6.
Figure 8.
*
* Includes all probe and fixture capacitance.
Figure 9. Test Circuit
Page 7 of 10
www.lansdale.com
Issue A
ML145159
LANSDALE Semiconductor, Inc.
DESIGN CONSIDERATIONS
The oscillator can be “trimmed” on–frequency by making a
portion or all of C1 variable. The crystal and associated com-
CRYSTAL OSCILLATOR CONSIDERATIONS
ponents must be located as close as possible to the OSC and
in
OSC
out
pins to minimize distortion, stray capacitance, stray
The following options may be considered to provide a ref-
erence frequency to Lansdale’s CMOS frequency synthesizers.
inductance, and start–up stabilization time. Circuit stray capac-
itance can also be handled by adding the appropriate stray
Use of a Hybrid Crystal Oscillator
value to the values for C and C . For this approach, the
in out
Commercially available temperature–compensated crystal
oscillators (TCXOs) or crystal–controlled data clock oscilla-
tors provide very stable reference frequencies. An oscillator
capable of sinking and sourcing 50 µA at CMOS logic levels
may be direct or DC coupled to OSC . In general, the highest
frequency capability is obtained utilizing a direct coupled
square wave having a rail–to–rail (V
swing. If the oscillator does not have CMOS logic levels on the
outputs, capacitive or AC coupling to OSC may be used.
term C
stray
becomes zero in the above expression for C .
L
Power is dissipated in the effective series resistance of the
crystal, R , in Figure 12. The maximum drive level specified
e
by the crystal manufacturer represents the maximum stress that
a crystal can withstand without damaging or excessive shift in
operating frequency. R1 in Figure 10 limits the drive level. The
use of R1 is not necessary in most cases.
in
to V ) voltage
DD
SS
To verify that the maximum dc supply voltage does not over-
drive the crystal, monitor the output frequency as a function of
in
OSC , an unbuffered output, should be left floating.
out
voltage at OSC . (Care should be taken to minimize load-
out
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the eem
Electronic Engineers Master Catalog, the Gold Book, or simi-
lar publications.
ing.) The frequency should increase very slightly as the dc sup-
ply voltage is increased. An overdriven crystal will decrease in
frequency or become unstable with an increase in supply volt-
age. The operating supply voltage must be reduced or R1 must
be increased in value if the overdriven condition exists. The
user should note that the oscillator start–up time is proportion-
al to the value of R1.
Design an Off–Chip Reference
The user may design an off–chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the ML12061 MECL device. The reference signal from the
MECL device is AC coupled to OSC . For large amplitude
signals (standard CMOS logic levels), DC coupling is used.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have developed
expertise in CMOS oscillator design with crystals. Discussions
with such manufacturers can prove very helpful. See Table 1.
in
OSC , an unbuffered output, should be left floating. In gen-
out
eral, the highest frequency capability is obtained with a
direct–coupled square wave having rail–to–rail voltage swing.
Use of the On–Chip Oscillator Circuitry
The on–chip amplifier (a digital inverter) along with an ap-
propriate crystal may be used to provide a reference source fre-
quency. A fundamental mode crystal, parallel resonant at the
desired operating frequency, should be connected as shown in
Figure 10.
For V
= 5 V, the crystal should be specified for a loading
DD
* May be deleted in certain cases. See text.
capacitance, CL, which does not exceed 32 pF for frequencies
to approximately 8 MHz, 20 pF for frequencies in the area of 8
to 15 MHz, and 10 pF for higher frequencies. These are guide-
lines that provide a reasonable compromise between IC capaci-
tance, drive capability, swamping variations in stray and IC
Figure 10. Pierce Crystal Oscillator Circuit
input/output capacitance, and realistic C values. Assuming
L
R1 = 0 Ω. the shunt load capacitance, C , presented across the
L
crystal can be estimated to be:
Figure 11. Parasitic Capacitances of the
Amplifier and C
stray
C C
in out
C1 • C2
C1 + C2
C =
L
+ C + C
+
stray
a
C
+ C
in
out
where
C
= 5 pF (see Figure 11)
= 6 pF (see Figure 11)
in
C
out
C = 1 pF (see Figure 11)
a
C1 and C2 = external capacitors (see Figure 10)
C
= the total equivalent external circuit stray
capacitance appearing across the
crystal terminals
stray
NOTE: Values are supplied by crystal manufacturer
(parallel resonant crystal).
Figure 12. Equivalent Crystal Networks
Page 8 of 10
www.lansdale.com
Issue A
ML145159
LANSDALE Semiconductor, Inc.
Table 1. Partial List of Crystal Manufacturers
Address
Name
Phone
United States Crystal Corp.
Crystek Crystal
Statek Corp.
3605 McCart Ave., Ft. Worth, TX 76110
2351 Crystal Dr., Ft. Myers, FL 33907
512 N. Main St., Orange, CA 92668
(817) 921–3013
(813) 936–2109
(714) 639–7810
NOTE: Lansdalecannotrecommendonesupplieroveranotherandinnowaysuggeststhatthisisacomplete
listing of crystal manufacturers.
Control”, Electro–Technology, June, 1969.
P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic
Design, May, 1966.
D. Babin, “Designing Crystal Oscillators”, Machine Design,
March 7, 1985.
RECOMMENDED READING
Technical Note TN–24, Statek Corp.
Technical Note TN–7, Statek Corp.
E. Hafner, “The Piezoelectric Crystal Unit – Definitions and
Method of Measurement”, Proc. IEEE, Vol. 57, No. 2 Feb.,
1969.
D. Babin, “Guidelines for Crystal Oscillator Design”, Ma-
chine Design, April 25, 1985.
D. Kemper, L. Rosine, “Quartz Crystals for Frequency
÷
÷
Figure 13. Timing Diagram for Minimum Divide Value (N = 16)
Page 9 of 10
www.lansdale.com
Issue A
ML145159
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
PLASTIC DIP 20 = RP
(MC145159RP)
CASE 738-03
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
20
1
11
10
B
C
L
INCHES
MIN
DIM
A
B
C
D
E
MAX
1.010
0.240
0.150
0.015
1.070 25.66
0.260
0.180
0.022
-T-
SEATING
PLANE
K
M
0.050 BSC
0.050
0.070
F
E
N
G
J
K
L
M
N
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
J 20 PL
0.300 BSC
15
0.040
7.62 BSC
D 20 PL
0.25 (0.010)
M
M
0.25 (0.010)
T
B
0°
°
0
0.51
°
15°
0.020
1.01
M
M
T
A
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabil-
ity, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the cus-
tomer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 10 of 10
www.lansdale.com
Issue A
相关型号：
MC14515BCLDS
4000/14000/40000 SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CDIP24, 623-05
MOTOROLA
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