MC145162D [LANSDALE]
60 MHz and 85 MHz Universal Programmable Dual PLL Frequency Synthesizers CMOS; 60 MHz和85 MHz的通用可编程双PLL频率合成器的CMOS
| 型号： | MC145162D |
| 厂家： | 
LANSDALE SEMICONDUCTOR INC. |
| 描述： | 60 MHz and 85 MHz Universal Programmable Dual PLL Frequency Synthesizers CMOS |
| 文件： | 总24页 (文件大小：1131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ML145162
60 MHz and 85 MHz Universal
Programmable Dual PLL Frequency
Synthesizers
CMOS
Legacy Device: Motorola MC145162
The ML145162 is a dual phase–locked loop (PLL) frequency synthesizer
especially designed for CT–1 cordless phone applications worldwide. This
frequency synthesizer is also for any product with a frequency operation at
60MHz or below.
P DIP 16 = EP
PLASTIC DIP
CASE 648
16
1
The device features fully programmable receive, transmit, reference, and
auxiliary reference counters accessed through an MCU serial interface. This
feature allows this device to operate in any CT–1 cordless phone application.
The device consists of two independent phase detectors for transmit and
receive loops. A common reference oscillator, driving two independent refer-
ence frequency counters, provides independent reference frequencies for
transmit and receive loops. The auxiliary reference counter allows the user to
select an additional reference frequency for receive and transmit loops if
required.
SOG 16 = -5P
SOG PACKAGE
CASE 751B
16
1
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 16
SOG 16
MC145162P
MC145162D
ML145162EP
ML145162-5P
• Operating Voltage Range: 2.5 to 5.5 V
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
• Operating Temperature Range: T = – 40 to +75°C
A
• Operating Power Consumption: 3.0 mA @ 2.5 V
• Maximum Operating Frequency: 60 MHz @ 200 mV p–p, V
• Three or Four Pins Used for Serial MCU Interface
= 2.5 V
DD
• Built–In MCU Clock Output with Frequency of Reference Oscillator ÷3/÷4
• Power Saving Mode Controlled by MCU
• Lock Detect Signal
• On–Chip Reference Oscillator Supports External Crystals to 16.0 MHz
• Reference Frequency Counter Division Range: 16 to 4095
• Auxiliary Reference Frequency Counter Division Range: 16 to 16,383
• Transmit Counter Division Range: 16 to 65,535
PIN ASSIGNMENT
CLK
1
2
16
15
LD
AD
in
TxPD
out
D
3
4
5
6
7
8
14
13
12
11
10
9
f
–T
in
in
ENB
TxPS/f
Tx
• Receive Counter Division Range: 16 to 65,535
MCUCLK
V
DD
RxPS/F
V
SS
Rx
OSC
in
RxPD
out
OSC
out
f
–R
in
Page 1 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
BLOCK DIAGRAM
A
B
f
R1
7
12–BIT PROGRAMMABLE
REFERENCE COUNTER
4
OSC
in
C
D
25
f
R2
14–BIT PROGRAMMABLE
AUXILIARY REFERENCE
COUNTER
8
5
OSC
out
TRANSMIT
SELECT
3/
4
MCUCLK
Tx
12–BIT SHIFT
REGISTER
14–BIT SHIFT
REGISTER
15
16
PHASE
DETECTOR
TxPD
LD
out
2
1
3
4
AD
in
MCU INTERFACE PROGRAMMING
MODE CONTROL
CLK
D
in
CONTROL REGISTER
ENB
13
11
TxPS/f
Tx
RxPS/f
Rx
16–BIT SHIFT REGISTER
RECEIVE
SELECT
14
Rx
16–BIT Tx PROGRAMMABLE
COUNTER
10
f
–T
in
PHASE
RxPD
out
DETECTOR
16–BIT SHIFT REGISTER
16–BIT Rx PROGRAMMABLE
COUNTER
V
V
= PIN 12
= PIN 6
9
DD
SS
f
–R
in
Page 2 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
This device contains protection circuitry to
guard against damage due to high static volt-
ages or electric fields. However, precautions
must be taken to avoid application of any voltage
higher than maximum rated voltages to this
high–impedance circuit. For proper operation,
Symbol
Rating
DC Supply Voltage
Value
Unit
V
V
DD
– 0.5 to + 6.0
V
Input Voltage, All Inputs
DC Current Drain Per Pin
– 0.5 to V
DD
+ 0.5
V
in
I , I
10
mA
mA
°C
in out
, I
V
V
and V
should be constrained to the range
in
out
I
DC Current Drain V
DD
or V
Pins
30
DD SS
SS
Storage Temperature Range
≤ (V or V ) ≤ V
in out DD
.
SS
Unused pins must always be tied to an
appropriate logic voltage level (e.g., either V
T
stg
– 65 to + 150
SS
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
or V ). Unused outputs must be left open.
DD
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V , T = 25°C)
SS
A
Guaranteed Limit
Symbol
Characteristic
Power Supply Voltage Range
Output Voltage
V
Unit
V
Min
Max
DD
V
DD
—
2.5
5.5
V
OL
0 Level
1 Level
0 Level
1 Level
Source
Sink
2.5
5.5
—
—
0.1
0.1
V
(I = 0)
out
(V = V or 0)
DD
V
OH
2.5
5.5
2.45
5.45
—
—
in
V
IL
Input Voltage
(V = 0.5 V or V
2.5
5.5
—
—
0.75
1.65
V
– 0.5 V)
out DD
V
IH
2.5
5.5
1.75
3.85
—
—
I
Output Current (V
(V
= 2.2 V)
= 5.0 V)
2.5
5.5
– 0.18
– 0.55
—
—
mA
µA
OH
out
out
I
(V
out
(V
out
= 0.3 V)
= 0.5 V)
2.5
5.5
0.18
0.55
—
—
OL
I
IL
Input Current
OSC , f –T, f –R
in in in
2.5
5.5
—
—
– 30
– 66
(V = 0)
in
AD , CLK, D , ENB
in in
2.5
5.5
—
—
– 1.0
– 1.0
I
IH
(V = V
in
– 0.5)
DD
OSC , f –T, f –R
in in in
2.5
5.5
—
—
30
66
AD , CLK, D , ENB
in in
2.5
5.5
—
—
5.0
5.0
I
Three–State Leakage Current (V
= 0 V or 5.5 V)
out
5.5
—
—
—
—
100
8.0
nA
pF
OZ
C
Input Capacitance
in
C
Output Capacitance
Standby Current
—
8.0
pF
out
I
2.5
5.5
—
—
0.3
1.5
mA
DD(stdby)
(All Counters are in Power–Down Mode with Oscillator On)
I
Operating Current
mA
DD
ML145162: 200 mV p–p input at f –T and f –R = 60 MHz
2.5
—
3.0
in
in
Page 3 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
SWITCHING CHARACTERISTICS (T = 25°C, C = 50 pF)
A
L
Guaranteed Limit
Figure
No.
Symbol
Characteristic
V
DD
Unit
Min
Max
t
Output Rise Time
Output Fall Time
1
1
2
3
2.5
5.5
—
—
200
100
ns
TLH
THL
t
2.5
5.5
—
—
200
100
ns
µs
t , t
r f
Input Rise and Fall Time
Input Pulse Width
OSC
in
2.5
5.5
—
—
5.0
4.0
t
w
CLK and ENB
2.5
5.5
80
60
—
—
ns
f
Input Frequency
OSC
2.5 – 5.5
2.5 – 5.5
—
—
16
60
MHz
max
in
Input = Sine Wave @ ≥ 200 mV p–p
Minimum Start–Up Time
Setup Time
f –R, f –T
in in
t
st
10
ms
ns
t
su
DATA to CLK
ENB to CLK
5
5
5
2.5
5.5
100
200
—
—
t
h
Hold Time
CLK to DATA
3.0
5.0
80
40
—
—
ns
ns
t
Recovery Time
ENB to CLK
3.0
5.0
80
40
—
—
rec
t
Setup Time
ENB to CLK
CLK to ENB
4
4
2.5 – 5.5
2.5 – 5.5
80
600
dc
—
—
ns
ns
su1
t
Hold Time
h1
f
Phase Detector Frequency
Output Clock Frequency
12.5
5.33
kHz
MHz
f
MCUCLK
dc
MCUCLK
(OSC
3)
in
Page 4 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
SWITCHING WAVEFORMS
t
t
f
t
t
THL
r
TLH
CLK, OSC
in in
,
in
ANY
OUTPUT
90%
10%
90%
10%
f
–T, f –R
Figure 1.
Figure 2.
t
w
ENB, CLK
50%
V
V
DD
AD
,
in
in
50%
D
SS
Figure 3.
t
t
h
su
V
V
DD
CLK
ENB
50%
FIRST
CLK
LAST
CLK
V
V
DD
SS
CLK
LAST
CLK
FIRST
CLK
t
t
su
rec
SS
V
V
DD
50%
t
t
h1
su1
V
V
DD
SS
ENB
PREVIOUS
DATA
LATCHED
SS
Figure 4. ENB High During Serial Transfer
Figure 5. ENB Low During Serial Transfer
Page 5 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
PIN DESCRIPTIONS
register. Details of the counter test mode are in the Tx/Rx
Channel Counter Test section of this data sheet.
INPUT PINS
f –T/f –R
in in
OSC /OSC
in
out
Transmit/Receive Counter Inputs (Pins 14, 9)
Reference Oscillator Input/Output (Pins 7, 8) These pins
form a reference oscillator when connected to an external par-
allel–resonant crystal. Figure 6 shows the relationship of dif-
ferent crystal frequencies and reference frequencies for cord-
less phone applications in various countries. OSC may also
serve as input for an externally generated reference signal
which is typically AC coupled.
f –T and f –R are inputs to the transmit and the receive
in
in
counters, respectively. These signals are typically driven from
the loop VCO and AC coupled. The minimum input signal
level is 200 mV p–p @ 60.0 MHz.
in
OUTPUT PINS
TxPD /RxPD
out
out
MCUCLK
Transmit/Receive Phase Detector Outputs (Pins 15, 10)
System Clock (Pin 5)
These are three–state outputs of the transmit and receive
phase detectors for use as loop error signals (see Figure 7 for
phase detector output wave forms). Phase detector gain
This output pin provides a signal of the crystal frequency
(OSC ) divided by 3 or 4 that is controlled by a bit in the
out
control register.
isV /4 π volts per radian.
DD
This signal can be a clock source for the MCU or other sys-
tem clocks.
Frequency f > f or f leading: output = negative pulse.
V
R
V
V
Frequency f < f or f lagging: output = positive pulse.
V
V
R
Frequency f = f and phase coincidence: output = high–
R
ADi , D , CLK, ENB
n
in
impedance state.
Auxiliary Data In, Data In, Clock, Enable (Pins 2, 3, 1, 4)
NOTE: f is the divided–down reference frequency at the
R
These four pins provide an MCU serial interface for pro-
gramming the reference counter, the transmit–channel count-
er, and the receive–channel counter. They also provide various
controls of the PLL including the power saving mode and the
programming format.
phase detector input and f is the divided–down VCO frequen-
V
cy at the phase detector input.
LD
Lock Detect (Pin 16)
The lock detect signal is associated with the transmit loop.
The output at a high level indicates an out–of–lock condition
(see Figure 7 for the LD output wave form).
TxPS/f , RxPS/f
Tx
Rx
Transmit Power Save, Receive Power Save (Pins 13, 11)
For a normal application, these output pins provide the status
of the internal power saving mode operation. If the
POWER SUPPLY
transmit–channels counter circuitry is in power down mode,
V
TxPS/f outputs a high state. If the receive–channels counter
DD
Positive Power Supply (Pin 12)
Tx
circuitry is in power down mode, RxPS/f is set high. These
Rx
outputs can be applied for controlling the external power
switch for the transmitter and the receiver to save MCU control
pins.
V
is the most positive power supply potential ranging
DD
from 2.5 to 5.5 V with respect to V
.
SS
In the Tx/Rx channel counter test mode, the TxPS/f and
V
SS
Tx
RxPS/f pins output the divided value of the transmit channel
Rx
Negative Power Supply (Pin 6)
counter (f ) and the receive channel counter (f ), respec-
Tx
Rx
V
is the most negative supply potential and is usually con-
SS
nected to ground.
tively. This test mode operation is controlled by the control
A
f
R1
R2
B
C
N (12 BITS)
4
OSC
in
25
f
D
M (14 BITS)
OSC
out
Crystal
N Value
f
f
R1→B
R2→C
1.0 kHz
11.150 MHz
11.150 MHz
10.240 MHz
12.000 MHz
446
223
512
600
6.25 kHz
12.5 kHz
5.0 kHz
5.0 kHz
Figure 6. Reference Frequencies for Cordless Phone Applications of Various Countries
Page 6 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
V
H
f
, REFERENCE
R
(OSC
in
REFERENCE COUNTER)
V
V
L
f , FEEDBACK
V
H
(f –T
in
Tx COUNTER OR
Rx COUNTER)
f
–R
in
V
L
*
V
TxPD
out
H
OR
HIGH IMPEDANCE
RxPD
out
LD
V
V
= High voltage level.
= Low voltage level.
H
L
*At this point, when both f and f are in phase, the output is forced to near mid supply.
R
V
NOTE: The TxPD
out
and RxPD
generate error pulses during out–of–lock conditions. When locked in phase and fre-
out
quency, the output is high impedance and the voltage at that pin is determined by the low–pass filter capacitor.
Figure 7. Phase Detector/Lock Detector Output Waveforms
MCU PROGRAMMING SCHEME
power–down mode for current saving. (Other power down
modes are also provided through the control register per Table
2 and Figure 8.) At the falling edge of the ENB signal, the data
is stored in the registers.
There are two interfacing schemes for the universal channel
mode: the three–pin and the four–pin interfacing schemes. The
three–pin interfacing scheme is suited for use with the MCU
SPI (serial peripheral interface) (Figure 10), while the four–pin
interfacing scheme is commonly used for general I/O port con-
nection (Figure 11).
For the three–pin interfacing scheme, the auxiliary data
select bit is set to 0. All 32 bits of data, which define both
the16–bit transmit counter and the 16–bit receive counter, latch
into the PLL internal register through the data in pins at the
leading edge of CLK. See Figures 12 and 13.
For the four–pin interfacing scheme, the auxiliary data select
bit is set to 1. In this scheme, the 16–bit transmit counter’s data
The MCU programming scheme is defined in two formats
controlled by the ENB input. If the enable signal is high during
the serial data transfer, control register/reference frequency
programming is selected. If the ENB is low, programming of
the transmit and receive counters is selected. During program-
ming of the transmit and receive counters, both AD and D
pins can input the data to the transmit and receive counters.
Both counters’ data is clocked into the PLL internal shift regis-
ter at the leading edge of the CLK signal. It is not necessary to
reprogram the reference frequency counter/control register
when using the enable signal to program the transmit/receive
channels.
In programming the control register/reference frequency
scheme, the most significant bit (MSB) of the programming
word identifies whether the input data is the control word or
the reference frequency data word. If the MSB is 1, the input
data is the control word (Figure 8). Also see Figure 8 and Table
1 for control register and bit function. If the MSB is 0, the
input data is the reference frequency (Figure 9).
The reference frequency data word is a 32–bit word contain-
ing the 12–bit reference frequency data, the 14–bit auxiliary
reference frequency counter information, the reference fre-
quency selection plus, the auxiliary reference frequency count-
er enable bit (Figure 9).
in
in
enters into the AD pin at the same time as the 16–bit receive
in
counter’s data enters into the D pin. This simultaneous entry
in
of the transmit and receive counters causes the programming
period of the four–pin scheme to be half that of the three–pin
scheme (see Figures 14 and 15).
While programming Tx/Rx Channel Counter, the ENB pin
must be pulsed to provide falling edge to latch the shifted data
after the rising edge of the last clock. Maximum data transfer
rate is 500 kbps.
If the AUX REF ENB bit is high, the 14–bit auxiliary refer-
ence frequency counter provides an additional phase reference
frequency output for the loops. If AUX REF ENB bit is low,
the auxiliary reference frequency counter is forced into
NOTE
10 ms should be allowed for initial start–up time for
the oscillator to allow all registers to clear and enable
programming of new register values.
Page 7 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
CONTROL REGISTER IDENTIFIER = 1
CONTROL REGISTER DATA
AUX
DATA
SELECT
REF
OUT
3/
TEST
BIT
TxPD
ENABLE
RxPD
ENABLE
REF PD
ENABLE
D
in
1
0
4
MSB
LSB
CLK
ENB
NOTE: ENB must be high during the serial transfer.
Figure 8. Programming Format of the Control Register
Table 1. Control Register Function Bits Description
Test Bit
Set to 1 for Tx/Rx channel counter test mode
Set to 0 for normal application
Aux Data Select
Set to 1 for both AD and D pins inputting the transmit 16–bits data and receive 16–bits data
in in
respectively.
Set to 0 for normal application interfacing with MCU serial peripheral interface. Does not use AD pin;
in
tie AD to V
.
in SS
If set to 1, REF
If set to 0, REF
output frequency is equal to OSC
out
3.
REF
out
3/
4
out
out
output is OSC
out
4.
TxPD Enable
RxPD Enable
Ref PD Enable
If set to 1, the transmit counter, transmit phase detector, and the associated circuitry is in power–
down mode.
Tx PS/f is set “High”.
Tx
If set to 1, the receive counter, receive phase detector, and the associated circuitry is in power–
down mode.
Rx PS/f
is set “High”.
Rx
If set to 1, both 12–bit and 14–bit reference frequency counters are in power–down mode.
Table 2. Control Register Power Down Bits Function
TxPD
Enable
RxPD
Enable
REF PD
Enable
Reference
Frequency Counter
Tx–Channel Counter
Rx–Channel Counter
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
—
—
—
—
—
Power Down
—
—
Power Down
Power Down
—
—
Power Down
—
Power Down
Power Down
Power Down
Power Down
—
Power Down
—
Power Down
Power Down
Power Down
Page 8 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
REFERENCE FREQUENCY COUNTER
IDENTIFIER = 0
REFERENCE
FREQUENCY
COUNTER
REFERENCE
FREQUENCY
SELECT
REFERENCE
FREQUENCY
SELECT
AUX REFERENCE
FREQUENCY COUNTER
DIVIDE RATIO
DIVIDE RATIO
AUX
REF
ENABLE
Tx–0
Rx–0
12–BITS REF FREQ
DATA
f
f
14–BITS AUX REF FREQ
DATA
R1
S1
R1
S2
D
0
in
SELECT SELECT
CLK
ENB
NOTE: ENB must be high during the serial transfer.
Figure 9. Programming Format of the Auxiliary/Reference Frequency Counters
D
in
MCU
UNIVERSAL PLL
AUX DATA BIT = 0
USING
CLK
ENB
SERIAL PERIPHERAL
INTERFACE PORT
Figure 10. MCU Interface Using SPI
AD
in
D
in
MCU
USING
NORMAL I/O PORT
UNIVERSAL PLL
AUX DATA BIT = 1
CLK
ENB
Figure 11. MCU Interface Using Normal I/O Ports with
Both D and AD for Faster Programming Time
in
in
Page 9 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
CONTROL REGISTER IDENTIFIER = 1
CONTROL REGISTER DATA
AUX
REF
OUT
3/
REF PD
ENABLE
TEST
BIT
TxPD
ENABLE
RxPD
ENABLE
DATA
D
1
0
in
SELECT
4
MSB
LSB
AUX DATA SELECT = 0
CLK
ENB
NOTE: ENB must be high during the serial transfer.
Figure 12. Programming Format for Control Register (3–Pin Interfacing Scheme)
16–BIT Tx COUNTER
DIVIDE RATIO
16–BIT Rx COUNTER
DIVIDE RATIO
D
in
LAST
CLOCK
CLK
ENB
NOTE: ENB must be low during the serial transfer.
Figure 13. Programming Format for Transmit and Receive Counters
(3–Pin Interfacing Scheme)
CONTROL REGISTER IDENTIFIER = 1
CONTROL REGISTER DATA
REF
OUT
3/
AUX
DATA
SELECT
TxPD
ENABLE
RxPD
ENABLE
REF PD
ENABLE
TEST
BIT
D
1
0
in
4
MSB
LSB
AUX DATA SELECT = 1
CLK
ENB
NOTE: ENB must be high during the serial transfer.
Figure 14. Programming Format for Control Register (4–Pin Interfacing Scheme)
Page 10 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
16–BIT Tx COUNTER
DIVDE RATIO
AD
D
in
16–BIT Rx COUNTER
DIVIDE RATIO
in
LAST
CLOCK
CLK
ENB
NOTE: ENB must be low during the serial transfer.
Figure 15. Programming Format for Transmit and Receive Counters
(4–Pin Interfacing Scheme)
Table 3. Global CT–1 Reference Frequency Setting vs Channel Frequencies
Country
U.S.A.
Channels Frequency
46/49 MHz (10, 15, 25 Channels)
26/41 MHz
f
f
R2
R1
5.0 kHz
6.25 kHz/12.5 kHz
5.0 kHz
—
France
—
Spain
31/41 MHz
—
Australia
U.K.
30/39 MHz
5.0 kHz
—
1.7/47 MHz
6.25 kHz
1.0 kHz
1.0 kHz
New Zealand
1.7/34/40 MHz
6.25 kHz
REFERENCE FREQUENCY SELECTION
AND PROGRAMMING
and ÷ 25 module can offer all the reference frequencies for
global CT–1 transmit and receive channel requirements. Users
can select their own reference frequency by introducing the
additional 14–bit auxiliary reference frequency counter.
Again, the 14–bit auxiliary reference frequency counter can
be shut down by the auxiliary reference enable bit in the refer-
ence counter programming word by setting the bit to 0. At this
Figure 16 shows the bit function of the reference frequency
programming word. The user can either select the “fixed” ref-
erence frequency for all channels accordingly or provide a spe-
cific reference frequency for a particular channel by using two
reference frequency counters (e.g., for an application in
France, the base set transmit channel common fixed reference
frequency is 6.25 kHz or 12.5 kHz). (See Table 3 and Figure 6
for reference frequencies for various countries.) However,
transmit channels 6, 8, and 14 can be set to 25 kHz, and chan-
nel 8 reference frequency can be set to 50 kHz. But this refer-
ence frequency may not be applied to the receiving side; there-
fore, the receiving side reference frequency must be generated
by another reference frequency counter. The higher the refer-
ence frequency, the better the phase noise performance and
faster the lock time, but the PLL consumes more current if
both reference frequency counters are in operation.
state, the f is automatically connected to point C (the ÷25
R2
block output), and f can be connected to point A or B by
R1
setting the f –S1 and f –S2 bits in the reference counter
R1
R1
program word. The 14–bit auxiliary reference frequency count-
er data will be in “Don’t Care” state.
If the 14–bit auxiliary reference frequency counter is enabled
(auxiliary reference enable = 1), then f is automatically con-
R2
nected to point D (14–bit counter output), and f can be
R1
selected to connect to point A, B, or C, depending on the bit
setting of f –S1 and f –S2. Table 4 and Figure 16 describe
R1 R1
the functions of the auxiliary reference enable bit and the
–S1 and f –S2 bits selection.
f
R1
R1
In general, the 12–bit reference frequency counter plus the ÷ 4
Page 11 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
A
B
f
R1
12–BIT PROGRAMMABLE
REFERENCE COUNTER
4
OSC
OSC
in
C
D
25
f
R2
14–BIT PROGRAMMABLE
AUXILIARY REFERENCE
COUNTER
out
Tx
1
TxPD
LD
PHASE
MAXIMUM
CRYSTAL FREQUENCY
16.0 MHz
out
DETECTOR
Tx–0
SELECT
0
Rx
1
PHASE
RxPD
out
DETECTOR
Rx–0
SELECT
0
REF FREQUENCY
COUNTER IDENTIFIER = 0
REFERENCE
FREQUENCY
SELECT
REFERENCE
FREQUENCY
COUNTER
REFERENCE
FREQUENCY
SELECT
AUXILIARY REFERENCE
FREQUENCY COUNTER
AUX
REF
ENABLE
Tx–0
Rx–0
12–BITS REF FREQ
DATA
f
f
14–BITS AUX REF FREQ
DATA
R1
S1
R1
S2
D
0
in
SELECT SELECT
CLK
ENB
NOTE: ENB must be high during the serial transfer.
Figure 16. Reference Frequency Counter/Selection Programming Mode
Table 4. Bit Function and the Reference Frequency Selection Bit Setting of the
Reference Frequency Counter Programming Word
AUX REF
Enable
Auxiliary Reference Frequency
Counter Mode
Module
Select
f
f
R1
R1
S1
S2
f
Routing
R1
0
14–Bit Auxiliary Reference Frequency
Counter Disable
f
→ C
0
0
0
1
N/A
R1
R2
f
f
→ A
1
1
0
1
→ B
R1
N/A
N/A
1
14–Bit Auxiliary Reference Frequency
Counter Enable
f
→ D
0
0
0
1
R2
f
f
→ A
R1
R1
R1
1
1
0
1
→ B
→ C
f
N/A = Not Applicable
Page 12 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
POWER SAVING OPERATION
The output pins TxPS/f and RxPS/f output the status of
the internal power saving setting. If the bit TxPD enable is set
“high” (transmit counter is set to power–down mode), then the
Tx
Rx
This PLL has a programmable power–saving scheme. The
transmit and receive counters and the reference frequency
counter can be powered down individually by setting the TxPD
enable, RxPD enable, and Ref PD enable bits of the control
register. The functions of the power down control bits are
explained in Table 2 and the programming format is in Figure 8.
TxPS/f pin will also output a “high” state. This TxPS/f
out-put can control an external power switch to switch off the
transmitter, as shown in Figure 17. This scheme can be applied
Tx
Tx
to the RxPS/f output to control the receiver power saving
Rx
operation as required.
UNIVERSAL DUAL PLL
POWER SUPPLY
V
DD
TxPS/f
Tx
Tx POWER–DOWN
ENABLE FLAG
Q
POWER SWITCH FOR TRANSMITTER
Tx DIVIDER CHAIN COUNTER, PHASE DETECTOR
V
DD
Tx
POWER
AMP
RxPS/f
Rx
Rx POWER–DOWN
ENABLE FLAG
Q
TO CONTROL THE RECEIVER
POWER SWITCH
Rx DIVIDER CHAIN COUNTER, PHASE DETECTOR
Figure 17. TxPS/f and RxPS/f
Outputs to Control Power Switches
Tx
Rx
of the Transmitter and the Receiver
Page 13 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
Tx/Rx CHANNEL COUNTER TEST
In normal applications, the TxPS/f and the RxPS/f out-
put pins indicate the power saving mode status. However, the
user can examine the Tx and Rx channel counter outputs by
setting the Test bit in the control register to 1. The final value
of the transmit–channel counter and the receive–channel count-
er multiplex out to TxPS/f and RxPS/f respectively. The
Tx
Rx
Tx
Rx
user can verify the divided–down output waveform associated
with the RF input level in the PLL circuitry implementation
(Figure 18).
16–BIT Tx PROGRAMMABLE
CHANNELS COUNTER
f
–T
Tx
in
f
Tx
TxPS/f
TxPS
IF TEST BIT IS SET TO 1, THE f
Tx
CONTROL REGISTER IDENTIFIER = 1
AND f ARE MUXED OUT AT PINS
Rx
CONTROL REGISTER
TxPS/f AND RxPS/f
,
Tx
Rx
RESPECTIVELY, FOR Rx/Tx
CHANNEL COUNTER TEST.
AUX
DATA
SELECT
REF
OUT
3/
TEST
BIT
TxPD
ENABLE
RxPD
ENABLE
REF PD
ENABLE
D
1
0
in
4
16–BIT Rx PROGRAMMABLE
CHANNELS COUNTER
f
–R
Rx
in
f
Rx
RxPS/f
RxPS
Figure 18. RF Buffer Sensitivity
Page 14 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
Table 5. France CT–1 Base Set Frequency
Tx Channel
Frequency
(MHz)
Tx Counter Value
(Ref. Freq. =
6.25 kHz)
f
–R Input
Rx Counter Value
(Ref. Freq. =
6.25 kHz)
in
Channel
Number
Frequency (MHz)
[1st IF = 10.7 MHz]
1
2
26.4875
26.4750
26.4625
26.4500
26.4375
26.4250
26.4125
26.4000
26.3875
26.3750
26.3625
26.3500
26.3375
26.3250
26.3125
4238
4236
4234
4232
4230
4228
4226
4224
4222
4220
4218
4216
4214
4212
4210
30.7875
30.7750
30.7625
30.7500
30.7375
30.7250
30.7125
30.7000
30.6875
30.6750
30.6625
30.6500
30.6375
30.6250
30.6125
4926
4924
4922
4920
4918
4916
4914
4912
4910
4908
4906
4904
4902
4900
4898
3
4
5
6
7
8
9
10
11
12
13
14
15
Table 6. France CT–1 Handset Frequency
Tx Channel
Frequency
(MHz)
Tx Counter Value
(Ref. Freq. =
6.25 kHz)
f
–R Input
Rx Counter Value
(Ref. Freq. =
6.25 kHz)
in
Channel
Number
Frequency (MHz)
[1st IF = 10.7 MHz]
1
2
41.4875
41.4750
41.4625
41.4500
41.4375
41.4250
41.4125
41.4000
41.3875
41.3750
41.3625
41.3500
41.3375
41.3250
41.3125
6638
6636
6634
6632
6630
6628
6626
6624
6622
6620
6618
6616
6614
6612
6610
37.1875
37.1750
37.1625
37.1500
37.1375
37.1250
37.1125
37.1000
37.0875
37.0750
37.0625
37.0500
37.0375
37.0250
37.0125
5950
5948
5946
5944
5942
5940
5938
5936
5934
5932
5930
5928
5926
5924
5922
3
4
5
6
7
8
9
10
11
12
13
14
15
Page 15 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
Table 7. Spain CT–1 Base Set Frequency
Tx Channel
Frequency
(MHz)
Tx Counter Value
(Ref. Freq. =
5.00 kHz)
f
–R Input
Rx Counter Value
(Ref. Freq. =
5.00 kHz)
in
Channel
Number
Frequency (MHz)
[1st IF = 10.695 MHz]
1
2
31.0250
31.0500
31.0750
31.1000
31.1250
31.1500
31.1750
31.2000
31.2500
31.2750
31.3000
31.3250
6205
6210
6215
6220
6225
6230
6235
6240
6250
6255
6260
6265
29.2300
29.2550
29.2800
29.3050
29.3300
29.3550
29.3800
29.4050
29.4550
29.4800
29.5050
29.5300
5846
5851
5856
5861
5866
5871
5876
5881
5891
5896
5901
5906
3
4
5
6
7
8
9
10
11
12
Table 8. Spain CT–1 Handset Frequency
Tx Channel
Frequency
(MHz)
Tx Counter Value
(Ref. Freq. =
5.00 kHz)
f
–R Input
Rx Counter Value
(Ref. Freq. =
5.00 kHz)
in
Channel
Number
Frequency (MHz)
[1st IF = 10.7 MHz]
1
2
39.9250
39.9500
39.9750
40.0000
40.0250
40.0500
40.0750
40.1000
40.1500
40.1750
40.2000
40.2250
7985
7990
7995
8000
8005
8010
8015
8020
8030
8035
8040
8045
20.3300
20.3550
20.3800
20.4050
20.4300
20.4550
20.4800
20.5050
20.5550
20.5800
20.6050
20.6300
4066
4071
4076
4081
4086
4091
4096
4101
4111
4116
4121
4126
3
4
5
6
7
8
9
10
11
12
Page 16 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
Table 9. New Zealand CT–1 Base Set Frequency
Tx Channel
Frequency
(MHz)
f
–R Input
Rx Counter Value
in
Channel
Number
Frequency (MHz)
[1st IF = 10.7 MHz]
(Ref. Freq. =
6.25 kHz)
Tx Counter Value
1782
1
2
1.7820
1.7620
1.7420
1.7220
1.7020
34.3500
34.3625
34.3750
34.3875
34.4000
29.7625
29.7500
29.7375
29.7250
29.7125
29.7000
29.6875
29.6750
29.6625
29.6500
4762
4760
4758
4756
4754
4752
4750
4748
4746
4744
1762
1742
1722
1702
5496
5498
5500
5502
5504
Ref Freq
= 1.0 kHz
3
4
5
6
7
Ref Freq
= 6.25 kHz
8
9
10
Table 10. New Zealand CT–1 Handset Frequency
Tx Channel
Tx Counter Value
(Ref. Freq. =
6.25 kHz)
Channel
Number
f
–R Input
in
Frequency
(MHz)
Frequency (MHz)
2.2370
Rx Counter Value
1
2
40.4625
40.4500
40.4375
40.4250
40.4125
40.4000
40.3875
40.3750
40.3625
40.3500
6474
6472
6470
6468
6466
6464
6462
6460
6458
6456
2237
2.2170
2217
2197
2177
2157
3784
3786
3788
3790
3792
Ref Freq
= 455 kHz
Ref Freq
= 1.0 kHz
3
2.1970
4
2.1770
5
2.1570
6
23.6500
23.6625
23.6750
23.6875
23.7000
7
Ref Freq
= 10.7 kHz
Ref Freq
= 6.25 kHz
8
9
10
Page 17 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
Table 11. Australia CT–1 Base Set Frequency
Tx Channel
Frequency
(MHz)
Tx Counter Value
(Ref. Freq. =
5.00 kHz)
f
–R Input
Rx Counter Value
(Ref. Freq. =
5.00 kHz)
in
Channel
Number
Frequency (MHz)
[1st IF = 10.695 MHz]
1
2
30.0750
30.1250
30.1750
30.2250
30.2750
30.1000
30.1500
30.2000
30.2500
30.3000
6015
6025
6035
6045
6055
6020
6030
6040
6050
6060
29.0800
29.1300
29.1800
29.2300
29.2800
29.1050
29.1550
29.2050
29.2550
29.3050
5816
5826
5836
5846
5856
5821
5831
5841
5851
5861
3
4
5
6
7
8
9
10
Table 12. Australia CT–1 Handset Frequency
Tx Channel
Frequency
(MHz)
Tx Counter Value
(Ref. Freq. =
5.00 kHz)
f
–R Input
Rx Counter Value
(Ref. Freq. =
5.00 kHz)
in
Channel
Number
Frequency (MHz)
[1st IF = 10.7 MHz]
1
2
39.7750
39.8250
39.8750
39.9250
39.9750
39.8000
39.8500
39.9000
39.9500
40.0000
7955
7965
7975
7985
7995
7960
7970
7980
7990
8000
19.3800
19.4300
19.4800
19.5300
19.5800
19.4050
19.4550
19.5050
19.5550
19.6050
3876
3886
3896
3906
3916
3881
3891
3901
3911
3921
3
4
5
6
7
8
9
10
Page 18 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
Table 13. U.K. CT–1 Base Set Frequency
Tx Channel
Frequency
(MHz)
Tx Counter Value
(Ref. Freq. =
1.00 kHz)
f
–R Input
Rx Counter Value
(Ref. Freq. =
6.25 kHz)
in
Channel
Number
Frequency (MHz)
[1st IF = 10.7 MHz]
1
2
3
4
5
6
7
8
1.6420
1.6620
1.6820
1.7020
1.7220
1.7420
1.7620
1.7820
1642
1662
1682
1702
1722
1742
1762
1782
36.75625
36.76875
36.78125
36.79375
36.80625
36.81875
36.83125
36.84375
5881
5883
5885
5887
5889
5891
5893
5895
Table 14. U.K. CT–1 Handset Frequency
Tx Channel
Frequency
(MHz)
Tx Counter Value
(Ref. Freq. =
6.25 kHz)
f
–R Input
Rx Counter Value
(Ref. Freq. =
1.00 kHz)
in
Channel
Number
Frequency (MHz)
[1st IF = 455 kHz]
1
2
3
4
5
6
7
8
47.45625
47.46875
47.48125
47.49375
47.50625
47.51875
47.53125
47.54375
7593
7595
7597
7599
7601
7603
7605
7607
2.097
2.117
2.137
2.157
2.177
2.197
2.217
2.237
2097
2117
2137
2157
2177
2197
2217
2237
Page 19 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
Table 15. U.S.A. (10 Channels) CT–1 Base Set Frequency
Tx Channel
Frequency
(MHz)
Tx Counter Value
(Ref. Freq. =
5.00 kHz)
f
–R Input
Rx Counter Value
(Ref. Freq. =
5.00 kHz)
in
Channel
Number
Frequency (MHz)
[1st IF = 10.695 MHz]
1
2
46.610
46.630
46.670
46.710
46.730
46.770
46.830
46.870
46.930
46.970
9322
9326
9334
9342
9346
9354
9366
9374
9386
9394
38.975
38.150
38.165
39.075
39.180
39.135
39.195
39.235
39.295
39.275
7795
7830
7833
7815
7836
7827
7839
7847
7859
7855
3
4
5
6
7
8
9
10
Table 16. U.S.A. (10 Channels) CT–1 Handset Frequency
Tx Channel
Frequency
(MHz)
Tx Counter Value
(Ref. Freq. =
5.00 kHz)
f
–R Input
Rx Counter Value
(Ref. Freq. =
5.00 kHz)
in
Channel
Number
Frequency (MHz)
[1st IF = 10.7 MHz]
1
2
49.670
49.845
49.860
49.770
49.875
49.830
49.890
49.930
49.990
49.970
9934
9969
9972
9954
9975
9966
9978
9986
9998
9994
35.915
35.935
35.975
36.015
36.035
36.075
36.135
36.175
36.235
36.275
7183
7187
7195
7203
7207
7215
7227
7235
7247
7255
3
4
5
6
7
8
9
10
Page 20 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
Table 17. U.S.A. (25 Channels) CT–1 Base Set Frequency
Tx Channel
Frequency
(MHz)
Tx Counter Value
(Ref. Freq. =
5.00 kHz)
f
–R Input
Rx Counter Value
(Ref. Freq. =
5.00 kHz)
in
Channel
Number
Frequency (MHz)
[1st IF = 10.7 MHz]
1
43.72
43.74
43.82
43.84
43.92
43.96
44.12
44.16
44.18
44.20
44.32
44.36
44.40
44.46
44.48
46.61
46.63
46.67
46.71
46.73
46.77
46.83
46.87
46.93
46.97
8744
8748
8764
8768
8784
8788
8824
8832
8836
8840
8864
8872
8880
8892
8896
9322
9326
9334
9342
9346
9354
9366
9374
9386
9394
38.06
38.14
38.16
38.22
38.32
38.38
38.40
38.46
38.50
38.54
38.58
38.66
38.70
38.76
38.80
38.97
39.145
39.16
39.07
39.175
39.13
39.19
39.23
39.29
39.27
7612
7628
7632
7644
7664
7676
7680
7692
7700
7708
7716
7732
7740
7752
7760
7794
7829
7832
7814
7835
7826
7838
7846
7858
7854
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Page 21 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
Table 18. U.S.A. (25 Channels) CT–1 Handset Frequency
Tx Channel
Frequency
(MHz)
Tx Counter Value
(Ref. Freq. =
5.00 kHz)
f
–R Input
Rx Counter Value
(Ref. Freq. =
5.00 kHz)
in
Channel
Number
Frequency (MHz)
[1st IF = 10.7 MHz]
1
48.76
48.84
48.86
48.92
49.02
49.08
49.10
49.16
49.20
49.24
49.28
49.36
49.40
49.46
49.50
49.67
49.845
49.86
49.77
49.875
49.83
49.89
49.93
49.99
49.97
9752
9768
9772
9748
9804
9816
9820
9832
9840
9848
9856
9872
9880
9892
9900
9934
9969
9972
9954
9975
9966
9978
9986
9998
9994
33.02
33.04
33.12
33.14
33.22
33.26
33.42
33.46
33.48
33.50
33.62
33.66
33.70
33.76
33.78
33.91
33.93
33.97
36.01
36.03
36.07
36.13
36.17
36.23
36.27
6604
6608
6624
6628
6644
6652
6684
6692
6696
6700
6724
6732
6740
6752
6756
7182
7186
7194
7202
7206
7214
7226
7234
7246
7254
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Table 19. Korea CT–1 Base Set Frequency
Tx Channel
Frequency
(MHz)
Tx Counter Value
(Ref. Freq. =
5.00 kHz)
f
–R Input
Rx Counter Value
(Ref. Freq. =
5.00 kHz)
in
Channel
Number
Frequency (MHz)
[1st IF = 10.695 MHz]
1
2
46.610
46.630
46.670
46.710
46.730
46.770
46.830
46.870
46.930
46.970
46.510
46.530
46.550
46.570
46.590
9322
9326
9334
9342
9346
9354
9366
9374
9386
9394
9302
9306
9310
9314
9318
38.975
38.150
38.165
39.075
39.180
39.135
39.195
39.235
39.295
39.275
39.000
39.015
39.030
39.045
39.060
7795
7830
7833
7815
7836
7827
7839
7847
7859
7855
7800
7803
7806
7809
7812
3
4
5
6
7
8
9
10
11
12
13
14
15
Page 22 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
Table 20. Korea CT–1 Handset Frequency
Tx Channel
Frequency
(MHz)
Tx Counter Value
(Ref. Freq. =
5.00 kHz)
f
–R Input
Rx Counter Value
(Ref. Freq. =
5.00 kHz)
in
Channel
Number
Frequency (MHz)
[1st IF = 10.7 MHz]
1
2
49.670
49.845
49.860
49.770
49.875
49.830
49.890
49.930
49.990
49.970
49.695
49.710
49.725
49.740
49.755
9934
9969
9972
9954
9975
9966
9978
9986
9998
9994
9939
9942
9945
9948
9951
35.915
35.935
35.975
36.015
36.035
36.075
36.135
36.175
36.235
36.275
35.815
35.835
35.855
35.875
35.895
7183
7187
7195
7203
7207
7215
7227
7235
7247
7255
7163
7167
7171
7175
7179
3
4
5
6
7
8
9
10
11
12
13
14
15
Table 21. China CT–1 Base Set Frequency
Tx Channel
Frequency
(MHz)
Tx Counter Value
(Ref. Freq. =
5.00 kHz)
f
–R Input
Rx Counter Value
(Ref. Freq. =
5.00 kHz)
in
Channel
Number
Frequency (MHz)
[1st IF = 10.7 MHz]
1
2
45.250
45.275
45.300
45.325
45.350
45.375
45.400
45.425
45.450
45.475
9050
9055
9060
9065
9070
9075
9080
9085
9090
9095
37.550
37.575
37.600
37.625
37.650
37.675
37.700
37.725
37.750
37.775
7510
7515
7520
7525
7530
7535
7540
7545
7550
7555
3
4
5
6
7
8
9
10
Table 22. China CT–1 Handset Frequency
Tx Channel
Frequency
(MHz)
Tx Counter Value
(Ref. Freq. =
5.00 kHz)
f
–R Input
Rx Counter Value
(Ref. Freq. =
5.00 kHz)
in
Channel
Number
Frequency (MHz)
[1st IF = 10.7 MHz]
1
2
48.250
48.275
48.300
48.325
48.350
48.375
48.400
48.425
48.450
48.475
9650
9655
9660
9665
9670
9675
9680
9685
9690
9695
34.550
34.575
34.600
34.625
34.650
34.675
34.700
34.725
34.750
34.775
6910
6915
6920
6925
6930
6935
6940
6945
6950
6955
3
4
5
6
7
8
9
10
Page 23 of 24
www.lansdale.com
Issue 0
ML145162
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
P DIP 16 = EP
(ML145162EP)
PLASTIC DIP
CASE 648–08
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
S
INCHES
MILLIMETERS
DIM
A
B
C
D
F
MIN
MAX
0.770
0.270
0.175
0.021
0.70
MIN
18.80
6.35
3.69
0.39
1.02
MAX
19.55
6.85
4.44
0.53
1.77
F
0.740
0.250
0.145
0.015
0.040
C
L
SEATING
PLANE
–T–
G
H
J
K
L
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
K
M
0.008
0.015
0.130
0.305
10
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295
0
2.80
7.50
0
G
D 16 PL
M
S
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T A
SOG 16 = -5P
(ML145162-5P)
SOG PACKAGE
CASE 751B–05
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
1
9
8
–B–
P 8 PL
M
S
B
0.25 (0.010)
G
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
0.386
0.150
0.054
0.014
0.016
R X 45
K
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
D
16 PL
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
A
0.25 (0.010)
T
B
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili-
ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 24 of 24
www.lansdale.com
Issue 0
相关型号：
©2020 ICPDF网 联系我们和版权申明