MC145403DW [LANSDALE]
Drivers/Receivers RS 232/EIAâ232âE and CCITT V.28;
| 型号： | MC145403DW |
| 厂家： | 
LANSDALE SEMICONDUCTOR INC. |
| 描述： | Drivers/Receivers RS 232/EIAâ232âE and CCITT V.28 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总8页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ML145403 ML145405
ML145404 ML145408
Drivers/Receivers
RS 232/EIA–232–E and CCITT V.28
Legacy Device: Motorola MC145403, MC145404, MC145405, MC145408
These devices are silicon gate CMOS ICs that combine both the
transmitter and receiver to fulfill the electrical specifications of EIA
Standard 232–E and CCITT V.28. The drivers feature true TTL input
compatibility, slew rate limiting outputs, 300 Ω power–off source
impedance, and output typically switching to within 25% of the sup-
ply rails. The receivers can handle up to 25 V while presenting 3 to
7 kΩ impedance. Hysteresis in the receivers aid in the reception of
noisy signals. By combining both drivers and receivers in a single
CMOS chip, these devices provide efficient, low–power solutions for
both EIA–232–E and V.28 applications.
These devices offer the following performance features:
• Operating Temperature Range T = –40° to +85°C
A
Drivers
•
5 to 12 V Supply Range
• 300 Ω Power–Off Source Impedance
• Output Current Limiting
• TTL and CMOS Compatible Inputs
• Driver Slew Rate Range Limited to 30 V/µs Maximum
Receivers
•
25 V Input Range
• 3 to 7 kΩ Input Impedance
• 0.8 V of Hysteresis for Enhanced Noise Immunity
• TTL and CMOS Compatible Outputs
Available Driver/Receiver Combinations
Device
Drivers
Receivers
Figure
No. of Pins
ML145403
ML145404
ML145405
ML145408
3
4
5
5
5
4
3
5
1
2
3
4
20
20
20
24
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
Alternative EIA–232 devices to consider are:
Three Supply
Single Supply
ML145406 (3 x 3)
ML145407 (3 x 3)
Page 1 of 8
www.lansdale.com
Issue A
ML145403, ML145404, ML145405, ML145408
LANSDALE Semiconductor, Inc.
PIN ASSIGNMENTS
(DIPAND SOG)
ML145403
3 DRIVERS/5 RECEIVERS
ML145404
4 DRIVERS/4 RECEIVERS
ML145405
5 DRIVERS/3 RECEIVERS
ML145408
5 DRIVERS/5 RECEIVERS
1
20
1
20
1
20
1
24
V
V
V
V
V
V
V
V
CC
DD
CC
DD
CC
DD
CC
DD
2
23
2
19
2
19
2
19
R
R
R
R
R
R
R
R
R
Rx1
DO1
Rx1
DO1
Rx1
Tx1
DO1
DI1
Rx1
Tx1
Rx2
Tx2
Rx3
Tx3
Rx4
DO1
DI1
3
18
3
4
5
6
7
8
22
21
20
19
18
17
3
4
18
17
3
4
18
17
D
D
D
D
D
D
D
Tx1
Rx2
DI1
Tx1
Rx2
DI1
4
5
6
17
16
15
R
R
DO2
DO2
DO2
DI2
DI2
Tx2
Rx2
Tx3
5
6
7
16
15
14
5
6
7
16
15
14
R
Tx2
Rx3
Tx3
Rx4
Tx4
DI3
DO2
DI3
D
D
D
D
Rx3
Tx2
Rx4
DO3
DI2
D
D
DO3
DI3
DO3
DI3
7
14
13
12
11
R
R
DO4
D
D
Tx4
Rx3
Tx5
DI4
8
13
12
11
8
13
12
11
8
R
R
Rx5
Tx3
DO5
DI3
DO4
DI4
R
DO3
DI5
DO4
9
16
15
9
9
9
D
D
Tx4
Rx5
DI4
10
10
10
10
DO5
V
GND
V
GND
V
SS
GND
SS
SS
11
12
14
13
Tx5
DI5
V
GND
SS
FUNCTIONAL DIAGRAM
RECEIVER
DRIVER
V
V
CC
DD
ESD
PROTECTION
V
V
DD
CC
15 k
Ω
V
CC
+
–
Rx
+
DO
300
Ω
DI
LEVEL
SHIFT
Tx
5.4 kΩ
–
1.4 V
V
SS
V
SS
1.0 V
1.8 V
Page 2 of 8
www.lansdale.com
Issue A
LANSDALE Semiconductor, Inc.
ML145403, ML145404, ML145405, ML145408
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND, except where noted)
This device contains circuitry to protect the
inputs and outputs against damage due to high
static voltages or electric fields; however, it is
advised that normal precautions be taken to
avoid applications of any voltage higher than
maximum rated voltages to this high imped-
ance circuit.
Rating
Symbol
Value
Unit
DC Supply Voltage (V
≥ V
CC
)
V
– 0.5 to + 13.5
+ 0.5 to – 13.5
– 0.5 to + 6.0
V
DD
DD
V
SS
V
CC
Input Voltage Range
V
IR
V
Rx1 – Rxn
DI1 – DIn
V
– 15 to V
+ 15
+ 15
SS
0.5 to V
DD
For proper operation it is recommended that
CC
00
V
and V be constrained to the ranges
out
in
described as follows:
DC Current Drain per Pin
Power Dissipation
I
mA
W
Digital I/O: Driver Inputs (DI):
P
D
1
(GND ≤ V ≤ V ).
DI CC
Receiver Outputs (DO):
(GND ≤ V ≤ V ).
Operating Temperature Range
Storage Temperature Range
T
A
– 40 to + 85
°C
°C
DO CC
T
stg
– 85 to + 150
EIA–232 I/O: Driver Outputs (Tx):
(V ≤ V
≤ V ).
SS Tx1 – Txn
DD
Receiver Inputs (Rx):
– 15 V ≤ V
V
≤ V
Rx1 – Rxn DD
SS
+ 15 V).
Reliabilityofoperationisenhancedifunused
outputs are tied off to an appropriate logic
voltage level (e.g., either GND or V
and GND for Rx).
for DI,
CC
DC ELECTRICAL CHARACTERISTICS (All polarities referenced to GND = 0 V, T = – 40 to + 85°C)
A
Parameter
Symbol
Min
Typ
Max
Unit
DC Supply Voltage
V
4.5
– 4.5
4.5
5 to 12
– 5 to – 12
5
13.2
– 13.2
5.5
V
DD
V
SS
CC
V
Quiescent Supply Current (Outputs Unloaded, Inputs Low)
V
= + 12 V
= – 12 V
CC
I
—
—
—
425
– 400
110
635
– 600
200
µA
DD
DD
V
I
SS
SS
CC
V
= + 5 V
I
RECEIVER ELECTRICAL SPECIFICATIONS
(Voltage polarities referenced to GND = 0 V, V
= + 12 V, V
SS
= – 12 V, T = – 40 to + 85°C, V
= + 5 V, 10%)
DD
A
CC
Characteristic
Symbol
Min
Typ
Max
Unit
Input Turn–On Threshold
= V
Rx1 – Rxn
Rx1 – Rxn
V
1.35
1.8
2.35
V
on
V
DO
OL
Input Turn–Off Threshold
= V
V
off
0.75
0.6
3
1
1.25
—
V
V
k
V
DO
OH
Input Threshold Hysteresis
V
hys
0.8
5.4
∆ = V – V
on
off
Input Resistance
R
7
in
(V
SS
– 15 V) ≤ V Rx1 – Rxn ≤ (V + 15 V)
DD
High Level Output Voltage
= – 3 to – 25 V* (DO1 – DOn)
I
= – 20 µA
= – 1.0 mA
V
4.9
3.8
4.9
4.3
—
—
V
V
out
OH
V
I
out
Rx
Low Level Output Voltage
= + 3 to + 25 V* (DO1 – DOn)
I
I
= + 2 mA
= + 4 mA
V
—
—
0.02
0.5
0.5
0.7
out
out
OL
V
Rx
* This is the range of input voltages as specified by EIA–232–E to cause a receiver to be in the high or low.
Page 3 of 8
www.lansdale.com
Issue A
ML145403, ML145404, ML145405, ML145408
LANSDALE Semiconductor, Inc.
DRIVER ELECTRICAL SPECIFICATIONS
(Voltage Polarities Referenced to GND = 0 V, V
= + 12 V, V
SS
= – 12 V, T = – 40 to + 85°C, V
CC
= + 5 V, 10%)
Typ
DD
A
Characteristic
Symbol
Min
Max
Unit
Digital Input Voltage
Logic 0
DI1 – DIn
DI1 – DIn
Tx1 – Txn
V
V
IH
—
2
—
—
0.8
—
IL
Logic 1
V
Input Current
µA
V
DI
V
DI
= GND
I
IH
—
—
7
—
—
1.0
IL
= V
I
CC
Output High Voltage
V
OH
V
V
= Logic 0, R = 3 kΩ
DI
L
V
= + 5.0 V, V
= + 6.0 V, V
= – 5.0 V
= – 6.0 V
SS
3.5
4.3
9.2
3.9
4.7
9.5
—
—
—
DD
DD
DD
SS
SS
V
V
= + 12.0 V, V
= – 12.0 V
Output Low Voltage*
Tx1 – Txn
V
OL
V
V
= Logic 1, R = 3 kΩ
DI
L
V
= + 5.0 V, V
= + 6.0 V, V
= – 5.0 V
= – 6.0 V
– 4
– 4.5
– 10
– 4.3
– 5.2
– 10.3
—
—
—
DD
DD
DD
SS
SS
V
V
= + 12.0 V, V
= – 12.0 V
SS
Input Current
(Figure 5)
Tx1 – Txn
Tx1 – Txn
Z
300
—
—
off
Output Short Circuit Current
I
SC
mA
V
DD
= + 12 V, V
= – 12 V
SS
Tx Shorted to GND**
—
—
22
60
60
100
Tx Shorted to 15 V***
*Voltage specifications are in terms of absolute values.
**Specification is for one Tx output pin to be shorted at a time. Should all three driver outputs be shorted simultaneously, device power dissipation
limits will be exceeded.
***This condition could exceed package limitations.
SWITCHING CHARACTERISTICS (V
CC
= + 5 V, 10%, V
DD
= + 12 V, V = – 12 V, T = – 40 to + 85°C; See Figures 2 and 3)
SS A
Characteristic
Symbol
Min
Typ
Max
Unit
Drivers
Propagation Delay Time Tx
Low–to–High
t
ns
PLH
R
= 3 kΩ, C = 50 pF
—
—
500
700
1000
1000
L
L
High–to–Low
= 3 kΩ, C = 50 pF
t
PHL
SR
R
L
L
Output Slew Rate
Minimum Load
V/µs
R
= 7 kΩ, C = 0 pF (V
= 6 to 12 V, V
= – 6 to – 12 V)
—
4
6
30
—
L
L
DD
SS
Maximum Load
= 3 kΩ, C = 2500 pF (V = 12 V, V
DD
R
= – 12 V, V
CC
= 5 V)
—
L
L
SS
Receivers (C = 50 pF)
L
Propagation Delay Time
Low–to–High
t
t
ns
PLH
—
—
—
—
360
130
250
40
610
610
400
100
High–to–Low
Output Rise Time
Output Fall Time
PHL
t
r
ns
ns
t
f
Page 4 of 8
www.lansdale.com
Issue A
LANSDALE Semiconductor, Inc.
ML145403, ML145404, ML145405, ML145408
1
24
V
V
DD CC
Tx1
22
20
18
16
14
3
DI1
DI2
DI3
5
Tx2
Tx3
V
=
2 V
in
7
9
DI4
DI5
Tx4
Tx5
11
V
GND
DD
12
Vin
I
Rout
13
Figure 1. Power–Off Source Resistance
Illustrated for ML145408
DRIVERS
+ 3 V
0 V
DI
50%
t
t
r
f
V
OH
OL
90%
Tx
10%
V
t
t
PLH
PHL
RECEIVERS
DRIVERS
+ 3 V
0 V
Rx
50%
+ 3 V
– 3 V
+ 3 V
– 3 V
Tx
t
t
PLH
PHL
90%
t
t
V
SHL
SLH
OH
DO
10%
6 V
or t
V
OL
Slew Rate =
t
t
f
t
SLH
SHL
r
Figure 2. Switching Characteristics
Figure 3. Slew Rate Characteristics
PIN DESCRIPTIONS
VSS
Most Negative Device Pin
VCC
Digital Power Supply
The most negative power supply pin, which is typically – 5 to – 12V.
The digital supply pin, which is connected to the logic power Rx1 – Rxn
supply (+ 5.5 V maximum).
Receive Data Input Pins
GND
These are the EIA–232–E receive signal inputs. A voltage
between + 3 and + 25 V is decoded as a space, and causes the
corresponding DO pin to swing to ground (0 V). A voltage
between – 3 and – 25 V is decoded as a mark, and causes the
Ground
Ground return pin is typically connected to the signal ground
pin of the EIA–232–E connector (Pin 7) as well as to the logic
power supply ground.
corresponding DO pin to swing to V
.
CC
DO1 – DOn
Data Output Pins
VDD
Most Positive Device Pin
These are the receiver digital output pins which swing
fromV to GND. Each output pin is capable of driving one
The most positive power supply pin, which is typically + 5 to
+ 12 V.
CC
LSTTL input load.
Page 5 of 8
www.lansdale.com
Issue A
ML145403, ML145404, ML145405, ML145408
LANSDALE Semiconductor, Inc.
DI1 – DIn
switched off while the + 5 V is on and the off supply is a low
impedance to ground, the diode D1 will prevent current flow
through the internal diode.
Data Input Pins
These are the high impedance digital input pins to the driv-
ers. Input voltage levels on these pins are LSTTL compatible
and must be between V and GND. A weak pull–up on each
input sets all unused DI pins to V , causing the correspon-
The diode D2 is used as a voltage clamp, to prevent V
SS
from drifting positive to V , in the event that power is re-
CC
CC
moved from V (Pin 12). If V power is removed, and the
SS SS
CC
impedance from the V pin to ground is greater than approxi-
SS
ding unused driver outputs to be at V
.
SS
mately 3 kΩ, this pin will be pulled to V
by internal circuit-
pin.
CC
ry causing excessive current in the V
If by design, neither of the above conditions are allowed to
exist, then the diodes D1 and D2 are not required.
CC
Tx1 – TXn
Transmit Data Output Pins
These are the EIA–232–E transmit signal output pins, which
swing from V to V . A logic 1 at the DI input causes the
corresponding Tx output to swing to V . A logic 0 at the DI
input causes the corresponding Tx out to swing to V . The
actual levels and slew rate achieved will depend on the output
DD SS
ESD PROTECTION – CAUTION
SS
DD
ESD protection on IC devices that have their pins accessible
to the outside world is essential. High static voltages applied to
the pins when someone touches them either directly or in
directly can cause damage to gate oxides and transistor junc-
tions by coupling a portion of the energy from the I/O pin to
the power supply buses of the IC. This coupling will usually
occur through the internal ESD protection diodes. The key to
protecting the IC is to shunt as much of the energy to ground
as possible before it enters the IC. Figure 4 shows a technique
which will clamp the ESD voltage at approximately 15 V
using the MMBZ15VDLT1. Any residual voltage which
appears on the supply pins is shunted to ground through the
capacitors C1 – C3. This scheme has provided protection to the
interface part up to 10kV, using the human body model test.
loading (R C ).
L// L
LEGACY APPLICATION INFORMATION
POWER SUPPLY CONSIDERATIONS
Figure 4 shows a technique to guard against excessive de-
vice current.
The diode D1 prevents excessive current from flowing
through an internal diode from the V
pin to the V
pin-
by approximately 0.6 V or greater. This
CC
DD
when V
DD
< V
CC
high current condition can exist for a short period of time dur-
ing power up/down. Additionally, if the + 12 V supply is
+ 12 V
D1
MMBZ15VDLT1 x 10
+ 5 V
1N4001
C1
V
V
CC
DD
1
24
C2
1N4001
Rx1
Tx1
2
3
23 DO1
22 DI1
R
D
Rx2
Tx2
4
5
21 DO2
20 DI2
R
R
R
R
D
D
Rx3
Tx3
Rx4
Tx4
6
7
8
9
19 DO3
18 DI3
17 DO4
16 DI4
15 DO5
D
Rx5 10
Tx5 11
14 DI5
D
V
12
13 GND
SS
C3
D2
1N5818
– 12 V
Figure 4.
Page 6 of 8
www.lansdale.com
Issue A
LANSDALE Semiconductor, Inc.
ML145403, ML145404, ML145405, ML145408
OUTLINE DIMENSIONS
P DIP 20 = RP
(ML145403RP, ML145404RP, ML145405RP)
PLASTIC DIP
CASE 738–03
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
20
1
11
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
B
10
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
E
MIN
MAX
1.070
0.260
0.180
0.022
MIN
25.66
6.10
3.81
0.39
MAX
27.17
6.60
1.010
0.240
0.150
0.015
4.57
-T-
K
0.55
SEATING
PLANE
M
0.050 BSC
1.27 BSC
0.050
0.070
1.27
1.77
F
E
N
G
J
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
J 20 PL
K
L
0.300 BSC
15
0.040
7.62 BSC
15
0.51 1.01
D 20 PL
0.25 (0.010)
M
M
0.25 (0.010)
T
B
0
°
°
0°
°
M
N
0.020
M
M
T
A
P DIP 24 = LP
(ML145408LP)
PLASTIC DIP
CASE 724–03
–A–
NOTES:
1. CHAMFERED CONTOUR OPTIONAL.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
24
13
12
–B–
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1
4. CONTROLLING DIMENSION: INCH.
INCHES
MILLIMETERS
L
DIM
A
B
C
D
E
MIN
MAX
1.265
0.270
0.175
0.020
MIN
31.25
6.35
3.69
0.38
MAX
32.13
6.85
4.44
0.51
C
1.230
0.250
0.145
0.015
NOTE 1
–T–
K
0.050 BSC
1.27 BSC
SEATING
PLANE
F
0.040
0.060
0.100 BSC
1.02
2.54 BSC
1.52
N
M
E
G
J
0.007
0.110
0.012
0.140
0.18
2.80
0.30
3.55
G
J 24 PL
F
K
L
M
M
0.300 BSC
7.62 BSC
0.25 (0.010)
T B
D 24 PL
0.25 (0.010)
M
N
0
15
0.040
0
0.51
15
1.01
0.020
M
M
T
A
Page 7 of 8
www.lansdale.com
Issue A
ML145403, ML145404, ML145405, ML145408
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
SO 20W = -6P
(ML145403-6P, ML145404-6P, ML145405-6P)
SOG PACKAGE
CASE 751D–04
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
20
1
11
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
10X P
–B–
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
M
M
0.010 (0.25)
B
10
MILLIMETERS
INCHES
20X D
0.010 (0.25)
DIM
A
MIN
12.65
7.40
2.35
0.35
0.50
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
0.510
0.299
0.104
0.019
0.035
J
0.499
0.292
0.093
0.014
0.020
M
S
S
T
A
B
B
C
D
F
F
G
J
1.27 BSC
0.050 BSC
0.25
0.10
0
10.05
0.25
0.32
0.25
7
10.55
0.75
0.010
0.004
0
0.395
0.010
0.012
0.009
7
0.415
0.029
R X 45
K
M
P
C
R
SEATING
PLANE
–T–
M
18X G
K
SO 24W = -6P
(ML145408-6P)
SOG PACKAGE
CASE 751E–04
–A–
NOTES:
24
13
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
–B– 12X P
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.010 (0.25)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
1
12
24X D
J
MILLIMETERS
INCHES
M
S
S
0.010 (0.25)
T
A
B
DIM
A
MIN
15.25
7.40
2.35
0.35
0.41
MAX
15.54
7.60
2.65
0.49
0.90
MIN
MAX
0.612
0.299
0.104
0.019
0.035
0.601
0.292
0.093
0.014
0.016
B
F
C
D
R X 45
F
G
J
1.27 BSC
0.050 BSC
0.23
0.13
0
10.05
0.25
0.32
0.29
8
10.55
0.75
0.009
0.005
0
0.395
0.010
0.013
0.011
8
0.415
0.029
C
K
K
–T–
M
P
M
SEATING
PLANE
R
22X G
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili-
ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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