MC145428DW [LANSDALE]
Asynchronous-to-Synchronous and Synchronous-to-Asynchronous Converter; 异步到同步和同步到异步转换器
| 型号： | MC145428DW |
| 厂家： | 
LANSDALE SEMICONDUCTOR INC. |
| 描述： | Asynchronous-to-Synchronous and Synchronous-to-Asynchronous Converter |
| 文件： | 总14页 (文件大小：1343K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ML145428
Asynchronous–to–Synchronous
and Synchronous–to–
Asynchronous Converter
Legacy Device: Motorola MC145428
The ML145428 Data Set Interface provides asynchronous-to-synchronous
and synchronous-to-asynchronous data conversion. It is ideally suited for
voice/data digital telesets supplying an EIA-232 compatible data port into a
synchronous transmission link. Other applications include: data multiplexers,
concentrators, data-only switching, and PBX-based local area networks. This
low-power CMOS device directly interfaces with either the 64 kbps or 8kbps
channel of Motorola’s MC145422 and MC145426 Universal Digital Loop
Transceivers (UDLTs), as well as the MC145421 and MC145425 Second
Generation Universal Digital Loop Transceivers (UDLT II).
P DIP 20 = RP
PLASTIC
CASE 732
20
1
SOG 20 = -6P
PLASTIC
CASE 751D
20
1
CROSS REFERENCE/ORDERING INFORMATION
• Provides the Interface Between Asynchronous Data Ports and
Synchronous Transmission Lines
PACKAGE
MOTOROLA
LANSDALE
P DIP 20
SOG 20
MC145428P
MC145428DW
ML145428RP
ML145428-6P
• Up to 128 kbps Asynchronous Data Rate Operation
• Up to 2.1 Mbps Synchronous Data Rate Operation
• On-Board Bit Rate Clock Generator with Pin Selectable Bit Rates of
300, 1200, 1400, 4800, 9600, 19200 and 38400 bps or an Externally
Supplied 16 Times Bit Rate Clock
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
• Accepts Asynchronous Data Words of 8 or 9 Bits in Length
• False Start Detection Provided
• Automatic Sync Insertion and Checking
• Single 5 V Power Supply
• Low Power Consumption of 5 mW Typical
• Application Notes AN943 and AN946
PIN ASSIGNMENT
• Operating Temperature Range T = –40º to +85ºC.
A
TxS
TxD
1
2
3
4
5
20
V
DD
19 RESET
18 DCO
17 DOE
16 CM
DL
BLOCK DIAGRAM
BRCLK
BCLK
TxS
BR1
BR2
6
7
15 DCLK
14 DIE
SYNCHRONOUS
CHANNEL
TRANSMITTER
Tx
FIFO
DATA
STRIPPER
TxD
DL
DCO
BR3
SB
8
9
13 DCI
12 RxS
V
SS
10
11 RxD
DOE
DIE
BR1-BR3
BCLK
BAUD
RATE
GEN
CONTROL
DCLK
CM
BRCLK
RESET
DCI
SYNCHRONOUS
CHANNEL
RECEIVER
DATA
FORMATTER
Rx
FIFO
RxD
SB
RxS
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ML145428 DSI PIN DESCRIPTIONS
RxS. RECEIVE STATUS OUTPUT
This pin will go low if framing of the synchronous channel
is lost or not established or if RESET is low, or if the receive
FIFO is overwritten.
V
V
. POSITIVE POWER SUPPLY
DD
The most positive power supply pin, normally 5 volts.
. NEGATIVE POWER SUPPLY
SS
The most negative supply pin, normally 0 volts.
SB, STOP BITS INPUT
This pin controls the number of stop bits the DATA FOR-
MATTER will re–create when outputting data at the RxD
asynchronous output. A high on this pin selects two stop bits; a
low selects one stop bit.
TxD. TRANSMIT DATA INPUT
Input for asynchronous data, idle is logic high; break is 11
baud or more of logic low. One stop bit is required
DL, DATA LENGTH INPUT
RxD. RECEIVE DATA OUTPUT
This pin instructs the DSI to look for either 8 or 9 bits of
data to be input at the TxD asynchronous input between the
start and stop bits. The DL input also instructs the DSI’s SYN-
CHRONOUS CHANNEL RECEIVER and SYNCHRONOUS
CHANNEL TRANSMITTER to expecct 8 or 9 bit data words
and also instructs the DSI’s DATA FORMATTER to re–create
8 or 9 data bits between the start and stop bits when outputting
data at its RxD asynchronous output. A high on this pin selects
a 9 bit data word, a low selects an 8 bit data word length.
Output for asynchronous data. The number of stop bits and
the data word length are selected by teh SB and DL pins. Idle
is logic high; break is a continuous logic low.
TxS. TRANSMIT STATUS OUTPUT
This pin will go low if the transmit FIFO holds 2 or more
data words or if RESET is low.
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ML145428 DSI PIN DESCRIPTIONS – cont’d
DOE, DATA OUTPUT ENABLE INPUT
See DCO pin description and the SYNCHRONOUS CHAN-
NEL INTERFACE section.
BC, BAUD CLOCK INPUT
This pin serves as an input for an externally supplied 16
times data clock. Otherwise, the BC pin expects a 4.096 MHz
clock signal which is internally divided to obtain the 16 times
clock for the most frequentlly used standard bit rates (see BR1
- BR3 pin description).
DIE, DATA INPUT ENABLE OUTPUT
See DCI and DCO pin descriptions and the SYNCHRO-
NOUS CHANNEL INTERFACE section.
CM, CLOCK MODE INPUT
BRCLD, 16 TIMES CLOCK INTERNAL OUTPUT
See the SYNCHRONOUS CHANNEL INTERFACE section
and the SYNCHRONOUS CLOCKING MODE SUMMARY.
(See Table 2.)
This pin outputs the internal 16 times asynchronous data rate
clock.
BR1, BR2, BR3, BIT RATE SELECT INPUTS
RESET, RESET INPUT
These three pins select the asynchronous bit rate, either
externally supplied at the BC pin (16 times clock) or one of
the internally supplied bit rates. (See Table 1.)
When held low, this pin clears the internal FIFO’s, forces the
TxD asynchronous input to appear high to the DSI’s internal
circuitry, forces TxS and RxS low. When returned high, normal
operation results.
When the RESET input is returned high the DSI’s SYN-
CHRONOUS CHANNEL RECEIVER will not accept or trans-
fer any incoming data words on the DCI pin to the Rx FIFO
until one “flag” word is input at the DCI pin. (Also see RxS
pin description)
DCO, DATA CHANNEL OUTPUT
This pin is a three–state output pin. Synchronous data is out-
put when DOE is high. This pin will go high impedance when
DOE or RESET are low. When CM is low, synchronous data is
output on DCO on the falling edges of DC as long as DOE is
high. When CM is high, synchronous data is output on DCO on
the rising edges of DC, while DOE is held high. No more than
eight data bits can be output during a given DOE high interval
when CM = high. This feature allows the DSI to interface direct-
ly with the MC145422/26 Universal Digital Loop Transceivers
(UDLT’s) and PABX time division multiplexed highways.
DCI, DATA CHANNEL INPUT
Synchronous data is input on this pin on the falling edges of
DC when DIE is high.
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CIRCUIT DESCRIPTION
An externally supplied 16 times clock may also be used, in
which case the BR1, BR2, and BR3 pins should all be at logic
zero and the 16 times sampling clock supplied at the BC pin.
Data input at the TxD pin is stripped of start and stop bits
and is loaded into a four–word deep FIFO register. A break
condition is also recognized at the TxD pin and this informa-
tion is relayed to the synchronous channel transmitter which
codes this condition so it may be re–created at the remote
receiving device.
The synchronous channel transmitter sends one bit at a time
under control of the DC, CM and DOE pins. The synchronous
channel transmitter transmits one of three possible data pat-
terns based on whether or not the top of the Tx FIFO is full
and whether or not a break condition has been recognized by
the data stripper. When no data is available at the top of the Tx
FIFO for transmission, the synchronous data transmitter sends
a special synchronizing flag pattern (011111110). When a
break condition is detected by the data stripper and no data is
available at the top of the Tx FIFO, the break pattern
(111111110) is sent. Figure 2A depicts this operation.
The ML145428 Data Set Interface provides a means for con-
version of an asynchronous (start/stop format) data channel to
a synchronous data channel and synchronous to asynchronous
data channel conversion. Although primarily intended to facili-
tate the implementation of RS - 232 compatible asynchronous
data ports in digital telephone sets using the MC145422/26
UDLTs, this device is also useful in many applications that
require the conversion of synchronous and asynchronous data.
TRANSMIT CIRCUIT
Asynchronous data is input on the TxD pin. This data is
expected to consist of a start bit (logic low) followed by eight
or nine data bits and one or more stop bits (logic high). The
length of the data word is selected by the DL pin. The data
baud rate is selected with the BR1, BR1 and BR3 pins to
obtain the internal sampling clock. This internal sampling
clock is selected to be 16 times the baud rate at the TxD pin.
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If the incoming data rate at TxD exceeds the rate at which it
is output at DCO, the FIFO will fill. The TxS pin will go low
when the FIFO contains two or more words. TxS may, there-
fore, be used as a local Clear-to-Send control line at the asyn-
chronous interface port to avoid transmit data over-runs.
In order to insure synchronization during the transfer of a
continuous stream of data the DSI’s synchronous channel
transmitter will insert a flag synchronnizing word (01111110)
every 61st data word. The DSI’s synchronous channel receiver
checks for this synchronizing word and if not present, the loss
of synchronizaion will be indicated by the RxS pin being
latched low until the flag synchronizing word is received. Note
that under these conditions the data will continue to output at
RxD.
RECEIVE CIRCUIT
Data incoming from the synchronous channel is loaded into
the ML145428 at the DCI pin under the control of the DC and
DIE pins (see SYNCHRONOUS CHANNEL INTERFACE
section). Framing information, break code detection, and data
word recovery functions are performed by the SYNCHRO-
NOUS CHANNEL RECEIVER. Recovered data words are
loaded into the four word deep Rx FIFO. When the recovered
data words reach the top of the Rx FIFO they are taken by the
DATA FORMATTER, start and stop bits are re-inserted and
the re-constructed asynchronous data is output at the TxD pin
at the same baud rate as the transmit side. The number of stop
bits and word length are those selected by the SB and DL pins.
When stripped data words reach the top of the Tx FIFO they
are loaded into the SYNCHRONOUS CHANNEL TRANS-
MITTER and are sent using a special zero insertion technique.
When stripped data is being transmitted, the synchronous data
transmitter will insert a binary 0 after any succession of five
continuous 1’s of data. Therefore, using this technique, no pat-
tern of (01111110) or (11111110) can occur while sending
data. This also allows the DSI to synchronize itself to the
incoming synchronous data word boundaries based on the data
alone.
The receive section of the DSI (synchronous channel receiv-
er) performs the reverse operation by removing a binary 0 that
follows five continuous 1’s in order to recover the transmitted
data. (note that a binary 1 which follows five continuous 1’s is
not removed so that flags and breaks may be detected.) Figure
2B shows an example of this process.
Loss of framing, if it occurs, is indicated by the RxS pin
going low. Data will continue to be output under these condi-
tions, but RxS will remain low until frame synchronization,
i.e., the detection of a framing flag word, is re-established. If
the output data rate is less than the data rate of the incoming
synchronous data channel, data will be lost at the rate of one
word at a time due to the bottom word on the Rx FIFO being
overwritten. In order to prevent data loss (in the form of asyn-
chronous terminal to asynchronous terminal over-runs) due to
clock slip between remote DSI links, (during long bursts the
stop bit which it re-creates at its RxD output by 1/32nd. This
action allows the originator of a transmission (of asynchronous
data) to be up to 3% faster than the receive device is expecting
for any given data rate. This tolerance is well with in the nor-
mally expected differences in clock frequencies between
remote stations. If the Rx FIFO is overwriting the RxS line
will pulse low for one DC clock period following the over-
writing of the bottom level of the Rx FIFO.
INITIALIZATION
Initialization is accomplished by use of the RESET pin.
When held low, the internal FIFOs are cleared, the TxD input
appears high to the data strippers, internal circuitry. DCO is
forced to a high impedance state, TxS and RxS are forced low.
When brought high normal operation resumes and and the syn-
chronous channel transmitter sends the flag code until data has
reached the top of the Tx FIFO. Note that the TxS line will
immediately go high after RESET goes high, while RxS will
remain low until framing is detected. The synchronous channel
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LANSDALE Semiconductor, Inc.
receiver section of the DSI is forced into a “HOLD” state
clock periods the last data bit B8 will remain at the output of
while the RESET line is low. The synchronous channel receiv- the DCO pin until the DOE enable is brought low to reinitial-
er remains in the “HOLD” state after RESET goes high until a ize the sequence. Similarly the DSI’s SYNCHRONOUS
flag code word (01111110) is received at the DCI pin. While in CHANNEL RECEIVER will read (at its DCI input) a mini-
the “HOLD” state no data words can be transferred to the Rx
FIFO and, therefore, the DATA FORMATTER and RxD line
are hold in the MARK idle state. After receiving the flag code
pattern the RxS line goes high and normal operation proceeds.
RESET should be held low when power is first applied to the
DSI. RESET may be tied high permanently, if a short period of
undefined operation at initial power application can be tolerat-
ed.
mum of eight data bits for any given DIE high period.
The CM = high mode, using 8 bits of data, is the typical set
up for interfacing the DSI to the 64 kbps channel of the
MC145422 or MC145426 Universal Digital Loop
Transceivers. (See Figure 3B and Figure 5).
In the third mode of operation, an unlimited variable number
of data bits may be clocked into or out of the synchronous side
of the DSI at a time. When the CM line is low, any number of
data bits may be clocked into or out of the DSI’s synchronous
channels provided that the respective enable signal is high.
Figure 3C illustrates three data bits being clocked out of the
DCO pin and three data bits being clocked into the DCI pin.
SYNCHRONOUS CHANNEL INTERFACE
The synchronous channel interface is generally operated in
one of three basic modes of operation. The first is a continuous
mode. A new data bit is clocked out of the DCO pin on each
successive falling edge of the DC clock, and a new data bit is
accepted by the DSI at its DCI pin on each successive falling
edge of the DC clock. In this mode of operation, the CM con-
trol line is always low and the DOE and DIE enable control
lines are always High. This is the typical setup when interfac-
ing the DSI to the 8 kbps signal bit inputs and outputs of the
MC145422/26 UDLTs (See Figures 3A and 4)
In the CM = low mode of operation, an internal clock is
formed, which is the logical NAND of DC, DOE and CM,
(IDC•DOE•CM). It is on the rising edge of this signal that a
new data bit is clocked out of the DCO pin. Therefore, the
DOE signal should be raised and lowered following the falling
edge of the DC clock (i.e., when the DC clock is low).
Also in the CM = low mode of operation another internal
clock is formed which is the logical NAND of DC, DIE, and
CM (DC•DIE•CM). It is on the falling edge of this signal that
a new bit is clocked into the DCI pin. Therefore the DIE signal
should be raised or lowered following the rising edge of the
DC clock (i.e., when the DC clock is high).
The second synchronous clocking mode is one in which 8
bits at a time are clocked out at the SYNCHRONOUS CHAN-
NEL TRANSMITTER, and 8 bits are read by the SYNCHRO-
NOUS CHANNEL RECEIVER at a time. The transferring of
these 8 bit groups of data would normally be repeated on some
cyclic basis. An example is a time division multiplexed data
highway. In this mode (Cm = 1), the rising edge of the enable
signal DIE and DOE should be roughly aligned to the rising
edge of the DC clock signal. When enabled, the data is clocked
out on the rising edge of the DC clock through the DCO pin
and clocked in on the falling edge of the DC clock through the
DCI pin. A variation of this clocking mode is to transfer less
than 8 bits of data into or out of the DSI on a cyclic basis. If
less than eight bits are to be transmitted and received, enable
pins DIE and DOE should be returned low while the DC clock
is low. This is illustrated in Figure 3D where five bits are being
locked out of the DSI through the DCO pin and four bits are
being input to the DSI through the DCI pin.
The following table summarizes when data bits are advanced
from the synchronous channel transmitter and when data bits
are read by the synchronous channel receiver dependent on the
CM control line. (Shown below in Table 2.)
This restriction does not apply if eight bits are to be clocked
into or out of the synchronous channels of the DSI, i.e., the
DSI has internal circuitry to prevent more than eight clocks
following the rising edge of the respective enable signal(s).
Figure 3B illustrates a timing diagram depicting an eight bit
data format. If the DOE enable is held high beyond the eight
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OUTLINE DIMENSIONS
SO 20 = -6P
(ML145428-6P)
CASE 751J-01
NOTES:
–A–
1. DIMENSIONS “A” AND “B” ARE DATUMS AND
“T” IS A DATUM SURFACE.
2. DIMENSIONING AND TOLERANCING PER
ANSI Y 14.5M, 1982.
3. CONTROLLING DIM: MILLIMETER.
4. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
20
1
11
10
–B–
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
G
S 10 PL
MILLIMETERS
MIN MAX
12.55 12.80 0.494 0.504
INCHES
MIN MAX
0.13 (0.005) M
M
B
DIM
A
B
C
D
G
5.10
–
0.35
5.40 0.201 0.213
2.00 0.079
0.45 0.014 0.018
0.050 BSC
–
J
1.27 BSC
C
J
K
L
M
0.18
0.55
0.05
0°
0.23 0.007 0.009
0.85 0.022 0.033
0.20 0.002 0.008
0.10 (0.004)
M
D 20 PL
L
K
SEATING
–T–
7°
0°
7°
PLANE
S
7.40
8.20 0.291 0.323
M
S
S
A
0.13 (0.005)
T
B
OUTLINE DIMENSIONS
PLASTIC DIP 20 = RP
(ML145428RP)
CASE 738–03
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1210
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
B
1
10
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
C
L
INCHES
MILLIMETERS
DIM
A
B
C
D
E
F
G
J
K
L
M
N
1.010
1.070
0.260
0.180
0.022
25.66
6.10
3.81
0.39
27.17
6.60
4.57
0.55
0.240
0.150
0.015
-T-
SEATING
PLANE
K
M
0.050 BSC
1.27 BSC
0.050
0.070
1.27
1.77
E
N
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
J 20 PL
0.300 BSC
7.62 BSC
D 20 PL
M
M
0.25 (0.010)
T
B
0
°
15
°
0
°
15
°
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T
A
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabil-
ity, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the cus-
tomer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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