ML13145-9P [LANSDALE]
UHF Wideband Receiver Subsystem (LNA, Mixer, VCO, Prescaler, IF Subsystem, Coiless Detector); 超高频宽带接收器子系统（ LNA ，混频器， VCO ，分频器，中频子系统， Coiless探测器）
| 型号： | ML13145-9P |
| 厂家： | 
LANSDALE SEMICONDUCTOR INC. |
| 描述： | UHF Wideband Receiver Subsystem (LNA, Mixer, VCO, Prescaler, IF Subsystem, Coiless Detector) |
| 文件： | 总17页 (文件大小：2485K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ML13145
UHF Wideband Receiver Subsystem
(LNA, Mixer, VCO, Prescaler, IF
Subsystem, Coiless Detector)
LOW POWER INTEGRATED RECEIVER FOR ISM BAND APPLICATIONS
SEMICONDUCTOR TECHNICAL DATA
Legacy Device: Motorola MC13145
The ML13145 is a dual conversion integrated RF receiver intended for ISM
band applications. It features a Low Noise Amplifier (LNA), two 50 Ω linear
Mixers with linearity control, Voltage Controlled Oscillator (VCO), second
LO amplifier, divide by 64/65 dual modulus Prescalar, split IF Amplifier and
Limiter, RSSI output, Coilless FM/FSK Demodulator and power down con-
trol. Together with the transmit chip (ML13146) and the baseband chip
(MC33410 or MC33411A/B), a complete 900 MHz cordless phone system
can be implemented. This device may be used in applications up to 1.8 GHz,
1
48
LQFP 48 = -9P
PLASTIC PACKAGE
CASE 932
and operating temperature T = –20° to +70°C.
A
CROSS REFERENCE/ORDERING INFORMATION
• Low (<1.8 dB @ 900 MHz) Noise Figure LNA with 14 dB Gain
• Externally Programmable Mixer linearity: IIP3 = 10(nom.) to 17 dBm
(Mixer1); IIP3 = 10 (nom.) to 17 dBm (Mixer2)
PACKAGE
MOTOROLA
LANSDALE
LQFP 48
MC13145FTA
ML13145-9P
• 50 Ω Mixer Input Impedance and Open Collector Output (Mixer 1 and
Mixer 2); 50 Ω Second LO (LO2) Input Impedance
• Low Power 64/65 Dual Modulus Prescalar (ML12054A type)
• Split IF for Improved Filtering and Extended RSSI Range
• Internal 330 Ω Terminations for 10.7 MHz Filters
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
• Linear Coilless FM/FSK Demodulator with Externally Programmable Bandwidth,
Center Frequency and Audio level
•2.7 to 6.5 V Operation, Low Current Drain (<27 mA, Typ @ 3.6 V) with Power Down
Mode (<10 µA, Typ)
•2.4 GHz RF, 1.0 GHz IF1 and 50 MHz IF2 Bandwidth
PIN CONNECTIONS AND FUNCTIONAL BLOCK DIAGRAM
12 11 10
9
8
7
6
5
4
3
2
1
48 V
V
13
EE
EE
Demod
47 BWadj
LNA In 14
46 Lim Dec2
45 Lim Dec1
44 Lim In
V
V
15
16
EE
EE
LNA
/64, 65
Lim
RF
LNA Out 17
18
43 V
CC
V
EE
42 V
CC
Mxr In 19
1
41 IF Out
40 IF Dec2
39 IF Dec1
38 IF In
Lin Adj1 20
Enable 21
oscC 22
oscE 23
IF
LO
37 V
EE
oscB 24
IF2
25 26 27 28 29 30 31 32 33 34 35 36
ESD Sensitive —
Handle with Care
This device contains
626 active transistors.
IF1
Page 1 of 17
www.lansdale.com
Issue 0
ML13145
LANSDALE Semiconductor, Inc.
MAXIMUM RATINGS
Rating
Power Supply Voltage
Symbol
(max)
Value
7.0
Unit
Vdc
°C
V
CC
T (max)
Junction Temperature
150
J
Storage Temperature Range
Maximum Input Signal
T
–65 to 150
5.0
°C
stg
P
dBm
in
NOTES: 1. Meets Human Body Model (HBM) ≤250 V and Machine Model (MM) ≤25 V.
RECOMMENDED OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
Power Supply Voltage (T = 25°C)
V
V
2.7
0
–
0
6.5
0
Vdc
A
CC
EE
Input Frequency (LNA In, Mxr In)
1
f
100
–20
–
–
–
1800
70
MHz
°C
in
Ambient Temperature Range
T
A
Input Signal Level (with minor performance degradation)
P
–10
–
dBm
in
RECEIVER DC ELECTRICAL CHARACTERISTICS (T = 25°C; V
= 3.6 Vdc; No Input Signal,
CC
A
unless otherwise noted)
Characteristics
Symbol
Min
24
–
Typ
27
Max
34
Unit
mA
A
Total Supply Current (Enable = V
CC)
I
total
total
Power Down Current (Enable = V
EE)
I
10
50
RECEIVER AC ELECTRICAL CHARACTERISTICS (T = 25°C; V
= 3.6 Vdc; RF In = 1.0 GHz; 1st LO Freq = 1070.7 MHz; 2nd
A
CC
= 1.0 kHz; f = 40 kHz; IF filter bandwidth = 280 kHz, unless otherwise noted. See Figure 1 Test Circuit)
dev
LO Freq = 60 MHz; f
mod
Input
Pin
Measure
Pin
Characteristics
Symbol
MIn
12
–
Typ
20
Max
–
Unit
dB
SINAD @ –110 dBm LNA Input
LNA In
LNA In
Det Out
Det Out
SINAD
12 dB SINAD Sensitivity (Apps Circuit with
C–message filter at DetOut)
SINAD
–115
–
dBm
12dB
30 dB SINAD Sensitivity (No IF filter distortion within
40 kHz)
LNA In
LNA In
Det Out
Det Out
SINAD
–
–
–
–100
5.0
–
–
dBm
dB
30dB
SINAD Variation with IF Offset of 40 kHz (No IF filter
distortion within 40 kHz)
Noise Figure: LNA, 1st Mixer & 2nd Mixer
Power Gain: LNA, 1st Mixer & 2nd Mixer
RSSI Dynamic Range
LNA In
LNA In
IF In
IF Out
IF Out
RSSI
RSSI
NF
G
–
–
15
–
3.5
19
80
5.0
25
–
dB
dB
dB
µA
RSSI Current
IF In
–
–10 dBm @ IF Input
–20 dBm @ IF Input
–30 dBm @ IF Input
–40 dBm @ IF Input
–50 dBm @ IF Input
–60 dBm @ IF Input
–70 dBm @ IF Input
–80 dBm @ IF Input
–90 dBm @ IF Input
35
–
–
–
15
–
–
–
–
40
35
30
25
20
15
10
5.0
1.0
55
–
–
–
37
–
–
–
7.0
Input 1.0 dB Compression Point(Measured at IF
output)
P
–
–
–18
–8.0
1.0
–
–
dBm
dBm
in1dB
Input 3rd Order Intercept Point (Measured at IF
output)
IIP3
Demodulator Output Swing (50 k || 56 pF Load)
IF In
Det Out
V
0.8
1.2
V
pp
out
Page 2 of 17
www.lansdale.com
Issue 0
LANSDALE Semiconductor, Inc.
ML13145
RECEIVER AC ELECTRICAL CHARACTERISTICS (T = 25°C; V
= 3.6 Vdc; RF In = 1.0 GHz; 1st LO Freq = 1070.7 MHz; 2nd
= 1.0 kHz; f = 40 kHz; IF filter bandwidth = 280 kHz, unless otherwise noted. See Figure 1 Test Circuit)
dev
A
CC
LO Freq = 60 MHz; f
mod
Input
Pin
Measure
Pin
Characteristics
Symbol
MIn
Typ
Max
Unit
Demodulator Bandwidth ( 1.0 dB bandwidth)
Det Out
BW
–
100
–
kHz
Prescalar Output Level (10 k //8.0 pF load)
Prescaler 64 Frequency = 16.72968 MHz
Prescaler 65 Frequency = 16.4723 MHz
PRSC
V
out
V
pp
out
0.4
0.4
0.51
0.51
0.6
0.6
MC Current Input (High)
MC Current Input (Low)
Input high voltage
MC
MC
I
70
100
–100
–
130
–70
µA
µA
V
ih
I
–130
il
Enable
V
V
– 0.4
V
CC
ih
CC
Input low voltage
Input Current
Enable
Enable
V
0
–
–
0.4
50
–
V
il
I
in
–50
µA
nS
dB
PLL Setup Time [Note 1]
MC
PRSC
out
T
–
–
10
50
PLL
SNR @ –30 dBm Signal Input (<40 kHz
deviation;with C–Message Filter)
–
Total Harmonic Distortion (<40 kHz deviation;with
C–Message Filter)
–
–
1.0
12
–
–
%
Spurious Response SINAD (RF In: –50 dBm)
dB
Page 3 of 17
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Issue 0
ML13145
LANSDALE Semiconductor, Inc.
Figure 1. Test Circuit
MC
PRSC Out
10 k
10 n
7.2 p
1.0 n
RSSI
2.0 k
2.0 k
51 k
56 p
51 k
Det Out
10 k
100 n
4
68 k
2.7 k
1.0 n
12 11 10
9
8
7
6
5
3
2
1
V
V
6.8 n
LNA In
CC CC
100 p
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
6.8 p 1.5 p
100 k
1.0 n
BWadj
64/65
LNA
100 n
1.0 n
Lim
1.0 n
20
6.8 n
1.0 p
V
V
CC
CC
1.0 M
ML13145
1.0 n
1.0 n
100 n
1.0 n
EN
IF
1.0 n
4.7 p
4.7 p
3.3 nH
V
V
CC
CC
47 p
25 26 27 28 29 30 31 32 33 34 35 36
10 n
1.0 M
1.0 n
10 p
1.0 k
50
RF
LO
12 p
16 p
10
T1**
100 n
V
CC
1.0 µ
1.0 µ
10 n
100 n
1.0 n
1.0 n
RF
LO2
IF In
10
1.0 µ
100 n
T2
TC4
*CF1 & CF2 = 280 kHz, 6.0 dB BW, 10.7 MHz Ceramic Filter
**T1 = Toko Part # 600ENAS–A998EK
IF Out
Page 4 of 17
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Issue 0
LANSDALE Semiconductor, Inc.
ML13145
General
ly 80 dB of dynamic range with temperature compensation.
Linearity of the RSSI is optimized by using external ceramic
bandpass filters which have an insertion loss of 4.0 dB and
330 Ω source and load impedance.
The ML13145 is a low power dual conversion wideband FM
receiver incorporating a split IF. This device is designated for
use as the receiver in analog and digital FM systems such as
900 Mhz ISM Band Cordless phones and wideband data links
with data rates up to 150kbps. It contains a 1st and 2nd mixer,
1st and 2nd local oscillator, Received Signal Strength Indicator
(RSSI), IF amplifier, limiting IF, a unique coilless quadrature
detector, and a device enable function.
IF Amplifier
The first IF amplifier section is composed of three differen-
tial stages with the second and third stages contributing to the
RSSI. This section has internal DC feedback and external input
decoupling for improved symmetry and stability. The total gain
of the IF amplifier block is approximately 40 dB up to 40MHz.
The fixed internal input impedance is 330 Ω. When using
ceramic filters requiring source and load impedances of 330Ω,
no external matching is necessary. Overall RSSI linearity is
dependent on having total midband attenuation of 10 dB (4.0
dB insertion loss plus 6.0 dB impedance matching loss) for the
filter. The output of the IF amplifier is buffered and the imped-
ance is 330 Ω.
Current Regulation/Enable
The ML13145 is designed for battery powered portable
applications. Supply current is typically 27 mA at 3.6 Vdc.
Temperature compensating, voltage independent current reg-
ulators are controlled by the Enable Pin where ”high” powers
up and ”low” powers down the entire circuit.
Low Noise Amplifier (LNA)
The LNA is a cascoded common emitter amplifier configu-
ration. Under very large RF input signals, the DC base current
of the common emitter and cascode transistors can become
very significant. To maintain linear operation of the LNA, ade-
quate dc current source is needed to establish the 2Vbe refer-
ence at the base of the RF cascoded transistor and to provide
the base voltage on the common emitter transistor. A sensing
circuit, together with a current mirror guarantees that there is
always sufficient DC base current available for the cascode
transistor under all power levels.
Limiter
The limiter section is similar to the IF amplifier section
except that five stages are used with the middle three con-
tributing to the RSSI. The fixed internal input impedance is
330 Ω. The total gain of the limiting amplifier section is
approximately 84 dB. This IF limiting amplifier section inter-
nally drives the coilless quadrature detector section.
Coilless Quadrature Detector
The coilless detector is a unique design which eliminates the
conventional tunable quadrature coil in FM receiver systems.
The frequency detector implements a phase locked loop with a
fully integrated on chip relaxation oscillator which is current
controlled and externally adjusted, a bandwidth adjust, and an
automatic frequency tuning circuit. The loop filter is external
to the chip allowing the user to set the loop dynamics. Two
outputs are used: one to deliver the audio signal (detector out-
put) and the other to filter and tune the detector (AFT).
1st and 2nd Mixer
Each mixer is a double–balanced class AB four quadrant
multiplier which may be externally biased for high mixer
dynamic range. Mixer input third order intercept point of up
to17 dBm is achieved with only 7.0 mA of additional supply
current. The 1st mixer has a single–ended input at 50 Ω and
operates at 1.0 GHz with –3.0 dB of power gain at approxi-
mately 100 mVrms LO drive level. The mixers have open col-
lector differential outputs to provide excellent mixer dynamic
range and linearity.
Figure 2. 2nd Mixer NF & Gain
versus LO Power
25
20
15
10
5.0
0
–2.0
–4.0
–6.0
–8.0
–10
1st Local Oscillator
The 1st LO has an on–chip transistor which operates with
coaxial transmssion line and LC resonant elements up to 1.8
GHz. A VCO output is available for multi–frequency operation
under PLL synthesizer control.
NF
RSSI
Gain
The received signal strength indicator (RSSI) output is a cur-
rent proportional to the log of the received signal amplitude.
The RSSI current output (Pin 7) is derived by summing the
currents from the IF and limiting amplifier stages. An increase
in RSSI dynamic range, particularly at higher input signal lev-
els is achieved. The RSSI circuit is designed to provide typical-
V
T
P
= 3.6 Vdc
= 25°C
= –25 dBm
CC
A
RF
Lim Adj Current = 0
–12
11
–14
–9.0
–4.0
–1.0
6.0
LO POWER (dBm)
Page 5 of 17
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Issue 0
ML13145
LANSDALE Semiconductor, Inc.
PIN FUNCTION DESCRIPTION
Description
Pin
Symbol/Type
Description
47
BWadj
See Figure 3.
COILLESS DETECTOR
Bandwidth Adjust
The deviation bandwidth of the detector response is
determined by the combination of an on–chip
capacitor and an external resistor to ground.
2
F
V
Frequency Adjust
adj
The free running frequency of the detector
oscillator is defined by the combination of an
on–chip capacitor and an external resistor, Radj
from frequency adjust pin to ground.
1, 48
3
V
, Negative Supply
EE
EE
These pins are V
circuit.
supply for the coilless detector
EE
AFT Out
AFT Out
The AFT is low pass filtered with a corner frequency
below the audio bandwidth allowing the error to be
added to the center frequency adjust signal at Fadj,
Pin 2. The low frequency high pass corner is set by
the external capacitor, Ct from AFT out (Pin 3) to
AFT in (Pin 4) and external resistor, Rt from AFT
out to Fadj (Pin 2).
4
5
6
AFT In
Det Gain
Det Out
AFT In
The AFT in is used to set the buffer transfer
function.
Detector Gain
The AFT buffer is used to set the buffer transfer
function.
Detector Output
Set gain and output level of detector with resistor to
Det Out Pin.
Figure 3. Coilless Detector Internal Circuit
i
Current Amplifier
i
Phase
Detector
ICO
V
V
CC
CC
IF
V
4
5
6
A * i
A * i
AFT In
V
ref2
RI
C
t
Fadj
2I
2
Rt
3
ref1
AFT Out
Det Out
BWadj
47
Rb
Rf
2Ib
V
EE
48, 1
Page 6 of 17
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Issue 0
LANSDALE Semiconductor, Inc.
ML13145
Pin
Symbol/Type
Description
Description
8
V
EE
V , Negative Supply Voltage
EE
11
V
CC
9
PRSCout
Prescaler Output
The prescaler output provides typically 500 mVpp
9
drive to the fin pin of a PLL synthesizer. Conjugately
matching the interface will increase the drive
delivered to the PLL input.
PRSC Out
1.0 mA
8
V
CC
V
EE
10
10
MC
Dual Modulus Control Current Input
This requires a current input of typically 200 µApp.
MC
11, 12
V
CC
V
, Positive Supply
CC
CC
V
pin is taken to the incoming positive battery or
regulated dc voltage through a low impedance trace
on the PCB. It decoupled to V
of the IC.
ground at the pin
EE
17
14
LNA In
LNA In
LNA
out
The input is the base of the common emitter
transistor. Minimum external matching is required to
optimize the input return loss and gain.
15, 16
V
EE
13
13, 15,
& 16
V
EE
V
, Negative Supply
EE
EE
V
ref2
V
EE
14
V
pin is taken to an ample dc ground plane
through a low impedance path. The path should be
kept as short as possible. A minimum two sided
PCB is recommended so that ground returns can
be easily made through via holes.
V
ref1
LNA
in
2.0 mA
11,12
V
CC
17
19
LNAout
LNA Out
The output is from the collector of the cascode
transistor amplifier. The output may be conjugately
matched with a shunt L (needed to dc bias the open
collector), and series L and C network.
V
Mxr In
1
1st Mixer Input
CC
The mixer input impedance is broadband 50 Ω for
applications up to 2.4 GHz. It easily interfaces with
a RF ceramic filter.
20
LinAdj1
20
Lin Adj1
1st Mixer Linearity Control
The mixer linearity control circuit accepts
approximately 0 to 300 µA control current to set the
dynamic range of the mixer. An Input Third Order
Intercept Point, IIP3 of 17 dBm may be achieved at
300 µA of control current.
19
Mxr In
1
450 µA
Page 7 of 17
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Issue 0
ML13145
LANSDALE Semiconductor, Inc.
Pin
Symbol/Type
Description
Description
21
Enable
Enable
Enable the receiver by pulling the pin up to V
.
CC
21
10 k
Enable
26
27
V
V
, Negative Supply
EE
EE
EE
V
supply for the mixer IF output.
27
IF1+
IF1+
IF1–
1st Mixer Outputs
The Mixer is a differential open collector output
26
configuration which is designed to use over a wide
frequency range. The differential output of the mixer
has back to back diodes across them to limit the
output voltage swing and to prevent pulling of the
VCO. Differential to single–ended circuit
configuration and matching options are shown in
the Test Circuit. Additional mixer gain can be
achieved by matching the outputs for the desired
passband Q.
V
EE
28
28
IF1–
22
23
24
25
Collector
Emitter
Base
On–board VCO Transistor
The transistor has the emitter, base, collector, VCC,
and VEE pins available. Internal biasing which is
compensated for stability over temperature is
provided. It is recommended that the base pin is
pulled up to VCC through an RFC chosen for the
particular oscillator center frequency .
25
V
CC
24
Base
18, 26
V
CC
V
, Positive Supply Voltage
V
CC
EE
A VCC pin is provided for the VCO. The operating
supply voltage range is from 2.7 Vdc to 6.5 Vdc.
23
Emitter
2.0 mA
500 µA
18, 26
29
V
V
, Negative Supply Voltage
22
EE
EE
Collector
Lin Adj2
2nd Mixer Linearity Control
31, V
CC
The mixer linearity control circuit accepts
approximately 0 to 400 µA control current to set the
dynamic range of the mixer. An Input Third Order
Intercept Point, IIP3 of 17 dBm may be achieved at
400 µA of control current. IIP3 default with no
external bias is 10 dBm.
29
Lin Adj2
30
31
Mxr2 In
2nd Mixer Input
30
The mixer input impedance is broadband 50 Ω.
Mxr2 In
450 µA
V
CC
V
CC
, Positive Supply
Page 8 of 17
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Issue 0
LANSDALE Semiconductor, Inc.
ML13145
Pin
Symbol/Type
Description
Description
32, 34
V
EE
V , Negative Supply Voltage
EE
V
CC
LO Out+
LO Out–
(to Mxr2)
33
LO2
2nd Local Oscillator
The 2nd LO input impedance is broadband 50 Ω; it
is driven from an external 50 Ω source. Typical level
is –15 to –10 dBm.
33
LO2
390 µA
32
V
EE
35
36
IF2+
IF2–
2nd Mixer Outputs
The Mixer is a differential open collector
configuration.
35
IF2+
34
V
EE
36
IF2–
37
38
V
See Figure 4.
V
, Negative Supply Voltage
EE
EE
IF In
IF Amplifier Input
IF amplifier input source impedance is 330 Ω.. The
three stage amplifier has 40 dB of gain with 3.0 dB
bandwidth of 40 MHz.
39, 40
IF Dec1,
IF Dec2
IF Decoupling
These pins are decoupled to V
to provide stable
CC
operation of the limiting IF amplifier.
41
42
7
IF Out
IF Amplifier Output
IF amplifier output load impedance is 330 Ω.
V
CC
V
CC
, Positive Supply Voltage
RSSI
RSSI
The RSSI circuitry in the 2nd & 3rd amplifier stages
outputs a current when the output of the previous
stage enters limiting. The net result is a RSSI
current which represents the logarithm of the IF
input voltage. An external resistor to ground is used
to provide a voltage output.
Page 9 of 17
www.lansdale.com
Issue 0
ML13145
LANSDALE Semiconductor, Inc.
Figure 4. IF Amplifier Functional Diagram
RSSI
39
IF Dec1
Σ
38
IF In
40
IF Dec2
41
IF Out
Pin
Symbol/Type
Description
Description
43
V
CC
See Figure 5.
V
CC
, Positive Supply Voltage
44
Lim In
Limiting Amplifier Input
Limiting amplifier input source impedance is 330 Ω.
This amplifier has 84 dB of gain with 3.0 dB
bandwidth of 40 MHz; this enables the IF and
limiting ampliers chain to hard limit on noise.
45, 46
7
Lim Dec1,
Lim Dec2
If Decoupling
These pins are decoupled to V
to provide stable
CC
operation of the 2nd IF limiting amplifier.
RSSI
RSSI
The RSSI circuitry in the 2nd, 3rd, & 4th amplifier
stages outputs a current when the output of the
previous stage enters limiting. The net result is a
RSSI current which represents the logarithm of the
IF input voltage. An external resistor to ground is
used to provide a voltage output.
Figure 5. Limiter Amplifier Functional Diagram
7
RSSI
45
Lim Dec1
Σ
44
Lim+
Lim–
Lim In
46
Demod
Lim Dec2
Page 10 of 17
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Issue 0
LANSDALE Semiconductor, Inc.
ML13145
Figure 7. 2nd Mixer P
versus LO Drive
Figure 6. 2nd Mixer Gain
versus LO Drive
1dB
–6.0
–6.4
–6.8
–7.2
–7.6
–8.0
6.0
5.0
4.0
3.0
2.0
1.0
0
V
T
P
= 3.6 V
CC
A
RF
= 25°C
= –25 dBm
Lin Adj Current = 400µA
V
T
= 3.6 V
CC
= 25°C
A
Lin Adj Current = 400µA
–20
–18
–16
–14
–12
–10
–20
–18
–16
–14
–12
–10
LO DRIVE (dBm)
LO DRIVE (dBm)
Figure 8. 2nd Mixer IP3/P
1dB
Figure 9. 2nd Mixer Gain
versus Lin Adj Current
versus Lin Adj Current
18
16
14
12
10
8.0
6.0
4.0
2.0
0
–6.0
–6.2
–6.4
–6.6
–6.8
–7.0
V
T
P
P
= 3.6 V
CC
A
LO
RF
= 25°C
= –15 dBm
= –25 dBm
IP3
V
T
P
= 3.6 V
= 25°C
= –15 dBm
CC
A
LO
Adj Channel = 75 kHz
P
1dB
0
100
200
300
400
500
600
0
100
200
300
400
500
60
LIN ADJ CURRENT ( µA)
LIN ADJ CURRENT ( µA)
Figure 10. Test Circuit for Figures 6 thru 9.
5.1 k
10 n
29
Lin Adj2
Lin Adj
Current
V
CC
35
IF2+
IF2–
T1
IF
30
33
Mxr2 In
LO2
out
RF
in
in
1.0 k
36
LO2
16:1
T1 = Toko 600ENAS–A998EK
Page 11 of 17
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LANSDALE Semiconductor, Inc.
Figure 12. Fadj Resistor
versus IF Frequency
Figure 11. Fadj Current
versus IF Frequency
500
450
400
350
300
250
200
150
100
7.0
6.0
5.0
4.0
3.0
2.0
1.0
5.0
10
IF FREQUENCY (MHz)
15
20
5.0
10
IF FREQUENCY (MHz)
15
20
Figure 13. BWadj Resistor
versus BWadj Current
Figure 14. IF Frequency
versus BWadj Current
900
800
700
600
500
400
300
200
100
10.90
10.85
10.80
10.75
10.70
10.65
10.60
10.55
1.0
2.0
3.0
4.0
5.0
6.0
1.0
2.0
3.0
4.0
5.0
60.
BWadj CURRENT ( µA)
BWadj CURRENT ( µA)
Page 12 of 17
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LANSDALE Semiconductor, Inc.
ML13145
Table 1. LNA S–Parameters: 3.6 Vdc
Freq
(MHz)
S11
Mag
S11
Ang
S21
Mag
S21
Ang
S12
Mag
S12
Ang
S22
mag
S22
Ang
25
0.84
0.84
0.83
0.81
0.78
0.73
0.66
0.64
0.62
0.51
0.49
0.47
0.46
0.44
0.45
0.55
0.48
0.43
0.43
0.45
0.47
0.51
0.55
–3.0
–71
10.8
10.7
10.3
10.
9.6
9.0
7.8
7.4
7.0
5.5
5.2
4.9
4.6
4.3
3.9
3.5
3.1
2.5
2.1
1.8
1.5
1.2
1.0
176
171
162
154
147
132
116
111
106
80
0.00005
0.0004
0.0006
0.0011
0.001
–27
76
1.0
1.0
–1.2
–3.7
–4.9
–7.3
–9.7
–15
–19
–21
–23
–33
–36
–37
–38
–40
–41
–50
–65
–74
–85
–96
–106
–118
–129
50
100
–15
61
0.99
0.99
0.99
0.99
0.95
0.96
0.96
0.94
0.93
0.92
0.92
0.91
0.95
0.099
0.94
0.93
0.92
0.91
0.89
0.88
0.85
150
–22
91
200
–28
60
300
–41
0.002
42
400
–50
0.00070
0.0014
0.0009
0.0013
0.002
22
450
–54
39
500
–59
69
750
–77
–51
–80
–120
–130
–142
–162
140
63
800
–80
75
850
–81
71
0.004
900
–82
67
0.0057
0.008
950
––82
–81
62
1000
1250
1500
1750
2000
2250
2500
2750
3000
58
0.014
–94
47
0.029
–120
–126
–135
–145
–155
–167
–180
24
0.02
6.9
–9.9
–27
–43
–60
–78
0.0066
0.0099
0.017
79
129
133
132
130
120
0.021
0.03
0.039
Page 13 of 17
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ML13145
LANSDALE Semiconductor, Inc.
CF2
CF3
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ML13145
Legacy Applications Information
Figure 16. Evaluation PCB Component Side
Figure 17. Evaluation PCB Solder Side
2.25″
2.25″
2.5″
2.5″
CF1
CF2,CF3
C1, C3, C5, C7, C13, C17, C31,
480/481
10.7M
100 p
C45
C46, C47
C49
3.3 p
2.0 p
22
C41, C42, C43, C44, C48, C51
C2
C6, C12, C21, C23, C26, C27,
C28, C29, C33, C34, C36, C37,
C38, C39, C54
C8, C15, C16, C18, C32, C53
C9
C10
C11
C14
C19
C20
C50
1.0
U/D
6.8 n
5.6 n
2.7
1.5 p
1.0 n
R1, R7, R8, L8, L9, R12, C52
L1
L2
L4, L5
L6
L7
R3
R5
R6,R14
R11,R9
R10
R13
T1
0.01
16 p
10 p
12 p
2.0–4.0 p
36 p
39 p
0.1
RFC
2.7 n
33 k
27 k
51 k
68 k
2.7 k
51
C22, C24, C25, C30, C35
R2, C40
10
A099
ML13145
U1
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Legacy Applications Information
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ML13145
LANSDALE Semiconductor, Inc.
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili-
ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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