ML1350 [LANSDALE]
Monolithic IF Amplifier; 单片中频放大器型号: | ML1350 |
厂家: | LANSDALE SEMICONDUCTOR INC. |
描述: | Monolithic IF Amplifier |
文件: | 总6页 (文件大小:582K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ML1350
Monolithic IF Amplifier
Legacy Device: Motorola MC1350
The ML1350 is an integrated circuit featuring wide range
AGC for use as a linear IF amplifier in AM radio, shortwave,
TV and instrumentation.
P DIP = PP
PLASTIC PACKAGE
• Power Gain: 50 dB Typ at 45 MHz
50 dB Typ at 58 MHz
• AGC Range: 60 dB Min, DC to 45 MHz
• Nearly Constant Input & Output Admittance over the
Entire AGC Range
8
CASE 626
1
SO 8 = -5P
•
Constant (–3.0 dB) to 90 MHz
Y21
PLASTIC PACKAGE
8
• Low Reverse Transfer Admittance: << 1.0 µmho Typical
• 12 V Operation, Single–Polarity Power Supply
CASE 751
(SO–8)
1
• Operating Temperature Range T = 0° to +75° C
A
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
P DIP 8
SO 8
MOTOROLA
MC1350P
MC1350D
LANSDALE
ML1350PP
ML1350-5P
Note: See ML1490 Similar Function
MAXIMUM RATINGS (T = +25°C, unless otherwise noted.)
A
Rating
Power Supply Voltage
Symbol
Value
+18
Unit
Vdc
Vdc
Vdc
Vdc
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
+
V
Output Supply Voltage
AGC Supply Voltage
Differential Input Voltage
V , V
+18
1
8
+
V
V
AGC
V
in
5.0
Power Dissipation (Package Limitation)
Plastic Package
Derate above 25°C
P
D
625
5.0
mW
mW/°C
Operating Temperature Range
T
A
0 to +75
°C
Figure 1. Typical ML1350 Video IF Amplifier and MC1330 Low–Level Video Detector Circuit
0.002µF
470
220
+18Vdc
18V
Auxiliary Video
Output
0.1µF
3.3k
0.002µF
68pF
0.001µF
10V
Primary Video
and Sound Output
7.7V
4
22
7
6
3
5
4
3
2
1
T1
45MHz
Input
3.9k
50
MC1330AP
ML1350
0
5
6
7
8
8
2
1
12pF
33pF
AFT Output
3.9k
L1
T1
5"
AGC
3"
≈16
16
3
16
"
1
4
"
10
Turns
5
6
Turns
Turns
All windings #30 AWG tinned nylon acetate
wire tuned with Carbonyl E or J slugs.
L1 wound with #26 AWG tinned nylon
acetate wire tuned by distorting winding.
Page 1 of 6
www.lansdale.com
Issue A
ML1350
LANSDALE Semiconductor, Inc.
+
ELECTRICAL CHARACTERISTICS (V = +12 Vdc, T = +25°C, unless otherwise noted.)
A
Characteristics
AGC Range, 45 MHz (5.0 V to 7.0 V) (Figure 1)
Power Gain (Pin 5 grounded via a 5.1 kΩ resistor)
Symbol
Min
Typ
Max
Unit
dB
60
68
–
A
p
dB
f = 58 MHz, BW = 4.5 MHz
f = 45 MHz, BW = 4.5 MHz
f = 10.7 MHz, BW = 350 kHz
f = 455 kHz, BW = 20 kHz
See Figure 6(a)
See Figure 6(a), (b)
See Figure 7
–
46
–
48
50
58
62
–
–
–
–
–
Maximum Differential Voltage Swing
0 dB AGC
–30 dB AGC
V
O
V
pp
–
–
20
8.0
–
–
Output Stage Current (Pins 1 and 8)
Total Supply Current (Pins 1, 2 and 8)
Power Dissipation
I
1
+ I
–
–
–
5.6
14
–
mA
mAdc
mW
8
I
S
17
P
D
168
204
+
DESIGN PARAMETERS, Typical Values (V = +12 Vdc, T = +25°C, unless otherwise noted.)
A
Frequency
Parameter
Single–Ended Input Admittance
Symbol
455 kHz 10.7 MHz 45 MHz
58 MHz
Unit
g
11
b
11
0.31
0.36
0.50
0.39
2.30
0.5
2.75
mmho
0.022
Input Admittance Variations with AGC
(0 dB to 60 dB)
∆g
∆b
–
–
–
–
60
0
–
–
µmho
µmho
µmho
µmho
11
11
Differential Output Admittance
g
22
b
22
4.0
3.0
4.4
110
30
390
60
510
Output Admittance Variations with AGC
(0 dB to 60 dB)
∆g
22
∆b
22
–
–
–
–
4.0
90
–
–
Reverse Transfer Admittance (Magnitude)
|y
|
< < 1.0
< < 1.0
< < 1.0
< < 1.0
12
Forward Transfer Admittance
Magnitude
Angle (0 dB AGC)
Angle (–30 dB AGC)
|y
< y
< y
|
160
–5.0
–3.0
160
–20
–18
200
–80
–69
180
–105
–90
mmho
Degrees
Degrees
21
21
21
Single–Ended Input Capacitance
Differential Output Capacitance
C
C
7.2
1.2
7.2
1.2
7.4
1.3
7.6
1.6
pF
pF
in
O
Figure 2. Typical Gain Reduction
Figure 3. Noise Figure versus Gain Reduction
22
0
20
18
16
I
= 0.1 mA
AGC
20
58 MHz
14
12
40
60
45 MHz
(Figure 6)
10
I
= 0.2 mA
8.0
6.0
(Figures 6 and 7)
5.0
AGC
80
4.0
6.0
, SUPPLY VOLTAGE (V)
7.0
0
10
20
30
40
V
GAIN REDUCTION (dB)
AGC
Page 2 of 6
www.lansdale.com
Issue A
ML1350
LANSDALE Semiconductor, Inc.
GENERAL OPERATING INFORMATION
The input amplifiers (Q1 and Q2) operate at constant emitter
currents so that input impedance remains independent of AGC
action. Input signals may be applied single–ended or differen-
AGC action occurs as a result of an increasing voltage on the
base of Q4 and Q5 causing these transistors to conduct more
heavily thereby shunting signal current from the interstage
tially (for AC) with identical results. Terminals 4 and 6 may be amplifiers Q3 and Q6. The output amplifiers are supplied from
driven from a transformer, but a DC path from either terminal
to ground is not permitted.
an active current source to maintain constant quiescent bias
thereby holding output admittance nearly constant. Collector
voltage for the output amplifier must be supplied through a
center–tapped tuning coil to Pins 1 and 8. The 12 V supply
(V+) at Pin 2 may be used for this purpose, but output admit-
tance remains more nearly constant if a separate 15 V supply
(V+ +) is used, because the base voltage on the output amplifi-
er varies with AGC bias.
Figure 4. Circuit Schematic
AGC Amplifier Section
V+
2
(+)
1.47k
AGC
Input
8
V + +
70
Output
5
12.1
k
5.53k
470
470
Q6
Q3 Q4
Q5
2.0k
Figure 5. Frequency Response Curve
(45 MHz and 58 MHz)
1 ( – )
Q7
Q10
4 ( – )
Q8
Q9
45
1.4k
5.6k
Inputs
Q1
66
Q2
2.8k
200 200
2.8k
6 ( + )
5.0k
5.0k
1.9k
1.1k
1.1k
8.4k
200
7
Scale: 1.0 MHz/cm
Gnd
Input Amplifier Section
Bias Supplies
Output Amplifier Section
Figure 6. Power Gain, AGC and Noise Figure Test Circuits
(a) 45 MHz and 58 MHz
(b) Alternate 45 MHz
+12V
0.001µF
L
P
L
0.001µF
P
Input
0.68µH
.001
+12V
Input
= 50
R
Ω
L1
S
C2
L
P
1.5–20pF
1
0.1
0.001
0.33µH
µF
R
= 50
Ω
C1
Output
= 50
S
4
5
3
2
1
8
L1
4
3
2
C1
T1
R
Ω
L
R
= 50Ω
Output
L
ML1350
ML1350
6
7
5.1k
C2
5.1k
5
6
7
8
5.1k
V
AGC
V
*
AGC
0.001µF
0.001
C3
0.001
0.001µF 0.001µF
*Connect to ground for maximum power gain test.
All power supply chokes (Lp), are self–resonant at input frequency. L
See Figure 5 for Frequency Response Curve.
≥ 20 kΩ.
Ferrite Core
14 Turns 28 S.W.G.
P
L1
C1
C2
C3
5–25 pF
5–25 pF
5–25 pF
L1 @ 45 MHz = 7 1/4 Turns on a 1/4
L1 @ 58 MHz = 6 Turns on a 1/4 coil form
T1 Primary Winding = 18 Turns on a 1/4 coil form, center–tapped, #25 AWG
" coil form
"
"
Secondary Winding = 2 Turns centered over Primary Winding @ 45 MHz
= 1 Turn @ 58 MHz
Slug = Carbonyl E or J
45 MHz
58 MHz
L1
T1
C1
C2
0.4 µH
Q ≥ 100
Q ≥ 100 @ 2.0 µH
0.3 µH
Q ≥ 100
Q ≥ 100 @ 2.0 µH
8.0 pF to 60 pF
3.0 pF to 35 pF
1.3 µH to 3.4 µH
1.2 µH to 3.8 µH
50 pF to 160 pF
8.0 pF to 60 pF
Page 3 of 6
www.lansdale.com
Issue A
ML1350
LANSDALE Semiconductor, Inc.
Legacy Applications Information
Figure 7. Power Gain and AGC Test Circuit
(455 kHz and 10.7 MHz)
Frequency
Input
R
= 50Ω
L1
Component
455 kHz
10.7 MHz
S
12 V
C1
–
–
80–450 pF
5.0–80 pF
0.001 µF
0.05 µF
36 pF
0.05 µF
0.05 µF
4.6 µF
C3
C2
C3
C4
C5
C8
C7
L1
C2
C1
C4
0.05 µF
0.05 µF
0.001 µF
0.05 µF
0.05 µF
–
4
3
2
1
8
T1
C5
Output
= 50
MC1350
R
Ω
S
5.1k
5
6
7
V
*
AGC
T1
Note 1
Note 2
C7
C6
*Grounded for
maximum power gain.
NOTES: 1. Primary: 120 µH (center–tapped)
NOTES: 1. Q = 140 at 455 kHz
u
NOTES: 1. Primary: Secondary turns ratio ≈ 13
NOTES: 2. Primary: 6.0 µH
NOTES: 2. Primary winding = 24 turns #36 AWG
NOTES: 2. (close–wound on 1/4" dia. form)
NOTES: 2. Core = Carbonyl E or J
NOTES: 2. Secondary winding = 1–1/2 turns #36 AWG, 1/4" dia.
NOTES: 2. (wound over center–tap)
Figure 8. Single–Ended Input Admittance
Figure 9. Forward Transfer Admittance
500
400
300
200
100
0
0
5.0
4.0
<
Y
(–30 dB gain)
21
–40
–80
–120
–160
–200
<
Y
(max gain)
21
b
11
11
3.0
2.0
1.0
0
Y21
g
10
20
30
40
50
70
100
1.0
2.0
3.0 5.0
10
20
30 50
100
f, FREQUENCY (MHz)
f, FREQUENCY (MHz)
Figure 11. Differential Output Voltage
Figure 10. Differential Output Admittance
1.0
0.8
0.6
0.4
0.2
0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
(Single–ended output
admittance exhibits
twice these values.)
+ +
+ +
V
V
= 14 V
= 12 V
b
22
22
g
0
10
20
30
40
50
60
70
80
10
20
30
40
50
70
100
GAIN REDUCTION (dB)
f, FREQUENCY (MHz)
Page 4 of 6
www.lansdale.com
Issue A
ML1350
LANSDALE Semiconductor, Inc.
Typical application of a AM
Figure 12.
Modulator using ML1350
V1
12V
+V
C4
.1uF
C1
220pF
L2
1uH
R2
P1
RF input
C6
470pF
50
4
3
1
8
2
T1
C5
47pF
RF out
P3
V2
10V
+V
U2
ML1350
6
7
5
R1
5.1k
R3
10k 40%
C7
1uF
AGC
C2
P2
.1uF
C3
.1uF
MOD input
Page 5 of 6
www.lansdale.com
Issue A
ML1350
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
P DIP 8 = PP
(ML1350PP)
PLASTIC PACKAGE
CASE 626–05
ISSUE K
8
5
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
–B–
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
1
4
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
F
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MIN
9.40
6.10
3.94
0.38
1.02
MAX
10.16
6.60
4.45
0.51
1.78
MIN
MAX
0.400
0.260
0.175
0.020
0.070
–A–
NOTE 2
0.370
0.240
0.155
0.015
0.040
L
C
2.54 BSC
0.100 BSC
0.76
0.20
2.92
7.62 BSC
–––
1.27
0.30
3.43
0.030
0.008
0.115
0.300 BSC
–––
0.050
0.012
0.135
J
–T–
N
SEATING
PLANE
M
0.76
1.01
0.030
0.040
D
K
G
H
M
M
M
0.13 (0.005)
T
A
B
SO 8 = -5P
(ML1350-5P)
PLASTIC PACKAGE
CASE 751–05
(SO–8)
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
ISSUE N
8
5
4
4X P
–B–
M
M
0.25 (0.010)
B
1
G
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
K
M
P
MIN
4.80
3.80
1.35
0.35
0.40
MAX
5.00
4.00
1.75
0.49
1.25
MIN
MAX
0.196
0.157
0.068
0.019
0.049
0.189
0.150
0.054
0.014
0.016
R X 45°
F
C
SEATING
PLANE
–T–
1.27 BSC
0.050 BSC
K
J
M
0.18
0.10
0.25
0.25
0.007
0.004
0.009
0.009
8X D
0.25 (0.010)
M
S
S
T
B
A
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
R
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili-
ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 6 of 6
www.lansdale.com
Issue A
相关型号:
ML13FAD-FREQ-OUT21
CMOS Output Clock Oscillator, 0.000002MHz Min, 0.032768MHz Max, 0.032768MHz Nom, NICKEL HEADER, DIP-4
MTRONPTI
©2020 ICPDF网 联系我们和版权申明