ML145151YP_技术文档

ML145151 ML145156

ML145152 ML145157

ML145155 ML145158

PLL Frequency Synthesizer Family - CMOS

The devices described in this document are typically used as low–power, phase–locked loop frequency

synthesizers. When combined with an external low–pass filter and voltage–controlled oscillator, these

devices can provide all the remaining functions for a PLL frequency synthesizer operating up to the

device's frequency limit. For higher VCO frequency operation, a down mixer or a prescaler can be used

between the VCO and the synthesizer IC.

These frequency synthesizer chips can be found in the following and other applications:

CATV

TV Tuning

AM/FM Radios

Two–Way Radios

Scanning Receivers

Amateur Radio

÷

R

OSC

φ

CONTROL LOGIC

÷

A

N

÷

EXTERNAL

COMPONENTS

÷

P/P

+ 1

VCO

OUTPUT

FREQUENCY

CONTENTS

Page

DEVICE DETAIL SHEETS

ML145151 Parallel–Input, Single–Modulus ...........................................................................................2

ML145152 Parallel–Input, Dual–Modulus..............................................................................................5

ML145155 Serial–Input, Single–Modulus ..............................................................................................9

ML145156 Serial–Input, Dual–Modulus...............................................................................................13

ML145157 Serial–Input, Single–Modulus ............................................................................................17

ML145158 Serial–Input, Dual–Modulus...............................................................................................20

FAMILY CHARACTERISTICS

Maximum Ratings..................................................................................................................................23

DC Electrical Characteristics.................................................................................................................23

AC Electrical Characteristics.................................................................................................................25

Timing Requirements.............................................................................................................................26

Frequency Characteristics......................................................................................................................27

Phase Detector/Lock Detector Output Waveforms................................................................................27

DESIGN CONSIDERATIONS

Phase–Locked Loop – Low–Pass Filter Design ....................................................................................28

Crystal Oscillator Considerations..........................................................................................................29

Dual–Modulus Prescaling......................................................................................................................30

Page 1 of 35

www.lansdale.com

Issue A

ML145151

Parallel-Input PLL

Frequency Synthesizer

Interfaces with Single–Modulus Prescalers

Legacy Device: Motorola/Freescale MC145151

The ML145151 is programmed by 14 parallel–input data

lines for the N counter and three input lines for the R counter.

The device features consist of a reference oscillator, selec-

table–reference divider, digital–phase detector, and 14–bit

programmable divide–by–N counter.

P DIP 28 = YP

PLASTIC DIP

CASE 710

28

1

SO 28W = -6P

SOG PACKAGE

CASE 751F

• Operating Temperature Range: T

A =

– 40 to 85°C

• Low Power Consumption Through Use of CMOS

Technology

1

• 3.0 to 9.0 V Supply Range

CROSS REFERENCE/ORDERING INFORMATION

PACKAGE

MOTOROLA

LANSDALE

• On– or Off–Chip Reference Oscillator Operation

• Lock Detect Signal

• ÷ N Counter Output Available

P DIP 28

SO 28W

MC145151P2

MC145151DW2 ML145151-6P

ML145151YP

Note: Lansdale lead free (Pb) product, as it

becomes available, will be identified by a part

number prefix change from ML to MLE.

• Single Modulus/Parallel Programming

• 8 User–Selectable ÷ R Values: 8, 128, 256, 512, 1024,

2048, 2410, 8192

• ÷ N Range = 3 to 16383

• “Linearized” Digital Phase Detector Enhances Transfer

Function Linearity

PIN ASSIGNMENT

• Two Error Signal Options: Single–Ended (Three–State)

or Double–Ended

• Chip Complexity: 8000 FETs or 2000 Equivalent Gates

f

1

2

28

27

LD

in

V

OSC

SS

DD

out

in

V

3

26

25

24

23

22

21

20

19

18

17

OSC

N11

N10

N13

N12

T/R

N9

out

PD

4

RA0

RA1

RA2

5

6

7

φ

8

R

φ

9

V

f

10

N8

V

N0 11

N1 12

N7

N6

N2 13

N3 14

16

15

N5

N4

Page 2 of 35

www.lansdale.com

Issue A

LANSDALE Semiconductor, Inc.

ML145151

ML145151 BLOCK DIAGRAM

RA2

RA1

14 x 8 ROM REFERENCE DECODER

14

OSC

out

RA0

LOCK

LD

PD

DETECT

OSC

14–BIT

÷

R COUNTER

in

PHASE

DETECTOR

A

out

f

in

14–BIT

÷

N COUNTER

14

V

PHASE

DETECTOR

B

DD

φ

V

R

TRANSMIT OFFSET ADDER

T/R

f

V

N13

N11

N9

N7 N6

N4

N2

N0

NOTE: N0 – N13 inputs and inputs RA0, RA1, and RA2 have pull–up resistors that are not shown.

PIN DESCRIPTIONS

nificant and N13 is the most significant. Pull–up resistors en-

sure that inputs left open remain at a logic 1 and require only

an SPST switch to alter data to the zero state.

INPUT PINS

f

in

Frequency Input (Pin 1)

T/R

Transmit/Receive Offset Adder Input (Pin 21)

Input to the ÷N portion of the synthesizer. f is typically

in

This input controls the offset added to the data provided at

the N inputs. This is normally used for offsetting the V

quency by an amount equal to the IF frequency of the trans-

ceiver. This offset is fixed at 856 when T/R is low and gives no

offset when T/R is high. A pull–up resistor ensures that no

connection will appear as a logic 1 causing no offset addition.

derived from loop V

CO

and is AC coupled into the device. For

fre-

CO

larger amplitude signals (standard CMOS logic levels) DC

coupling may be used.

RA0 – RA2

Reference Address Inputs (Pins 5, 6, 7)

These three inputs establish a code defining one of eight

possible divide values for the total reference divider, as defined

by the table below.

Pull–up resistors ensure that inputs left open remain at a

logic 1 and require only a SPST switch to alter data to the zero

state.

OSC , OSC

in

out

Reference Oscillator Input/Output (Pins 27, 26)

These pins form an on–chip reference oscillator when con-

nected to terminals of an external parallel resonant crystal.

Frequency setting capacitors of appropriate value must be con-

nected from OSC to ground and OSC

may also serve as the input for an externally generated refer-

ence signal. This signal is typically AC coupled to OSC , but

for larger amplitude signals (standard CMOS logic levels) DC

coupling may also be used. In the external reference mode, no

to ground. OSC

in

out

in

Total

Divide

Value

Reference Address Code

in

RA2

RA1

RA0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8

128

256

512

1024

2048

2410

8192

connection is required to OSC

OUTPUT PINS

PDout

.

out

Phase Detector A Output (Pin 4)

Three–state output of phase detector for use as loop–error

signal. Double–ended outputs are also available for this pur-

pose (see ΦV and ΦR).

N0 – N11

Frequency f > f or f Leading: Negative Pulses

Frequency f < f or f Lagging: Positive Pulses

Frequency f = f and Phase Coincidence: High–Imped-

V

R

V

N Counter Programming Inputs (Pins 11 – 20, 22 – 25)

These inputs provide the data that is preset into the ÷ N

counter when it reaches the count of zero. N0 is the least sig-

R

ance State

Page 3 of 35

www.lansdale.com

Issue A

LANSDALE Semiconductor, Inc.

ML145151

φR,φV

nally connected to the phase detector input. With this output

available, the ÷ N counter can be used independently.

Phase Detector B Outputs (Pins 8, 9)

These phase detector outputs can be combined externally for LD

a loop–error signal. A single–ended output is also available for Lock Detector Output (Pin 28)

this purpose (see PD ).

out

Essentially a high level when loop is locked (f , f of same

R V

If frequency f is greater than f or if the phase of f is

V

R

V

phase and frequency). Pulses low when loop is out of lock.

leading, then error information is provided by φV pulsing low.

φR remains essentially high.

POWER SUPPLY

If the frequency f is less than f or if the phase of f is

V

R

V

DD

lagging, then error information is provided by φR pulsing low.

φV remains essentially high.

Positive Power Supply (Pin 3)

The positive power supply potential. This pin may range

If the frequency of f = f and both are in phase, then both

V

R

from + 3 to + 9 V with respect to V

.

SS

φV and φR remain high except for a small minimum time peri-

V

od when both pulse low in phase.

SS

Negative Power Supply (Pin 2)

f

V

The most negative supply potential. This pin is usually-

ground.

N Counter Output (Pin 10)

This is the buffered output of the ÷ N counter that is inter-

TYPICAL APPLICATIONS

2.048 MHz

NC

OSC

in

OSC

out

f

RA2 RA1

RA0

PD

in

VOLTAGE

CONTROLLED

OSCILLATOR

ML145151

out

N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0

5 – 5.5 MHz

0 1 1 1 0 0 0 1 0 0 0 = 5 MHz

1 0 1 0 1 1 1 1 1 0 0 = 5.5 MHz

Figure 1. 5 MHz to 5.5 MHz Local Oscillator Channel Spacing = 1 kHz

LOCK DETECT SIGNAL

TRANSMIT: 440.0 – 470.0 MHz

RECEIVE: 418.6 – 448.6 MHz

(25 kHz STEPS)

“1”

“0”

CHOICE OF

DETECTOR

ERROR

OSC

RA2

RA1

RA0

LD

f

V

out

SIGNALS

PD

out

OSC

in

LOOP

FILTER

φ

f

VCO

X6

+ V

R

V

DD

SS

ML145151

REF. OSC.

10.0417 MHz

(ON–CHIP OSC.

OPTIONAL)

f

in

T: 73.3333 – 78.3333 MHz

R: 69.7667 – 74.7667 MHz

T/R

T: 13.0833 – 18.0833 MHz

R: 9.5167 – 14.5167 MHz

DOWN

MIXER

“0” “0” “1”

CHANNEL PROGRAMMING

N = 2284 TO 3484

RECEIVE

÷

TRANSMIT

(ADDS 856 TO

N VALUE)

÷

X6

60.2500 MHz

NOTES:

1. f = 4.1667 kHz; ÷ R = 2410; 21.4 MHz low side injection during receive.

R

2. Frequency values shown are for the 440 – 470 MHz band. Similar implementation applies to the 406 – 440 MHz band.

For 470 – 512 MHz, consider reference oscillator frequency X9 for mixer injection signal (90.3750 MHz).

Figure 2. Synthesizer for Land Mobile Radio UHF Bands

ML145151 Data Sheet Continued on Page 23

Page 4 of 35

www.lansdale.com

Issue A

ML145152

Parallel-Input PLL

Frequency Synthesizer

Interfaces with Dual–Modulus Prescalers

Legacy Device: Motorola/Freescale MC145152

The ML145152 is programmed by sixteen parallel inputs

for the N and A counters and three input lines for the R

counter. The device features consist of a reference oscillator,

selectable–reference divider, two–output phase detector,

10–bit programmable divide–by–N counter, and 6–bit pro-

grammable ÷ A counter.

P DIP 28 = YP

PLASTIC DIP

CASE 710

28

1

SO 28W = -6P

SOG PACKAGE

CASE 751F

28

• Operating Temperature Range: T = – 40 to 85°C

A

• Low Power Consumption Through Use of CMOS

Technology

1

CROSS REFERENCE/ORDERING INFORMATION

PACKAGE

MOTOROLA

LANSDALE

• 3.0 to 9.0 V Supply Range

• On– or Off–Chip Reference Oscillator Operation

• Lock Detect Signal

P DIP 28

SO 28W

MC145152P2

MC145152DW2 ML145152-6P

ML145152YP

Note: Lansdale lead free (Pb) product, as it

becomes available, will be identified by a part

number prefix change from ML to MLE.

• Dual Modulus/Parallel Programming

• 8 User–Selectable ÷ R Values: 8, 64, 128, 256, 512,

1024, 1160, 2048

• ÷ N Range = 3 to 1023, ÷ A Range = 0 to 63

• Chip Complexity: 8000 FETs or 2000 Equivalent Gates

• See Application Note AN980

PIN ASSIGNMENT

f

1

2

28

27

LD

in

V

OSC

SS

in

V

3

4

5

6

7

8

9

26

25

24

23

22

21

20

19

18

17

OSC

A4

A3

A0

A2

A1

N9

N8

N7

N6

DD

out

RA0

RA1

RA2

φ

R

φ

V

MC

A5 10

N0 11

N1 12

N2 13

N3 14

16

15

N5

N4

Page 5 of 35

www.lansdale.com

Issue A

LANSDALE Semiconductor, Inc.

ML145152

ML145152 BLOCK DIAGRAM

RA2

RA1

RA0

12 x 8 ROM REFERENCE DECODER

12

OSC

out

LOCK

DETECT

LD

OSC

in

12–BIT

÷

R COUNTER

MC

φ

V

CONTROL

LOGIC

PHASE

DETECTOR

R

f

in

6–BIT

A5

÷

A COUNTER

10–BIT

N2

÷

N COUNTER

A3 A2

A0

N0

N4 N5

N7

N9

NOTE: N0 – N9, A0 – A5, and RA0 – RA2 have pull–up resistors that are not shown.

PIN DESCRIPTIONS

tors that ensure that inputs left open will remain at a logic 1.

INPUT PINS

OSC , OSC

in

out

Reference Oscillator Input/Output (Pins 27, 26)

f

in

Frequency Input (Pin 1)

These pins form an on–chip reference oscillator when con-

nected to terminals of an external parallel resonant crystal.

Frequency setting capacitors of appropriate value must be con-

Input to the positive edge triggered ÷ N and ÷ A counters.

f

is typically derived from a dual–modulus prescaler and is

in

nected from OSC to ground and OSC

to ground. OSC

in

out

in

AC coupled into the device. For larger amplitude signals (stan-

dard CMOS logic levels) DC coupling may be used.

may also serve as the input for an externally generated refer-

ence signal. This signal is typically AC coupled to OSC , but

in

RA0, RA1, RA2

Reference Address Inputs (Pins 4, 5, 6)

for larger amplitude signals (standard CMOS logic levels) DC

coupling may also be used. In the external reference mode, no

connection is required to OSC

OUTPUT PINS

φR,φV

.

These three inputs establish a code defining one of eight

possible divide values for the total reference divider. The total

reference divide values are as follows:

out

Phase Detector B Outputs (Pins 7, 8)

Total

Divide

Value

Reference Address Code

These phase detector outputs can be combined externally for

a loop–error signal.

If the frequency f is greater than f or if the phase of f is

leading, then error information is provided by φV pulsing low.

φR remains essentially high.

If the frequency f is less than f or if the phase of f is

RA2

RA1

RA0

V

R

V

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8

64

128

256

512

1024

1160

2048

V

R

V

lagging, then error information is provided by φR pulsing low.

φV remains essentially high.

If the frequency of f = f and both are in phase, then both

V

R

φV and φR remain high except for a small minimum time peri-

od when both pulse low in phase.

N0 – N9

N Counter Programming Inputs (Pins 11 – 20)

MC

Dual–Modulus Prescale Control Output (Pin 9)

The N inputs provide the data that is preset into the ÷ N

counter when it reaches the count of 0. N0 is the least signifi-

cant digit and N9 is the most significant. Pull–up resistors en-

sure that inputs left open remain at a logic 1 and require only a

SPST switch to alter data to the zero state.

Signal generated by the on–chip control logic circuitry for

controlling an external dual–modulus prescaler. The MC level

will be low at the beginning of a count cycle and will remain

low until the ÷ A counter has counted down from its pro-

grammed value. At this time, MC goes high and remains high

until the ÷ N counter has counted the rest of the way down

from its programmed value (N – A additional counts since

both ÷ N and ÷ A are counting down during the first portion of

the cycle). MC is then set back low, the counters preset to

A0 – A5

A Counter Programming Inputs(Pins 23, 21, 22, 24, 25, 10)

The A inputs define the number of clock cycles of f that

in

require a logic 0 on the MC output (see Dual–Modulus Pres-

caling section). The A inputs all have internal pull–up resis-

Page 6 of 35

www.lansdale.com

Issue A

LANSDALE Semiconductor, Inc.

ML145152

POWER SUPPLY

their respective programmed values, and the above sequence

repeated. This provides for a total programmable divide value

(NT)=N•P+A where P and P + 1 represent the dual–modulus

prescaler divide values respectively for high and low MC lev-

els, N the number programmed into the ÷ N counter, and A the

number programmed into the ÷ A counter.

VDD

Positive Power Supply (Pin 3)

The positive power supply potential. This pin may range from

+ 3 to + 9 V with respect to V

.

SS

V

SS

Negative Power Supply (Pin 2)

LD

Lock Detector Output (Pin 28)

The most negative supply potential. This pin is usually-

ground.

Essentially a high level when loop is locked (f , f of same

R V

phase and frequency). Pulses low when loop is out of lock.

TYPICAL APPLICATIONS

NO CONNECTS

“1”

150 – 175 MHz

5 kHz STEPS

LOCK DETECT SIGNAL

R2

10.24 MHz

NOTE 1

C

OSC

out

RA2

RA1

RA0

LD

R1

φ

–

+

R

OSC

in

VCO

φ

V

MC33171

NOTE 2

ML145152

R2

C

MC

V

+ V

DD

f

in

SS

N9

N0 A5

A0

ML12017

CHANNEL PROGRAMMING

÷

64/65 PRESCALER

NOTES:

1. Off–chip oscillator optional.

2. The φ and φ outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter

R

V

Design page for additional information. The φ and φ outputs swing rail–to–rail. Therefore, the user should be careful

R

V

not to exceed the common mode input range of the op amp used in the combiner/loop filter.

Figure 1. Synthesizer for Land Mobile Radio VHF Bands

Page 7 of 35

www.lansdale.com

Issue A

LANSDALE Semiconductor, Inc.

ML145152

RECEIVER 2ND L.O.

30.720 MHz

REF. OSC.

15.360 MHz

NO CONNECTS

(ON–CHIP OSC.

OPTIONAL)

RECEIVER FIRST L.O.

825.030 844.980 MHz

X2

“1”

LOCK DETECT SIGNAL

R2

→

C

(30 kHz STEPS)

OSC

out

RA2

RA1

RA0

LD

R1

φ

–

+

R

OSC

in

X4

NOTE 6

VCO

φ

V

ML145152

NOTE 5

NOTE 7

V

+ V

DD

R2

C

MC

SS

f

X4

TRANSMITTER

in

NOTE 6

MODULATION

N9

N0 A5

A0

ML12017

TRANSMITTER SIGNAL

825.030 844.980 MHz

(30 kHz STEPS)

÷

64/65 PRESCALER

CHANNEL PROGRAMMING

→

NOTE 6

NOTES:

1. Receiver 1st I.F. = 45 MHz, low side injection; Receiver 2nd I.F. = 11.7 MHz, low side injection.

2. Duplex operation with 45 MHz receiver/transmit separation.

3. f = 7.5 kHz; ÷ R = 2048.

R

total

4. N

= N 64 + A = 27501 to 28166; N = 429 to 440; A = 0 to 63.

5. ML145158 may be used where serial data entry is desired.

6. High frequency prescalers may be used for higher frequency VCO and f

implementations.

ref

7. The φ and φ outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter Design page for

R

V

additional information. The φ and φ outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common mode

R

V

input range of the op amp used in the combiner/loop filter.

Figure 2. 666–Channel, Computer–Controlled, Mobile Radiotelephone Synthesizer

for 800 MHz Cellular Radio Systems

ML145152 Data Sheet Continued on Page 23

Page 8 of 35

www.lansdale.com

Issue A

ML145155

Serial–Input PLL

Frequency Synthesizer

Interfaces with Single–Modulus Prescalers

Legacy Device: Motorola/Freescale MC145155-2

The ML145155 is programmed by a clocked, serial input,

16–bit data stream. The device features consist of a reference

oscillator, selectable–reference divider, digital–phase detector,

14–bit programmable divide–by–N counter, and the necessary

shift register and latch circuitry for accepting serial input

data.

P DIP 18 = VP

PLASTIC DIP

CASE 707

18

1

• Operating Temperature Range: T = – 40 to 85°C

• Low Power Consumption Through Use of CMOS

Technology

A

SOG 20W = -6P

SOG PACKAGE

CASE 751D

20

1

• 3.0 to 9.0 V Supply Range

• On– or Off–Chip Reference Oscillator Operation with

Buffered Output

• Compatible with the Serial Peripheral Interface (SPI) on

CMOS MCUs

CROSS REFERENCE/ORDERING INFORMATION

PACKAGE

MOTOROLA

LANSDALE

P DIP 18

MC145155P2

ML145155VP

SOG 20W

MC145155DW2 ML145155-6P

• Lock Detect Signal

Note: Lansdale lead free (Pb) product, as it

becomes available, will be identified by a part

number prefix change from ML to MLE.

• Two Open–Drain Switch Outputs

• 8 User–Selectable ÷ R Values: 16, 512, 1024, 2048,

3668, 4096, 6144, 8192

• Single Modulus/Serial Programming

• ÷ N Range = 3 to 16383

• “Linearized” Digital Phase Detector Enhances Transfer

Function Linearity

• Two Error Signal Options: Single–Ended (Three–State)

or Double–Ended

• Chip Complexity: 6504 FETs or 1626 Equivalent Gates

PIN ASSIGNMENTS

PLASTIC DIP

SOG PACKAGE

RA1

RA2

1

2

3

4

5

6

18

17

16

15

14

13

RA0

OSC

REF

RA1

RA2

1

2

20

19

RA0

OSC

in

φ

3

4

18

OSC

V

out

V

out

φ

17

REF

φ

R

out

R

out

V

5

6

16

15

NC

V

SW2

DD

out

DD

PD

SW2

SW1

ENB

DATA

CLK

PD

SW1

ENB

DATA

CLK

out

V

7

14

13

12

11

V

7

8

9

12

11

10

SS

NC

SS

LD

8

LD

9

f

in

f

10

in

NC = NO CONNECTION

Page 9 of 35

www.lansdale.com

Issue A

ML145155

LANSDALE Semiconductor, Inc.

ML145155 BLOCK DIAGRAM

RA2

14 x 8 ROM REFERENCE DECODER

RA1

RA0

LOCK

DETECT

14

OSC

REF

out

LD

OSC

14–BIT

÷

R COUNTER

in

f

PHASE

DETECTOR

A

R

PD

out

f

V

out

f

in

R COUNTER

14

PHASE

DETECTOR

B

φ

V

R

V

DD

SW2

SW1

ENB

LATCH

14

14–BIT SHIFT REGISTER

DATA

CLK

2–BIT SHIFT

REGISTER

PIN DESCRIPTIONS

signals SW1 and SW2. The entry format is as follows:

INPUT PINS

in

f

÷

N COUNTER BITS

Frequency Input (PDIP – Pin 9, SOG – Pin 10)

Input to the ÷ N portion of the synthesizer. f is typically

in

derived from loop VCO and is AC coupled into the device. For

larger amplitude signals (standard CMOS logic levels) DC

coupling may be used.

LAST DATA BIT IN (BIT NO. 16)

FIRST DATA BIT IN (BIT NO. 1)

RA0, RA1, RA2

Reference Address Inputs (PDIP – Pins 18, 1, 2; SOG –

Pins 20, 1, 2)

These three inputs establish a code defining one of eight

possible divide values for the total reference divider, as defined

by the table below:

ENB

Latch Enable Input (PDIP – Pin 12, SOG – Pin 13)

When high (1), ENB transfers the contents of the shift reg-

ister into the latches, and to the programmable counter inputs,

and the switch outputs SW1 and SW2. When low (0), ENB

inhibits the above action and thus allows changes to be made

in the shift register data without affecting the counter program-

ming and switch outputs. An on–chip pull–up establishes a

continuously high level for ENB when no external signal is

applied. ENB is normally low and is pulsed high to transfer

data to the latches.

Total

Divide

Value

Reference Address Code

RA2

RA1

RA0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

16

512

1024

2048

3668

4096

6144

8192

OSC , OSC

in

out

Reference Oscillator Input/Output (PDIP – Pins 17, 16;

SOG – Pins 19, 18)

These pins form an on–chip reference oscillator when con-

nected to terminals of an external parallel resonant crystal.

Frequency setting capacitors of appropriate value must be con-

CLK, DATA

Shift Register Clock, Serial Data Inputs

(PDIP – Pins 10, 11; SOG – Pins 11, 12)

Each low–to–high transition clocks one bit into the on–chip

16–bit shift register. The Data input provides programming

information for the 14–bit ÷ N counter and the two switch

nected from OSC to ground and OSC

to ground. OSC

in

out

in

may also serve as the input for an externally–generated refer-

ence signal. This signal is typically ac coupled to OSC , but

in

for larger amplitude signals (standard CMOS logic levels) DC

coupling may also be used. In the external reference mode, no

connection is required to OSC

.

out

Page 10 of 35

www.lansdale.com

Issue A

LANSDALE Semiconductor, Inc.

ML145155

OUTPUT PINS

phase and frequency). LD pulses low when loop is out of lock.

PD

out

Phase Detector A Output (PDIP, SOG – Pin 6)

Three–state output of phase detector for use as loop error

signal. Double–ended outputs are also available for this pur-

pose (see φV and φR).

SW1, SW2

Band Switch Outputs (PDIP – Pins 13, 14; SOG – Pins 14, 15)

SW1 and SW2 provide latched open–drain outputs corre-

sponding to data bits numbers one and two. These outputs can

be tied through external resistors to voltages as high as 15 V,

Frequency f > f or f Leading: Negative Pulses

V

R

V

Frequency f < f or f Lagging: Positive Pulses

independent of the V

supply voltage. These are typically

R

DD

Frequency f = f and Phase Coincidence: High–Imped-

used for band switch functions. A logic 1 causes the output to

assume a high–impedance state, while a logic 0 causes the out-

put to be low.

V

R

ance State

φR, φV

Phase Detector B Outputs (PDIP, SOG – Pins 4, 3)

REF

out

These phase detector outputs can be combined externally for

a loop–error signal. A single–ended output is also available for

Buffered Reference Oscillator Output (PDIP, SOG – Pin 15)

Buffered output of on–chip reference oscillator or externally

provided reference–input signal.

this purpose (see PD ).

out

If frequency f is greater than f or if the phase of f is

V

R

V

leading, then error information is provided by f pulsing low.

POWER SUPPLY

V

f remains essentially high.

R

If the frequency f is less than f or if the phase of f is

VDD

V

R

V

lagging, then error information is provided by f pulsing low.

Positive Power Supply (PDIP, SOG – Pin 5)

The positive power supply potential. This pin may range

R

f

remains essentially high.

V

If the frequency of f = f and both are in phase, then both

from + 3 to + 9 V with respect to V

.

V

R

SS

f

and f remain high except for a small minimum time peri-

V

R

od when both pulse low in phase.

VSS

Negative Power Supply (PDIP, SOG – Pin 7)

The most negative supply potential. This pin is usually

ground.

LD

Lock Detector Output (PDIP – Pin 8, SOG – Pin 9)

Essentially a high level when loop is locked (f , f of same

R V

TYPICAL APPLICATIONS

4.0 MHz

UHF/VHF

TUNER OR

CATV

φ

FRONT END

–

+

R

f

in

MC120xx

PRESCALER

ML145155

φ

V

1/2 MC1458*

DATA

CLK

ENB

CMOS

MPU/MCU

3

MC14489

KEYBOARD

LED DISPLAY

* The φ and φ outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop – Low–Pass Filter Design page

R

V

foradditionalinformation.TheφRandφVoutputsswingrail–to–rail.Therefore,theusershouldbecarefulnottoexceedthecommon

mode input range of the op amp used in the combiner/loop filter.

Figure 1. Microprocessor–Controlled TV/CATV Tuning System with Serial Interface

Page 11 of 35

www.lansdale.com

Issue A

ML145155

LANSDALE Semiconductor, Inc.

ML145155

2.56 MHz

φ

TO

AM/FM

OSCILLATORS

–

+

f

R

in

ML12019

÷20 PRESCALER

FM

OSC

ML145155

CLK

φ

V

1/2 MC1458*

AM

OSC

DATA

ENB

CMOS

MPU/MCU

KEYBOARD

TO DISPLAY

* The φ and φ outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop – Low–Pass Filter Design page

R

V

foradditionalinformation.Theφ andφ outputsswingrail–to–rail. Therefore, theusershouldbecarefulnottoexceedthecommon

R

V

mode input range of the op amp used in the combiner/loop filter.

Figure 2. AM/FM Radio Synthesizer

Page 12 of 35

www.lansdale.com

Issue A

ML145156

Serial–Input PLL

Frequency Synthesizer

Interfaces with Dual–Modulus Prescalers

Legacy Device: Motorola/Freescale MC145156-2

The ML145156 is programmed by a clocked, serial input,

19–bit data stream. The device features consist of a reference

oscillator, selectable–reference divider, digital–phase detector,

10–bit programmable divide–by–N counter, 7–bit program-

mable divide–by–A counter, and the necessary shift register

and latch circuitry for accepting serial input data.

P DIP 20 = RP

PLASTIC DIP

CASE 738

20

1

SOG 20W = -6P

SOG PACKAGE

CASE 751D

• Operating Temperature Range: T = – 40 to 85°C

A

• Low Power Consumption Through Use of

CMOS Technology

20

1

• 3.0 to 9.0 V Supply Range

CROSS REFERENCE/ORDERING INFORMATION

PACKAGE

MOTOROLA

LANSDALE

• On– or Off–Chip Reference Oscillator Operation with

Buffered Output

• Compatible with the Serial Peripheral Interface (SPI) on

CMOS MCUs

P DIP 20

SOG 20W

MC145156P2

MC145156DW2 ML145156-6P

ML145156RP

Note: Lansdale lead free (Pb) product, as it

becomes available, will be identified by a part

number prefix change from ML to MLE.

• Lock Detect Signal

• Two Open–Drain Switch Outputs

• Dual Modulus/Serial Programming

• 8 User–Selectable ÷ R Values: 8, 64, 128, 256, 640,

1000, 1024, 2048

• ÷ N Range = 3 to 1023, ÷A Range = 0 to 127

• “Linearized” Digital Phase Detector Enhances Transfer

Function Linearity

• Two Error Signal Options: Single–Ended (Three–State)

or Double–Ended

• Chip Complexity: 6504 FETs or 1626 Equivalent Gates

PIN ASSIGNMENT

RA1

RA2

1

2

20

19

RA0

OSC

in

φ

3

4

18

V

out

φ

17

REF

R

V

5

6

16

15

TEST

SW2

DD

PD

V

out

SS

7

14

13

12

11

SW1

ENB

DATA

CLK

MC

LD

8

9

f

10

in

Page 13 of 35

www.lansdale.com

Issue A

ML145156

LANSDALE Semiconductor, Inc.

ML145156 BLOCK DIAGRAM

RA2

RA1

RA0

12 x 8 ROM REFERENCE DECODER

12

LOCK

DETECT

12–BIT

÷ R COUNTER

OSC

in

LD

OSC

REF

out

f

PHASE

DETECTOR

A

CONTROL LOGIC

R

out

PD

out

f

V

MC

PHASE

DETECTOR

B

7–BIT

÷

A COUNTER

10–BIT

÷

N COUNTER

10

f

φ

in

V

φ

R

7

V

SW2

SW1

DD

ENB

LATCH

÷

A COUNTER LATCH

7

÷

N COUNTER LATCH

10

DATA

CLK

2–BIT SHIFT

REGISTER

7–BIT SHIFT REGISTER

10–BIT SHIFT REGISTER

A COUNTER BITS

N COUNTER BITS

PIN DESCRIPTIONS

INPUT PINS

f

in

Frequency Input (Pin 10)

Input to the positive edge triggered ÷ N and ÷ A counters.

is typically derived from a dual–modulus prescaler and is

AC coupled into the device. For larger amplitude signals (stan-

dard CMOS logic levels), DC coupling may be used.

LAST DATA BIT IN (BIT NO. 19)

FIRST DATA BIT IN (BIT NO. 1)

f

in

ENB

Latch Enable Input (Pin 13)

When high (1), ENB transfers the contents of the shift reg-

ister into the latches, and to the programmable counter inputs,

and the switch outputs SW1 and SW2. When low (0), ENB

inhibits the above action and thus allows changes to be made

in the shift register data without affecting the counter program-

ming and switch outputs. An on–chip pull–up establishes a

continuously high level for ENB when no external signal is

applied. ENB is normally low and is pulsed high to transfer

data to the latches.

RA0, RA1, RA2

Reference Address Inputs (Pins 20, 1, 2)

These three inputs establish a code defining one of eight

possible divide values for the total reference divider, as defined

by the table below:

Total

Divide

Value

Reference Address Code

RA2

RA1

RA0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8

64

OSC , OSC

in

out

Reference Oscillator Input/Output (Pins 19, 18)

128

256

640

1000

1024

2048

These pins form an on–chip reference oscillator when con-

nected to terminals of an external parallel resonant crystal.

Frequency setting capacitors of appropriate value must be con-

nected from OSC to ground and OSC

to ground. OSC

in

out

in

may also serve as the input for an externally–generated refer-

ence signal. This signal is typically AC coupled to OSC , but

in

for larger amplitude signals (standard CMOS logic levels) DC

coupling may also be used. In the external reference mode, no

CLK, DATA

Shift Register Clock, Serial Data Inputs (Pins 11, 12)

Each low–to–high transition clocks one bit into the on–chip

19–bit shift register. The data input provides programming in-

formation for the 10–bit ÷ N counter, the 7–bit ÷ A counter,

and the two switch signals SW1 and SW2. The entry format is

as follows:

connection is required to OSC

.

out

TEST

Factory Test Input (Pin 16)

Used in manufacturing. Must be left open or tied to V

.

SS

Page 14 of 35

www.lansdale.com

Issue A

LANSDALE Semiconductor, Inc.

ML145156

OUTPUT PINS

respective programmed values, and the above sequence repeat-

ed. This provides for a total programmable divide value (N ) =

T

PDout

N • P + A where P and P + 1 represent the dual–modulus

prescaler divide values respectively for high and low MC lev-

els, N the number programmed into the ÷ N counter, and A the

number programmed into the ÷ A counter.

Phase Detector A Output (Pin 6)

Three–state output of phase detector for use as loop–error

signal. Double–ended outputs are also available for this pur-

pose (see φ and φ ).

V

R

LD

Frequency f > f or f Leading: Negative Pulses

V

R

V

Lock Detector Output (Pin 9)

Frequency f < f or f Lagging: Positive Pulses

V

R

Frequency f = f and Phase Coincidence: High–Imped-

Essentially a high level when loop is locked (f , f of same

R V

ance State

phase and frequency). LD pulses low when loop is out of lock.

φR, φV

SW1, SW2

Band Switch Outputs (Pins 14, 15)

Phase Detector B Outputs (Pins 4, 3)

These phase detector outputs can be combined externally for

a loop–error signal. A single–ended output is also available for

SW1 and SW2 provide latched open–drain outputs corre-

sponding to data bits numbers one and two. These outputs can

be tied through external resistors to voltages as high as 15 V,

this purpose (see PD ).

out

If frequency f is greater than f or if the phase of f is

independent of the V

supply voltage. These are typically

V

R

V

DD

leading, then error information is provided by φ pulsing low.

used for band switch functions. A logic 1 causes the output to

assume a high–impedance state, while a logic 0 causes the out-

put to be low.

V

φ remains essentially high.

R

If the frequency f is less than f or if the phase of f is

V

R

V

lagging, then error information is provided by φ pulsing low.

R

φ

remains essentially high.

REF

out

V

If the frequency of f = f and both are in phase, then both

Buffered Reference Oscillator Output (Pin 17)

V

R

φ

and φ remain high except for a small minimum time

V

R

Buffered output of on–chip reference oscillator or externally

provided reference–input signal.

period when both pulse low in phase.

MC

POWER SUPPLY

Dual–Modulus Prescale Control Output (Pin 8)

Signal generated by the on–chip control logic circuitry for-

controlling an external dual–modulus prescaler. The MC level-

will be low at the beginning of a count cycle and will remain-

low until the ÷ A counter has counted down from its pro-

grammed value. At this time, MC goes high and remains high-

until the ÷ N counter has counted the rest of the way down-

from its programmed value (N – A additional counts since

both ÷ N and ÷ A are counting down during the first portion of

the cycle). MC is then set back low, the counters preset to their

V

DD

Positive Power Supply (Pin 5)

The positive power supply potential. This pin may range

from + 3 to + 9 V with respect to V

.

SS

V

SS

Negative Power Supply (Pin 7)

The most negative supply potential. This pin is usually-

ground.

Page 15 of 35

www.lansdale.com

Issue A

ML145156

LANSDALE Semiconductor, Inc.

ML145156

TYPICAL APPLICATIONS

+ 12 V

LOCK DETECT SIGNAL

3.2 MHz

NOTES 1

AND 2

FM B +

+ 12 V

AM B +

+ V

OSC

RA2 RA1 RA0 LD SW1 SW2

in

out

OPTIONAL

LOOP

ERROR SIGNAL

PD

out

V

DD

–

+

φ

ML145156

R

SS

VCO

REF

φ

V

out

1/2 MC1458

NOTE 3

f

CLK

DATA

ENB

in

MC

KEY–

BOARD

CMOS MPU/MCU

ML12019

20/21 DUAL MODULUS PRESCALER

÷

TO DISPLAY DRIVER (e.g., MC14489)

NOTES:

1. For AM: channel spacing = 5 kHz,

2. For FM: channel spacing = 25 kHz,

÷

R =

÷

640 (code 100).

÷ 128 (code 010).

÷

R =

3. Theφ andφ outputsarefedtoanexternalcombiner/loopfilter.SeethePhase–LockedLoop–Low–PassFilterDesignpage

R

V

for additional information. The φ and φ outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the

R

V

common mode input range of the op amp used in the combiner/loop filter.

Figure 1. AM/FM Radio Broadcast Synthesizer

3.2 MHz (NOTE 3)

VCO RANGE

NAV = 01

COM = 10

NAV: 97.300 – 107.250 MHz

COM–T: 118.000 – 135.975 MHz

COM–R: 139.400 – 157.375 MHz

LOCK DETECT SIGNAL

+ V

OSC

out

RA2 RA1 RA0 LD SW1 SW2

in

PD

out

V

DD

–

+

ML145156

φ

R

SS

VCO

REF

φ

V

out

MC33171

NOTE 5

f

CLK

DATA

ENB

in

MC

CMOS MPU/MCU

R/T

ML12016 (NOTES 2 AND 4)

40/41 DUAL MODULUS PRESCALER

÷

CHANNEL

TO DISPLAY DRIVER

SELECTION

(e.g., MC14489)

NOTES:

1. For NAV: f = 50 kHz,

÷

R = 64 using 10.7 MHz lowside injection, N

= 1946 – 2145.

total

R

For COM–T: f = 25 kHz,

÷

R = 128, N

= 4720 – 5439.

R

total

R = 128, using 21.4 MHz highside injection, N

For COM–R: f = 25 kHz,

= 5576 – 6295.

R

total

32/33 dual modulus approach is provided by substituting an ML12015 for the ML12016.The devices are pin equivalent.

3. A 6.4 MHz oscillator crystal can be used by selecting R = 128 (code 010) for NAV and R = 256 (code 011) for COM.

4. ML12013 + MC10131 combination may also be used to form the 40/41 prescale.r

5. The φ and φ outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop – Low–Pass Filter Design

2. A

÷

R

V

page for additional information.The φ and φ outputs swing rail–to–rail.Therefore, the user should be careful not to exceed

R

V

the common mode input range of the op amp used in the combiner/loop filter.

Figure 2. Avionics Navigation or Communication Synthesizer

ML145156 Data Sheet Continued on Page 23

Page 16 of 35

www.lansdale.com

Issue A

ML145157

Serial–Input PLL

Frequency Synthesizer

Interfaces with Single–Modulus Prescalers

Legacy Device: Motorola/Freescale MC145157-2

The ML145157 has a fully programmable 14–bit reference

counter, as well as a fully programmable ÷ N counter. The

counters are programmed serially through a common data

input and latched into the appropriate counter latch, accord-

ing to the last data bit (control bit) entered.

P DIP 16 = EP

PLASTIC DIP

CASE 648

16

1

• Operating Temperature Range: T = – 40 to 85°C

A

• Low Power Consumption Through Use of CMOS

Technology

SOG 16 = -5P

SOG PACKAGE

CASE 751G

16

1

• 3.0 to 9.0 V Supply Range

• Fully Programmable Reference and ÷ N Counters

• ÷ R Range = 3 to 16383

• ÷ N Range = 3 to 16383

CROSS REFERENCE/ORDERING INFORMATION

PACKAGE

MOTOROLA

LANSDALE

P DIP 16

MC145157P2

ML145157EP

SOG 20W

MC145157DW2 ML145157-5P

• f and f Outputs

V

R

• Lock Detect Signal

Note: Lansdale lead free (Pb) product, as it

becomes available, will be identified by a part

number prefix change from ML to MLE.

• Compatible with the Serial Peripheral Interface

(SPI) on CMOS MCUs

• “Linearized” Digital Phase Detector

• Single–Ended (Three–State) or Double–Ended Phase

Detector Outputs

PIN ASSIGNMENT

• Chip Complexity: 6504 FETs or 1626 Equivalent Gates

OSC

in

1

2

16

15

φ

R

OSC

out

V

f

3

4

14

13

REF

V

out

V

f

R

DD

out

PD

5

6

12

11

S/R

out

V

ENB

DATA

CLK

SS

LD

7

10

9

f

8

in

Page 17 of 35

www.lansdale.com

Issue A

ML145157

LANSDALE Semiconductor, Inc.

ML145157 BLOCK DIAGRAM

14–BIT SHIFT REGISTER

14

f

R

ENB

REFERENCE COUNTER LATCH

14

LOCK

DETECT

LD

PD

OSC

14–BIT

÷

R COUNTER

in

out

PHASE

DETECTOR

A

OSC

REF

out

PHASE

DETECTOR

B

φ

V

14–BIT

÷

N COUNTER

14

f

in

R

÷

N COUNTER LATCH

14

f

V

1–BIT

CONTROL

S/R

DATA

CLK

S/R

out

14–BIT SHIFT REGISTER

PIN DESCRIPTIONS

the control bit is at a logic low. A logic low on this pin allows

the user to change the data in the shift registers without affect-

ing the counters. ENB is normally low and is pulsed high to

transfer data to the latches.

INPUT PINS

fin

Frequency Input (Pin 8)

OSCin, OSCout

Reference Oscillator Input/Output (Pins 1, 2)

Input frequency from VCO output. A rising edge signal on

this input decrements the ÷ N counter. This input has an invert-

er biased in the linear region to allow use with AC coupled sig-

nals as low as 500 mV p–p. For larger amplitude signals (stan-

dard CMOS logic levels), DC coupling may be used.

These pins form an on–chip reference oscillator when con-

nected to terminals of an external parallel resonant crystal.

Frequency setting capacitors of appropriate value must be con-

nected from OSC to ground and OSC

to ground. OSC

in

out

in

may also serve as the input for an externally–generated refer-

CLK, DATA

Shift Clock, Serial Data Inputs (Pins 9, 10)

ence signal. This signal is typically AC coupled to OSC , but

in

for larger amplitude signals (standard CMOS logic levels) DC

coupling may also be used. In the external reference mode, no

Each low–to–high transition of the clock shifts one bit of

data into the on–chip shift registers. The last data bit entered

determines which counter storage latch is activated; a logic

1selects the reference counter latch and a logic 0 selects the

÷ N counter latch. The entry format is as follows:

connection is required to OSC

.

out

OUTPUT PINS

PD

out

Single–Ended Phase Detector A Output (Pin 5)

This single–ended (three–state) phase detector output pro-

duces a loop–error signal that is used with a loop filter to con-

trol a VCO.

Frequency fV > fR or fV Leading: Negative Pulses

Frequency fV < fR or fV Lagging: Positive Pulses

Frequency fV = fR and Phase Coincidence:

High–Impedance State

FIRST DATA BIT INTO SHIFT REGISTER

ENB

Latch Enable Input (Pin 11)

φR, φV

Double–Ended Phase Detector B Outputs (Pins 16, 15)

These outputs can be combined externally for a loop–error

signal. A single–ended output is also available for this purpose

A logic high on this pin latches the data from the shift regis-

ter into the reference divider or ÷ N latches depending on the

control bit. The reference divider latches are activated if the

control bit is at a logic high and the ÷ N latches are activated if

(see PD ).

out

Page 18 of 35

www.lansdale.com

Issue A

LANSDALE Semiconductor, Inc.

ML145157

REF

If frequency f is greater than f or if the phase of f is

out

V

R

V

Buffered Reference Oscillator Output (Pin 14)

leading, then error information is provided by φ pulsing low.

V

This output can be used as a second local oscillator, refer-

ence oscillator to another frequency synthesizer, or as the sys-

tem clock to a microprocessor controller.

φ remains essentially high.

R

If the frequency f is less than f or if the phase of fV is

V

R

lagging, then error information is provided by φ pulsing low.

R

φ

remains essentially high.

V

S/R

out

If the frequency of f = f and both are in phase, then both

and φ remain high except for a small minimum time peri-

V

R

Shift Register Output (Pin 12)

φ

V

R

od when both pulse low in phase.

This output can be connected to an external shift register to

provide band switching, control information, and counter pro-

gramming code checking.

f , f

R V

RCounter Output, N Counter Output (Pins 13, 3)

Buffered, divided reference and f frequency outputs. The

in

POWER SUPPLY

f and f outputs are connected internally to the ÷ R and ÷ N

R

V

counter outputs respectively, allowing the counters to be used

independently, as well as monitoring the phase detector inputs.

V

DD

Positive Power Supply (Pin 4)

The positive power supply potential. This pin may range

LD

from +3 to +9 V with respect to V

.

SS

Lock Detector Output (Pin 7)

This output is essentially at a high level when the loop is

V

SS

Negative Power Supply (Pin 6)

locked (f , f of same phase and frequency), and pulses low

R V

when loop is out of lock.

The most negative supply potential. This pin is usually

ground.

Page 19 of 35

www.lansdale.com

Issue A

ML145158

Serial–Input PLL

Frequency Synthesizer

Interfaces with Dual–Modulus Prescalers

Legacy Device: Motorola/Freescale MC145158-2

The ML145158 has a fully programmable 14–bit reference

counter, as well as fully programmable ÷ N and ÷ A counters.

The counters are programmed serially through a common

data input and latched into the appropriate counter latch,

according to the last data bit (control bit) entered.

P DIP 16 = EP

PLASTIC DIP

CASE 648

16

1

• Operating Temperature Range: T

A =

• Low Power Consumption Through Use of CMOS

Technology

– 40 to 85°C

SOG 16 = -5P

SOG PACKAGE

CASE 751G

16

1

• 3.0 to 9.0 V Supply Range

• Fully Programmable Reference and ÷ N Counters

• ÷ R Range = 3 to 16383

• ÷ N Range = 3 to 1023

CROSS REFERENCE/ORDERING INFORMATION

PACKAGE

MOTOROLA

LANSDALE

P DIP 16

SOG 16

MC145158P2

MC145158DW2 ML145158-5P

ML145158EP

• Dual Modulus Capability; ÷ A Range = 0 to 127

• f and f Outputs

Note: Lansdale lead free (Pb) product, as it

becomes available, will be identified by a part

number prefix change from ML to MLE.

V

R

• Lock Detect Signal

• Compatible with the Serial Peripheral Interface (SPI) on

CMOS MCUs

• “Linearized” Digital Phase Detector

• Single–Ended (Three–State) or Double–Ended Phase

Detector Outputs

• Chip Complexity: 6504 FETs or 1626

Equivalent Gates

PIN ASSIGNMENT

OSC

in

1

2

16

15

φ

R

OSC

out

V

f

3

4

14

13

REF

out

V

f

R

DD

out

PD

5

6

12

11

MC

V

ENB

SS

LD

7

10

9

DATA

CLK

f

8

in

Page 20 of 35

www.lansdale.com

Issue A

LANSDALE Semiconductor, Inc.

ML145158

ML145158 BLOCK DIAGRAM

14–BIT SHIFT REGISTER

14

f

R

ENB

REFERENCE COUNTER LATCH

14

LOCK

DETECT

LD

PD

OSC

in

14–BIT

÷ RCOUNTER

PHASE

DETECTOR

A

OSC

out

CONTROL LOGIC

REF

7–BIT

COUNTER

÷

A

10–BIT ÷ N

PHASE

DETECTOR

B

φ

V

f

in

COUNTER

R

7

10

÷

A COUNTER

LATCH

÷

N COUNTER

LATCH

f

V

7

10

1–BIT

CONTROL

S/R

DATA

CLK

MC

7–BIT S/R

10–BIT S/R

÷

A

÷

N

PIN DESCRIPTIONS

INPUT PINS

Frequency Input (Pin 8)

f

in

Input frequency from VCO output. A rising edge signal on

this input decrements the ÷ A and ÷ N counters. This input has

an inverter biased in the linear region to allow use with AC

coupled signals as low as 500 mV p–p. For larger amplitude

signals (standard CMOS logic levels), DC coupling may be

used.

FIRST DATA BIT INTO SHIFT REGISTER

ENB

Latch Enable Input (Pin 11)

A logic high on this pin latches the data from the shift regis-

ter into the reference divider or ÷ N, ÷ A latches depending on

the control bit. The reference divider latches are activated if the

control bit is at a logic high and the ÷ N, ÷ A latches are acti-

vated if the control bit is at a logic low. A logic low on this pin

allows the user to change the data in the shift registers without

affecting the counters. ENB is normally low and is pulsed high

to transfer data to the latches.

CLK, DATA

Shift Clock, Serial Data Inputs (Pins 9, 10)

Each low–to–high transition of the CLK shifts one bit of

data into the on–chip shift registers. The last data bit entered

determines which counter storage latch is activated; a logic 1

selects the reference counter latch and a logic 0 selects the

÷ A, ÷ N counter latch. The data entry format is as follows:

OSC , OSC

in

out

Reference Oscillator Input/Output (Pins 1, 2)

These pins form an on–chip reference oscillator when con-

nected to terminals of an external parallel resonant crystal.

Frequency setting capacitors of appropriate value must be con-

÷

R

nected from OSC to ground and OSC

to ground. OSC

in

out

in

may also serve as the input for an externally–generated refer-

ence signal. This signal is typically AC coupled to OSC , but

in

for larger amplitude signals (standard CMOS logic levels) DC

coupling may also be used. In the external reference mode, no

FIRST DATA BIT INTO SHIFT REGISTER

connection is required to OSC

.

out

Page 21 of 35

www.lansdale.com

Issue A

ML145158

LANSDALE Semiconductor, Inc.

ML145158

OUTPUT PINS

lus prescaler divide values respectively for high and low modu-

lus control levels, N the number programmed into the ÷ N

counter, and A the number programmed into the ÷ A counter.

Note that when a prescaler is needed, the dual–modulus ver-

sion offers a distinct advantage. The dual–modulus prescaler

allows a higher reference frequency at the phase detector input,

increasing system performance capability, and simplifying the

loop filter design.

PD

out

Phase Detector A Output (Pin 5)

This single–ended (three–state) phase detector output pro-

duces a loop–error signal that is used with a loop filter to con-

trol a VCO.

Frequency f > f or f Leading: Negative Pulses

V

R

V

Frequency f < f or f Lagging: Positive Pulses

V

R

f , f

R V

Frequency f = f and Phase Coincidence:

V

R

R Counter Output, N Counter Output (Pins 13, 3)

High–Impedance State

Buffered, divided reference and fin frequency outputs. The

φR, φV

f and f outputs are connected internally to the ÷ R and ÷ N

R

V

Phase Detector B Outputs (Pins 16, 15)

counter outputs respectively, allowing the counters to be used

independently, as well as monitoring the phase detector inputs.

Double–ended phase detector outputs. These outputs can be

combined externally for a loop–error signal. A single–ended

LD

output is also available for this purpose (see PD ).

out

Lock Detector Output (Pin 7)

If frequency f is greater than f or if the phase of f is

V

R

V

leading, then error information is provided by φ pulsing low.

This output is essentially at a high level when the loop is

V

φ remains essentially high.

locked (f , f of same phase and frequency), and pulses low

R

R V

If the frequency f is less than f or if the phase of f is

when loop is out of lock.

V

R

V

lagging, then error information is provided by φ pulsing low.

R

φ

remains essentially high.

REF

out

V

If the frequency of f = f and both are in phase, then both

Buffered Reference Oscillator Output (Pin 14)

V

R

φ

and φ remain high except for a small minimum time peri-

V

R

This output can be used as a second local oscillator, refer-

ence oscillator to another frequency synthesizer, or as the sys-

tem clock to a microprocessor controller.

od when both pulse low in phase.

MC

Dual–Modulus Prescaler Control Output (Pin 12)

POWER SUPPLY

This output generates a signal by the on–chip control logic

circuitry for controlling an external dual–modulus prescaler.

The MC level is low at the beginning of a count cycle and

remains low until the ÷ A counter has counted down from its

programmed value. At this time, MC goes high and remains

high until the ÷ N counter has counted the rest of the way

down from its programmed value (N – A additional counts

since both ÷ N and ÷ A are counting down during the first por-

tion of the cycle). MC is then set back low, the counters preset

to their respective programmed values, and the above sequence

repeated. This provides for a total programmable divide value

V

DD

Positive Power Supply (Pin 4)

The positive power supply potential. This pin may range

from + 3 to + 9 V with respect to VSS.

V

SS

Negative Power Supply (Pin 6)

The most negative supply potential. This pin is usually-

ground.

(N ) = N • P + A where P and P + 1 represent the dual–modu-

T

Page 22 of 35

www.lansdale.com

#

LANSDALE Semiconductor, Inc.

ML1451xx

ML14515X FAMILY CHARACTERISTICS AND DESCRIPTIONS - CONTINUED

MAXIMUM RATINGS* (Voltages Referenced to V

)

SS

These devices contain protection circuitry to

Symbol

Parameter

DC Supply Voltage

Value

Unit

V

protect against damage due to high static

voltages or electric fields. However, precau-

tionsmust betakentoavoidapplicationsofany

voltage higher than maximum rated voltages

to these high–impedance circuits. For proper

V

DD

– 0.5 to + 10.0

V , V

in out

Input or Output Voltage (DC or Transient)

except SW1, SW2

– 0.5 to V

+ 0.5

DD

V

operation, V and V

to the range V

SS

except for SW1 and SW2.

SW1 and SW2 can be tied through external

resistors to voltages as high as 15 V, indepen-

dent of the supply voltage.

Unused inputs must always be tied to an

appropriatelogicvoltagelevel(e.g.,eitherV

should be constrained

V

Output Voltage (DC or Transient),

– 0.5 to + 15

10

V

in

out

(V or V

in out

)

V

DD

SW1, SW2 (R

= 4.7 kΩ)

pull–up

I

, I

in out

Input or Output Current (DC or Transient),

per Pin

mA

I

, I

Supply Current, V

or V

Pins

SS

30

500

mA

mW

C

DD SS

DD

P

Power Dissipation, per Package†

Storage Temperature

D

SS

orV ),exceptforinputswithpull–updevices.

DD

Unused outputs must be left open.

T

stg

– 65 to + 150

260

T

Lead Temperature, 1 mm from Case for

10 seconds

C

L

* Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the limits in the Electrical Characteristics

tables or Pin Descriptions section.

†Power Dissipation Temperature Derating:

Plastic DIP: – 12 mW/ C from 65 to 85 C

SOG Package: – 7 mW/ C from 65 to 85 C

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

)

SS

– 40 C

25 C

Max

85 C

Max

V

DD

V

Symbol

Parameter

Test Condition

Unit

Min

Max

Min

V

DD

Power Supply Voltage

Range

–

3

9

3

9

3

9

V

I

ss

Dynamic Supply Current

f

= OSC = 10 MHz,

3

5

9

–

3.5

10

30

–

3

7.5

24

–

3

7.5

24

mA

in

1 V p–p AC coupled sine

wave

R = 128, A = 32, N = 128

I

Quiescent Supply Current

(not including pull–up

current component)

V

= V

DD

= 0 µA

or V

SS

3

5

9

–

800

1200

1600

–

800

1200

1600

–

1600

2400

3200

µA

SS

in

I

out

V

Input Voltage – f , OSC

in

Input AC coupled sine wave

–

500

–

500

–

500

–

mV p–p

V

in

V

IL

LowLevel Input V oltage

– f , OSC

V

2.1 V

3.5 V

6.3 V square wave

Input DC

coupled

3

5

9

–

0

–

0

–

0

out

V

out

in

V

out

V

High–Level Input Voltage

– f , OSC

V

0.9 V

1.5 V

2.7 V square wave

Input DC

coupled

3

5

9

3.0

5.0

9.0

–

3.0

5.0

9.0

–

3.0

5.0

9.0

–

V

IH

out

V

out

in

V

out

V

Low–Level Input Voltage

– except f , OSC

3

5

9

–

0.9

1.5

2.7

–

0.9

1.5

2.7

–

0.9

1.5

2.7

IL

in

V

IH

High–Level Input Voltage

– except f , OSC

3

5

9

2.1

3.5

6.3

–

2.1

3.5

6.3

–

2.1

3.5

6.3

–

in

I

Input Current (f , OSC

in

)

in

V

= V

or V

SS

9

2

–

50

2

–

25

2

–

22

µA

in

DD

SS

I

IL

Input Leakage Current

(Data, CLK, ENB –

without pull–ups)

– 0.3

– 0.1

– 1.0

in

I

IH

Input Leakage Current (all

inputs except f , OSC

V

in

= V

9

–

0.3

–

0.1

–

1.0

µA

DD

)

in

(continued)

Page 23 of 35

www.lansdale.com

Issue A

ML1451xx

LANSDALE Semiconductor, Inc.

DC ELECTRICAL CHARACTERISTICS (continued)

– 40 C

25 C

85 C

V

DD

V

Symbol

Parameter

Test Condition

Unit

Min

Max

Min

Max

Min

Max

I

IL

Pull–up Current (all inputs

with pull–ups)

V

in

= V

9

– 20

– 400

– 20

– 200

– 20

– 170

µA

SS

C

Input Capacitance

Low–Level Output

–

10

–

10

–

10

pF

V

in

V

OL

I

V

0 µA

3

5

9

–

0.9

1.5

2.7

–

0.9

1.5

2.7

–

0.9

1.5

2.7

out

in

Voltage – OSC

= V

out

DD

V

OH

High–Level Output

Voltage – OSC

I

V

0 µA

3

5

9

2.1

3.5

6.3

–

2.1

3.5

6.3

–

2.1

3.5

6.3

–

V

out

in

= V

out

SS

V

OL

Low–Level Output

Voltage – Other Outputs

I

0 µA

3

5

9

–

0.05

–

0.05

–

0.05

V

out

V

OH

High–Level Output

Voltage – Other Outputs

I

0 µA

3

5

9

2.95

4.95

8.95

–

2.95

4.95

8.95

–

2.95

4.95

8.95

–

V

out

V

Drain–to–Source

Breakdown Voltage –

SW1, SW2

R

= 4.7 kΩ

pull–up

–

15

–

15

–

15

–

V

(BR)DSS

I

Low–Level Sinking

Current – MC

V

= 0.3 V

= 0.4 V

= 0.5 V

3

5

9

1.30

1.90

3.80

–

1.10

1.70

3.30

–

0.66

1.08

2.10

–

mA

OL

out

V

out

V

out

I

High–Level Sourcing

Current – MC

V

= 2.7 V

= 4.6 V

= 8.5 V

3

5

9

– 0.60

– 0.90

– 1.50

–

– 0.50

– 0.75

– 1.25

–

– 0.30

– 0.50

– 0.80

–

OH

out

V

out

I

Low–Level Sinking

Current – LD

V

= 0.3 V

= 0.4 V

= 0.5 V

3

5

9

0.25

0.64

1.30

–

0.20

0.51

1.00

–

0.15

0.36

0.70

–

OL

out

V

out

I

High–Level Sourcing

Current – LD

V

= 2.7 V

= 4.6 V

= 8.5 V

3

5

9

– 0.25

– 0.64

– 1.30

–

– 0.20

– 0.51

– 1.00

–

– 0.15

– 0.36

– 0.70

–

OH

out

V

out

I

Low–Level Sinking

Current – SW1, SW2

V

= 0.3 V

= 0.4 V

= 0.5 V

3

5

9

0.80

1.50

3.50

–

0.48

0.90

2.10

–

0.24

0.45

1.05

–

OL

OH

out

V

out

V

out

I

Low–Level Sinking

Current – Other Outputs

V

= 0.3 V

= 0.4 V

= 0.5 V

3

5

9

0.44

0.64

1.30

–

0.35

0.51

1.00

–

0.22

0.36

0.70

–

out

V

out

V

out

I

High–Level Sourcing

Current – Other Outputs

V

= 2.7 V

= 4.6 V

= 8.5 V

3

5

9

– 0.44

– 0.64

– 1.30

–

– 0.35

– 0.51

– 1.00

–

– 0.22

– 0.36

– 0.70

–

out

V

out

V

out

I

Output Leakage Current –

V

= V

or V

SS

9

–

0.3

10

–

0.1

10

–

1.0

3.0

10

µA

pF

OZ

out

DD

PD

Output in Off State

out

Output Leakage Current –

SW1, SW2

V

out

= V or V

SS

9

OZ

DD

Output in Off State

C

Output Capacitance –

PD – Three–State

–

out

PD

out

Page 24 of 35

www.lansdale.com

Issue A

LANSDALE Semiconductor, Inc.

ML1451xx

AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 10 ns)

L

r

f

V

DD

V

Guaranteed Limit

255C

– 40 to 85°C

Symbol

, t

Parameter

Unit

t

Maximum Propagation Delay, f to MC

in

3

5

9

110

60

35

120

70

40

ns

PLH PHL

(Figures 1 and 4)

t

Maximum Propagation Delay, ENB to SW1, SW2

(Figures 1 and 5)

3

5

9

160

80

50

180

95

60

PHL

t

w

Output Pulse Width, φ , φ , and LD with f in Phase with f

V

3

5

9

25 to 200

20 to 100

10 to 70

25 to 260

20 to 125

10 to 80

R

V

R

(Figures 2 and 4)

t

Maximum Output Transition Time, MC

(Figures 3 and 4)

3

5

9

115

60

40

115

75

60

TLH

Maximum Output Transition Time, MC

(Figures 3 and 4)

3

5

9

60

34

30

70

45

38

THL

t

, t

TLH THL

Maximum Output Transition Time, LD

(Figures 3 and 4)

3

5

9

180

90

70

200

120

90

t

, t

TLH THL

Maximum Output Transition Time, Other Outputs

(Figures 3 and 4)

3

5

9

160

80

60

175

100

65

SWITCHING WAVEFORMS

V

DD

SS

INPUT

50%

– V

t

w

t

PHL

PLH

50%

φ

, φ , LD*

R V

OUTPUT

50%

* f in phase with f .

R

V

Figure 1.

Figure 2.

t

THL

TLH

ANY

OUTPUT

90%

10%

Figure 3.

V

DD

TEST POINT

15 k

TEST POINT

OUTPUT

Ω

OUTPUT

DEVICE

UNDER

TEST

DEVICE

UNDER

TEST

C *

L

* Includes all probe and fixture capacitance.

Figure 4. Test Circuit

* Includes all probe and fixture capacitance.

Figure 5. Test Circuit

Page 25 of 35

www.lansdale.com

Issue A

ML1451xx

LANSDALE Semiconductor, Inc.

TIMING REQUIREMENTS (Input t = t = 10 ns unless otherwise indicated)

r

f

V

DD

V

Guaranteed Limit

25 C

Guaranteed Limit

– 40 to 85 C

Symbol

Parameter

Unit

f

Serial Data Clock Frequency, Assuming 25% Duty Cycle

3

5

9

DC to 5.0

DC to 7.1

DC to 10

DC to 3.5

DC to 7.1

DC to 10

MHz

clk

NOTE: Refer to CLK t

(Figure 6)

below

w(H)

t

Minimum Setup Time, Data to CLK

(Figure 7)

3

5

9

30

20

18

30

20

18

ns

µs

su

t

Minimum Hold Time, CLK to Data

(Figure 7)

3

5

9

40

20

15

40

20

15

h

t

su

Minimum Setup Time, CLK to ENB

(Figure 7)

3

5

9

70

32

25

70

32

25

t

Minimum Recovery Time, ENB to CLK

(Figure 7)

3

5

9

5

10

20

5

10

20

rec

t

Minimum Pulse Width, CLK and ENB

(Figure 6)

3

5

9

50

35

25

70

35

25

w(H)

t , t

r

Maximum Input Rise and Fall Times – Any Input

(Figure 8)

3

5

9

5

4

2

5

4

2

f

SWITCHING WAVEFORMS

– V

DD

t

DATA

w(H)

50%

– V

DD

V

SS

CLK,

ENB

t

su

50%

t

h

V

*

SS

1

– V

DD

4 f

clk

LAST

CLK

FIRST

CLK

ENB

50%

V

SS

*Assumes 25% Duty Cycle.

t

su

rec

– V

DD

Figure 6.

50%

V

SS

LATCHED

t

f

r

ANY

OUTPUT

– V

DD

90%

10%

Figure 7.

V

SS

Figure 8.

Page 26 of 35

www.lansdale.com

Issue A

LANSDALE Semiconductor, Inc.

ML1451xx

FREQUENCY CHARACTERISTICS (Voltages References to V , C = 50 pF, Input t = t =10 ns unless otherwise indicated)

SS

L

r

f

– 40 C

25 C

Max

85 C

Max

V

DD

V

Symbol

Parameter

Input Frequency

Test Condition

Min

Max

Min

Unit

f

i

R ≥ 8, A ≥ 0, N ≥ 8

= 500 mV p–p

AC coupled sine wave

3

5

9

–

6

15

–

6

15

–

6

15

MHz

(f , OSC

)

in

V

in

R ≥ 8, A ≥ 0, N ≥ 8

= 1 V p–p AC coupled

sine wave

3

5

9

–

12

22

25

–

12

20

22

–

7

20

22

V

in

R ≥ 8, A ≥ 0, N ≥ 8

3

5

9

–

13

25

–

12

22

25

–

8

22

25

V

in

= V

to V

DD

SS

DC coupled square wave

NOTE: Usually, the PLL's propagation delay from f to MC plus the setup time of the prescaler determines the upper frequency limit of the system.

in

The upper frequency limit is found with the following formula:f = P /(t + t ) where f is the upper frequency in Hz, P is the lower of the dual

P

set

modulus prescaler ratios, t is the f to MC propagation delay in seconds, and t

is the prescaler setup time in seconds.

P

in

set

For example, with a 5 V supply, the f to MC delay is 70 ns. If the MC12028A prescaler is used, the setup time is 16 ns. Thus, if the 64/65

ratio is utilized, the upper frequency limit is f = P/(t + t ) = 64/(70 + 16) = 744 MHz.

set

in

P

f

V

R

H

REFERENCE

OSC

÷

R

V

L

f

H

V

FEEDBACK

(f N)

÷

V

in

L

H

*

HIGH IMPEDANCE

PD

out

V

L

H

φ

R

V

L

H

φ

V

L

H

LD

V

L

V

H

V

L

= High Voltage Level.

= Low Voltage Level.

* At this point, when both f and f are in phase, the output is forced to near mid–supply.

R

V

NOTE: The PD

generates error pulses during out–of–lock conditions.When locked in phase and frequency the output is high

out

and the voltage at this pin is determined by the low–pass filter capacitor.

Figure 9. Phase Detector/Lock Detector Output Waveforms

Page 27 of 35

www.lansdale.com

Issue A

ML1451xx

LANSDALE Semiconductor, Inc.

DESIGN CONSIDERATIONS

PHASE–LOCKED LOOP – LOW–PASS FILTER DESIGN

K

φ

VCO

A)

PD

out

VCO

ω

=

n

NR C

R

1

φ

–

R

V

C

Nω

n

ζ

φ

2K

K

VCO

φ

1

F(s) =

R sC + 1

1

PD

B)

VCO

out

K

φ

VCO

R

ω

=

1

n

NC(R + R )

1

2

φ

–

R

2

N

)

(

R C +

2

φ

ζ

=

0.5

ω

C

V

n

K

VCO

φ

R sC + 1

2

F(s) =

(R + R )sC + 1

1

2

R

2

K

VCO

PD

–

C)

φ

out

ω

=

n

NCR

C

1

R

1

_

+

φ

R

ω

R C

2

A

VCO

n

φ

V

ζ

=

2

1

ASSUMING GAIN A IS VERY LARGE, THEN:

R sC + 1

R

2

C

F(s) =

R sC

1

NOTE: Sometimes R is split into two series resistors, each R ÷2. A capacitor C is then placed from the midpoint to ground to further

1

R

1

C

filter φ and φ . The value of C should be such that the corner frequency of this network does not significantly affect ω .

V

C

n

The φ and φ outputs swing rail–to–rail.Therefore, the user should be careful not to exceed the common mode input range of the

R

V

op amp used in the combiner/loop filter.

DEFINITIONS:

N = Total Division Ratio in feedback loop

K

φ

K

φ

(Phase Detector Gain) = V /4π for PD

DD

out

(Phase Detector Gain) = V /2π for φ and φ

DD

V

R

2π∆f

VCO

K

VCO

(VCO Gain) =

∆V

VCO

2πfr

10

for a typical design w (Natural Frequency)

(at phase detector input).

n

Damping Factor: ζ ≅ 1


型号：	ML145151YP
厂家：	LANSDALE SEMICONDUCTOR INC.
描述：	Parallel-Input PLL Frequency Synthesizer Interfaces with Single-Modulus Prescalers 并行输入锁相环频率合成器的接口与单预分频系数光电二极管局域网
文件：	总35页 (文件大小：2437K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ML145151YP [LANSDALE]

相关型号：

ML145151_08

ML145152

ML145152-6P

ML145152YP

ML145155

ML145155-6P

ML145155VP

ML145156

ML145156-6P

ML145156RP

ML145157

ML145157-5P