ML145406-6P [LANSDALE]
Driver/Receiver EIA 232-E and CCITT V.28 (Formerly RS-232-D); 驱动器/接收器EIA 232 -E和CCITT V.28 （前身为RS- 232 -D ）
| 型号： | ML145406-6P |
| 厂家： | 
LANSDALE SEMICONDUCTOR INC. |
| 描述： | Driver/Receiver EIA 232-E and CCITT V.28 (Formerly RS-232-D) |
| 文件： | 总10页 (文件大小：759K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ML145406
Driver/Receiver
EIA 232–E and CCITT V.28
(Formerly RS–232–D)
Legacy Device: Motorola MC145406
The ML145406 is a silicon–gate CMOS IC that combines three drivers and
three receivers to fulfill the electrical specifications of standards EIA 232–E
and CCITT V.28. The drivers feature true TTL input compatibility,
slew–rate–limited output, 300–Ω power–off source impedance, and output typ-
ically switching to within 25% of the supply rails. The receivers can handle up
to 25 V while presenting 3 to 7 kΩ impedance. Hysteresis in the receivers
aids reception of noisy signals. By combining both drivers and receivers in a
single CMOS chip, the ML145406 provides efficient, low–power solutions for
EIA 232–E and V.28 applications.
P DIP 16 = EP
PLASTIC
CASE 648
16
1
SO 16W = -5P
SOG
CASE 751G
This device offers the following performance features:
16
• Operating Temperature Range = T –40° to +85°C
A
1
Drivers
5 V to 12 V Supply Range
• 300–Ω Power–Off Source Impedance
• Output Current Limiting
• TTL Compatible
•
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 16
SO 16W
MC145406P
ML145406EP
MC145406DW ML145406-6P
• Maximum Slew Rate = 30 V/µs
Receivers
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
•
25 V Input Voltage Range When V
= 12 V, V = – 12 V
SS
DD
• 3 to 7 kΩ Input Impedance
• Hysteresis on Input Switchpoint
BLOCK DIAGRAM
RECEIVER
PIN ASSIGNMENT
V
DD
V
DD
V
V
1
2
16
15
CC
V
DD
CC
V
CC
*
15 k
R
R
R
Rx
+
DO1
DI1
Rx1
Tx1
DO
–
3
4
5
6
7
14
13
12
11
10
5.4 k
D
D
D
V
1.0 V
1.8 V
SS
DO2
Rx2
Tx2
DI2
HYSTERESIS
DO3
Rx3
Tx3
V
DD
DRIVER
V
CC
DI3
300
+
–
DI
GND
V
8
LEVEL
SHIFT
9
SS
Tx
1.4 V
D = DRIVER
R = RECEIVER
V
SS
*Protection circuit
Page 1 of 10
www.lansdale.com
Issue A
ML145406
LANSDALE Semiconductor, Inc.
MAXIMUM RATINGS (Voltage polarities referenced to GND)
This device contains protection circuitry to pro-
tect the inputs against damage due to high static
voltages or electric fields; however, it is advised
that normal precautions be taken to avoid applica-
tion of any voltage higher than maximum rated
voltages to this high impedance circuit. For proper
operation, it is recommended that the voltages at
the DI and DO pins be constrained to the range
Rating
Symbol
Value
Unit
DC Supply Voltages (V
≥ V
CC
)
V
– 0.5 to + 13.5
+ 0.5 to – 13.5
– 0.5 to + 6.0
V
DD
DD
V
SS
CC
V
Input Voltage Range
Rx1–3 Inputs
V
IR
V
(V
SS
– 15) to (V
– 0.5 to (V
CC
+ 15)
DD
+ 0.5)
DI1–3 Inputs
GND≤V ≤V
andGND≤V ≤V .Also,the
DI CC
DO CC
voltage at the Rx pin should be constrained to
(V – 15 V) ≤ V ≤ (V + 15 V), and Tx
DC Current Per Pin
Power Dissipation
mA
100
1.0
SS Rx1–3 DD
should be constrained to V
≤ V
≤ V .
P
D
W
°C
°C
SS Tx1–3
DD
Unused inputs must always be tied to an ap-
Operating Temperature Range
Storage Temperature Rate
T
A
– 40 to + 85
propriate logic voltage level (e.g., GND or V
DI and Ground for Rx.)
for
CC
T
stg
– 85 to + 150
DC ELECTRICAL CHARACTERISTICS (All polarities referenced to GND = 0 V, T = – 40 to +85°C)
A
Parameter
Symbol
Min
Typ
Max
Unit
DC Supply Voltage
V
V
V
V
V
4.5
– 4.5
4.5
5 to 12
– 5 to – 12
5.0
13.2
– 13.2
5.5
DD
SS
CC DD
DD
V
SS
CC
(V
≥ V
CC
)
V
Quiescent Supply Current (Outputs unloaded, inputs low)
µA
V
DD
V
SS
V
CC
= + 12 V
= – 12 V
= + 5 V
I
—
—
—
140
340
300
400
600
450
DD
I
SS
CC
I
RECEIVER ELECTRICAL SPECIFICATIONS
(Voltage polarities referenced to GND = 0 V, V
= + 5 to + 12 V, V
= – 5 to – 12 V, V ≥ V , T = – 40 to + 85°C)
DD CC A
DD
SS
Characteristic
= 5.0 V 5%
= 5.0 V 5%
Symbol
Min
1.35
Typ
Max
Unit
Input Turn–on Threshold
= V , V
Rx1–Rx3
Rx1–Rx3
Rx1–Rx3
Rx1–Rx3
V
on
1.80
2.35
V
V
DO1–DO3
OL CC
Input Turn–off Threshold
= V , V
V
off
0.75
0.6
1.00
0.8
1.25
—
V
V
k
V
DO1–DO3
OH CC
Input Threshold Hysteresis
= 5.0 V 5%
V
–V
on off
V
CC
Input Resistance
(V – 15 V) ≤ V
R
3.0
5.4
7.0
in
≤ (V
Rx1–Rx3 DD
+ 15 V)
= – 3 V to (V
SS
High–Level Output Voltage (V
Rx1–Rx3
– 15 V))*
V
OH
V
SS
DO1–DO3
4.9
3.8
4.9
4.3
—
—
I
I
= – 20 µA, V
= + 5.0 V
CC
= + 5.0 V
OH
OH
= –1 mA, V
CC
Low–Level Output Voltage (V
Rx1–Rx3
= + 3 V to (V
+ 15 V))* DO1–DO3
V
OL
V
DD
I
I
I
= + 20 µA, V
= + 5.0 V
—
—
—
0.01
0.02
0.5
0.1
0.5
0.7
OL
OL
OL
CC
CC
= + 2 mA, V
= + 4 mA, V
CC
= + 5.0 V
= + 5.0 V
* This is the range of input voltages as specified by EIA 232–E to cause a receiver to be in the high or low logic state.
Page 2 of 10
www.lansdale.com
Issue A
ML145406
LANSDALE Semiconductor, Inc.
ELECTRICAL SPECIFICATIONS (Voltage polarities referenced to GND = 0 V, V
= + 5 V 5%, T = – 40 to + 85°C)
A
CC
Characteristic
Symbol
Min
Typ
Max
Unit
Digital Input Voltage
Logic 0
DI1–DI3
DI1–DI3
V
V
—
2.0
—
—
0.8
—
IL
Logic 1
V
IH
Input Current
I
in
—
—
1.0
µA
V
= V
CC
DI1–DI3
Output High Voltage (V
DI1–3
= Logic 0, R = 3.0 k )
Tx1–Tx3
= – 5.0 V
V
OH
V
L
V
= + 5.0 V, V
3.5
4.3
9.2
3.9
4.7
9.5
—
—
—
DD
SS
= + 6.0 V, V
V
= – 6.0
DD
= + 12.0 V, V
SS
V
= – 12.0 V
DD
SS
Output Low Voltage* (V
DI1–3
= Logic 1, R = 3.0 k )
Tx1–Tx3
= – 5.0 V
= – 6.0 V
V
OL
V
L
V
V
= + 5.0 V, V
= + 6.0 V, V
= + 12.0 V, V
– 4.0
– 4.5
– 10.0
– 4.3
– 5.2
– 10.3
—
—
—
DD
DD
SS
SS
SS
V
= – 12.0 V
DD
Off Source Resistance (Figure 1)
= V = GND = 0 V, V
Tx1–Tx3
300
—
—
V
=
2.0 V
DD
SS
Tx1–Tx3
Output Short–Circuit Current (V = + 12.0 V, V
= – 12.0 V)
Tx1–Tx3
I
mA
DD SS
SC
Tx1–Tx3 shorted to GND**
Tx1–Tx3 shorted to 15.0 V***
—
—
22
60
60
100
*The voltage specifications are in terms of absolute values.
**Specificationis for one Tx output pin to be shorted at a time. Should all three driver outputs be shorted simultaneously, device power dissipation
limits will be exceeded.
***This condition could exceed package limitations.
SWITCHING CHARACTERISTICS (V
= + 5 V 5%, T = – 40 to + 85°C
CC
A
Drivers
Characteristic
Symbol
Min
Typ
Max
Unit
Propagation Delay Time
Low–to–High
Tx1–Tx3
ns
R
= 3 k , C = 50 pF
t
t
—
—
300
300
500
500
L
L
PLH
High–to–Low
PHL
R
= 3 k
C = 50 pF
L
L
Output Slew Rate
Minimum Load
Tx1–Tx3
SR
V/µs
R
= 7 k , C = 0 pF, V
= + 6 to + 12 V, V
SS
= – 6 to – 12 V
—
9
30
L
L
DD
Maximum Load
R
= 3 k , C = 2500 pF
L
L
V
= + 12 V, V
= – 12 V
4
—
—
—
—
—
DD
V
SS
= + 5 V, V
= – 5 V
DD
SS
Receivers (C = 50 pF)
L
Characteristic
Symbol
Min
Typ
Max
Unit
Propagation Delay Time
Low–to–High
DO1–DO3
ns
t
t
—
—
—
—
150
150
250
40
425
425
400
100
PLH
High–to–Low
Output Rise Time
Output Fall Time
PHL
DO1–DO3
DO1–DO3
t
r
ns
ns
t
f
Page 3 of 10
www.lansdale.com
Issue A
ML145406
LANSDALE Semiconductor, Inc.
PIN DESCRIPTIONS
1
V
16
V
CC
VDD
DD
Positive Power Supply (Pin 1)
14
3
DI1
Tx1
The most positive power supply pin, which is typically + 5
to +12V.
V
12
10
5
7
in = 2 V
VSS
DI2
Tx2
Negative Power Supply (Pin 8)
The most negative power supply pin, which is typically – 5
to –12 V.
DI3
Tx3
V
CC
Digital Power Supply (Pin 16)
V
8
V
in
I
SS GND
9
R
=
out
The digital supply pin, which is connected to the logic power sup-
ply (maximum +5.5 V). V must be less than or equal to V
.
CC
DD
GND
Ground (Pin 9)
Figure 1. Power–Off Source Resistance (Drivers)
Ground return pin is typically connected to the signal ground
pin of the EIA 232–E connector (Pin 7) as well as to the logic
power supply ground.
DRIVERS
Rx1, Rx2, Rx3
3 V
Receive Data Input (Pins 2, 4, 6)
DI1–DI3
50%
These are the EIA 232–E receive signal inputs whose volt-
ages can range from (V
age between +3 and (V
0 V
+ 15 V) to (V – 15 V). A volt-
SS
DD
DD
t
t
f
r
+ 15 V) is decoded as a space and
V
OH
causes the corresponding DO pin to swing to ground (0V); a
voltage between – 3 and (VDD – 15 V) is decoded as a mark
90%
Tx1–Tx3
10%
t
and causes the DO pin to swing up to V . The actual turn–on
CC
V
OL
input switch point is typically biased at 1.8 V above ground,
and includes 800mV of hysteresis for noise rejection. The
nominal input impedance is 5 kΩ. An open or grounded input
t
PLH
PHL
pin is interpreted as a mark, forcing the DO pin to V
.
CC
RECEIVERS
+ 3 V
0 V
DO1, DO2, DO3
Data Output (Pins 11, 13, 15)
Rx1–Rx3
50%
These are the receiver digital output pins, which swing from
to GND. A space on the Rx pin causes DO to produce a
logic 0; a mark produces a logic 1. Each output pin is capable
of driving one LSTTL input load.
t
t
PLH
PHL
V
CC
V
OH
90%
DO1–DO3
50%
10%
V
OL
t
t
r
DI1, DI2, DI3
Data Input (Pins 10, 12,14)
f
These are the high–impedance digital input pins to the driv-
ers. TTL compatibility is accomplished by biasing the input
switchpoint at 1.4 V above GND. However, 5V CMOS compat-
ibility is maintained as well. Input voltage levels on these pins
Figure 2. Switching Characteristics
must be between V
and GND.
CC
DRIVERS
Tx1–Tx3
Tx1, Tx2, Tx3
Transmit Data Output(Pins 3, 5, 7)
3 V
3 V
These are the EIA 232–E transmit signal output pins, which
– 3 V
– 3 V
t
swing toward V
and V . A logic 1 at a DI input causes the
SS
DD
t
SHL
SLH
corresponding Tx output to swing toward V . A logic 0 caus-
SS
es the output to swing toward V
(the output voltages will be
DD
or V depending upon the output
– 3 V – (3 V)
3 V – ( – 3 V)
SLEW RATE (SR) =
OR
slightly less than V
DD
t
t
SS
load). Output slew rates are limited to a maximum of 30 V per
µs. When the ML145406 is off (V = V = V = GND),
SLH
SHL
DD SS CC
Figure 3. Slew–Rate Characterization
the minimum output impedance is 300 Ω.
Page 4 of 10
www.lansdale.com
Issue A
ML145406
LANSDALE Semiconductor, Inc.
Legacy Applications Information
The ML145406 has been designed to meet the electrical-
specifications of standards EIA 232–E and CCITT V.28. EIA
232–E defines the electrical and physical interface between
Data Communication Equipment (DCE) and DataTerminal
forces the appropriate DO pin to a logic 1 when its Rx input is
open or grounded as called for in the EIA 232–E specification.
Notice that TTL logic levels can be applied to the Rx inputs in
lieu of normal EIA 232–E signal levels. This might be helpful
Equipment (DTE). A DCE is connected to a DTE using a cable in situations where access to the modem or computer through
that typically carries up to 25 leads. These leads, referred to as the EIA 232–E connector is necessary with TTL devices.
interchange circuits, allow the transfer of timing, data, control, However, it is important not to connect the EIA 232–E outputs
and test signals. Electrically this transfer requires level shifting (Tx1–Tx3) to TTL inputs since TTL operates off + 5 V only,
between the TTL/CMOS logic levels of the computer or
modem and the high voltage levels of EIA 232–E, which can
range from 3 to 25 V. The ML145406 provides the neces-
sary level shifting as well as meeting other aspects of the EIA
232–E specification.
and may be damaged by the high output voltage of the
ML145406.
The DO outputs are to be connected to a TTL or CMOS
input (such as an input to a modem chip). These outputs will
swing from V
to ground, allowing the designer to operate
CC
the DO and DI pins from digital power supply. The Tx and Rx
sections are independently powered by V andV so that
one may run logic at + 5 V and the EIA 232–E signals at 12V.
DRIVERS
DD
SS
As defined by the specification, an EIA 232–E driver pres-
ents a voltage of between 5 to 15 V into a load of between 3
to 7 kΩ. A logic 1 at the driver input results in a voltage of
between –5 to – 15 V. A logic 0 results in a voltage between +
POWER SUPPLY CONSIDERATIONS
Figure 4 shows a technique to guard against excessive device
current.
The diode D1 prevents excessive current from flowing
5 to + 15V. When operating V
ML145406 meets this requirement. When operating at 5 V,
the ML145406 drivers produce less than 5 V at the output
and V at 7 to 12 V, the
DD
SS
through an internal diode from the V
pin to the V
pin
CC
DD
(when terminated), which does not meet EIA 232–E specifica- when V
tion. However, the output voltages when using a 5 V power
supply are high enough (around 4 V) to permit proper recep-
< V
by approximately 0.6 V. This high current
DD
CC
condition can exist for a short period of time during
powerup/down. Additionally, if the + 12 V supply is switched
tion by an EIA 232–E receiver, and can be used in applications off while the + 5 V is on and the off supply is a low impedance
where strict compliance to EIA 232–E is not required.
Another requirement of the ML145406 drivers is that they
withstand a short to another driver in the EIA 232–E cable.
The worst–case condition that is permitted by EIA 232–E is a
15V source that is current limited to 500 mA. The ML145406 removed from V (Pin 12). If V power is removed, and the
drivers can withstand this condition momentarily. In most short impedance from the V pin to ground is greater than approxi-
SS
circuit conditions the source driver will have a series 300 Ω
output impedance needed to satisfy the EIA 232–E driver
requirements. This will reduce the short circuit current to
under 40 mA which is an acceptable level for the ML145406
to withstand.
to ground, the diode D1 will prevent current flow through the
internal diode.
The diode D2 is used as a voltage clamp, to prevent V
from drifting positive to V , in the event that power is
CC
SS
SS SS
mately 3 kΩ, this pin will be pulled to V
by internal circuit-
pin.
CC
ry causing excessive current in the V
CC
If by design, neither of the above conditions are allowed to
exist, then the diodes D1 and D2 are not required.
Unlike some other drivers, the ML145406 drivers feature an
internally–limited output slew–rate that does not exceed 30 V
per µs.
ESD PROTECTION
ESD protection on IC devices that have their pins accessible
to the outside world is essential. High static voltages applied to
the pins when someone touches them either directly or indi-
rectly can cause damage to gate oxides and transistor junctions
by coupling a portion of the energy from the I/O pin to the
power supply buses of the IC. This coupling will usually occur
through the internal ESD protection diodes. The key to protect-
ing the IC is to shunt as much of the energy to ground as pos-
sible before it enters the IC. Figure 4 shows a technique which
will clamp the ESD voltage at approximately 15 V using the
RECEIVERS
The job of an EIA 232–E receiver is to level–shift voltages
in the range of – 25 to + 25 V down to TTL/CMOS logic lev-
els (0 to + 5 V). A voltage of between – 3 and – 25 V on Rx1
is defined as a mark and produces a logic 1 at DO1. A voltage
between + 3 and + 25 V is a space and produces a logic zero.
While receiving these signals, the Rx inputs must present a
resistance between 3 and 7 kΩ. Nominally, the input resistance MMVZ15VDLT1. Any residual voltage which appears on the
of the Rx1–Rx3 inputs is 5.4 kΩ.
The input threshold of the Rx1–Rx3 inputs is typically
supply pins is shunted to ground through the capacitors
C1–C3. This scheme has provided protection to the interface
biased at 1.8 V above ground (GND) with typically 800 mV of part up to 10kV, using the human body model test.
hysteresis included to improve noise immunity. The 1.8 V bias
Page 5 of 10
www.lansdale.com
Issue A
ML145406
LANSDALE Semiconductor, Inc.
Legacy Applications Information
V
DD
D1
MMBZ15VDLT
× 6
IN4001
0.1
V
CC
µF
0.1 µF
C1
C2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RxI
TxO
RxI
TO
ML145406
CONNECTOR
TxO
RxI
TxO
IN5818
D2
C3
V
0.1 µF
SS
Figure 4. ESD and Power Supply Networks
Page 6 of 10
www.lansdale.com
Issue A
ML145406
LANSDALE Semiconductor, Inc.
+ 5 V
0.1
16
µF
0.1 µF
1
6
V
20 k
Ω
9
V
V
CC
TLA
DSI
DD
DD
ML145406
X
in
C
R
DSI
TLA**
3.579
MHz
R
DSI
DTMF
INPUT
1
ML145442/3
8
3
3
14
15
12
Tx1
8
X
out
DI1
20 k
Ω
17
15
0.1
µF
TxA
CD
TxD
RxD
RxA2
11
5
2
5
4
DO1
2
3
Rx1
Tx2
R
600
Tx
EIA 232–E
DB–25
CONNECTOR
10 kΩ
10 kΩ
10
µ
F
+
16
DI2
TIP
RxA1
14
2
SQT
LB
*
7
600:600
NC 13 DO2
Rx2
Tx3
10 k
Ω
RING
18
10
10
7 NC
6
ExI
FB
V
DI3
DD
C
FB
10 k
Ω
10 k
0.1
µF
DO3
NC11
Rx3
13
7
0.1
µF
MODE
CDA
19
4
V
BYPASS
DD
V
AG
V
CDT
GND
12
GND
9
SS
C
CDA**
0.1
0.1
µF
0.1
C
µ
CDT
F
8
µF
V
BYPASS
SS
0.1
– 5 V
µF
*Line protection circuit
**Refer to the applications information for values of C
and R
CDA
TLA
Figure 5. 5–V 300–Baud Modem with EIA 232–E Interface
Page 7 of 10
www.lansdale.com
Issue A
ML145406
LANSDALE Semiconductor, Inc.
Legacy Applications Information
1
4
7
*
2
5
8
0
3
6
9
#
MC34119
SPEAKER
DRIVER
MC145412/13/16
PULSE/TONE
DIALER
HOOKSWITCH
LINE
INTERFACE
(TRANSFORMER
AND
RINGING
ML145503
FILTER/
CODEC
MC145426
UDLT
TWISTED
PAIR
PROTECTION)
SYNC
MC34129
SWITCHING
POWER
SUPPLY
(ISOLATED)
+ 5 V
GND
– 5 V
CONNECTION
TO EXTERNAL
TERMINAL
OR PC
ML145406
RS–232
DRIVER
ML145428
DATA
SET
LINE
FILTER
RECEIVER
INTERFACE
Figure 6. Line–Powered Voice/Data Telephone with Electrically Isolated EIA 232–E Interface
Page 8 of 10
www.lansdale.com
Issue A
ML145406
LANSDALE Semiconductor, Inc.
TR1
Figure 7. 80–kbps Limited Distance Modem with EIA 232–E Interface (Master)
Page 9 of 10
www.lansdale.com
Issue A
ML145406
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
P DIP 16 = EP
(ML145406EP)
CASE 648–08
NOTES:
-A-
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
8
B
INCHES
MILLIMETERS
DIM
A
B
C
D
F
G
H
J
K
L
MIN
MAX
0.770
0.270
0.175
0.021
0.070
MIN
18.80
6.35
3.69
0.39
1.02
2.54 BSC
1.27 BSC
0.21
MAX
19.55
6.85
4.44
0.53
1.77
F
C
L
0.740
0.250
0.145
0.015
0.040
0.100 BSC
0.050 BSC
0.008
S
SEATING
-T-
PLANE
M
K
0.015
0.130
0.305
0.38
3.30
7.74
H
J
0.110
0.295
2.80
7.50
G
D 16 PL
M
S
0°
10
0.040
°
0°
10
1.01
°
M
M
0.25 (0.010)
T
A
0.020
0.51
SOG 16 = -5P
(ML145406-5P)
CASE 751G–02
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
16
9
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
-B- P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
M
0.25 (0.010)
B
1
8
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
G 14 PL
J
F
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
10.15
7.40
2.35
0.35
0.50
MAX
10.45
7.60
2.65
0.49
0.90
MIN
MAX
0.411
0.299
0.104
0.019
0.035
0.400
0.292
0.093
0.014
0.020
R X 45°
F
1.27 BSC
0.050 BSC
G
J
K
M
P
R
C
0.25
0.10
0.32
0.25
0.010
0.004
0.012
0.009
-T-
0°
7
°
0°
7°
SEATING
M
K
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
PLANE
D 16 PL
0.25 (0.010)
M
S
S
T
A
B
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