ML620Q154B [LAPIS]
16-bit micro controller;
| 型号： | ML620Q154B |
| 厂家： | 
LAPIS Semiconductor Co., Ltd. |
| 描述： | 16-bit micro controller |
| 文件： | 总36页 (文件大小：825K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL620Q150B-01
Issue Date: Mar 30, 2017
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
16-bit micro controller
GENERAL DESCRIPTION
This LSI is a high-performance 16-bit CMOS microcontroller into which rich peripheral circuits, such as 10-bit A/D converter,
timer, PWM, synchronous serial port, UART, I2C bus interface (master), Low level detect circuit, are incorporated around 16-bit
CPU nX-U16/100.
The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe line architecture
parallel procesing. and, this LSI has a data flash-memory fill area by a software which can be written in. In addition, it has an
on-chip debugging function, which allows software debugging/rewriting with the LSI mounted on the board.
FEATURES
• CPU
− 16-bit RISC CPU (CPU name: nX-U16/100)
− Instruction system:16-bit instructions
− Instruction set:Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
− On-Chip debug function
− Minimum instruction execution time
Approx 30.5 µs (at 32.768kHz system clock)
Approx 0.122 µs (at 8.192MHz system clock)
• Internal memory
− Flash-memory
Product
Program area
Rewrite
cycle
ML620Q151B/ML620Q154B/ML620Q157B
ML620Q152B/ML620Q155B/ML620Q158B
ML620Q153B/ML620Q156B/ML620Q159B
* including unusable 1KByte TEST area
32-Kbyte* (16K × 16-bit)
48-Kbyte* (24K × 16-bit)
64-Kbyte* (32K × 16-bit)
100
Internal 2-Kbyte Data Flash (1-Kbyte × 2) Rewrite cycle: 10,000 times
− SRAM: Internal 2-Kbyte RAM (2-Kbyte × 8 -bits)
• Interrupt controller
− 2 non-maskable interrupt sources (Internal source: BACK-UP CLOCK, WDT)
− maskable interrupt
Product
Interrupt source
ML620Q151B/ML620Q154B/ML620Q157B
ML620Q152B/ML620Q155B/ML620Q158B
ML620Q153B/ML620Q156B/ML620Q159B
− 4 steps of interrupt level, and a mask function
27 (Internal source: 20, External source: 7)
28 (Internal source: 20, External source: 8)
28 (Internal source: 20, External source: 8)
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FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
• Time base counter
−
Low-speed time base counter × 1 channel
• Watchdog timer
− Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, 8s @32.768kHz)
• Timers
− 8 bits × 2ch (16-bits configuration available × 1ch)
− 16 bits × 4ch
• PWM
− 16bits × 4ch
− The auto reload timer mode / PWM mode
− Timer start-stop function by the software and an external trigger.
− A pulse width can be measured using an external-trigger input.
− An external event can be selected as the counter clock.
− Complement synchronous PWM
• Synchronous serial port
− 1ch
− Master/slave selectable
− LSB first/MSB first selectable
− 8-bit length/16-bit length selectable
• UART
− Full-duplex × 1ch ( Half-duplex × 2ch )
− Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
− Positive logic/negative logic selectable
− Built-in baud rate generator
• I2C bus interface
− Master function only
− Fast mode (400kbit/s), Standard mode (100kbit/s)
• Successive approximation type A/D converter
− 10-bit A/D converter
− Input: 12ch （Maximum）
− Conversion time: 43us, 13.5µs per channel (conversion-time is selectable)
•
Analog Comparator
− 1ch
− Edge for the interrupt and sampling function is selectable.
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FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
• General-purpose ports （including secondary functions）
− Input-only ports
Input-only ports (including multiple
functions)
Product
When not using the When using the
crystal resonator
crystal resonator
ML620Q151B/ML620Q152B/ML620Q153B
ML620Q154B/ML620Q155B/ML620Q156B
ML620Q157B/ML620Q158B/ML620Q159B
− Output-only ports : 4ch
6ch
7ch
7ch
5ch
6ch
6ch
− Input/output ports
Input/output ports (including multiple
functions)
When not using the When using the
Product
crystal resonator
31ch
crystal resonator
30ch
ML620Q151B/ML620Q152B/ML620Q153B
ML620Q154B/ML620Q155B/ML620Q156B
ML620Q157B/ML620Q158B/ML620Q159B
34ch
46ch
33ch
45ch
• Reset
− Reset through the RESET_N pin
− Power-on reset generation when powered on
− Reset by the watchdog timer (WDT) overflow
− Reset by the Low Level Detector (LLD)
•
Low Level detect function
− Threshold voltages: 4values (1.9V/2.55V/3.7V/4.2V)
A threshold voltage is selected as Code-Option.
− LLD is a ready as a supply-voltage supervisory reset.
Reset or an interrupt output is selectable as Code-Option.
• Clock
− Low-speed clock (This LSI can not guarantee the operation without low-speed clock)
Crystal oscillation (32.768 kHz) or Built-in RC oscillation (32.768kHz)
Crystal oscillation or Built-in RC oscillation is selectable as Code-Option.
− High-speed clock
Built-in RC oscillation (2.097MHz) or Built-in PLL oscillation (8.192MHz)
• Power management
− HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).
− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are
stopped.)
− Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation
clock)
− Block control function: Operation of an intact functional block circuit is powerd down. (register reset and clock stop)
3/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
• Package
Product
Package
ML620Q151B/ML620Q152B/ML620Q153B
ML620Q154B/ML620Q155B/ML620Q156B
48pinTQFP (P-TQFP48-0707-0.50-QK)
52pinTQFP (P-TQFP52-1010-0.65-TK)
64pinQFP (P-QFP64-1414-0.80-UK)
64pinTQFP (P-TQFP64-1010-0.50-ZK6)
ML620Q157B/ML620Q158B/ML620Q159B
• Guaranteed operating range
− Operating temperature: −40°C to +105°C
− Operating voltage: VDD = 1.8V to 5.5V
The difference point of this LSI is shown below.
function
ML620Q151B/152B/153B
ML620Q154B/155B/156B
52pinTQFP
ML620Q157B/158B/159B
Shipment
48pinTQFP
64pinQFP/TQFP
32Kbyte(ML620Q151B)
48Kbyte(ML620Q152B)
52Kbyte(ML620Q153B)
32Kbyte(ML620Q154B)
48Kbyte(ML620Q155B)
52Kbyte(ML620Q156B)
32Kbyte(ML620Q157B)
48Kbyte(ML620Q158B)
52Kbyte(ML620Q159B)
flash capacity
(program area)
maskable interrupt
27
28
28
Input-only port
(At the case of crystal unused)
6
7
Available
34
7
Available
46
P05 port
−
Input/output port
(At the case of crystal unused)
31
P36,P53,P64 ports
P37 port
Available
Available
Available
−
−
−
−
−
−
−
−
−
P50～P52 ports
P65～P67 ports
P70～P74 ports
Available
Available
Available
－:none
4/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
BLOCK DIAGRAM
Block Diagram of ML620Q151B/ML620Q152B/ML620Q153B(TQFP48)
CPU (nX-U16/100)
EPSW1～3
ELR1～3
LR
ECSR1～3
DSR/CSR
PC
GREG
0～15
PSW
EA
Program
Memory
Timing
ALU
Controller
SP
(FLASH)
BUS
32/48/64Kbyte
Instruction
Decoder
Instruction
Register
Controller
On-Chip
ICE
Data-bus
INT
VDD
VSS
SSIOx1
SCK0*
SIN0*
1
SOUT0*
RAM
INT
2
2Kbyte
RXD0*
TXD0*
RXD1*
TXD1*
UARTx1
(*1)
VDDL
Power
Interrupt
INT
1
Controller
RESET N
TEST0*3
RESET &
TEST
SDA0*
SCL0*
I2Cx1
INT
1
TEST1_N
INT
6
WDT
TBC
INT
1
8bit Timer
×2
16bit Timer
×4
TMHAOUT*
TMHBOUT*
XT0
XT1
INT
4
OSC
LSCLK*
OUTCLK*
PWM4*
PWM5*
PWM6*
INT
4
INT
1
16bitTimer
LLD
with PWMx4
PWM7*
INT
1
PW45EV0*
PW45EV1*
PW67EV0*
PW67EV1*
VDD
SA-ADC
VREF
INT
7
AIN0 to AIN11
INT
1
P00 to P04
P12*2
CMP0P
CMP0M
Analog
Comparator
×1
P13*2
GPIO
P14*3
P20 to P23
P30 to P35
P40 to P47
P54 to P57
P60 to P63
P80 to P87
* Secondary or tertiary or quaternary function
*1 Full-duplex × 1ch ( Half-duplex × 2ch )
*2 Cannot be used as I/O port when connecting the crystal resonator
*3 Cannot be used as I/O port when connecting the uEASE(On-chip debug emualtor)
Figure 1-1 Block Diagram of ML620Q151B/ML620Q152B/ML620Q153B(TQFP48)
5/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
Block Diagram of ML620Q154B/ML620Q155B/ML620Q156B(TQFP52)
CPU (nX-U16/100)
EPSW1～3
ELR1～3
LR
ECSR1～3
DSR/CSR
PC
GREG
0～15
PSW
EA
Program
Memory
Timing
ALU
Controller
SP
(FLASH)
BUS
32/48/64Kbyte
Instruction
Decoder
Instruction
Register
Controller
On-Chip
ICE
Data-bus
INT
VDD
VSS
SSIOx1
SCK0*
SIN0*
1
SOUT0*
RAM
INT
2
2Kbyte
RXD0*
TXD0*
RXD1*
TXD1*
UARTx1
(*1)
VDDL
Power
Interrupt
INT
1
Controller
RESET N
TEST0*3
RESET &
TEST
SDA0*
SCL0*
I2Cx1
INT
1
TEST1_N
INT
6
WDT
TBC
INT
1
8bit Timer
×2
16bit Timer
×4
TMHAOUT*
TMHBOUT*
XT0
XT1
INT
4
OSC
LSCLK*
OUTCLK*
PWM4*
PWM5*
PWM6*
INT
4
INT
1
16bitTimer
LLD
with PWMx4
PWM7*
INT
1
PW45EV0*
PW45EV1*
PW67EV0*
PW67EV1*
VDD
SA-ADC
VREF
INT
8
AIN0 to AIN11
INT
1
P00 to P05
P12*2
CMP0P
CMP0M
Analog
Comparator
×1
P13*2
GPIO
P14*3
P20 to P23
P30 to P36
P40 to P47
P54 to P57
P60 to P64
P80 to P87
* Secondary or tertiary or quaternary function
*1 Full-duplex × 1ch ( Half-duplex × 2ch )
*2 Cannot be used as I/O port when connecting the crystal resonator
*3 Cannot be used as I/O port when connecting the uEASE(On-chip debug emualtor)
Figure 1-2 Block Diagram of ML620Q154B/ML620Q155B/ML620Q156B(TQFP52)
6/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
Block Diagram of ML620Q157B/ML620Q158B/ML620Q159B(QFP64/TQFP64)
CPU (nX-U16/100)
ELR1～3
EPSW1～3
ECSR1～3
DSR/CSR
PC
GREG
0～15
PSW
LR
EA
SP
Program
Memory
Timing
ALU
Controller
(FLASH)
BUS
32/48/64Kbyte
Instruction
Decoder
Instruction
Register
Controller
On-Chip
ICE
Data-bus
INT
1
VDD
VSS
SSIOx1
SCK0*
SIN0*
SOUT0*
RAM
INT
2
2Kbyte
RXD0*
TXD0*
RXD1*
TXD1*
UARTx1
(*1)
VDDL
Power
Interrupt
INT
1
Controller
RESET N
TEST0*3
RESET &
TEST
SDA0*
SCL0*
I2Cx1
INT
1
TEST1_N
INT
6
WDT
TBC
INT
1
8bit Timer
×2
16bit Timer
×4
TMHAOUT*
TMHBOUT*
XT0
XT1
INT
4
OSC
LSCLK*
OUTCLK*
PWM4*
PWM5*
PWM6*
INT
4
INT
1
16bitTimer
LLD
with PWMx4
PWM7*
INT
1
PW45EV0*
PW45EV1*
PW67EV0*
PW67EV1*
VDD
SA-ADC
VREF
INT
8
AIN0 to AIN11
INT
1
P00 to P05
P12*2
CMP0P
CMP0M
Analog
Comparator
×1
P13*2
GPIO
P14*3
P20 to P23
P30 to P37
P40 to P47
P54 to P57
P60 to P64
P70 to P74
P80 to P87
* Secondary or tertiary or quaternary function
*1 Full-duplex × 1ch ( Half-duplex × 2ch )
*2 Cannot be used as I/O port when connecting the crystal resonator
*3 Cannot be used as I/O port when connecting the uEASE(On-chip debug emualtor)
Figure 1-3 Block Diagram of ML620Q157B/ML620Q158B/ML620Q159B(QFP64)
7/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
PIN CONFIGURATION
ML620Q151B/ML620Q152B/ML620Q153B TQFP48 package product
P00/EXI0/PW45EV0
37
P57/SOUT0/PWM7
P56/SCK0
P55/TXD0/SIN0/TXD1
P54/RXD0
24
23
22
21
20
19
18
17
16
15
14
13
P01/EXI1/PW67EV0
38
P02/EXI2/RXD0
39
P03/EXI3/RXD1
40
P04/EXI4
41
P20/LED0/LSCLK/PWM4
P47/AIN11/T16CK1/PWM5
P46/AIN10/T16CK0/SOUT0
42
43
44
45
(TOP VIEW)
TQFP48
P21/LED1/OUTCLK/PWM5
P22/LED2/TMHAOUT/PWM6
P23/LED3/TMHBOUT/PWM7
P45/AIN9/T1P5CK/SCK0
P44/AIN8/T0P4CK/SIN0
P43/AIN7/TXD0/PWM4/TXD1
P42/AIN6/RXD0/SOUT0
P41/SCL/SCK0/CMP0P
P40/SDA/SIN0/CMP0M
P14/TEST0
RESET_N
TEST1_N
46
47
48
Figure 1-4 Pin Layout of ML620Q151B/ML620Q152B/ML620Q153B TQFP48 Package
8/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
ML620Q154B/ML620Q155B/ML620Q156B TQFP52 package product
P57/SOUT0/PWM7
P56/SCK0
P00/EXI0/PW45EV0
40
26
P01/EXI1/PW67EV0
41
25
24
23
22
21
20
19
18
17
16
15
14
P55/TXD0/SIN0/TXD1
P54/RXD0
P02/EXI2/RXD0
42
P03/EXI3/RXD1
43
P53/TXD1/PWM6
P47/AIN11/T16CK1/PWM5
P46/AIN10/T16CK0/SOUT0
P04/EXI4
44
P05/EXI5
45
(TOP VIEW)
TQFP52
P20/LED0/LSCLK/PWM4
46
P21/LED1/OUTCLK/PWM5
P45/AIN9/T1P5CK/SCK0
P44/AIN8/T0P4CK/SIN0
P43/AIN7/TXD0/PWM4/TXD1
P42/AIN6/RXD0/SOUT0
P41/SCL/SCK0/CMP0P
P40/SDA/SIN0/CMP0M
47
P22/LED2/TMHAOUT/PWM6
48
P23/LED3/TMHBOUT/PWM7
49
P14/TEST0
50
RESET_N
51
TEST1_N
52
Figure 1-5 Pin Layout of ML620Q154B/ML620Q155B/ML620Q156B TQFP52 Package
9/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
ML620Q157B/ML620Q158B/ML620Q159B QFP64/TQFP64 package product
P57/SOUT0/PWM7
32
P00/EXI0/PW45EV0
49
P01/EXI1/PW67EV0
P56/SCK0
50
31
P02/EXI2/RXD0
51
P55/TXD0/SIN0/TXD1
30
P03/EXI3/RXD1
P54/RXD0
29
52
P04/EXI4
53
P53/TXD1/PWM6
P52/RXD1/SOUT0
28
27
26
25
24
23
22
21
20
19
18
17
P05/EXI5
54
55
56
57
58
59
60
61
62
63
64
P20/LED0/LSCLK/PWM4
P51/SCL/SCK0
P21/LED1/OUTCLK/PWM5
P22/LED2/TMHAOUT/PWM6
P23/LED3/TMHBOUT/PWM7
P72/RXD1/SIN0
P50/SDA/SIN0
P47/AIN11/T16CK1/PWM5
P46/AIN10/T16CK0/SOUT0
(TOP VIEW)
QFP64/TQFP
P45/AIN9/T1P5CK/SCK0
P44/AIN8/T0P4CK/SIN0
P43/AIN7/TXD0/PWM4/TXD1
P42/AIN6/RXD0/SOUT0
P41/SCL/SCK0/CMP0P
P40/SDA/SIN0/CMP0M
P73/TXD1/SCK0/TXD0
P74/SOUT0
P14/TEST0
RESET_N
TEST1_N
Figure 1-6 Pin Layout of ML620Q157B/ML620Q158B/ML620Q159B QFP64/TQFP Package
10/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
List of Pins
48
52
64
Primary function
Secondary function
Tertiary function
Quaternary function
Pin Pin Pin
No. No. No.
Pin
name
Pin
De-
Pin
De-
Pin
De-
I/O
Description
I/O
I/O
I/O
name
scription
name
scription
name
scription
Negative power
supply pin
Positive power
supply pin
3
5
3
5
3
5
Vss
VDD
Power supply for
internal logic
(internally
4
4
4
VDDL
generated)
P14/
TEST0
Input port/
Input pin for testing
Reset input pin
46
47
48
50
51
52
62
I
I
I
63 RESET_N
Input pin for testing
64
1
TEST1_N
Input port/
P12/
XT0
1
2
1
2
I
Low-speed clock
oscillation pin
Input/output port/
P13/
XT1
2
6
I/O Low-speed clock
oscillation pin
Reference power
supply pin of
Successive-approx
6
6
VREF
imation type ADC
Input port /
P00/EXI0/
PW45EV0
37
38
39
40
40
41
42
43
49
50
51
52
I
I
I
I
External interrupt /
PW45EV0 input
Input port /
External interrupt /
PW67EV0 input
Input port /
External interrupt
UART0 data input
Input port /
P01/EXI1/
PW67EV0
P02/EXI2/
RXD0
P03/EXI3/
RXD1
External interrupt
UART1 data input
Input port /
41
44
45
53
54
P04/EXI4
P05/EXI5
I
I
External interrupt
Input port /
External interrupt
Low-spe
ed clock
output
Low-spe
ed clock
output
P20/
LED0/
Output port / LED
drive
LSCL
K
PWM4
output
42
43
46
47
55
56
O
O
O
O
PWM4
PWM5
O
O
P21/
LED1/
Output port / LED
drive
OUTC
LK
PWM5
output
P22/
LED2/
Output port / LED
drive
TMHAO
UT
TimerA
output
PWM6
output
44
45
48
49
57
58
O
O
O
O
PWM6
PWM7
O
O
P23/
LED3/
Output port / LED
drive
TMHBO
UT
TimerB
output
PWM7
output
Input/output port /
PW45EV1 input /
I/O Successive
approximation type
P30/EXI6
PW45EV1
/
7
8
7
8
7
8
AIN0
ADC input
Input/output port /
PW67EV1 input /
I/O Successive
P31/EXI7
PW67EV1
/
approximation type
ADC input
AIN1
Input/output port /
PW45EV0 input /
I/O Successive
P32/
PW45EV0
/
9
9
9
approximation type
ADC input
AIN2
10
10
10
P33/
I/O Input/output port /
11/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
48
52
64
Primary function
Secondary function
Tertiary function
Quaternary function
Pin Pin Pin
No. No. No.
Pin
name
Pin
De-
Pin
De-
Pin
De-
I/O
Description
I/O
I/O
I/O
name
scription
name
scription
name
scription
PW67EV0
PW67EV0 input /
Successive
/
AIN3
approximation type
ADC input
Input/output port /
Successive
approximation type
ADC input
Input/output port /
Successive
approximation type
ADC input
P34/
AIN4/
PWM4
output
11
12
11
12
11
12
I/O
I/O
PWM4
PWM5
O
O
P35/
AIN5/
PWM5
output
Low-spe
ed clock
output
LSCL
K
13
14
13
14
17
P36
P37
I/O Input/output port
I/O Input/output port
O
O
13
I
Low-spe
ed clock
output
OUTC
LK
Input/output port /
I/O Comparator0
inverting input
I2C data
SSIO0
data
input
P40/
CMP0M
SDA
I/O input/out
put
SIN0
SSIO0
synchro
nous
clock
input/out
put
Input/output port /
I/O Comparator0
non-inverting input
I2C clock
I/O input/out
put
P41/
CMP0P
14
15
18
SCL
SCK0
I/O
Input/output port /
Successive
approximation type
ADC input
Input/output port /
Successive
approximation type
ADC input
UART0
data
input
SSIO0
data
output
P42/
AIN6
15
16
16
17
19
20
I/O
RXD0
TXD0
I
SOUT0
PWM4
O
O
UART1
data
output
UART0
data
output
P43/
AIN7
PWM4
output
I/O
O
TXD1
O
Input/output port /
PWM4
clock input/
Successive
approximation type
ADC input
Input/output port /
PWM5
clock input/
Successive
approximation type
ADC input
external
P44/
T0P4CK/
AIN8
SSIO0
data
input
17
18
18
19
21
22
I/O
I/O
SIN0
I
SSIO0
synchro
nous
clock
input/out
put
external
P45/
T1P5CK/
AIN9
SCK0
I/O
Input/output port /
Timer8,A /
P46/
T16CK0/
AIN10
PWM6
I/O clock input /
Successive
external
SSIO0
data
output
19
20
20
21
23
24
SOUT0
PWM5
O
O
approximation type
ADC input
Input/output port /
Timer9,B /
PWM7
P47/
T16CK1/
AIN11
external
PWM5
output
I/O clock input /
Successive
approximation type
ADC input
I2C data
SSIO0
data
input
SSIO0
synchro
nous
clock
input/out
put
25
26
P50
P51
I/O Input/output port
SDA
SCL
I/O input/out
put
SIN0
I
I2C clock
I/O input/out
put
I/O Input/output port
SCK0
I/O
12/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
48
52
64
Primary function
Secondary function
Tertiary function
Quaternary function
Pin Pin Pin
No. No. No.
Pin
name
Pin
De-
Pin
De-
Pin
De-
I/O
Description
I/O
I/O
I/O
name
scription
name
scription
name
scription
UART1
data
input
UART1
data
output
UART0
data
SSIO0
data
output
27
28
29
30
P52
P53
P54
P55
I/O Input/output port
I/O Input/output port
I/O Input/output port
I/O Input/output port
RXD1
TXD1
RXD0
TXD0
I
SOUT0
PWM6
O
O
I
21
22
22
23
24
PWM6
output
O
I
O
input
UART0
data
SSIO0
data
UART1
data
O
SIN0
TXD1
output
input
output
SSIO0
synchro
nous
clock
input/out
put
SSIO0
data
output
23
25
31
P56
I/O Input/output port
SCK0
I/O
PWM7
output
24
25
26
26
27
28
32
33
34
P57
P60
P61
I/O Input/output port
I/O Input/output port
I/O Input/output port
SOUT0
O
O
O
PWM7
PWM6
PWM7
O
O
O
I2C data
I/O input/out
TMHAO
UT
TimerA
output
PWM6
output
SDA
SCL
put
I2C clock
I/O input/out
put
TMHBO
UT
TimerB
output
PWM7
output
P62/
PW45EV1
P63/
Input/output port /
I/O
27
28
29
30
31
35
36
37
O
PW45EV1 input
Input/output port /
PW67EV1 input
I/O
PW67EV1
PWM4
output
P64
P65
I/O Input/output port
PWM4
Low-spe
ed clock
output
Low-spe
ed clock
output
LSCL
K
PWM5
output
38
39
I/O Input/output port
O
O
PWM5
PWM6
O
O
OUTC
LK
PWM6
output
P66
I/O Input/output port
40
15
P67
P70
I/O Input/output port
I/O Input/output port
PWM6
output
PWM7
output
SSIO0
data
PWM6
O
16
59
P71
P72
I/O Input/output port
I/O Input/output port
PWM7
SIN0
O
I
UART1
data
input
RXD1
I
input
SSIO0
synchro
nous
clock
input/out
put
UART1
data
output
UART0
data
output
60
P73
I/O Input/output port
TXD1
O
SCK0
I/O
TXD0
O
SSIO0
data
output
SSIO0
data
61
41
P74
P80
I/O Input/output port
I/O Input/output port
SOUT0
SIN0
O
I
I2C data
I/O input/out
put
29
32
SDA
input
SSIO0
synchro
nous
clock
input/out
put
SSIO0
data
output
I2C clock
I/O input/out
put
30
31
33
34
42
43
P81
P82
I/O Input/output port
I/O Input/output port
SCL
SCK0
I/O
O
SOUT0
13/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
48
52
64
Primary function
Secondary function
Tertiary function
Quaternary function
Pin Pin Pin
No. No. No.
Pin
name
Pin
De-
Pin
De-
Pin
De-
I/O
Description
I/O
I/O
I/O
name
scription
name
scription
name
scription
PWM5
output
32
33
35
36
44
45
P83
P84
I/O Input/output port
PWM5
O
UART1
data
input
SSIO0
data
input
SSIO0
synchro
nous
clock
input/out
put
I/O Input/output port
I/O Input/output port
RXD1
I
SIN0
I
UART1
data
output
34
37
46
P85
TXD1
O
SCK0
I/O
UART0
data
input
UART0
data
output
SSIO0
data
output
35
36
38
39
47
48
P86
P87
I/O Input/output port
I/O Input/output port
RXD0
TXD0
I
SOUT0
PWM4
O
O
PWM4
output
O
14/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
PIN DESCRIPTION
Primary/
Secondary/
Pin name
I/O
Description
Logic
Tertiary/
Quaternary
Power supply
VSS
—
—
—
Negative power supply pin
Positive power supply pin
—
—
—
—
VDD
VDDL
Positive power supply pin for internal logic (internally generated). Connect
capacitors (CL) (see Measuring Circuit 1) between this pin and VSS
—
—
.
Test
TEST0
I
I
Input/output pin for testing.
—
—
Positive
TEST1_N
System
RESET_N
Input/output pin for testing. This pin has a pull-up resistor built in.
Negative
I
Reset input pin. When this pin is set to a “L” level, the device is placed in system
reset mode and the internal circuit is initialized. If after that this pin is set to a “H”
level, program execution starts. This pin has a pull-up resistor built in.
—
Negative
XT0
XT1
I
Crystal connection pin for low-speed clock. A 32.768 kHz crystal oscillator (see
measuring circuit 1) is connected to this pin. Capacitors CDL and CGL are
connected across this pin and VSS as required.
—
—
—
—
—
O
LSCLK*
O
O
Low-speed clock output. This function is allocated to the secondary function of the Secondary
P20/P36/P65 pin.
OUTCLK*
High-speed clock output. This function is allocated to the secondary function of
the P21/P37/P66 pin.
Secondary
—
General-purpose input port
P00 to P05*
P12
I
General-purpose input or output ports.
I
I/O
I
Primary
Positive
Positive
P13
P14
General-purpose output port
P20 to P23
Secondary/
Tertiary/
O
General-purpose output ports. Provided with a secondary or tertiary or quaternary
function for each port. Cannot be used as ports if their secondary functions or
tertiary or quaternary are used.
Quaternary
General-purpose input/output port
Secondary/
Tertiary/
P30 to P37*
P40 to P47
P50 to P57*
P60 to P67*
P70 to P74*
P80 to P87
I/O General-purpose output ports. Provided with a secondary or tertiary or quaternary
Positive
function for each port. Cannot be used as ports if their secondary functions or
tertiary or quaternary are used.
Quaternary
*:ML620Q151B/ML620Q152B/ML620Q153B/ML620Q154B/ML620Q155B/ML620Q156B/ML620Q157B/
ML620Q158B/ ML620Q159B have a different pin configuration for each package. See “LIST OF PINS” for more
details.
15/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
Primary/
Secondary/
Logic
Pin name
I/O
Description
Tertiary/
Quaternary
UART
TXD0*
Secondary
Quaternary
UART0 data output pin. Allocated to the secondary function of the P43, P55 ,
P87 and the fourthly function of the P73.
O
I
Positive
UART0 data input pin. Allocated to the secondary function of the P02, P42,
P54 and P86.
RXD0*
TXD1*
Secondary Positive
Secondary
Positive
UART1 data output pin. Allocated to the secondary function of the P53, P73,
P85, and the fourthly function of the P43, P55.
O
I
Quaternary
UART1 data input pin. Allocated to the secondary function of the P03, P52,
P72 and P84.
RXD1*
Secondary Positive
I2C bus interface
SDA*
I2C data input/output pin. This pin is used as the secondary function of the
P40, P50, P60 and P80. This pin has an NMOS open drain output. When
using this pin as a function of the I2C, externally connect a pull-up resistor.
I/O
Secondary Positive
Secondary Positive
I2C clock output pin. This pin is used as the secondary function of the P41,
P51, P61 and P81. This pin has an NMOS open drain output. When using this
pin as a function of the I2C, externally connect a pull-up resistor.
SCL*
I/O
Synchronous serial (SSIO)
Synchronous serial data input pin. Allocated to the tertiary function of the
P40, P44, P50, P55, P72, P80 and P84.
SIN0*
I
Tertiary
Tertiary
Tertiary
Positive
—
Synchronous serial clock input/output pin. Allocated to the tertiary function of
the P41, P45, P51, P56, P73, P81 and P85.
SCK0*
SOUT0*
I/O
O
Synchronous serial data output pin. Allocated to the tertiary function of the
P42, P46, P52, P57, P74, P82 and P86.
Positive
PWM
PWM4 output pin. Allocated to the tertiary function of the P34, P43, P64 and
P87.
PWM4*
O
O
Tertiary
Tertiary
Positive
Positive
PWM5 output pin. Allocated to the tertiary function of the P35, P47, P65 and
P83.
PWM5*
PWM6*
Tertiary
PWM6 output pin. Allocated to the tertiary function of the P53, P66, P70 and
fourthly function of the P22 and P60.
O
O
Positive
Positive
Quaternary
PWM7*
Tertiary
PWM7 output pin. Allocated to the tertiary function of the P71 and fourthly
function of the P23, P57, and P61.
Quaternary
PW45EV0
PW45EV1
PW67EV0
PW67EV1
Control start /stop/clear for PWM4 and PWM5. Allocated to the primary
function of the P00, P30, P32 and P62.
I
I
Primary
Primary
—
—
Control start /stop/clear pin for PWM6 and PWM7. Allocated to the primary
function of the P01, P31, P33, and P63.
External clock input pin for timer 0 and PWM4. Allocated to the primary
function of the P44 pin.
T0P4CK
T1P5CK
I
I
Primary
Primary
—
—
External clock input pin for timer 1 and PWM5. Allocated to the primary
function of the P45 pin.
*:ML620Q151B/ML620Q152B/ML620Q153B/ML620Q154B/ML620Q155B/ML620Q156B/ML620Q157B/
ML620Q158B/ ML620Q159B have a different pin configuration for each package. See “LIST OF PINS” for more
details.
16/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
Primary/
Logic
Pin name
I/O
Description
Secondary
External interrupt
External maskable interrupt input pins. The interrupt is enabled and interrupt
edge is selectable by the software for each bit. Allocated to the primary
function of the P00 to P05 and P30 to P31.
EXI0～7*
Positive/
Negative
I
Primary
Timer
External clock input pin for 16bit timer 8, timer A and PWM6. Allocated to the
primary function of the P46 pin.
T16CK0
I
I
Primary
Primary
—
—
External clock input pin for 16bit timer 9, timer B and PWM7. Allocated to the
primary function of the P47 pin.
T16CK1
16bit timer A output pin. Allocated to the tertiary function of the P22 andn
P60.
TMHAOUT
O
O
Tertiary
Tertiary
Positive
Positive
TMHBOUT
LED drive
16bit timer B output pin. Allocated to the tertiary function of the P23 and P61.
LED0 to
LED3
Positive/
Negative
Pins for LED driving. Allocated to the primary function of the P20 to P23 pins.
O
Primary
Successive-approximation type A/D converter
Reference power supply pin for successive approximation type A/D
converter.
VREF
I
—
—
—
—
Analog inputs to Ch0–Ch11 of the successive-approximation type A/D
converter. Allocated to the secondary function of the P30 to P35 and P42 to
P47 pins.
AIN0 to
AIN11
I
Analog Comparator
Non-inverting input for comparator0. This pin is used as the primary function
of the P41 pin.
CMP0P
CMP0M
I
I
—
—
—
—
Inverting input for comparator0. This pin is used as the primary function of
the P40 pin.
*:ML620Q151B/ML620Q152B/ML620Q153B/ML620Q154B/ML620Q155B/ML620Q156B/ML620Q157B/
ML620Q158B/ ML620Q159B have a different pin configuration for each package. See “LIST OF PINS” for more
details.
17/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
TERMINATION OF UNUSED PINS
How to Terminate Unused Pins
Pin
Recommended pin termination
RESET_N
P14/TEST0
TEST1_N
VREF
open
open
open
Connect to VDD
Connect VDD or VSS
Connect VDD or VSS
open
P00 to P05*1
P12*2
P13*2
P20 to P23
P30 to P37*1
P40 to P47
P50 to P57*1
P60 to P67*1
P70 to P74*1
P80 to P87
open
open
open
open
open
open
open
*1:ML620Q151B/ML620Q152B/ML620Q153B/ML620Q154B/ML620Q155B/ML620Q156B/ML620Q157B/
ML620Q158B/ ML620Q159B have a different pin configuration for each package. See “LIST OF PINS” for more
details.
*2: Handling in the case a crystal resonator is not connected.
Note:
For unused input ports or unused input/output ports, if the corresponding pins are configured as high-impedance
inputs and left open, the supply current may become excessively large. Therefore, it is recommended to
configure those pins as either inputs with a pull-down resistor/pull-up resistor or outputs.
18/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(VSS = 0V)
Parameter
Power supply voltage 1
Power supply voltage 2
Reference voltage
Analog input voltage
Input voltage
Symbol
Condition
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Rating
Unit
V
VDD
VDDL
VREF
VAI
−0.3 to +6.5
−0.3 to +2.0
V
−0.3 to VDD+0.3
−0.3 to VDD+0.3
−0.3 to VDD+0.3
−0.3 to VDD+0.3
V
V
VIN
V
Output voltage
VOUT
Ta = 25°C
Port3,4,5,6,7,8
V
Output current 1
IOUT1
−12 to +11
mA
Ta = 25°C
Port2 Ta = 25°C
When N-channel open drain
output is selected
Ta = 25°C
Output current 2
(P20 to P23)
IOUT2
−12 to +20
mA
Power dissipation
PD
1
W
Storage temperature
TSTG
―
−55 to +150
°C
Recommended Operating Conditions
(VSS = 0V)
Parameter
Operating temperature
Operating voltage
Symbol
Condition
Range
−40 to +105
1.8 to 5.5
1.8 to VDD
Unit
°C
V
TOP
VDD
―
―
―
Reference voltage
VREF
V
Analog input voltage
VAI
fOP
fXTL
―
―
―
VSS to VREF
30k to 8.4M
32.768k
V
Operating frequency (CPU)
Low-speed crystal oscillation frequency
Hz
Hz
Use 32.768KHz Crystal
Oscillator DT-26
(DAISHINKU CORP.)
CDL
CGL
CV
12 to 25
12 to 25
Low-speed crystal oscillation
external capacitor
pF
Capacitor externally connected to VDD pin
Capacitor externally connected to VDDL pin
―
―
2.2±30% or more
2.2±30%
µF
µF
CL
19/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
Flash Memory Operating Conditions
(VSS = 0V)
Parameter
Operating temperature
Operating voltage
Symbol
TOP
Condition
Data flash memory, At write/erase
Flash ROM, At write/erase
At write/erase
Range
-40 to +105
0 to +40
1.8 to 5.5
10,000
100
Unit
°C
VDD
CEPD
CEPP
―
V
Data Flash
Program Flash
Chip erase
Maximum rewrite count *1
times
All area
8
―
Program Flash
Block erase
KB
KB
KB
Erase unit
Erase time
―
―
―
Data Flash
2
Sector erase (Data Flash only)
Chip erase, Block erase, Sector
1
100
ms
erase
Write unit
Write time (Max.)
Data retention period
―
―
YDR
―
1 word (2 Bytes)
―
1 word (2 Bytes)
―
µs
years
40
15
*1: One rewrite cycle includes both one time erase and one time write, it counts as one even if the erase is aborted.
DC Characteristics (IDD)
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Meas
Parameter
Symbol
IDD1
Condition
Min.
Typ.
Max. Unit uring
circuit
CPU is in STOP state.
-40 to +35℃
-40 to +105℃
-40 to +35℃
―
―
―
1.0
1.0
2.5
6
22
7
Supply current
1
Low-speed/high-speed oscillation is
stopped. VDD=3.0V
Crystal Oscillating. CPU is in HALT
state (LTBC,WBC: Operating*1).
High-speed oscillation is stopped.
VDD=3.0V
―
―
-40 to +105℃
-40 to +35℃
2.5
3.5
24
Supply current
2
µA
IDD2
IDD3
Internal RC Oscillating. CPU is in HALT
state (LTBC,WBC: Operating*1).
High-speed oscillation is stopped.
VDD=3.0V
9
1
―
-40 to +105℃
3.5
26
CPU: Running at 32kHz*2
High-speed oscillation is stopped.
VDD=3.0V
-40 to +35℃
―
―
13
13
20
42
Supply current
3
-40 to +105℃
Supply current
4
IDD4
IDD5
CPU: Running at 2MHz RC oscillating mode*2
VDD=5.0V
―
0.64
2.0
mA
8
Supply current
5
CPU: Running at 8.192MHz PLL oscillating mode*2
VDD=5.0V
―
5
*1 : Significant bits of BLKCON0, BLKCON2 to BLKCON4, BLKCON6 and BLKCON7 registers are all “1”.
*2: Case when the CPU operating rate is 100% (with no HALT state)
20/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
DC Characteristics (VOHL, IOHL)
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Measuring
circuit
Parameter
Symbol
VOH1
Condition
Min.
Typ.
Max.
Unit
Output voltage 1
(P20 to P23)
(P30 to P37)*
(P40 to P47)
(P50 to P57)*
(P60 to P67)*
(P70 to P74)*
(P80 to P87)
IOH1 = −0.5mA
1 pin output
VDD
−0.5
―
―
IOL1 = +0.5mA
1 pin output
―
0.5
VOL1
―
IOL2 = +10mA
VDD ≥ 5.0V
1 pin output
IOL2 = +8mA
VDD ≥ 3.0V
1 pin output
IOL3 = +3mA
VDD ≥ 2.0V
1 pin output
IOL3 = +2mA
2.0V > VDD ≥ 1.8V
1 pin output
―
―
―
―
―
―
0.5
0.5
0.4
When N-channel
VOL2 open drain output
is selected
V
2
Output voltage 2
(P20–P23)
Output voltage 3
(P40 to P41)
(P50 to P51)*
(P60 to P61)*
(P80 to P81)
When I2C mode
VOL3
is selected
VDD*
0.2
―
―
―
―
Output leakage
current
VOH = VDD
(in high-impedance state)
IOOH
IOOL
1
(P20 to P23)
(P30 to P37)*
(P40 to P47)
(P50 to P57)*
(P60 to P67)*
(P70 to P74)*
(P80 to P87)
µA
3
VOL = VSS
(in high-impedance state)
−1
―
―
*:ML620Q151B/ML620Q152B/ML620Q153B/ML620Q154B/ML620Q155B/ML620Q156B/ML620Q157B/
ML620Q158B/ ML620Q159B have a different pin configuration for each package. See “LIST OF PINS” for more details.
DC Characteristics (IIHL)
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Measuring
circuit
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Input current 1
(RESET_N)
(TEST1_N)
IIH1
IIL1
VIH1 = VDD
VIL1 = VSS
0
―
1
−1500
−300
−20
Input current 2
(P00 to P05)*
(P30 to P37)*
(P40 to P47)
(P50 to P57)*
(P60 to P67)*
(P70 to P74)*
(P80 to P87)
IIH2
IIL2
VIH2 = VDD (when pulled down)
VIL2 = VSS (when pulled up)
2
−250
―
30
−30
―
250
−2
1
µA
4
VIH2 = VDD
(in high-impedance state)
VIL2 = VSS
IIH2Z
IIL2Z
-1
―
―
(in high-impedance state)
*:ML620Q151B/ML620Q152B/ML620Q153B/ML620Q154B/ML620Q155B/ML620Q156B/ML620Q157B/
ML620Q158B/ ML620Q159B have a different pin configuration for each package. See “LIST OF PINS” for more details.
21/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
DC Characteristics (VIHL)
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Measuring
circuit
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Input voltage 1
(RESET_N)
(P14/TEST0)
(TEST1_N)
(P00 to P05)*
(P12, P13)
(P30 to P37)*
(P40 to P47)
(P50 to P57)*
(P60 to P67)*
(P70 to P74)*
(P80 to P87)
0.7×
VDD
VIH1
VIL1
―
―
VDD
V
5
0.3×
VDD
―
0
―
Input pin capacitance
(RESET_N)
(P14/TEST0)
(TEST1_N)
(P00 to P05)*
f = 10kHz
Vrms = 50mV
Ta = 25°C
(P12, P13)
(P30 to P37)*
(P40 to P47)
(P50 to P57)*
(P60 to P67)*
(P70 to P74)*
(P80 to P87)
CIN
―
―
10
pF
―
*:ML620Q151B/ML620Q152B/ML620Q153B/ML620Q154B/ML620Q155B/ML620Q156B/ML620Q157B/
ML620Q158B/ ML620Q159B have a different pin configuration for each package. See “LIST OF PINS” for more details.
22/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
DC Characteristics (LLD)
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Meas
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
uring
circuit
When power rising
1.85
1.8
1.98
1.9
2.1
2
LD1 to 0 = 0H
LD1 to 0 = 1H
LD1 to 0 = 2H
When power falling
When power rising
When power falling
When power rising
When power falling
When power rising
When power falling
―
VD-
2.5
2.63
2.55
3.78
3.7
2.75
2.65
3.9
3.8
4.4
4.3
―
2.45
3.65
3.6
LLD threshold voltage
Hysterisis
V
1
VD+
4.15
4.1
4.28
4.2
LD1 to 0 = 3H
―
―
Vhys
80
mV
mA
DC Characteristics (Analog Comparator)
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Meas
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
uring
circuit
CMPnM
VIN
VDD
-1.4
―
―
0
0
―
―
Common mode Input
voltage
V
CMPnP
VIN
VDD
1
Input offset voltage
Response time
―
―
―
100
1
VCMPOF
TCMP
5
mV
CMPnP = CMPnM ± 100mV
―
µS
23/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
Measuring circuit 1
CGL
XT0
XT1
CDL
32.768kHz
crystal
CGH
VDD VREF VDDL
VSS
A
CV
CL
CGL
CDL
：2.2μF
：2.2μF
：12pF
：12pF
CV
CL
32.768kHz Crystal oscillator
(DT-26 DAISHINKU Corp.)
Measuring circuit 2
(*2)
VIH
V
(*1)
VIL
VDD VDDL VREF
VSS
(*1) Input logic circuit to determine the specified measuring conditions.
(*2) Measured at the specified output pins.
24/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
Measuring circuit 3
(*2)
VIH
(*1)
A
VIL
VDDL VREF
VDD
VSS
(*1) Input logic circuit to determine the specified measuring conditions.
(*2) Measured at the specified output pins.
Measuring circuit 4
(*3)
A
VSS
VDD VDDL VREF
*3: Measured at the specified input pins.
Measuring circuit 5
VIH
(*1)
VIL
VSS
VDD VDDL VREF
*1: Input logic circuit to determine the specified measuring conditions.
25/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
AC Characteristics (Oscillation Circuit)
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Measur
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
ing
circuit
Low-speed crystal oscillation
start time*1
TXTL
―
―
0.6
2
s
Typ
-1%
Typ
-2.5%
Typ
-3%
Typ
-5%
Typ
Typ
+1%
Typ
+2.5%
Typ
+3%
Typ
+5%
Typ
Ta= +25°C
32.768k
32.768k
32.768k
2.097
Hz
Low-speed RC oscillator
frequency
fLCR
Ta= -40 to 85°C
Ta= -40 to 105°C
Ta= +25°C
Hz
Hz
1
MHz
MHz
MHz
High-speed RC oscillator
ferequency
fHCR
Ta= -40°C to +105°C
2.097
-15%
Typ
-1%
+15%
Typ
+1%
LSCLK=32.768kHz
2,048 clock average
PLL oscillation frequency
fPLL
8.192
*1: Use 32.768KHz Crystal Oscillator DT-26 (Daishinku) with capacitance CGL/CDL＝12pF.
AC Characteristics (Power On Reset Sequence)
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Measur
Parameter
Reset pulse width
Symbol
Condition
Min.
Typ.
Max.
Unit
ing
circuit
PRST
PNRST
TPOR
―
―
―
100
―
―
―
―
―
0.4
10
µs
Reset noise rejection pulse width
Power On Reset rising time
1
ms
―
When using RESET_N pin
0.9*VDD
VDD
VIL1
PRST
VIL1
VIL1
PRST
RESET_N
When using power on reset
1.8V
0V
VDD
TPOR
26/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
AC Characteristics (External Interrupt)
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Parameter
External interrupt disable
period
Symbol
TNUL
Condition
Interrupt: Enabled (MIE = 1),
CPU: NOP operation
Min.
2.5×
LSCLK
Typ.
Max.
3.5×
LSCLK
Unit
―
µs
EXI0 to EXI7
(Rising-edge interrupt)
tNUL
tNUL
tNUL
EXI0 to EXI7
(Falling-edge interrupt)
EXI0 to EXI7
(Both-edge interrupt)
27/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
AC Characteristics (Synchronous Serial Port)
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Parameter
SCK input cycle
(slave mode)
Symbol
tSCYC
Condition
Min.
10
Typ.
―
Max.
―
Unit
µs
High-speed oscillation stopped
During high-speed oscillation
500
―
―
ns
SCK output cycle
(master mode)
tSCYC
tSW
―
―
SCK(*1)
―
sec
High-speed oscillation stopped
During high-speed oscillation
4
―
―
―
―
µs
SCK input pulse width
(slave mode)
200
ns
SCK output pulse width
(master mode)
SOUT output delay time
(slave mode)
SOUT output delay time
(master mode)
SIN input setup time
(slave mode)
SCK(*1)
×0.4
SCK(*1)
×0.5
SCK(*1)
×0.6
―
―
―
―
sec
ns
tSW
tSD
tSD
tSS
―
―
80
―
―
―
180
80
ns
―
ns
SIN input setup time
(Master mode)
SIN input hold time
―
―
240
80
―
―
―
―
ns
ns
tSS
tSH
*1: Clock period selected by SnCK3–0 of the serial port n mode register (SIOnMOD1)
tSCYC
tSW
tSW
SCK0*
SOUT0*
SIN0*
tSD
tSD
tSS
tSH
*: Indicates the secondary function of the corresponding port.
28/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
AC Characteristics (I2C Bus Interface: Standard Mode 100kHz)
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Rating
Parameter
SCL clock frequency
Symbol
Condition
Unit
Min.
0
Typ.
Max.
100
fSCL
kHz
SCL hold time
tHD:STA
4.0
µs
(start/restart condition)
SCL ”L” level time
SCL ”H” level time
SCL setup time
(restart condition)
SDA hold time
SDA setup time
SDA setup time
(stop condition)
Bus-free time
tLOW
tHIGH
4.7
4.0
µs
µs
tSU:STA
4.7
µs
tHD:DAT
tSU:DAT
0
0.25
µs
µs
tSU:STO
tBUF
4.0
4.7
µs
µs
AC Characteristics (I2C Bus Interface: Fast Mode 400kHz)
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Rating
Parameter
SCL clock frequency
Symbol
Condition
Unit
Min.
0
Typ.
Max.
400
fSCL
kHz
SCL hold time
tHD:STA
0.6
µs
(start/restart condition)
SCL ”L” level time
SCL ”H” level time
SCL setup time
(restart condition)
SDA hold time
SDA setup time
SDA setup time
(stop condition)
Bus-free time
tLOW
tHIGH
1.3
0.6
µs
µs
tSU:STA
0.6
µs
tHD:DAT
tSU:DAT
0
0.1
µs
µs
tSU:STO
tBUF
0.6
1.3
µs
µs
Start
condition
Restart
condition
Stop
condition
SDA
SCL
tBUF
tSU:STO
tHD:STA
tLOW tHIGH
tSU:STA tHD:STA
tSU:DAT tHD:DAT
29/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
Characteristics of Successive Approximation Type A/D Converter
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Parameter
Resolution
Symbol
n
Condition
―
Min.
―
Typ.
―
Max.
10
Unit
bits
2.7V ≤ VREF ≤ 5.5V
2.2V ≤ VREF ＜ 2.7V
1.8V ≤ VREF ＜ 2.2V
SACK bit *1 = 1
2.7V ≤ VREF ≤ 5.5V
2.2V ≤ VREF ＜ 2.7V
1.8V ≤ VREF ＜ 2.2V
SACK bit *1 = 1
RI ≤ 5kΩ
−4
−6
―
+4
―
+6
Integral non-linearity error
INL
−10
―
+10
−3
−5
―
―
+3
+5
LSB
Differential non-linearity error
DNL
−9
―
+9
Zero-scale error
Full-scale error
Input impedance
A/D operating voltage
VOFF
FSE
RI
−6
−6
―
―
―
―
―
+6
+6
5k
RI ≤ 5kΩ
―
Ω
VREF
VREF ≤ VDD
2.7
5.5
V
SACK bit *1 = 0
SACK bit *1 = 1
SACK bit *1 = 0
SACK bit *1 = 1
―
―
―
―
13.5
43
―
―
―
―
PLL oscillation
mode
Conversion time
μs
tCONV
16
High-speed RC
oscillation mode
44
*1: Bit 1 of SA-ADC control register 0 (SADCON0)
VDD
Reference
voltage
VREF
VDDL
1μF
2.2μF
A
AIN0
to
AIN11
RI≤5kΩ
0.1μF
-
2.2μF
+
Analog input
VSS
30/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
PACKAGE DIMENSIONS
ML620Q151B/ML620Q152B/ML620Q153B Package Dimension (48pin TQFP)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name,
pin number, package code and desired mounting conditions (reflow method, temperature and times).
31/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
ML620Q154B/ML620Q155B/ML620Q156B Package Dimension (52pin TQFP)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name,
pin number, package code and desired mounting conditions (reflow method, temperature and times).
32/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
ML620Q157B/ML620Q158B/ML620Q159B Package Dimension (64pin QFP)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name,
pin number, package code and desired mounting conditions (reflow method, temperature and times).
33/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
ML620Q157B/ML620Q158B/ML620Q159B Package Dimension (64pin TQFP)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name,
pin number, package code and desired mounting conditions (reflow method, temperature and times).
34/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
REVISION HISTORY
Page
Document
No.
Date
Mar 30, 2017
Description
Previous Current
Edition
–
Edition
–
FEDL620Q150B-01
First Edition
35/36
FEDL620Q150B-01
ML620Q151B/2B/3B/4B/5B/6B/7B/8B/9B
Notes
1) The information contained herein is subject to change without notice.
2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can
break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure,
please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention
designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for any damages
arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor.
3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate
the standard usage and operations of the Products.The peripheral conditions must be taken into account when designing
circuits for mass production.
4) The technical information specified herein is intended only to show the typical functions of the Products and examples of
application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property rights
or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this document;
therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by
third parties, arising out of the use of such technical information.
5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication, consumer systems,
gaming/entertainment sets) as well as the applications indicated in this document.
6) The Products specified in this document are not designed to be radiation tolerant.
7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and
consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary
communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and
power transmission systems.
8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power
control systems, and submarine repeaters.
9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the
recommended usage conditions and specifications contained herein.
10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document.
However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have no
responsibility for any damages arising from any inaccuracy or misprint of such information.
11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.
For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no
responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.
12) When providing our Products and technologies contained in this document to other countries, you must abide by the
procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US
Export Administration Regulations and the Foreign Exchange and Foreign Trade Act.
13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor.
Copyright 2017 LAPIS Semiconductor Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku,
Yokohama 222-8575, Japan
http://www.lapis-semi.com/en/
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