ML620Q503_技术文档

FEDL620Q504-01

Issue Date: Mar. 13, 2015

ML620Q503/Q504

Ultra Low Power 16-bit Microcontroller

GENERAL DESCRIPTION

This LSI family is a high-performance 16-bit CMOS microcontroller into which rich peripheral circuits, such as

synchronous serial port, UART, I²C bus interface (master), supply voltage level detect circuit, RC oscillation

type A/D converter, and successive approximation type A/D converter are incorporated around 16-bit CPU

nX-U16/100.

The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe

line architecture parallel processing. The Flash ROM that is installed as program memory achieves low-voltage

low-power consumption operation (read operation) is most suitable for battery-driven applications. And, this LSI

has a data flash-memory fill area by a software which can be written in.

The on-chip debug function that is installed enables program debugging and programming.

FEATURES

• CPU

− 16-bit RISC CPU (CPU name: nX-U16/100)

− Instruction system: 16-bit instructions

− Instruction set:

Transfer, arithmetic operations, comparison, logic operations, multiplication/division,

bit manipulations, bit logic operations, jump, conditional jump, call return stack

manipulations, arithmetic shift, and so on

− Build-in On-Chip debug function

− Minimum instruction execution time

30.5 µs (@32.768 kHz system clock)

62.5ns (@16 MHz system clock)

• Built-in coprocessor for multiplication, division, and multiply-accumulate operations

− Signed or unsigned operation setting

− Multiplication: 16bit × 16bit (operation time 4 cycles)

− Division: 32bit / 16bit (operation time 8 cycles)

− Division: 32bit / 32bit (operation time 16 cycles)

− Multiply-accumulate (non-saturating): 16bit × 16bit + 32bit (operation time 4 cycles)

− Multiply-accumulate (saturating): 16bit × 16bit + 32bit (operation time 4 cycles)

• Internal memory

− Supports ISP function (re-writing the program memory area by software)

− Number of segments

Flash memory

Product name

SRAM

Program area^*

Data area

ML620Q503

ML620Q504

32KB (16K × 16bit)

64KB (32K × 16bit)

2KB (1K × 16bit)

6KB (3K × 16bit)

*: including 1KB of unusable test area

• Interrupt controller (INTC)

− 1 non-maskable interrupt sources (Internal source: 1)

− 37 maskable interrupt sources (Internal sources: 29, External sources: 8)

− Software interrupt (SWI): maximum 64 sources

− External interrupts and comparator allow edge selection and sampling selection

− Priority level (4-level) can be set for each interrupt

• Time base counter (TBC)

− Low-speed time base counter ×1 channel

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ML620Q503/Q504

• Timers (TMR)

− 8 bits × 8 channels

(Timer0-7: 16-bit × 4 configuration available by using Timer0-1 or Timer2-3, Timer4-5, Timer6-7)

− Selection of one shot timer mode is possible

− External clock can be selected as timer clock.

• Function Timers (FTM)

− 16-bit × 4 channels

− Equipped with the timer/capture/PWM functions using a 16-bit counter

− Timer start/stop function by software/event trriger(external pin or other timer)

− External pin can be selected as counter clock

− Capture function (the measurement such as the pulse width is possible using external trigger input)

− Two types of PWM with the same period and different duties and complementary PWM with the dead time

set can be output.

• Watchdog timer (WDT)

− Non-maskable interrupt and reset

− Free running

− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s when LSCLK = 32.768 kHz)

• Synchronous serial port (SSIOF/SSIO)

− without FIFOs (SSIO) : 1 channel

− with 4-byte transmits and receives FIFOs (SSIOF) : 1 channel

− Master/slave are selectable

− LSB first/MSB first are selectable

− 8-bit length/16-bit length are selectable

− Phase/Polarity of clock are selectable

− supports slave-select signal (only SSIOF)

• UART (UARTF/UART)

− without FIFOs (UART) : 1ch

− with 4-byte transmits and receives FIFOs (UARTF) : 1ch

− Full duplex buffer system

− Communication speed: Settable within the range of 2400bps to 115200bps.

− Programmable interface (data length, parity, stop bits selectable)

• I²C bus interface (I²C)

− Master function × 2 channel

− Fast mode (400 kbps), standard mode (100 kbps)

• General-purpose ports (PORT)

− Input port × 2, Input/output port × 36 channels

• Melody driver (MELODY)

− Tempo: 15 types

− Scale: 29 types (Melody sound frequency: 508 Hz to 10.922 kHz)

− Tone length: 63 types

− Buzzer output mode (4 output modes, 8 buzzer frequencies, 7duty levels at 4.096kHz /15 duty levels at

other buzzer frequencies)

• RC oscillation type A/D converter (RC-ADC)

− Time division × 2 channels

− 24-bit counter

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ML620Q503/Q504

• Successive approximation type A/D converter (SA-ADC)

− Input × 12 channels

− 12-bit A/D converter

− Starting by trigger of Timer/FTM function.

− Capacitive touch sense function

• Analog Comparator (CMP)

− Input × 2ch

− Common mode input voltage: 0.2V to V_DD－0.2V

− Input offset voltage: 30mV(max)

− Interrupt allow edge selection and sampling selection are selectable

• Voltage Level Supervisor (VLS)

− Threshold voltages: selectable from 9 levels

− interrupt or reset generate are selectable

• Low Level Detector(LLD)

− Judgement Voltage: 1.8V±0.2V

− Usable as low level detection reset

• Reset

− Reset by the RESET_N pin

− Reset by power-on detection

− Reset by overflow of watchdog timer (WDT)

− Reset by Voltage Leve Supervisor(VLS)

− Reset by Low Level Detector(LLD)

• Clock

− Low-speed clock: (This LSI can not guarantee the operation without low-speed clock)

− Crystal oscillation (32.768 kHz)

− External clock input (30kHz to 36kHz)

− Built-in RC oscillation (32.768kHz)

− High-speed clock:

− Crystal/Ceramic oscillation (16 MHz)

− External clock input (300kHz to 16 MHz)

− Built-in RC oscillation (16MHz)

• Power management

− HALT mode: Instruction execution by CPU is suspended. All peripheral circuits can keep in operating

states.

− HALT-H mode: Instruction execution by CPU is suspended. Stop of high-speed oscillation automatically.

All peripheral circuits can keep in operating states.

− DEEP-HALT mode: Instruction execution by CPU is suspended. Some peripheral circuits(Timer, LTB,

etc.) can keep in operating states.

− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral

circuits are stopped.)

− Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4,

1/8,1/16,1/32 of the oscillation clock)

− Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused

peripherals.

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FEDL620Q504-01

ML620Q503/Q504

• Shipment

− Die * Please contact our responsible sales person for the pad layout information.

− 48-pin plastic TQFP

Tray

ML620Q503-xxxTBZWAAL

ML620Q504-xxxTBZWAAL

Tape and Reel

ML620Q503-xxxTBZWABL

ML620Q504-xxxTBZWABL

• Guaranteed operating range

− Operating temperature (ambient) : −40°C to +85°C

− Operating voltage: V_DD= 1.8V to 3.6V

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FEDL620Q504-01

ML620Q503/Q504

BLOCK DIAGRAM

Block Diagram of ML620Q503/Q504

CPU (nX-U16/100)

ELR1~3

co-processor

(muldiv)

EPSW1~3

PSW

ECSR1~3

DSR/CSR

PC

GREG

0~15

LR

EA

SP

Timing

ALU

Controller

Program

Memory

BUS

Instruction

Decoder

Instruction

Register

Controller

(Flash)

On-Chip

ICE

32K/64Kbyte

Data-bus

INT

2

V_SS

SCK0

SIN0

Power

SSIO x 1

SOUT0

SSIOF x 1

RAM

V_DD

SCKF0

2K/6Kbyte

SINF0

SOUTF0

SSF0

V_DDL

V_DDX

Interrupt

RESET_N

RESET &

TEST0

Controller

INT

3

INT

1

TEST

RXD0

TXD0

RXDF0

TXDF0

TEST1_N

UART x 1

INT

WDT

TBC

UARTF x 1

XT0

XT1

OSC0

1

INT

3

INT

2

OSC1

LSCLKO

OUTCLK

OSC

SDA0

SCL0

SDA1

SCL1

I²C x 2

INT

8

LSCLKI

Timer

×8

INT

4

CLKIN

INT

1

TMOUT0-9

TMOUTA-F

TMCKI0-7

Function

Timer x 4

IN0

CS0

RS0

RT0

RCT0

RCM

IN1

CS1

RS1

RT1

RC-ADC

SA-ADC

INT

1

INT

1

MELODY

MD0

VLS

LLD

INT

8

INT

1

P00 to P05

PXT0 to PXT1

V_REF

P10 to P11

P20 to P23

P30 to P37

GPIO

AIN0 to AIN11

INT

2

CMP0P

CMP0M

P40 to P47

P50 to P57

Analog

Comparator

x 2

CMP1P

CMP1M

Figure 1. Block Diagram of ML620Q503/Q504

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ML620Q503/Q504

PIN CONFIGURATION

Pin Layout of ML620Q503/Q504 TQFP Package

P05 | RCM

P04 | RT0

P03 | AIN11 | RS0 | *3$

P02 | AIN10 | RCT0 | *2$

*4 | P54

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

18

17

16

15

14

13

*5 | P55

*6 | P56

*7 | P57

TEST0

P01 | AIN9 | CS0 | *1$

P00 | AIN8 | IN0 | *0$

P23 | AIN7 | RT1 | *7$

P22 | AIN6 | RS1 | *6$

P21 | AIN5 | CS1 | *5$

P20 | AIN4 | IN1 | *4$

V_SS

TEST1_N

V_DDL

V_DD

V_SS

V_DDX

LSCLKI | XT1 | PXT1

XT0 | PXT0

V_DD

External intteruput inputpin(EXI) can be assigned to P00-P05, PXT0-1, P20-P57.

*0 to *7 and *0$ to *7$ has following functions. But 0$-7$ has limited function. Please refer to the pin list.

*0 : SDA0, SOUT0, RXD0

*1 : SCL0, SIN0 , TXD0

*2 : SCK0, TMOUT ,TMCKI

*3 : MD0, TMOUT , TMCKI

*0$ : SOUT0, RXD0

*4 : SDA1, SOUTF0, RXDF0

*5 : SCL1, SINF0, TXDF0

*6 : LSCLKO,SCKF0, TMOUT, TMCKI

*7 : OUTCLK,SSF0, TMOUT, TMCKI

*4$ : SOUTF0, RXDF0

*1$ : SIN0 , TXD0

*5$ : SIN F0, TXDF0

*2$ : SCK0, TMOUT

*6$ : SCKF0, TMOUT

*3$ : MD0(P33 only), TMOUT

*7$ : SSF0, TMOUT

Figure 2. Pin Layout of ML620Q503/Q504 TQFP Package

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PIN LIST

1st Function

2nd/3rd/4th Function

PKG

No.

Pin name

I/O Reset State

Function

pin name I/O

function

pin name I/O

function

pin name I/O function

14,

45

Negative power supply

V_SS

－

13,

44

Positive power supply

V_DD

Power supply pin for

internal circuit

(internally generated)

43

46

12

V_DDL

Power supply pin for

internal circuit (internally

generated)

V_DDX

－

Reference voltage

input pin of SA-ADC

V_REF

I

Pull-up

Input

1

RESET_N

TEST1_N

TEST0

I

Reset input pin

－

Pull-up

Input

42

41

Input pin for testing

Pull-down Input/output pin

I/O

Input

for testing

Input port/

PXT0/

EXII0/

XT0

Input

disable

External interrupt/

Low-speed oscillation

port

48

47

I

－

Input-Output port/

External interrupt/

Low-speed oscillation

port

PXT1/

EXI1/

XT1/

Hi-Z

output

I/O

LSCLKI

Low-speed external

clock input

P00/

EXI00/

AIN8

Input-Output port/

External interrupt/

SA-ADC input

UART

data

input

Hi-Z

output

RC-ADC oscillation

input

19

20

21

22

23

24

2

I/O

IN0

CS0

RCT0

RS0

RT0

RCM

－

I

SOUT0

SIN0

SCK0

－

O

I

SSIO data output

SSIO data input

RXD0

TXD0

TMOUT0

TMOUT1

－

I

P01/

EXI01/

AIN9

Input-Output port/

External interrupt/

SA-ADC input

RC-ADC reference

capacitance

connection pin

UART

data

output

Hi-Z

output

O

－

O

－

RCADC

P02/

EXI02/

AIN10

Input-Output port/

External interrupt/

SA-ADC input

Hi-Z

output

resistor/capacitor

sensor connection

SSIO clock

input/output

FTM

output

I/O

－

P03/

EXI03/

AIN11

Input-Output port/

External interrupt/

SA-ADC input

RC-ADC reference

resistor connection

Hi-Z

output

FTM

output

－

RC-ADC

P04/

EXI04

Hi-Z

output

Input-Output port/

External interrupt

measurement

resistor sensor

connection pin

－

P05/

EXI05

Hi-Z

output

Input-Output port/

External interrupt

RC-ADC oscillation

monitor

－

Input-Output port/

High-speed oscillation

port

P10/

OSC0

Hi-Z

output

－

Input-Output port/

High-speed oscillation

port

High-speed external

clock input

P11/

OSC1/

CLKIN

Hi-Z

output

3

I/O

－

P20/

EXI20/

AIN4

Input-Output port/

External interrupt/

SA-ADC input

UARTF

data

input

Hi-Z

output

RC-ADC oscillation

input

SSIOF data

output

15

16

17

I/O

IN1

CS1

RS1

I

SOUTF0

SINF0

O

I

RXDF0

TXDF0

I

P21/

EXI21/

AIN5

Input-Output port/

External interrupt/

SA-ADC input

RC-ADC reference

capacitance

connection pin

UARTF

data

output

Hi-Z

output

O

SSIOF data input

O

P22/

EXI22/

AIN6

Input-Output port/

External interrupt/

SA-ADC input

RC-ADC reference

resistor connection

Hi-Z

output

SSIOF clock

input/output

FTM

output

SCKF0 I/O

TMOUT2

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FEDL620Q504-01

ML620Q503/Q504

1st Function

2nd/3rd/4th Function

PKG

No.

Pin name

I/O Reset State

Function

pin name I/O

function

RC-ADC

measurement

resistor sensor

connection pin

pin name I/O

function

pin name I/O function

FTM

P23/

EXI23/

AIN7

Input-Output port/

External interrupt/

SA-ADC input

Hi-Z

SSIOF select

input/output

18

4

I/O

RT1

SDA0

SCL0

－

O

I/O

O

SSF0

SOUT0

SIN0

I/O

O

I

TMOUT3

O

output

P30/

EXI30/

CMP0P

Input-Output port/

External interrupt/

Comparator plus input

UART

data

Hi-Z

output

I²C data

input/output

SSIO data output

SSIO data input

RXD0

I

input

Input-Output port/

External interrupt/

Comparator minus

input

P31/

EXI31/

CMP0M

UART

data

output

Hi-Z

output

5

I²C clock output

TXD0

O

I

P32/

EXI32/

CMP1P

Input-Output port/

External interrupt/

Comparator plus input

Hi-Z

output

SSIO clock

input/output

FTM

output

6

－

O

－

SCK0

－

I/O

－

O

I

TMOUT4

TMOUT5

RXDF0

TXDF0

TMOUT6

TMOUT7

RXD0

Input-Output port/

External interrupt/

Comparator minus

input

P33/

EXI33/

CMP1M

Hi-Z

output

Melody/Buzzer

output

FTM

output

7

MD0

SDA1

SCL1

－

P34/

EXI34/

AIN0

Input-Output port/

External interrupt/

SA-ADC input

UARTF

data

input

Hi-Z

output

I²C data

input/output

SSIOF data

output

8

I/O

O

SOUTF0

SINF0

P35/

EXI35/

AIN1

Input-Output port/

External interrupt/

SA-ADC input

UARTF

data

output

Hi-Z

output

9

I²C clock output

SSIOF data input

O

I

P36/

EXI36/

AIN2

Input-Output port/

External interrupt/

SA-ADC input

Hi-Z

output

SSIOF clock

input/output

FTM

output

10

11

25

26

－

I/O

O

－

SCKF0 I/O

P37/

EXI37/

AIN3

Input-Output port/

External interrupt/

SA-ADC input

Hi-Z

output

SSIOF select

input/output

FTM

output

－

SSF0

SOUT0

SIN0

I/O

O

I

P40/

EXI40/

LED

Input-Output port/

External interrupt/

LED output

UART

data

Hi-Z

output

I²C data

input/output

SDA0

SCL0

SSIO data output

SSIO data input

input

P41/

EXI41/

LED

Input-Output port/

External interrupt/

LED output

UART

data

Hi-Z

output

I²C clock output

TXD0

O

output

P42/

EXI42/

TMCKI0

Input-Output port/

External interrupt/

Timer clock input

Hi-Z

output

SSIO clock

input/output

FTM

output

27

28

I/O

－

SCK0

I/O

TMOUT8

TMOUT9

O

P43/

EXI43/

TMCKI1

Input-Output port/

External interrupt/

Timer clock input

Hi-Z

output

Melody/Buzzer

output

FTM

output

MD0

O

－

UARTF

data

input

P44/

EXI44

Hi-Z

output

Input-Output port/

External interrupt

I²C data

input/output

SSIOF data

output

29

30

31

I/O

SDA1

SCL1

I/O

O

SOUTF0

SINF0

O

I

RXDF0

TXDF0

I

UARTF

data

output

P45/

EXI45

Hi-Z

output

Input-Output port/

External interrupt

I²C clock output

SSIOF data input

O

P46/

EXI46/

TMCKI2

Input-Output port/

External interrupt/

Timer clock input

Hi-Z

output

Low-speed clock

output

SSIOF clock

input/output

FTM

output

LSCLKO

O

SCKF0 I/O

TMOUTA

P47/

EXI47/

TMCKI3

Input-Output port/

External interrupt/

Timer clock input

Hi-Z

output

High-speed clock

output

SSIOF select

input/output

FTM

output

32

33

34

I/O

OUTCLK

SDA0

O

I/O

O

SSF0

SOUT0

SIN0

I/O

O

I

TMOUTB

RXD0

O

I

UART

data

input

P50/

EXI50

Hi-Z

output

Input-Output port/

External interrupt

I²C data

input/output

SSIO data output

SSIO data input

UART

data

output

P51/

EXI51

Hi-Z

output

Input-Output port/

External interrupt

SCL0

I²C clock output

TXD0

O

P52/

EXI52/

TMCKI4/

LED

Input-Output port/

External interrupt/

Timer clock input/

LED output

Hi-Z

output

SSIO clock

input/output

FTM

output

35

36

I/O

－

SCK0

I/O

TMOUTC

TMOUTD

O

P53/

EXI53/

TMCKI5/

LED

Input-Output port/

External interrupt/

Timer clock input/

LED output

Hi-Z

output

Melody/Buzzer

output

FTM

output

MD0

O

－

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FEDL620Q504-01

ML620Q503/Q504

1st Function

2nd/3rd/4th Function

PKG

No.

Pin name

I/O Reset State

Function

pin name I/O

function

I²C data

pin name I/O

function

pin name I/O function

UARTF

P54/

EXI54

Hi-Z

Input-Output port/

External interrupt

SSIOF data

output

37

38

I/O

SDA1

SCL1

I/O

O

SOUTF0

SINF0

O

I

RXDF0

I

data

output

input/output

input

UARTF

data

P55/

EXI55

Hi-Z

Input-Output port/

External interrupt

I²C clock output

SSIOF data input

TXDF0

O

output

P56/

EXI56/

TMCKI6

Input-Output port/

External interrupt/

Timer clock input

Hi-Z

output

Low-speed clock

output

SSIOF clock

input/output

FTM

output

39

40

I/O

LSCLKO

OUTCLK

O

SCKF0 I/O

TMOUTE

TMOUTF

O

P57/

EXI57/

TMCKI7

Input-Output port/

External interrupt/

Timer clock input

Hi-Z

output

High-speed clock

output

SSIOF select

input/output

FTM

output

SSF0

I/O

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PIN DESCRIPTION

The pin name represents the function pin name of the primary function of each terminal, The pin mode

represents the set of mode register of Port Control.

(1^st:primary function, 2^nd:secondary function, 3^rd: tertiary function, 4^th: quartic function)

Pin mode

—

Pin name

System

I/O

I

Description

LSI pin name

RESET_N

Logic

L

Reset input pin. When this pin is set to a “L” level,

system reset mode is set and the internal section

is initialized. When this pin is set to a “H” level

subsequently, program execution starts. A pull-up

resistor is internally connected.

RESET_N

Crystal connection pin for low-speed clock.

Capacitors C_DLand C_GLare connected across

this pin and V_SSas required.

PXT0

PXT1

XT0

XT1

I

1st

—

O

External clock input for Low-speed clock.

PXT1

P10

LSCLKI

OSC0

OSC1

I

1st

—

Crystal/ceramic connection pin for high-speed

clock

(16 MHz max.). Capacitors C_DHand C_GHare

connected across this pin and V_ss.

O

P11

CLKIN

LSCLKO

OUTCLK

I

External clock input for High-speed clock.

Low-speed clock output pin.

P11

P46,P56

P47,P57

1st

2nd

—

O

High-speed clock output pin.

General-purpose input/output port

General-purpose input port(without

pull-up/pull-down resister).

PXT0-PXT1

I

PXT0-

PXT1

1st

—

General-purpose input/output port.

P00-P05

P10-P11

P20-P23

P30-P37

P40-P47

P50-P57

I/O

P00-P05

P10-P11

P20-P23

P30-P37

P40-P47

P50-P57

1st

—

External interrupt

EXII0-EXII1

EXI00-05

EXI20-23

EXI30-37

EXI40-47

EXI50-57

LED

External maskable interrupt input pins. It is

possible, for each bit, to specify

whether the interrupt is enabled and select the

interrupt edge by software.

I

PXT0-PXT1

P00-P05

P20-P23

P30-P37

P40-P47

P50-P57

1st

H/L

N-channel open drain output pins to drive LED.

Melody/buzzer signal output pin.

—

H

LED

O

P40,P41,P52,P53

P33,P43,P53

1st

Melody/Buzzer

MD0

UART

—

2nd

UART0 data output pin.

P01,P31,P41,P51

P00,P30,P40,P50

P21,P35,P45,P55

P20,P34,P44,P54

TXD0

RXD0

O

I

4th

—

UART0 data input pin.

UART with FIFO data output pin.

UART with FIFO data input pin.

TXDF0

RXDF0

O

I

10/34

FEDL620Q504-01

ML620Q503/Q504

Description

LSI pin name

P30,P40,P50

Pin name

I²C bus interface

SDA0

I/O

Pin mode Logic

I²C0 data input/output pin. This pin has an NMOS

open drain output. When using this pin as a

function of the I²C, externally connect a pull-up

resistor.

I/O

2nd

—

I²C0 clock output pin.

P31,P41,P51

P34,P44,P54

P35,P45,P55

SCL0

SDA1

SCL1

O

I/O

O

This pin has an NMOS open drain output. When

using this pin as a function of the I²C, externally

connect a pull-up resistor.

I²C1 data input/output pin. This pin has an NMOS

open drain output. When using this pin as a

function of the I²C, externally connect a pull-up

resistor.

I²C1 clock output pin. This pin has an NMOS open

drain output. When using this pin as a function of

the I²C, externally connect a pull-up resistor.

Synchronous serial

Synchronous serial(SSIO) clock input/output pin.

Synchronous serial(SSIO) data input pin.

Synchronous serial(SSIO) data output pin.

P02,P32,P42,P52

P01,P31,P41,P51

P00,P30,P40,P50

P22,P36,P46,P56

SCK0

I/O

3rd

—

SIN0

I

SOUT0

SCKF0

O

Synchronous serial with FIFO(SSIOF) clock

I/O

input/output pin.

Synchronous serial with FIFO(SSIOF) data input

pin.

Synchronous serial with FIFO(SSIOF) data output P20,P34,P44,P54

pin.

Synchronous serial with FIFO(SSIOF) select

input/output pin.

P21,P35,P45,P55

SINF0

SOUTF0

SSF0

I

3rd

—

L

O

P23,P37,P47,P57

I/O

FTM

FTM output pin.

TMOUT0-9

TMOUTA-F

O

I

P02,P03,P22,P23

P32,P33,P36,P37,

P42,P43,P46,P47

P52,P53,P56,P57

P42,P43,P46,P47,

P52,P53,P56,P57

4th

1st

—

External clock input pin for FTM

TMCKI0-7

RC oscillation type A/D converter

Channel 0 oscillation input pin.

P00

P01

P03

P04

IN0

CS0

RS0

RT0

I

2nd

—

Channel 0 reference capacitor connection pin.

Reference resistor connection pin of Channel 0.

O

Resistor sensor connection pin of Channel 0 for

measurement.

Resistor/capacitor sensor connection pin of

Channel 0 for measurement.

—

P02

RCT0

O

2nd

RC oscillation monitor pin.

P05

P20

P21

P22

P23

RCM

IN1

O

I

2nd

—

Oscillation input pin of Channel 1.

Reference capacitor connection pin of Channel 1.

Reference resistor connection pin of Channel 1.

CS1

RS1

RT1

O

Resistor sensor connection pin for measurement

of Channel 1.

—

11/34

FEDL620Q504-01

ML620Q503/Q504

Description

Successive approximation type A/D converter

LSI pin name

V_REF

Pin name

I/O

Pin mode Logic

Reference voltage input pin for successive

approximation type A/D converter.

Channel 0 analog input for successive

approximation type A/D converter.

—

V_REF

I

—

P34,P35,P36,P37,

P20,P21,P22,P23,

P00,P01,P02,P03

1st

AIN0-11

I

Analog comparator

Comparator0 Non-inverted input pin.

Comparator0 Inverted input pin.

Comparator1 Non-inverted input pin.

Comparator1 Inverted input pin.

P30

P31

P32

P33

1st

CMP0P

CMP0M

CMP1P

CMP1M

I

—

For testing

TEST0

Input/output pin for testing. A pull-down resistor is

internally connected.

Input pin for testing. A pull-up resistor is internally

connected.

TEST0

—

I/O

I

—

TEST1_N

Power supply

V_SS

Negative power supply pin.

Positive power supply pin.

V_SS

V_DD

—

V_DD

Positive power supply pin (internally generated)

for internal logic. Capacitors C_L0and C_L1are

V_DDL

connected between this pin and V_SS

.

Positive power supply pin (internally generated)

for low-speed oscillation. Capacitor C_X1is

V_DDX

—

V_DDX

—

connected between this pin and V_SS

.

12/34

FEDL620Q504-01

ML620Q503/Q504

TERMINATION OF UNUSED PINS

Table 1 shows methods of terminating the unused pins.

Table 1 Termination of Unused Pins

Recommended pin termination

RESET_N

TEST0

open

TEST1_N

V_REF

open

Connect to V_DD

open

P00 to P05

PXT0 to PXT1

P10 to P11

P20 to P23

P30 to P37

P40 to P47

P50 to P57

open

Note:

For unused input ports or unused input/output ports, if the corresponding pins are configured as high-impedance

inputs and left open, the supply current may become excessively large. Therefore, it is recommended to

configure those pins as either inputs with a pull-down resistor/pull-up resistor or outputs.

13/34

FEDL620Q504-01

ML620Q503/Q504

ELECTRIC CHARACTERISTICS

Absolute Maximum Ratings

(V_SS=0V)

Unit

Parameter

Power supply voltage 1

Power supply voltage 2

Power supply voltage 3

Input voltage

Symbol

V_DD

Condition

Ta=25°C

Rating

-0.3 to +4.6

-0.3 to +2.0

-0.3 to V_DD+0.3

-12 to +11

V

V_DDL

V_DDX

V_IN

Ta=25°C

V

Ta=25°C

V

Ta=25°C

Output voltage

V_OUT

I_OUT1

I_OUT2

PD

V

Ta=25°C

Output current 1

mA

W

°C

Port 0 to 2 Ta=25°C

Port 3 to 5 Ta=25°C

Ta=25°C

Output current 2

-12 to +20

Power dissipation

Storage temperature

0.9

T_STG

―

-55 to +150

14/34

FEDL620Q504-01

ML620Q503/Q504

Recommended Operating Conditions

(V_SS=0V)

Unit

Parameter

Symbol

T_OP

Condition

Range

Operating temperature

(Ambience)

―

-40 to +85

°C

Operating voltage

Reference voltage

V_DD

―

1.8 to 3.6

1.8 to V_DD

V

V_REF

Operating frequency

（CPU）

Low-speed

external clock input

High-speed

external clock input

Low speed crystal

oscillation frequency

Low speed crystal

oscillation external

capacitor 1

30k to 16.8M

30k to 36k

f_OP

Hz

f_EXTL

f_EXTH

―

300k to 16M

f_XTL

C_DL

C_GL

C_DL

C_GL

C_DL

C_GL

32.768k

6.8 to 12

12 to 16

12 to 22

Using VT-200-FL(from SII）

Using DT-26(from Daishinku)

Using VT-200-F(from SII）

―

pF

Hz

pF

Low speed crystal

oscillation external

capacitor 2

Low speed crystal ^*1

oscillation external

capacitor 3

High speed Crystal/

Ceramic oscillation

frequency

High speed crystal

oscillation external

capacitor

f_XTH

16M

C_DH

C_GH

C_DH

C_GH

12 to 20

Using NX8045GB

(from Nihon Denpa Kogyo)

Using FCSTCE16M0V53

(from Murata manufacturing)

Build in CL type

0 to 5

Ceramic oscillation

External capacitor

V_DDLexternal capacitor

C_L

C_X

2.2 ± 30%

μF

ESR ≦ 500mΩ

*2

V_DDXexternal capacitor

―

0.33 ± 30%

*1：Please use this crystal except DEEPHALT mode because this LSI may not be functioning at DEEPHALT mode with the crystal.

Please evaluate the matching when other crystal oscillator/ ceramic oscillator is used.

*2：Please evaluate on user’s conditions, put on C_L0( = 0.1uF) if necessary.

15/34

FEDL620Q504-01

ML620Q503/Q504

Operating Conditions of Flash Memory

(V_SS= 0V)

Unit

Parameter

Symbol

T_OP

Condition

Range

Data area : write/erase

-40 to +85

0 to +40

1.8 to 3.6

10,000

°C

Operating temperature

(Ambience)

Program area : write/erase

Write/erase

V_DD

C_EPD

C_EPP

V

Operating voltage

Write time

Data area (1,024B x 2)

Program area

times

100

Program area

Block erase

8

2

KB

Data area

Erase unit

―

Sector erase

Block erase/Sector erase

―

1

KB

ms

―

100

Erase time(Maximum)

―

1 word (2 byte)

Write unit

16/34

FEDL620Q504-01

ML620Q503/Q504

AC characteristics (Oscillation, reset)

(V_DD=1.8 to 3.6V, V_SS=0V, Ta=-40 to +85°C , unless otherwise specified)

Rating

Measuring

circuit

Parameter

Symbol

Condition

Unit

Max.

2

Min.

Typ.

Low speed crystal

oscillation start time

T_XTL

―

s

High speed crystal

oscillation start time

T_XTH

―

20

ms

typ

-1.5%

typ

+1.5%

Ta=25°C

32.768

16

Low speed built-in RC

oscillation frequency^*1*2

f_LCR

kHz

typ

-5%

typ

+5%

Ta=-40 ~

85°C

typ

-1%

typ

+1%

Ta=25°C

1

High speed build-in RC

oscillation frequency^*1*2

f_HCR

MHz

us

typ

-5%

typ

+5%

Ta=-40 to

85°C

16

―

Reset pulse width

P_RST

―

200

―

Reset noise elimination

pulse width

0.3

10

P_NRST

―

us

Power-on reset

activation

–

T_POR

ms

power rise time

*1 : Mean value of 1024 cycle.

*2 : Guarantee value at the time of the shipment.

0.9*V_DD

V_DD

0.3*V_DD

RESET_N

P_RST

External reset sequence

0.9*V_DD

V_DD

0.1*V_DD

T_POR

Power on reset sequence

17/34

FEDL620Q504-01

ML620Q503/Q504

DC Characteristics (IDD)

(V_DD=1.8 to 3.6V, V_SS=0V, Ta=-40 to +85°C, unless otherwise specified)

Rating^*1

Measuring

Parameter Symbol

Condition

unit

circuit

Min. Typ. Max.

Ta=25°C

―

0.25 0.8

15

CPU is Stopped

Low/High-speed oscillation is

stopped

Power

IDD1

μA

Ta=-40 to

85°C

consumption 1

―

DEEP-HALT mode *³*⁵

(LBTC function)

Ta=25°C

―

0.45 1.3

Low-speed crystal oscillating

(32.768kHz)

Power

IDD2

μA

consumption 2

Ta=-40 to

85°C

―

15

High-speed oscillation is

stopped

HALT mode *³*⁵

(LTBC function)

Ta=25°C

2

2.7

Power

IDD3

Low-speed crystal oscillating

(32.768kHz)

μA

consumption 3

Ta=-40 to

85°C

1

―

10

―

18

12

25

High speed oscillation is

stopped.

CPU Low-speed *²*⁵

Low-speed built-in CR

oscillating

Ta=25°C

Power

IDD4

Ta=-40 to

85°C

consumption 4

High speed oscillation is

stopped.

CPU High-speed(16MHz) *²*⁵

High-speed Built-in CR

oscillating

CPU High-speed(16MHz) *²*⁴*⁵

High speed crystal oscillating

(16MHz)

Ta=25°C

―

4

―

6

5.5

6

Power

IDD5

mA

Ta=-40 to

85°C

consumption 5

Ta=25°C

7.5

8

Power

IDD6

Ta=-40 to

85°C

consumption 6

―

*¹: typ.rating is V_DD=3.0V

*²: at CPU activity rate =100%（No HALT state）

*³: Using 32.768KHz crystal oscillator VT-200-FL (from SII)(C_GL/C_DL＝12pF)

Using 32.768KHz crystal oscillator DT-26(from Daishinku)(C_GL/C_DL＝12pF)

*⁴: Using NX8045GB(from Nihon denpa kogyo) (C_GH/C_DH＝16pF)

*⁵: BLKCON0~BLKCON5 valid bits are all “1”.

18/34

FEDL620Q504-01

ML620Q503/Q504

DC Characteristics (VLS)

(V_DD=1.8 to 3.6V, V_SS=0V, Ta=-40 to +85°C, unless otherwise specified)

Rating

Measuring

circuit

Parameter

Symbol

Condition

unit

Min.

Typ.

Max.

1.798 1.898 1.998

1.900 2.000 2.100

1.993 2.093 2.193

2.096 2.196 2.296

2.209 2.309 2.409

2.309 2.409 2.509

2.505 2.605 2.705

2.700 2.800 2.900

2.968 3.068 3.168

vlscon = 3H

vlscon = 4H

vlscon = 5H

vlscon = 6H

vlscon = 7H

vlscon = 8H

vlscon = 9H

vlscon = AH

vlscon = BH

VLS judge

voltage

(V_DD=fall)

V

1

V_VLS

x

1.8%

V_VLS

x

3.8%

V_VLS

x

6.3%

V_VLShysteresis

width (V_DD=rise)

V

H^VLS

―

DC characteristics (LLD)

(V_DD=1.8 to 3.6V, V_SS=0V, Ta=-40 to +85°C, unless otherwise specified)

Rating

Measuring

circuit

Parameter

Symbol

VLLR

Condition

Unit

V

Min.

1.60

Typ.

Max.

2.00

LLD judge

Voltage

―

1

1.80

DC characteristics (Analog comparator)

(V_DD=1.8 to 3.6V, V_SS=0V, Ta=-40 to +85°C, unless otherwise specified)

Rating

Typ.

Measuring

circuit

Parameter

Symbol

Condition

Unit

Min.

0.2

Max.

Common input

voltage range

V_DD

-0.2

V_CMPIN

V_CMPOF

T_CMP

―

V

Input offset

voltage

Comparator

judge time

1

―

-30

30

2

mV

µs

CMPP- CMPM =40mV

―

19/34

FEDL620Q504-01

ML620Q503/Q504

DC characteristics (VOHL, IOHL)

(V_DD=1.8 to 3.6V, V_SS=0V, Ta=-40 to +85°C, unless otherwise specified)

Rating

Measuring

circuit

Parameter

Symbol

VOH1

Condition

Unit

Min.

Typ.

Max.

V_DD

-0.5

1.8V ≦ V_DD≦ 3.6V

―

Output voltage 1

(P00-P05, P10-P11

P20-P23, P30-P37

P40-P47, P50-P57)

IOH=-1mA

1.8V ≦ V_DD≦ 3.6V

VOL1

VOL2

―

0.4

IOL=+0.5mA

Output voltage 2

(P40,P41, P52,

P53)

2.7V ≦ V_DD≦ 3.6V

―

0.6

0.4

IOL=+5.0mA

1.8V ≦ V_DD< 2.7V

(LED mode

is selected)

IOL=+2.0mA

Output voltage 3

(P30,P31, P34,

P35,

P40, P41, P44, P45,

P50, P51, P54, P55)

(I²C mode is

selected)

2

V

IOL3= +3mA（I²Cspec）

（V_DD≧ 2V）

VOL3

―

0.4

Output voltage 4

(P30, P31, P34,

P35, P40, P41, P44,

P45, P50, P51, P54,

P55)

IOL3= +2mA（I²Cspec）

（V_DD< 2V）

V_DD

×0.2

VOL4

(I²C mode is

selected)

Output leak 1

VOH=V_DD(at high impedance)

―

+1

IOOH1

(P00-P05,P20-P23,

P30-P37,P40-P47,

P50-P57)

IOOL1 VOL=V_SS(at high impedance)

-1

―

μA

3

IOOH2 VOH=V_DD(at high impedance)

IOOL2 VOL=V_SS(at high impedance)

―

+2

Output leak 2

(P10-P11)

-2

―

20/34

FEDL620Q504-01

ML620Q503/Q504

DC characteristics (IIHL)

(V_DD=1.8 to 3.6V, V_SS=0V, Ta=-40 to +85°C, unless otherwise specified)

Rating^*1

Measuring

circuit

Parameter

Symbol

Condition

Unit

Min.

Typ.

Max.

1

Input current 1

(RESET_N,

TEST1_N)

IIH1

VIH1=V_DD

―

IIL1

IIH2

IIL2

IIH3

IIL3

VIL1=V_SS

VIH2=V_DD

-900

20

-300

300

―

-20

900

―

Input current 2

(TEST0)

VIL2=V_SS

-1

VIH3=V_DD(at pull down)

VIL3=V_SS(at pull up)

1

15

200

-1

Input current 3

(PXT0-PXT1,

P00-P05,

P20-P23,

P30-P37,

P40-P47,

P50-P57)

-200

-15

VIH3=V_DD

(at high impedance)

VIL3=V_SS

IIH3Z

IIL3Z

―

1

4

µA

-1

―

(at high impedance)

IIH4

IIL4

VIH4=V_DD(at pull down)

VIL4=V_SS(at pull up)

1

15

200

-1

-200

-15

Input current 4

(P10-P11)

VIH4=V_DD

(at high impedance)

VIL4=V_SS

IIH4Z

―

2

IIL4Z

-2

―

(at high impedance)

*¹: typ.rating is Ta=25°C , V_DD=3.0V

DC characteristics (VIHL)

(V_DD=1.8 to 3.6V, V_SS=0V, Ta=-40 to +85°C, unless otherwise specified)

Rating

Measuring

circuit

Parameter

Symbol

Condition

unit

Min.

Typ.

Max.

Input voltage 1

(RESET_N,

TEST0,

TEST1_N,

PXT0-PXT1,

P00-P05,

0.7

×V_DD

VIH1

VIL1

―

V_DD

5

V

P10-P11,

P20-P23,

P30-P37,

P40-P47,

0.3

×V_DD

―

0

―

P50-P57)

Input terminal

capacitance

(RESET_N,

TEST0,

TEST1_N,

PXT0-PXT1,,

P00-P05,

f=10kHz

―

V_rms=50mV

CIN

―

10

pF

Ta=25°C

P10-P11,

P20-P23,

P30-P37,

P40-P47,

P50-P57)

21/34

FEDL620Q504-01

ML620Q503/Q504

Measuring circuit

Measuring circuit 1

C_GL

C_DL

XT0

XT1

32.768kHz

Crystal

Oscillator

C_GH

C_DH

OSC0

OSC1

16MHz

V_SS

V_DDV_REF

V_DDL

V_DDX

Crystal

Oscillator

C_V

C_L

:

1.0μF

2.2μF

A

C_X

: 0.33μF

C_V

C_X

C_L

C_GL

C_DL

C_GH

C_DH

:

12pF

16pF

32.768kHz crystal oscillator : DT-26 (from Daishinku)

16MHz crystal oscillator

: NX8045GB (from Nihon denpa kogyo)

Measuring circuit 2

(*2)

VIH

(*1)

V

VIL

V_DDX

V_SS

V_DDV_DDLV_REF

(*1) Input logic circuit to determine the specified measuring conditions.

(*2) Measured at the specified output pins.

22/34

FEDL620Q504-01

ML620Q503/Q504

Measuring circuit 3

(*2)

A

VIH

(*1)

VIL

V_DDL

V_REFV_DDX

V_SS

V_DD

(*1) Input logic circuit to determine the specified measuring conditions.

(*2) Measured at the specified output pins.

Measuring circuit 4

(*3)

A

V_DD

V_DDL

V_REF

V_DDX

V_SS

(*3) Measured at the specified output pins.

23/34

FEDL620Q504-01

ML620Q503/Q504

Measuring circuit 5

VIH

(*1)

VIL

V_DDX

V_SS

V_DDV_DDL

V_REF

(*1) Input logic circuit to determine the specified measuring conditions.

24/34

FEDL620Q504-01

ML620Q503/Q504

AC characteristics (external interrupt)

(V_DD=1.8 to 3.6V, V_SS=0V, Ta=-40 to +85°C, unless otherwise specified)

Rating

Parameter

Symbol

t_NUL

Condition

unit

Min.

Typ.

Max.

Interruput enable (MIE=1)

CPU : NOP operation

2.5 x

3.5 x

External interrupt disable

period

―

φ

sysclk

EXI0-7

(Rising-edge interrupt)

t_NUL

EXI0-7

(Falling-edge interrupt)

(Both-edge interrupt)

t_NUL

EXI0-7

t_NUL

25/34

FEDL620Q504-01

ML620Q503/Q504

AC characteristics (synchronous serial port)

(V_DD=1.8 to 3.6V, V_SS=0V, Ta=-40 to +85°C, unless otherwise specified)

Rating

Parameter

Symbol

Conditon

unit

Min.

10

Typ.

Max.

High-speed oscillation

is not active

―

μs

ns

s

SCK input cycle

(slave mode)

t_SCYC

t_SW

High speed oscillation is

active

500

―

SCK*¹

―

SCK output cycle

(master mode)

―

High-speed oscillation

is not active

4

μs

ns

SCK input pulse width

(slave mode)

High speed oscillation is

active

200

―

SCK output pulse

width

t_SCYC

×0.4

t_SCYC

×0.5

t_SCYC

×0.6

t_SW

t_SD

―

s

(master mode)

SOUT output delay

time

―

180

80

ns

(slave mode)

SOUT output delay

time

(master mode)

SIN input

Setup time

(slave mode)

SINinput

t_SS

―

50

―

ns

t_SH

Hold time

*1：The clock period which is selected by the below registers(min:250ns@reguraly, min:500ns@P02,

P22 is used)

In case of SSIO : S0CK2-0 of serial port 0 mode register(SIO0MOD).

In case of SSIOF : SF0BR9-0 of SIOF0 port register(SF0BRR)

t_SCYC

t_SW

SCK0

SCKF0

t_SD

SOUT0

SOUTF0

t_SS

t_SH

SIN0

SINF0

26/34

FEDL620Q504-01

ML620Q503/Q504

AC characteristics（I²C Bus interface : Standard mode 100kHz）

(V_DD=1.8 to 3.6V, V_SS=0V, Ta=-40 to +85°C, unless otherwise specified)

Rating

Parameter

Symbol

Condition

unit

Min.

0

Typ.

Max.

100

SCL clock frequency

f_SCL

―

kHz

SCL hold time

(Start/restart condition)

t_HD:STA

4.0

―

μs

SCL”L” level time

SCL”H” level time

t_LOW

t_HIGH

―

4.7

4.0

―

μs

SCL setup time

(restart condition)

t_SU:STA

―

4.7

―

μs

SDA hold time

SDA setup time

t_HD:DAT

t_SU:DAT

t_SU:STO

t_BUF

―

0

―

3.45

μs

0.25

―

SCL setup time

(stop condition)

―

4.0

4.7

―

μs

Bus-free time

AC characteristics（I²C bus interface : fast mode 400kHz）

(V_DD=1.8 to 3.6V, V_SS=0V, Ta=-40 to +85°C, unless otherwise specified)

Rateing

Parameter

Symbol

Condition

unit

Min.

0

Typ.

Max.

400

SCL clock frequency

f_SCL

―

kHz

SCLhold time

(start/restart condition)

t_HD:STA

0.6

―

μs

SCL”L” level time

SCL”H” level time

t_LOW

t_HIGH

―

1.3

0.6

―

μs

SCL setup time

(restart condition)

t_SU:STA

―

0.6

―

μs

SDA hold time

SDA setup time

t_HD:DAT

t_SU:DAT

―

0

―

0.9

μs

0.1

―

SCLsetup time

(stop condition)

t_SU:STO

t_BUF

―

0.6

1.3

―

μs

Bus-free time

Start

condition

Restart

condition

Stop

condition

SDA

SCL

t_BUF

t_SU:STO

t_HD:STA

t_LOW

t_HIGH

t_SU:STAt_HD:STA

t_SU:DAT

t_HD:DAT

27/34

FEDL620Q504-01

ML620Q503/Q504

AC characteristics（RC Oscillation A/D Converter）

(V_DD=1.8 to 3.6V, V_SS=0V, Ta=-40 to +85°C, unless otherwise specified)

Rating

Typ.

Parameter

Symbol

Condition

unit

Min.

1

Max.

400

RS0,RS1,RT

0,RT0-1,RT1

f_{OSC1_0}

Resister for oscillation

―

kΩ

Resister for oscillation=1kΩ

Resister for oscillation=10kΩ

Resister for

―

528

59

―

kHz

Oscillation freqency

V_DD= 3.0V

f_{OSC2_0}

CVR=820pF

CS=560pF

f_{OSC3_0}

―

5.9

―

kHz

oscillation=100kΩ

RS to RT oscillation

frequency ratio *¹

V_DD= 3.0V

Kf1_0

Kf2_0

RT0, RT0-1, RT1=1kΩ

RT0, RT0-1, RT1=10kΩ

8.225

0.99

8.94

1

9.655

1.01

―

CVR=820pF

Kf3_0

RT0, RT0-1, RT1=100kΩ

0.093

0.101

0.109

―

CS=560pF

*¹：Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the

same conditions.

f_OSCX(RT0-1－CS0

f_OSCX(RT0－CS0 oscillation)

f_OSCX(RT1－CS1 oscillation)

f_OSCX(RS1－CS1 oscillation)

oscillation)

f_OSCX(RS0－CS0

oscillation)

Kfx =

f

_OSCX(RS0－CS0 oscillation)

,

( x = 1, 2, 3 )

Measuring circuit

CVR0

CVR1

RT0, RT0-1, RT1: 1kΩ/10kΩ/100kΩ

RS0, RS1: 10kΩ

CS0, CT0, CS1: 560pF

CVR0, CVR1: 820pF

IN0

CS0 RCT0 RS0

IN1 CS1 RS1 RT1

RCM

RT0

VIH

Measure frequency

(f_OSCX

)

(*1)

VIL

V_DDV_DDL

V_DDX

V_REF

V_SS

C_V

(*1) Input logic circuit to determine the specified measuring conditions.

C_L1C_L0

C_X

【Note】

・Please have the shortest layout for the common node (wiring patterns which are connected to the external

capacitors, resistors and IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wire between IN0/IN1

and RS0/RS1. The coupling capacitance on the wires may occur incorrect A/D conversion. Also, please do not

have signals which may be a source of noise around the node.

・When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please shield the

signal by V_SS(GND) .

・Please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. Wiring to

reserved components may affect to the A/D conversion operation by noise the components itself may have.

28/34

FEDL620Q504-01

ML620Q503/Q504

Electrical Characteristics of Successive Approximation Type A/D Converter

(V_DD=1.8 to 3.6V, V_SS=0V, Ta=-40 to +85°C, unless otherwise specified)

Rating

Parameter

Resolution

Symbol

n

Condition

Unit

bit

Min.

Typ.

Max.

―

-4

-6

12

―

+4

+6

2.7V ≦ V_REF≦ 3.6V

2.2V ≦ V_REF< 2.7V

1.8V ≦ V_REF< 2.2V

(using Low-speed clock)

2.7V ≦ V_REF≦ 3.6V

2.2V ≦ V_REF< 2.7V

1.8V ≦ V_REF< 2.2V

(using Low-speed clock)

Integral non-linearity

error

INL

-10

―

+10

-3

-5

―

+3

+5

Differential

non-linearity error

DNL

-9

-6

―

+9

+6

LSB

2.2V ≦ V_REF≦ 3.6V

1.8V ≦ V_REF< 2.2V

Zero-scale error

Full-scale error

V_OFF

FSE

-10

-6

+10

+6

(using Low-speed clock)

2.2V ≦ V_REF≦ 3.6V

1.8V ≦ V_REF< 2.2V

-10

+10

(using Low-speed clock)

Input impidance

RI

―

5k

Ω

Reference voltage

V_REF

1.8

V_DD

V

Using High-speed clock(max.

4MHz)

―

170

16

―

Conversion time

t_CONV

clk

Using Low-speed clock

Measuring circuit

V_DD

Reference

Voltage

V_REF

1μF

A

RI≦5kΩ

-

10μF

AIN

+

V_SS

0.47μF

29/34

FEDL620Q504-01

ML620Q503/Q504

Power-on and shutdown Procedures

In case of power-on or shutdown of V_DD, the procedures and constraints are shown as following.

10ms or less

0.9×V_DD

V_DD

0.1×V_DD

30mV or less

(V_SS= 0)

over 2sec

30/34

FEDL620Q504-01

ML620Q503/Q504

APPLICATION CIRCUIT EXAMPLE

3.3V

V_DD

C_V

RESET_N

TEST0

P00/IN0

CVR0

CS0

TEST1_N

P01/CS0

V_DDX

C_X1

RS0

RT0

P03/RS0

P04/RT0

ML620Q503/Q504

V_DDL

V_ss

C_L1

C_L0

P02/RCT0

P05/RCM

C_GH

P20/IN1

P10/OSC0

P11/OSC1

CS1

CVR1

RS1

X_H

R_D

P21/CS1

C_DH

P22/RS1

P23/RT1

16MHz

Xtal

C_GL

RT1

PXT0/XT0

PXT1/XT1

X_L

C_DL

V_REF

32.768KHz

C_AV

Xtal

P32

P51 P50

P33

P41

P40

(Output)

/SCL /SDA

/MD0

/LED

Buzzer

Vcc

SCL SDA

WP

A0

LED

I²C EEPROM

A2

Vss

A1

C_V

: 1uF*

C_L1

C_X1

C_GL

C_GH

R_D

: 2.2uF

C_L0

: open*

: 0.33uF

: 12~16pF*

: 12~20pF*

: 0Ω*

C_DL

C_DH

: 12~16pF*

: 12~20pF*

C_AV

: 1uF*

: 560 pF

RS0, RS1

CVR0, CVR1

: 10 KΩ

: 820 pF

CS0, CS1

RT0, RT1

X_H

: Thermistor (103AT/Semitec)

: NX8045GB/16.000MHz, Nihon Denpa Kogyo

: DT-26, Daishinku

X_L

*: Make a decision the parameters after evaluating on an user’s conditions when designing circuits for mass production.

31/34

FEDL620Q504-01

ML620Q503/Q504

PACKAGE DIMENSIONS

ML620Q503/Q504 Package Dimensions

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package

name, pin number, package code and desired mounting conditions(reflow method, temperature and times).

32/34

FEDL620Q504-01

ML620Q503/Q504

REVISION HISTORY

Document No.

Date

Page

Current

Edition

PEDL620Q504-01

FEDL620Q504-01

Jun.10.2014

Mar.13.2015

–

Preliminary first edition issued

Final Edition issued

33/34

FEDL620Q504-01

ML620Q503/Q504

Notes

1) The information contained herein is subject to change without notice.

2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality,

semiconductors can break down and malfunction due to various factors. Therefore, in order to prevent

personal injury or fire arising from failure, please take safety measures such as complying with the

derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and

fail-safe procedures. LAPIS Semiconductor shall have no responsibility for any damages arising out of the

use of our Products beyond the rating specified by LAPIS Semiconductor.

3) Examples of application circuits, circuit constants and any other information contained herein are provided

only to illustrate the standard usage and operations of the Products.The peripheral conditions must be taken

into account when designing circuits for mass production.

4) The technical information specified herein is intended only to show the typical functions of the Products and

examples of application circuits for the Products. No license, expressly or implied, is granted hereby under

any intellectual property rights or other rights of LAPIS Semiconductor or any third party with respect to the

information contained in this document; therefore LAPIS Semiconductor shall have no responsibility

whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such

technical information.

5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication,

consumer systems, gaming/entertainment sets) as well as the applications indicated in this document.

6) The Products specified in this document are not designed to be radiation tolerant.

7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please

contact and consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships,

trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical

systems, servers, solar cells, and power transmission systems.

8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment,

nuclear power control systems, and submarine repeaters.

9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance

with the recommended usage conditions and specifications contained herein.

10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this

document. However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS

Semiconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such

information.

11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the

RoHS Directive. For more details, including RoHS compatibility, please contact a ROHM sales office.

LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance

with any applicable laws or regulations.

12) When providing our Products and technologies contained in this document to other countries, you must

abide by the procedures and provisions stipulated in all applicable export laws and regulations, including

without limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade

Act.

13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS

Semiconductor.

2-4-8 Shinyokohama, Kouhoku-ku,

Yokohama 222-8575, Japan

http://www.lapis-semi.com/en/

34/34


型号：	ML620Q503
厂家：	LAPIS Semiconductor Co., Ltd.
描述：	Ultra Low Power 16-bit Microcontroller 微控制器
文件：	总34页 (文件大小：914K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ML620Q503 [LAPIS]

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