5962-9476101MXC [LATTICE]
EE PLD, 25ns, 96-Cell, CMOS, PQCC68, JLCC-68;
| 型号： | 5962-9476101MXC |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | EE PLD, 25ns, 96-Cell, CMOS, PQCC68, JLCC-68 时钟 输入元件 可编程逻辑 |
| 文件： | 总12页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ispLSI 1024/883
In-System Programmable High Density PLD
Functional Block Diagram
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— High-Speed Global Interconnect
— 4000 PLD Gates
A0
A1
A2
A3
A4
A5
A6
A7
C7
C6
C5
C4
C3
C2
C1
C0
— 48 I/O Pins, Six Dedicated Inputs
— 144 Registers
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Fast Random Logic
— Security Cell Prevents Unauthorized Copying
D
D
D
D
Q
Q
Q
Q
Logic
Array
GLB
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 60 MHz Maximum Operating Frequency
— tpd = 20 ns Propagation Delay
Global Routing Pool (GRP)
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100% Tested
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool
CLK
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
0139-A-isp
Description
— Reprogram Soldered Devices for Faster Debugging
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
The ispLSI 1024/883 is a High-Density Programmable
Logic Device processed in full compliance to MIL-STD-
883. This military grade device contains 144 Registers,
48 Universal I/O pins, six Dedicated Input pins, four
Dedicated Clock Input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1024/883
features5-Voltin-systemprogrammabilityandin-system
diagnostic capabilities. It is the first device which offers
non-volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
The basic unit of logic on the ispLSI 1024/883 device is
theGenericLogicBlock(GLB).TheGLBsarelabeledA0,
A1 .. C7 (see figure 1). There are a total of 24 GLBs in the
ispLSI 1024/883 device. Each GLB has 18 inputs, a
programmable AND/OR/XOR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicatedinputs. AlloftheGLBoutputsarebroughtback
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
unctional Block Diagram
Copyright©2000LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
1024MIL_01
1
Specifications ispLSI 1024/883
Functional Block Diagram
Figure 1.ispLSI 1024/883 Functional Block Diagram
RESET
Generic
Logic Blocks
(GLBs)
IN 5
IN 4
I/O 47
C7
I/O 46
I/O 0
I/O 45
A0
I/O 1
I/O 44
C6
C5
C4
C3
C2
C1
C0
I/O 2
I/O 3
A1
I/O 43
I/O 42
I/O 41
I/O 4
A2
I/O 5
I/O 40
Global
Routing
Pool
I/O 6
I/O 7
A3
A4
A5
A6
A7
I/O 39
I/O 38
I/O 37
I/O 36
(GRP)
I/O 8
I/O 9
I/O 10
I/O 11
I/O 35
I/O 34
I/O 33
I/O 32
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
SDO/IN 1
CLK 0
B0
B1
B2
B3
B4
B5
B6
B7
CLK 1
CLK 2
Clock
Distribution
Network
IOCLK 0
IOCLK 1
Megablock
Output Routing Pool (ORP)
Input Bus
ispEN
SCLK/IN 2
MODE/IN 3
I/O I/O I/O I/O
16 17 18 19
I/O I/O I/O I/O
20 21 22 23
I/O I/O I/O I/O
24 25 26 27
I/O I/O I/O I/O
28 29 30 31
Y
0
Y
1
Y
2
Y
3
0139D_1024.eps
The device also has 48 I/O cells, each of which is directly TheGRPhasasitsinputstheoutputsfromalloftheGLBs
connected to an I/O pin. Each I/O cell can be individually and all of the inputs from the bi-directional I/O cells. All of
programmed to be a combinatorial input, registered in- these signals are made available to the inputs of the
put, latched input, output or
bi-directional GLBs. Delays through the GRP have been equalized to
I/O pin with 3-state control. Additionally, all outputs are minimize timing skew.
polarity selectable, active high or active low. The signal
Clocks in the ispLSI 1024/883 device are selected using
levelsareTTLcompatiblevoltagesandtheoutputdrivers
can source 4 mA or sink 8 mA.
theClockDistributionNetwork.Fourdedicatedclockpins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
alsobedrivenfromaspecialclockGLB (B4ontheispLSI
1024/883 device). The logic of this GLB allows the user
to create an internal clock from a combination of internal
signals within the device.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected
toaset of 16universalI/O cellsby theORP. TheI/O cells
within the Megablock also share a common Output
Enable (OE) signal. The ispLSI 1024/883 device con-
tains three of these Megablocks.
2
Specifications ispLSI 1024/883
1
Absolute Maximum Ratings
Supply Voltage V ...................................-0.5 to +7.0V
cc
Input Voltage Applied........................ -2.5 to V +1.0V
CC
Off-State Output Voltage Applied ..... -2.5 to V +1.0V
CC
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T ) with Power Applied ... 150°C
J
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
PARAMETER
MIN.
MAX.
5.5
UNITS
Supply Voltage
Input Low Voltage
Input High Voltage
Military/883
TC = -55°C to +125°C
V
V
V
CC
IL
4.5
0
V
V
0.8
IH
2.0
Vcc + 1
0005A mil.eps
Capacitance (TA=25oC, f=1.0 MHz)
1
SYMBOL PARAMETER
MAXIMUM
UNITS
TEST CONDITIONS
CC=5.0V, VIN=2.0V
Dedicated Input Capacitance
10
10
pf
pf
V
C1
C2
I/O and Clock Capacitance
VCC=5.0V, VI/O, VY=2.0V
Table 2- 0006mil
1. Characterized but not 100% tested.
Data Retention Specifications
PARAMETER
Data Retention
MINIMUM
20
MAXIMUM
UNITS
—
—
Years
Erase/Reprogram Cycles
10000
Cycles
Table 2- 0008B
3
Specifications ispLSI 1024/883
Switching Test Conditions
Figure 2. Test Load
Input Pulse Levels
GND to 3.0V
≤ 3ns 10% to 90%
1.5V
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
+ 5V
1.5V
R
1
2
See figure 2
Device
Output
Test
Point
3-state levels are measured 0.5V from steady-state
active level.
Table 2- 0003
R
C *
L
Output Load Conditions (see figure 2)
*
C includes Test Fixture and Probe Capacitance.
L
Test Condition
R1
R2
CL
A
470Ω
390Ω
390Ω
390Ω
390Ω
35pF
35pF
35pF
5pF
B
Active High
Active Low
∞
470Ω
Active High to Z
at VOH - 0.5V
∞
C
Active Low to Z
470Ω
390Ω
5pF
at VOL + 0.5V
Table 2- 0004A
DC Electrical Characteristics
Over Recommended Operating Conditions
3
CONDITION
IOL =8 mA
PARAMETER
Output Low Voltage
MIN. TYP.
MAX.
0.4
UNITS
SYMBOL
–
2.4
–
–
–
V
V
V
V
OL
IOH =-4 mA
Output High Voltage
–
OH
0V ≤ VIN ≤ VIL (MAX.)
3.5V ≤ VIN ≤ VCC
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
isp Input Low Leakage Current
I/O Active Pull-Up Current
-10
10
µA
–
I
I
I
I
I
IL
IH
–
–
µA
µA
µA
mA
mA
0V ≤ VIN ≤ VIL (MAX.)
0V ≤ VIN ≤ VIL
–
–
-150
-150
IL-isp
IL-PU
–
–
1
VCC = 5V, VOUT = 0.5V
VIL = 0.5V, VIH = 3.0V
fTOGGLE = 1 MHz
Output Short Circuit Current
Operating Power Supply Current
–
–
OS
-200
215
2,4
–
135
I
CC
1. One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
2. Measured using six 16-bit counters.
3. Typical values are at VCC = 5V and TA = 25oC.
4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption sec-
tion of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum
ICC.
0007A-24 mil
4
Specifications ispLSI 1024/883
External Timing Parameters
Over Recommended Operating Conditions
-60
5
2
DESCRIPTION1
UNITS
TEST
PARAMETER
#
COND.
MIN. MAX.
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
–
–
–
–
1
Data Propagation Delay, 4PT bypass, ORP bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback3
–
–
20
25
–
t
pd1
ns
ns
2
3
4
5
6
7
8
9
t
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
pd2
60
38
83
9
MHz
MHz
MHz
ns
max (Int.)
max (Ext.)
max (Tog.)
su1
1
Clock Frequency with External Feedback
Clock Frequency, Max Toggle4
–
(
)
tsu2 + tco1
–
GLB Reg. Setup Time before Clock, 4PT bypass
GLB Reg. Clock to Output Delay, ORP bypass
GLB Reg. Hold Time after Clock, 4 PT bypass
GLB Reg. Setup Time before Clock
–
–
13
–
co1
ns
0
h1
ns
13
–
–
su2
ns
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
16
–
co2
ns
0
h2
ns
–
22.5
–
r1
ns
13
–
rw1
ns
14 Input to Output Enable
24
24
–
en
ns
15 Input to Output Disable
–
dis
ns
16 Ext. Sync. Clock Pulse Duration, High
17 Ext. Sync. Clock Pulse Duration, Low
6
wh
ns
6
–
wl
ns
18 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)
19 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
2.5
8.5
–
su5
ns
–
h5
ns
Table 2-0030-24 mil
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit loadable counter using GRP feedback.
4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions Section.
5
Specifications ispLSI 1024/883
1
Internal Timing Parameters
-60
2
PARAMETER
DESCRIPTION
UNITS
#
MIN. MAX.
Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
I/O Register Bypass
–
–
2.7
4.0
–
20
21
22
23
24
25
26
ns
ns
ns
ns
ns
ns
ns
I/O Latch Delay
I/O Register Setup Time before Clock
I/O Register Hold Time after Clock
I/O Register Clock to Out Delay
I/O Register Reset to Out Delay
Dedicated Input Delay
7.3
1.3
–
–
4.0
3.3
5.3
–
–
GRP
tgrp1
tgrp4
GRP Delay, 1 GLB Load
GRP Delay, 4 GLB Loads
GRP Delay, 8 GLB Loads
GRP Delay, 12 GLB Loads
GRP Delay, 16 GLB Loads
GRP Delay, 24 GLB Loads
–
–
–
–
–
–
2.0
2.7
4.0
5.0
6.0
8.3
27
28
29
30
31
32
ns
ns
ns
ns
ns
ns
tgrp8
tgrp12
tgrp16
tgrp24
GLB
t4ptbp
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgr
4 Product Term Bypass Path Delay
1 Product Term/XOR Path Delay
20 Product Term/XOR Path Delay
XOR Adjacent Path Delay3
33
34
35
36
37
38
39
40
41
42
43
44
–
–
8.6
9.3
10.6
12.7
1.3
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
GLB Register Bypass Delay
–
GLB Register Setup Time before Clock
GLB Register Hold Time after Clock
GLB Register Clock to Output Delay
GLB Register Reset to Output Delay
GLB Product Term Reset to Register Delay
GLB Product Term Output Enable to I/O Cell Delay
GLB Product Term Clock Delay
1.3
6.0
–
–
2.7
3.3
13.3
12.0
–
tptre
tptoe
tptck
–
–
4.6 9.9
ORP
torp
torpbp
ORP Delay
–
–
3.3
0.7
45
46
ns
ns
ORP Bypass Delay
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Lattice Hard Macros.
6
Specifications ispLSI 1024/883
1
Internal Timing Parameters
-60
2
PARAMETER
DESCRIPTION
UNITS
#
MIN. MAX.
Outputs
t
t
t
ob
Output Buffer Delay
–
–
–
4.0
6.7
6.7
47
48
49
ns
ns
ns
I/O Cell OE to Output Enabled
I/O Cell OE to Output Disabled
oen
odis
Clocks
t
t
t
t
t
gy0
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
Clock Delay, Y1 or Y2 to Global GLB Clock Line
Clock Delay, Clock GLB to Global GLB Clock Line
Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
Clock Delay, Clock GLB to I/O Cell Global Clock Line
6.0 6.0
4.6 7.3
1.3 6.6
4.6 7.3
1.3 6.6
50
51
52
53
54
ns
ns
ns
ns
ns
gy1/2
gcp
ioy2/3
iocp
Global Reset
tgr
Global Reset to GLB and I/O Registers
–
12.0
55
ns
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
7
Specifications ispLSI 1024/883
ispLSI Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Ded. In
#26
I/O Reg Bypass
GRP 4
#28
4 PT Bypass
#33
GLB Reg Bypass
#37
ORP Bypass
#46
#47
I/O Pin
#20
I/O Pin
(Output)
#48, 49
(Input)
Input
Register
GRP
Loading
Delay
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
Q
D
RST
D
Q
#45
#34, 35, 36
#55
#27, 29,
30, 31, 32
#55
#21 - 25
RST
#38, 39,
40, 41
Reset
Clock
Control
PTs
RE
OE
CK
Distribution
Y1,2,3
Y0
#51, 52,
53, 54
#42, 43,
44
#50
Derivations of tsu, th and t
co from the Product Term Clock1
t
t
t
su
= Logic + Reg su - Clock (min)
=
=
(tiobp +
t
grp4 +
#20 + #28 + #35
t
20ptxor
)
+
(tgsu) - (tiobp +
t
grp4 +
t
ptck(min)
)
(
)
+
(#38) - (#20 + #28 + #44
)
7.3 ns = (2.7 + 2.7 + 10.6) + (1.3) - (2.7 + 2.7 + 4.6)
h
= Clock (max) + Reg h - Logic
=
=
(tiobp +
t
grp4 +
#20 + #28 + #44
t
ptck(max)
)
+
(tgh) - (tiobp +
tgrp4 +
t20ptxor
)
(
)
+
(#39) - (#20 + #28 + #35
)
5.3 ns = (2.7 + 2.7 + 9.9) + (6.0) - (2.7 + 2.7 + 10.6)
co = Clock (max) + Reg co + Output
=
=
(tiobp +
t
grp4 +
#20 + #28 + #44
t
ptck(max)
)
+
(tgco
)
+
)
(torp +
tob
)
(
)
+
(#40
)
+
(#45 + #47
25.3 ns = (2.7+ 2.7 +9.9) + (2.7) + (3.3 + 4.0)
Derivations of tsu, th and t
co from the Clock GLB1
t
t
t
su
= Logic + Reg su - Clock (min)
=
=
(tiobp +
t
grp4 +
#20 + #28 + #35
t
20ptxor
)
+
(tgsu) - (tgy0(min) +
t
gco +
t
gcp(min)
)
(
)
+
(#38) - (#50 + #40 + #52
)
7.3 ns = (2.7 + 2.7 + 10.6) + (1.3) - (6.0 + 2.7 + 1.3)
h
= Clock (max) + Reg h - Logic
=
=
(tgy0(max) +
t
gco +
t
gcp(max)
#39) - (#20 + #28 + #35
)
+
(tgh) - (tiobp +
tgrp4 +
t
20ptxor
)
(
#50 + #40 + #52
)
+
(
)
5.3 ns = (6.0 + 2.7 + 6.6) + (6.0) - (2.7 + 2.7 + 10.6)
co = Clock (max) + Reg co + Output
=
=
(tgy0(max) +
t
gco +
t
gcp(max)
)
+
(tgco
)
+
(torp +
t )
ob
(
#50 + #40 + #52
)
+
(
#40 #45 + #47
)
+
(
)
25.3 ns = (6.0 + 2.7 + 6.6) + (2.7) + (3.3 + 4.0)
1. Calculations are based upon timing specifications for the ispLSI 1024-60.
8
Specifications ispLSI 1024/883
Maximum GRP Delay vs GLB Loads
ispLSI 1024-60
6
5
4
3
2
1
0
4
8
12
16
GLB Loads
0126A-80-24-mil.eps
Power Consumption
Power consumption in the ispLSI 1024/883 device de- used. Figure 3 shows the relationship between power
pends on two primary factors: the speed at which the and operating speed.
device is operating, and the number of Product Terms
Figure 3. Typical Device Power Consumption vs fmax
200
ispLSI 1024
150
100
50
0
10
20 30
40 50 60 70 80
max (MHz)
f
Notes: Configuration of Six 16-bit Counters
Typical Current at 5V, 25˚C
I
I
can be estimated for the ispLSI 1024 using the following equation:
= 42 + (# of PTs * 0.45) + (# of nets * Max. freq * 0.008) where:
CC
CC
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The I
estimate is based on typical conditions (V
= 5.0V, room temperature) and an assumption of 2 GLB loads on
CC
CC
average exists. These values are for estimates only. Since the value of I
program in the device, the actual I
is sensitive to operating conditions and the
CC
should be verified.
CC
0127A-24-80-isp
9
Specifications ispLSI 1024/883
Pin Description
JLCC
PIN NUMBERS
NAME
DESCRIPTION
I/O 0 - I/O 3
I/O 4 - I/O 7
22,
24, 25,
28, 29,
32, 33,
39, 40,
43, 44,
47, 48,
58, 59,
62, 63,
66, 67,
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
23,
27,
31,
38,
42,
46,
57,
61,
65,
4,
26,
30,
37,
41,
45,
56,
60,
64,
3,
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
5,
9,
6,
10,
7,
11,
8,
12,
13, 14
IN 4 - IN 5
ispEN
Input - These pins are dedicated input pins to the device.
2,
15
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO
and SCLK options become active.
19
1
SDI/IN 0
21
Input - This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN 0 is also used as one of the two control pins for the isp state
machine. It is a dedicated input pin when ispEN is logic high.
1
MODE/IN 3
55
34
49
—
Input - This pin performs two functions. When ispEN is logic low, it
functions as pin to control the operation of the isp state machine. It is a
dedicated input pin when ispEN is logic high.
1
SDO/IN 1
Output/Input - This pin performs two functions. When ispEN is logic low,
it functions as an output pin to read serial shift register data. It is a
dedicated input pin when ispEN is logic high.
1
SCLK/IN 2
Input - This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. It is a dedicated
input pin when ispEN is logic high.
2
NC
No Connect
RESET
Y0
20
16
54
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
Y1
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Y2
Y3
51
50
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
1,
35, 52
53, 68
18,
36,
GND
VCC
Ground (GND)
17,
VCC
Table 2 - 0002C-24 mil
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, Vcc or GND.
10
Specifications ispLSI 1024/883
Pin Configuration
ispLSI 1024/883 68-Pin JLCC Pinout Diagram
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
IN 5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
IN 3/MODE
Y1
1
Y0
VCC
VCC
ispLSI 1024/883
GND
GND
Y2
Top View
ispEN
RESET
SDI/IN 0
I/O 0
Y3
1
1
IN 2/SCLK
I/O 23
I/O 1
I/O 22
I/O 2
I/O 21
I/O 20
I/O 3
I/O 4
I/O 19
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
1. Pins have dual function capability.
0123-24-isp/JLCC
11
Specifications ispLSI 1024/883
Part Number Description
ispLSI
–
1024
XX
X
X
X
Device Family
ispLSI
Grade
/883 = 883 Military Process
Device Number
Package
H = JLCC
Speed
60 = 60 MHz fmax
Power
L = Low
00212-80B-isp1024 mil
Ordering Information
MILITARY/883
f
max (MHz)
t
pd (ns)
Ordering Number
Package
Family
ispLSI
SMD #
60
20
ispLSI 1024-60LH/883
68-Pin JLCC
5962-9476101MXC
Table 2-0041A-24-mil
Note: Lattice Semiconductor recognizes the trend in military device procurement towards
using SMD compliant devices, as such, ordering by this number is recommended.
12
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