GAL20RA10B-10LJ [LATTICE]
High-Speed Asynchronous E2CMOS PLD Generic Array Logic⑩; 高速异步E2CMOS PLD通用阵列Logic⑩
| 型号： | GAL20RA10B-10LJ |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | High-Speed Asynchronous E2CMOS PLD Generic Array Logic⑩ |
| 文件： | 总15页 (文件大小：241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GAL20RA10
High-Speed Asynchronous E2CMOS PLD
Generic Array Logic™
Features
Functional Block Diagram
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 83.3 MHz
PL
— 9 ns Maximum from Clock Input to Data Output
8
OLMC
I/O/Q
I/O/Q
I
I
I
I
I
I
I
I
I
I
— TTL Compatible 8 mA Outputs
— UltraMOS® Advanced CMOS Technology
8
8
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
— 75mA Typical Icc
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
• ACTIVE PULL-UPS ON ALL PINS
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100 ms)
— 20 Year Data Retention
I/O/Q
I/O/Q
8
8
8
8
8
8
I/O/Q
I/O/Q
• TEN OUTPUT LOGIC MACROCELLS
— Independent Programmable Clocks
— Independent Asynchronous Reset and Preset
— Registered or Combinatorial with Polarity
— Full Function and Parametric Compatibility with
PAL20RA10
I/O/Q
I/O/Q
I/O/Q
I/O/Q
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— State Machine Control
— Standard Logic Consolidation
— Multiple Clock Logic Designs
8
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
OE
The GAL20RA10 combines a high performance CMOS process
with electrically erasable (E2) floating gate technology to provide
the highest speed performance available in the PLD market. Lattice
Semiconductor’s E2CMOS circuitry achieves power levels as low
as 75mA typical ICC which represents a substantial savings in power
when compared to bipolar counterparts. E2 technology offers high
speed (<100ms) erase times providing the ability to reprogram,
reconfigure or test the devices quickly and efficiently.
Pin Configuration
DIP
1
Vcc
24
PLCC
PL
I/O/Q
I
I
I
I
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GAL
4
2
28
26
5
7
I
25
I/O/Q
I/O/Q
20RA10
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL20RA10 is a direct parametric compatible CMOS
replacement for the PAL20RA10 device.
I
I
6
23 I/O/Q
NC
18
I
I
GAL20RA10
Top View
NC
I
I
I
9
21
I/O/Q
Unique test circuitry and reprogrammable cells allow completeAC,
DC, and functional testing during manufacturing. Therefore, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
I
I
I
I/O/Q
11
19
18
I/O/Q
12
14
16
GND
13 OE
12
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
July 1997
1
20ra10_02
Specifications GAL20RA10
GAL20RA10 Ordering Information
Commercial Grade Specifications
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA)
Ordering #
Package
7.5
10
3
4
9
100
100
GAL20RA10B-7LJ
28-Lead PLCC
11
GAL20RA10B-10LP
GAL20RA10B-10LJ
GAL20RA10B-15LP
GAL20RA10B-15LJ
GAL20RA10B-20LP
GAL20RA10B-20LJ
GAL20RA10B-30LP
GAL20RA10B-30LJ
24-Pin Plastic DIP
100
100
100
100
100
100
100
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
15
20
30
7
15
20
30
10
20
Industrial Grade Specifications
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA)
Ordering #
Package
24-Pin Plastic DIP
28-Lead PLCC
20
10
20
120
120
GAL20RA10B-20LPI
GAL20RA10B-20LJI
Part Number Description
_
XXXXXXXX XX
X
X X
GAL20RA10B Device Name
Speed (ns)
Grade
Blank = Commercial
I = Industrial
L = Low Power Power
Package P = Plastic DIP
J = PLCC
2
Specifications GAL20RA10
Output Logic Macrocell (OLMC)
Asynchronous Reset and Preset
The GAL20RA10 OLMC consists of 10 D flip-flops with indi- Each GAL20RA10 macrocell has an independent asynchronous
vidual asynchronous programmable reset, preset and clock product reset and preset control product term. The reset and preset product
terms. The sum of four product terms and an Exclusive-OR pro- terms are level sensitive, and will hold the flip-flop in the reset or
vide a programmable polarity D-input to each flip-flop. An output preset state while the product term is active independent of the clock
enable term combined with the dedicated output enable pin pro- or D-inputs. It should be noted that the reset and preset term al-
vides tri-state control of each output. Each OLMC has a flip-flop ter the state of the flip-flop whose output is inverted by the output
bypass, allowing any combination of registered or combinatorial buffer. A reset of the flip-flop will result in the output pin becoming
outputs.
a logic high and a preset will result in a logic low.
The GAL20RA10 has 10 dedicated input pins and 10 program-
mable I/O pins, which can be either inputs, outputs, or dynamic I/
O. Each pin has a unique path to the logic array. All macrocells
have the same type and number of data and control product terms,
allowing the user to exchange I/O pin assignments without restric-
tion.
RESET PRESET
FUNCTION
0
1
0
1
0
0
1
1
Registered function of data product term
Reset register to "0" (device pin = "1")
Preset register to "1" (device pin = "0")
Register-bypass (combinatorial output)
Independent Programmable Clocks
Combinatorial Control
An independent clock control product term is provided for each
GAL20RA10 macrocell. Data is clocked into the flip-flop on the
active edge of the clock product term. The use of individual clock
control product terms allow up to ten separate clocks. These clocks
can be derived from any pin or combination of pins and/or feedback
from other flip-flops. Multiple clock sources allow a number of
asynchronous register functions to be combined into a single
GAL20RA10. This allows the designer to combine discrete logic
functions into a single device.
The register in each GAL20RA10 macrocell may be bypassed by
asserting both the reset and preset product terms. While both
product terms are active the flip-flop is bypassed and the D- input
is presented directly to the inverting output buffer. This provides
the designer the ability to dynamically configure any macrocell as
a combinatorial output, or to fix the macrocell as combinatorial only
by forcing both reset and preset product terms active. Some logic
compilers will configure macrocells as registered or combinatorial
based on the logic equations, others require the designer to force
the reset and preset product terms active for combinatorial
macrocells.
Programmable Polarity
The polarity of the D-input to each macrocell flip-flop is individually
programmable to be active high or low. This is accomplished with
a programmable Exclusive-OR gate on the D-input of each flip-
flop. The polarity of the pin is active low when XOR bit is pro-
grammed (or zero) and is active high when XOR bit is erased (or
one). Because of the inverted output buffer, the XOR gate output
node is opposite polarity from the pin. It should be noted that the
programmable polarity only affects the data latched into the flip-flop
on the active edge of the clock product term. The reset, preset and
preload will alter the state of the flip-flop independent of the state
of programmable polarity bit. The ability to program the active po-
larity of the D-inputs can be used to reduce the total number of
product terms used, by allowing the DeMorganization of the logic
functions. This logic reduction is accomplished by the logic com-
piler, and does not require the designer to define the polarity.
Parallel Flip-Flop Preload
The flip-flops of a GAL20RA10 can be reset or preset from the
I/O pins by applying a logic low to the preload pin (pin 1 on DIP
package / pin 2 on PLCC package) and applying the desired logic
level to each I/O pin. The I/O pins must remain valid for the preload
setup and hold time. All 10 flip-flops are reset or preset during
preload, independent of all other OLMC inputs.
A logic low on an I/O pin during preload will preset the flip-flop, a
logic high will reset the flip-flop. The output of any flip-flop to be
preloaded must be disabled. Enabling the output during preload
will maintain the current logic state. It should be noted that the
preload alters the state of the flip-flop whose output is inverted by
the output buffer. A reset of the flip-flop will result in the output pin
becoming a logic high and a preset will result in a logic low. Note
that the common output enable pin will disable all 10 outputs of the
GAL20RA10 when held high.
Output Enable
The output of each GAL20RA10 macrocell is controlled by the
“AND’ing” of an independent output enable product term and a
common active low output enable pin (pin 13 on DIP package / pin
16 on PLCC package). The output is enabled while the output en-
able product term is active and the output enable pin is low. This
output control structure allows several output enable alternatives.
3
Specifications GAL20RA10
Output Logic Macrocell Diagram
PL
OE
AR
PL
D
PD
Q
0
1
AP
XOR (n)
Output Logic Macrocell Configuration (Registered With Polarity)
PL
OE
AR
PL PD
D
Q
AP
XOR (n)
Output Logic Macrocell Configuration (Combinatorial With Polarity)
OE
XOR (n)
4
Specifications GAL20RA10
GAL20RA10 Logic Diagram
DIP (PLCC) Package Pinouts
1 (2)
0
4
8
12 16 20
24 28 32 36
PL
0
OLMC
23 (27)
22 (26)
280
XOR - 3200
2 (3)
3 (4)
4 (5)
5 (6)
6 (7)
7 (9)
320
600
OLMC
XOR - 3201
640
920
OLMC
21 (25)
20 (24)
XOR - 3202
960
OLMC
1240
XOR - 3203
1280
1560
OLMC
19 (23)
18 (21)
17 (20)
16 (19)
15 (18)
XOR - 3204
1600
1880
OLMC
XOR - 3205
1920
2200
OLMC
XOR - 3206
8 (10)
9 (11)
2240
2520
OLMC
XOR - 3207
2560
2840
OLMC
XOR - 3208
10 (12)
11 (13)
2880
3160
OLMC
14 (17)
13 (16)
XOR - 3209
OE
64-USER ELECTRONIC SIGNATURE FUSES
3210, 3211, ....
Byte7 Byte6 ....
.... 3272, 3273
.... Byte1 Byte0
MSB
LSB
5
Specifications GAL20RA10B
(1)
Absolute Maximum Ratings
Recommended Operating Conditions
Supply voltage VCC ....................................... -0.5 to +7V
Input voltage applied ........................... -2.5 to VCC +1.0V
Off-state output voltage applied .......... -2.5 to VCC +1.0V
Storage Temperature .................................-65 to 150°C
Ambient Temperature with
Commercial Devices:
Ambient Temperature (TA) ............................. 0 to +75°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.75 to +5.25V
Power Applied .........................................-55 to 125°C
Industrial Devices:
1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
Ambient Temperature (TA) ..........................-40 to +85°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.50 to +5.50V
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.3
MAX. UNITS
VIL
VIH
IIL1
Input Low Voltage
Vss – 0.5
2.0
—
—
—
—
—
—
—
—
—
—
0.8
Vcc+1
-100
10
V
V
Input High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
Output Low Voltage
0V ≤ VIN ≤ VIL (MAX.)
3.5V ≤ VIN ≤ VCC
µA
µA
V
IIH
—
VOL
VOH
IOL
IOL = MAX. Vin = VIL or VIH
IOH = MAX. Vin = VIL or VIH
—
0.5
Output High Voltage
2.4
—
—
V
Low Level Output Current
High Level Output Current
Output Short Circuit Current
8
mA
mA
mA
IOH
IOS2
—
-3.2
-135
VCC = 5V VOUT = 0.5V TA = 25°C
-50
COMMERCIAL
ICC
Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V
L -7/-10/-15/-20/-30
—
—
75
75
100
120
mA
mA
ftoggle = 15MHz Outputs Open
INDUSTRIAL
ICC
Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V
L -20
ftoggle = 15MHz Outputs Open
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C
6
Specifications GAL20RA10B
AC Switching Characteristics
Over Recommended Operating Conditions
COM
-7
COM
-10
COM
-15
COM / IND
-20
COM
-30
TEST
COND1.
DESCRIPTION
PARAM.
UNITS
MIN. MAX.
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
tpd
tco
A
A
Input or I/O to Combinatorial Output
Clock to Output Delay
2
2
7.5
9
2
2
10
11
—
—
—
—
—
15
15
—
—
—
—
—
20
20
—
—
—
—
—
30
30
—
—
—
ns
ns
tsu
—
—
A
Setup Time, Input or Fdbk before Clk↑
Hold Time, Input or Fdbk after Clk↑
3
—
—
—
4
7
10
3
20
ns
th
fmax3
2
3
3
10
ns
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
83.3
66.7
45.0
33.3
20.0
MHz
A
Maximum Clock Frequency with
No Feedback
83.3
—
71.4
—
50.0
—
41.7
—
25.0
—
MHz
twh
twl
—
—
Clock Pulse Duration, High
Clock Pulse Duration, Low
6
6
—
—
7.5
5
7
7
—
—
10
9
10
10
—
—
—
15
10
15
10
10
—
—
15
12
15
—
—
—
—
—
12
12
—
—
—
20
12
20
15
15
—
—
20
15
20
—
—
—
—
—
20
20
—
—
—
20
20
30
25
25
—
—
30
20
30
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ten/tdis B,C
ten/tdis B,C
I or I/O to Output Enabled / Disabled
OE to Output Enabled / Disabled
Input or I/O to Async. Reset / Preset
Async. Reset / Preset Pulse Duration
Async. Reset / Preset Recovery Time
Preload Pulse Duration
—
—
—
6
—
—
—
10
7
tar/tap
tarw/tapw
tarr/tapr
twp
A
9
11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7
8
10
7
tsp
Preload Setup Time
5
thp
Preload Hold Time
5
7
1) Refer to Switching Test Conditions section.
2) Refer to fmax Descriptions section.
Capacitance (TA = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
Input Capacitance
I/O Capacitance
MAXIMUM*
UNITS
pF
TEST CONDITIONS
VCC = 5.0V, VI = 2.0V
VCC = 5.0V, VI/O = 2.0V
CI
8
CI/O
10
pF
*Characterized but not 100% tested.
7
Specifications GAL20RA10
Switching Waveforms
INPUT or
I/O FEEDBACK
INPUT or
I/O FEEDBACK
VALID INPUT
VALID INPUT
pd
tsu
VALID CLOCK
th
t
VALID CLOCK
COMBINATORIAL
OUTPUT
CLK
tco
REGISTERED
OUTPUT
Combinatorial Output
Registered Output
INPUT or
I/O FEEDBACK
t
dis
ten
INPUT or
VALID INPUT
I/O FEEDBACK
OUTPUT
t
ar
Q-OUTPUT OF
REGISTER
Input or I/O to Output Enable/Disable
t
wl
twh
REGISTERED
OUTPUT PIN
CLK
t
ap
Q-OUTPUT OF
REGISTER
Clock Width
t
wp
REGISTERED
OUTPUT PIN
PL
t
sp
thp
Asynchronous Reset and Preset
ALL I/O
PINS
INPUT or
VALID INPUT
I/O FEEDBACK
DRIVING AP or AR
Parallel Preload
t
apr/arr
t
apw/arw
CLK
OE
Asynchronous Reset and Preset Recovery
tdis
ten
OUTPUT
OE to Enable / Disable
8
Specifications GAL20RA10
fmax Descriptions
CLK
CLK
LOGIC
ARRAY
REGISTER
LOGIC
REGISTER
ARRAY
t
su
tco
fmax with No Feedback
fmax with External Feedback 1/(tsu+tco)
Note: fmax with no feedback may be less
than 1/(twh + twl). This is to allow for a
clock duty cycle of other than 50%.
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
Switching Test Conditions
Input Pulse Levels
Input Rise and
Fall Times
GND to 3.0V
+5V
-7/-10
2ns 10% – 90%
3ns 10% – 90%
1.5V
-15/-20/-30
R
1
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
1.5V
See Figure
FROM OUTPUT (O/Q)
UNDER TEST
TEST POINT
3-state levels are measured 0.5V from steady-state active
level.
C L*
R
2
Output Load Conditions (see figure)
Test Condition
R1
R2
CL
A
B
470Ω
∞
470Ω
∞
390Ω
390Ω
390Ω
390Ω
390Ω
50pF
50pF
50pF
5pF
Active High
Active Low
Active High
Active Low
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
C
470Ω
5pF
9
Specifications GAL20RA10
Electronic Signature
Device Programming
An electronic signature word is provided in every GAL20RA10 GAL devices are programmed using a Lattice Semiconductor-
device. It contains 64 bits of reprogrammable memory that con- approved Logic Programmer, available from a number of manu-
tains user defined data. Some uses include user ID codes, revi- facturers (see the the GAL Development Tools section). Complete
sion numbers, pattern identification or inventory control codes. The programming of the device takes only a few seconds. Erasing of
signature data is always available to the user independent of the the device is transparent to the user, and is done automatically as
state of the security cell.
part of the programming cycle.
NOTE: The electronic signature bits if programmed to any value
other then zero(0) will alter the checksum of the device.
Input Buffers
GAL20RA10 devices are designed with TTL level compatible in-
put buffers. These buffers have a characteristically high impedance
and present a much lighter load to the driving logic than traditional
Security Cell
A security cell is provided in every GAL20RA10 device as a deter- bipolar devices.
rent to unauthorized copying of the device pattern. Once pro-
grammed, this cell prevents further read access of the device GAL20RA10 input buffers have active pull-ups within their input
pattern information. This cell can be only be reset by reprogram- structure. As a result, unused inputs and I/Os will float to a TTL
ming the device. The original pattern can never be examined once “high” (logical “1”). Lattice Semiconductor recommends that all un-
this cell is programmed. The Electronic Signature is always avail- used inputs and tri-stated I/O pins be connected to another active
able regardless of the security cell state.
input, Vcc, or GND. Doing this will tend to improve noise immu-
nity and reduce Icc for the device.
Latch-Up Protection
Typical Input Pull-up Characteristic
GAL20RA10 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pullups
instead of the traditional p-channel pullups to eliminate any pos-
sibility of SCR induced latching.
0
- 2 0
- 4 0
- 6 0
0
1 . 0
2 . 0
3 . 0
4 . 0
5 . 0
Input Voltage (Volts)
10
Specifications GAL20RA10
Power-Up Reset
Vcc (min.)
Vcc
tsu
twl
CLK
tpr
Internal Register
Reset to Logic "0"
INTERNAL REGISTER
Q - OUTPUT
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
Circuitry within the GAL20RA10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1µs MAX). As a result,
the state on the registered output pins (if they are enabled) will
be high on power-up, because of the inverting buffer on the output
pins. This feature can greatly simplify state machine design by
providing a known state on power-up. The timing diagram for
power-up is shown to the right. Because of the asynchronous
nature of system power-up, some conditions must be met to
provide a valid power-up reset of the GAL20RA10. First, the Vcc
rise must be monotonic. Second, the clock input must be at a static
TTL level as shown in the diagram during power up. The regis-
ters will reset within a maximum of 1µs. As in normal system op-
eration, avoid clocking the device until all input and feedback path
setup times have been met. The clock must also meet the mini-
mum pulse width requirements.
Input/Output Equivalent Schematics
PIN
PIN
Feedback
Active Pull-up
Circuit
Vcc
(Vref Typical = 3.2V)
Active Pull-up
Circuit
(Vref Typical = 3.2V)
Vcc
Tri-State
Control
Vref
Vcc
Vcc
Vref
ESD
Protection
Circuit
Data
Output
PIN
PIN
ESD
Protection
Circuit
Feedback
(To Input Buffer)
Typical Input
Typical Output
11
Specifications GAL20RA10
GAL10RA10B-7/-10: Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
Normalized Tsu vs Vcc
Normalized Tco vs Vcc
1.2
1.1
1
1.4
1.2
1
1.2
1.1
1
0.9
0.8
0.9
0.8
0.8
0.6
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
Supply Voltage (V)
Supply Voltage (V)
Supply Voltage (V)
Normalized Tsu vs Temp
Normalized Tpd vs Temp
Normalized Tco vs Temp
1.6
1.4
1.2
1
1.3
1.2
1.1
1
1.3
1.2
1.1
1
0.9
0.8
0.7
0.9
0.8
0.7
0.8
0.6
Temperature (deg. C)
Temperature (deg. C)
Temperature (deg. C)
Delta Tpd vs # of Outputs
Switching
Delta Tco vs # of Outputs
Switching
0
-0.5
-1
0
-0.5
-1
-1.5
-2
-1.5
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
Number of Outputs Switching
Number of Outputs Switching
Delta Tpd vs Output
Loading
Delta Tco vs Output
Loading
8
6
4
2
0
8
6
RISE
FALL
RISE
FALL
4
2
0
-2
-2
-4
-4
0
50
100
150
0
50
100
150
Output Loading (pF)
Output Loading (pF)
12
Specifications GAL20RA10
GAL10RA10B-7/-10: Typical AC and DC Characteristic Diagrams
Vol vs Iol
Voh vs Ioh
Voh vs Ioh
1
0.8
0.6
0.4
0.2
0
5
4
3
2
1
0
4
3.75
3.5
3.25
3
0
10
20
30
40
0
10
20
30
40
50
60
70
80
0.00
1.00
2.00
3.00
4.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
Normalized Icc vs Temp
Normalized Icc vs Freq.
1.2
1.1
1
1.3
1.2
1.1
1
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.9
0.8
0.7
0.9
0.8
4.50
4.75
5.00
5.25
5.50
0
25
50
75
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
Input Clamp (Vik)
Delta Icc vs Vin (1 input)
0
10
20
30
40
50
60
70
80
90
10
8
6
4
2
0
0.20 0.70 1.20 1.70 2.20 2.70 3.20 3.70
-2.00
-1.50
-1.00
-0.50
0.00
Vin (V)
Vik (V)
13
Specifications GAL20RA10
GAL10RA10B-15/-20/-30: Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
Normalized Tsu vs Vcc
Normalized Tco vs Vcc
1.2
1.1
1
1.6
1.4
1.2
1
1.1
1.05
1
PT H->L
PT L->H
RISE
FALL
0.8
0.6
0.4
0.9
0.95
0.8
0.9
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
Supply Voltage (V)
Supply Voltage (V)
Supply Voltage (V)
Normalized Tsu vs Temp
Normalized Tpd vs Temp
Normalized Tco vs Temp
1.4
1.3
1.2
1.1
1
1.3
1.3
1.2
1.1
1
PT H->L
PT L->H
RISE
FALL
1.2
1.1
1
0.9
0.8
0.7
0.6
0.9
0.8
0.7
0.9
0.8
0.7
Temperature (deg. C)
Temperature (deg. C)
Temperature (deg. C)
Delta Tpd vs # of Outputs
Switching
Delta Tco vs # of Outputs
Switching
0
-0.2
-0.4
-0.6
-0.8
-1
0
-0.2
-0.4
-0.6
-0.8
-1
RISE
RISE
FALL
9
FALL
9
-1.2
-1.2
1
2
3
4
5
6
7
8
10
1
2
3
4
5
6
7
8
10
Number of Outputs Switching
Number of Outputs Switching
Delta Tpd vs Output
Loading
Delta Tco vs Output
Loading
14
12
10
8
12
10
8
RISE
FALL
RISE
FALL
6
6
4
4
2
2
0
-2
-4
0
0
-2
-4
0
50
100
150
200
250
300
50
100
150
200
250
300
Output Loading (pF)
Output Loading (pF)
14
Specifications GAL20RA10
GAL10RA10B-15/-20/-30: Typical AC and DC Characteristic Diagrams
Vol vs Iol
Voh vs Ioh
Voh vs Ioh
3
2.5
2
5
4
3
2
1
0
3.75
3.625
3.5
1.5
1
3.375
0.5
0
3.25
0.00
20.00
40.00
60.00
80.00
0.00 10.00 20.00 30.00 40.00 50.00 60.00
0.00
1.00
2.00
3.00
4.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
Normalized Icc vs Temp
Normalized Icc vs Freq.
1.20
1.10
1.00
0.90
0.80
1.2
1.40
1.30
1.20
1.10
1.00
0.90
0.80
1.1
1
0.9
0.8
4.50
4.75
5.00
5.25
5.50
0
25
50
75
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
Delta Icc vs Vin (1 input)
Input Clamp (Vik)
5
4
3
2
1
0
0
10
20
30
40
50
60
70
80
90
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
-2.00
-1.00
0.00
Vin (V)
Vik (V)
15
相关型号：
©2020 ICPDF网 联系我们和版权申明