GAL26V12C-20LP [LATTICE]
EE PLD, 20ns, PAL-Type, CMOS, PDIP28, PLASTIC, DIP-28;
| 型号： | GAL26V12C-20LP |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | EE PLD, 20ns, PAL-Type, CMOS, PDIP28, PLASTIC, DIP-28 时钟 输入元件 光电二极管 可编程逻辑 |
| 文件： | 总16页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GAL26V12
High Performance E2CMOS PLD
Generic Array LogicTM
FEATURES
FUNCTIONAL BLOCK DIAGRAM
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 142.8 MHz
I/CLK 1
INPUT
I/O/Q
PRESET
— 4.5 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
8
OLMC 0
INPUT
— UltraMOS® Advanced CMOS Technology
8
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
OLMC 1
OLMC 2
• LOW POWER CMOS
— 90 mA Typical Icc
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/Guaranteed 100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
INPUT
INPUT/CLK 2
INPUT
10
12
14
16
16
14
12
10
8
OLMC 3
OLMC 4
OLMC 5
INPUT
• TWELVE OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
INPUT
OLMC 6
OLMC 7
OLMC 8
OLMC 9
OLMC 10
OLMC 11
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
INPUT
INPUT
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
INPUT
INPUT
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
INPUT
DESCRIPTION
8
INPUT
The GAL26V12, at 7.5ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E2) floating gate technology to provide the highest perform-
ance available of any 26V12 device on the market. E2 technol-
ogy offers high speed (<100ms) erase times, providing the ability
to reprogram or reconfigure the device quickly and efficiently.
RESET
PACKAGE DIAGRAMS
DIP
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL26V12 is fully function/fuse map/parametric
compatible with other 26V12 devices.
1
28
I
I/CLK1
PLCC
I/O/Q
I
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 100% field programmability and
functionality of all GAL® products. LATTICE also guarantees 100
erase/rewrite cycles.
I/CLK2
GAL
26V12
I
4
2
28
26
25
I
5
7
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
Vcc
7
I
I
I
I
I
21
VCC
23
GAL26V12
Top View
I
I
I
I
9
21
19
11
I
I
12
14
16
18
14
15 I/O/Q
I
Copyright ©2000 Lattice Semiconductor Corp. GAL, E2CMOS and UltraMOS are registered trademarks of Lattice Semiconductor Corp. Generic Array Logic is a trademark of Lattice Semiconduc-
tor Corp. The specifications herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A.
Tel. (503) 268-8000 or 1-800-LATTICE; FAX (503) 268-8556
November 2000
Specifications GAL26V12
GAL 26V12 ORDERING INFORMATION
Commercial Grade Specifications
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA)
Ordering #
Package
7.5
10
6
7
4.5
7
130
130
130
105
105
105
105
GAL26V12C-7LJ
28-Lead PLCC
28-Pin Plastic DIP
28-Lead PLCC
28-Pin Plastic DIP
28-Lead PLCC
28-Pin Plastic DIP
28-Lead PLCC
GAL26V12C-10LP
GAL26V12C-10LJ
GAL26V12C-15LP
GAL26V12C-15LJ
GAL26V12C-20LP
GAL26V12C-20LJ
15
20
10
12
8
12
Industrial Grade Specifications
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA)
Ordering #
Package
28-Pin Plastic DIP
28-Lead PLCC
10
15
20
7
7
8
150
150
150
150
150
150
GAL26V12C-10LPI
GAL26V12C-10LJI
GAL26V12C-15LPI
GAL26V12C-15LJI
GAL26V12C-20LPI
GAL26V12C-20LJI
10
12
28-Pin Plastic DIP
28-Lead PLCC
12
28-Pin Plastic DIP
28-Lead PLCC
PART NUMBER DESCRIPTION
_
XXXXXXXX XX X X X
GAL26V12C Device Name
Speed (ns)
Grade
Blank = Commercial
I = Industrial
L = Low Power Power
Package P = Plastic DIP
J = PLCC
2
Specifications GAL26V12
OUTPUT LOGIC MACROCELL (OLMC)
The GAL26V12 has a variable number of product terms per
OLMC. Of the ten available OLMCs, four OLMCs have access
to eight product terms (pins 15, 16, 26 and 27), two have ten prod-
uct terms (pins 17 and 25), two have twelve product terms (pins
18 and 24), two have fourteen product terms (pins 19 and 23), and
two OLMCs have sixteen product terms (pins 20 and 22). In ad-
dition to the product terms available for logic, each OLMC has an
additional product-term dedicated to output enable control.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either
active high or active low.
In the registered mode configuration the clock source for the
register can be selected. The two clock options, CLK1 and CLK2,
originate from input pin1 and pin4 respectively.
The GAL26V12 has a product term forAsynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two
product terms are common to all registered OLMCs. The Asyn-
chronous Reset sets all registers to zero any time this dedicated
product term is asserted. The Synchronous Preset sets all reg-
isters to a logic one on the rising edge of the next clock pulse after
this product term is asserted.
A R
D
4 TO 1
M U X
Q
CLK1/
CLK2
Q
NOTE: The AR and SP product terms will force the Q output of
the flip-flop into the same state regardless of the polarity of the
output. Therefore, a reset operation, which sets the register output
to a zero, may result in either a high or low at the output pin,
depending on the pin polarity chosen.
S P
2 TO 1
MUX
GAL26V12 OUTPUT LOGIC MACROCELL (OLMC)
OUTPUT LOGIC MACROCELL CONFIGURATIONS
COMBINATORIAL MODE
Each of the Macrocells of the GAL26V12 has two primary func-
tional modes: registered, and combinatorial I/O. The modes and
the output polarity are set by four architecture bits (S0, S1, S2 and
S3), which are normally controlled by the logic compiler. Each
of these two primary modes, and the bit settings required to enable
them, are described below and on the following page.
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the
output buffer drive either true (active high) or inverted (active low).
Output tri-state control is available as an individual product-term
for each output, and may be individually set by the compiler as
either “on” (dedicated output), “off” (dedicated input), or “product-
term driven” (dynamic I/O).
REGISTERED MODE
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC’s D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an in-
dividual product-term for each OLMC, and can therefore be de-
fined by a logic equation.
In combinatorial mode there are also two options for the feedback.
The first feedback option into the AND array is from the I/O pin
side of the output buffer. Both polarities (true and inverted) of the
pin are fed back into theAND array. The second option is to drive
the feedback from /Q of the buried register. This option provides
the combinatorial output with the ability to register the feedback
of the same combinatorial output.
There are two options for the feedback of the registered mode -
- internal /Q feedback and I/O pin feedback. The D flip-flop’s /Q
output is fed back into theAND array, with both the true and com-
plement of the feedback available as inputs to the AND array.
Similarly the I/O pin feedback with both true and complement input
to the AND array. The resulting polarity depends on the input
polarity selection as well as the registered I/O output polarity
configuration.
3
Specifications GAL26V12
REGISTERED MODE
A R
A R
D
Q
Q
D
Q
Q
CLK1/
CLK2
CLK1/
CLK2
S P
S P
ACTIVE HIGH REGISTERED OUTPUT
WITH BURIED FEEDBACK
ACTIVE LOW REGISTERED OUTPUT
WITH BURIED FEEDBACK
S0 = 1
S1 = 0
S3 = 1
S2 = 1 Selects CLK1
S2 = 0 Selects CLK2
S0 = 0
S1 = 0
S3 = 1
S2 = 1 Selects CLK1
S2 = 0 Selects CLK2
A R
A R
D
D
Q
Q
Q
Q
CLK1/
CLK2
CLK1/
CLK2
S P
S P
ACTIVE LOW REGISTERED OUTPUT
WITH I/O FEEDBACK
ACTIVE HIGH REGISTERED OUTPUT
WITH I/O FEEDBACK
S0 = 0
S1 = 0
S3 = 0
S2 = 1 Selects CLK1
S2 = 0 Selects CLK2
S0 = 1
S1 = 0
S3 = 0
S2 = 1 Selects CLK1
S2 = 0 Selects CLK2
4
Specifications GAL26V12
COMBINATORIAL MODE
ACTIVE HIGH COMBINATORIAL OUTPUT
WITH I/O FEEDBACK
ACTIVE LOW COMBINATORIAL OUTPUT
WITH I/O FEEDBACK
S0 = 1
S1 = 1
S3 = 1
S2 = 1 Selects CLK1
S2 = 0 Selects CLK2
S0 = 0
S1 = 1
S3 = 1
S2 = 1 Selects CLK1
S2 = 0 Selects CLK2
A R
AR
D
Q
Q
D
Q
Q
CLK1/
CLK2
CLK1/
CLK2
SP
SP
ACTIVE LOW COMBINATORIAL OUTPUT
WITH BURIED REGISTER FEEDBACK
ACTIVE HIGH COMBINATORIAL OUTPUT
WITH BURIED REGISTER FEEDBACK
S0 = 0
S1 = 1
S3 = 0
S2 = 1 Selects CLK1
S2 = 0 Selects CLK2
S0 = 1
S1 = 1
S3 = 0
S2 = 1 Selects CLK1
S2 = 0 Selects CLK2
5
Specifications GAL26V12
GAL26V12 LOGIC DIAGRAM / JEDEC FUSEMAP
1
0
4
8
12
16
20
24
28
32
36
40
44
48
28
27
ASYNCH
RESET
0000
0052
.
.
.
OLMC 27
S0-7800
S1-7812
S2-7824
S3-7836
0468
2
3
0520
.
.
.
OLMC 26
26
25
S0-7801
S1-7813
S2-7825
S3-7837
0936
0988
.
.
.
.
OLMC 25
S0-7802
S1-7814
S2-7826
S3-7838
1508
4
5
1560
.
.
.
.
.
OLMC 24
24
23
S0-7803
S1-7815
S2-7827
S3-7839
2184
2236
.
.
.
.
.
.
OLMC 23
S0-7804
S1-7816
S2-7828
S3-7840
2964
6
3016
.
.
OLMC 22
.
.
.
.
.
22
21
S0-7805
S1-7817
S2-7829
S3-7841
7
VCC
3848
8
0
4
8
12
16
20
24
28
32
36
40
44
48
CLK1 CLK2 AR SP
6
Specifications GAL26V12
GAL26V12 LOGIC DIAGRAM / JEDEC FUSEMAP (CONT.)
0
4
8
12
16
20
24
28
32
36
40
44
48
CLK1 CLK2 AR SP
3900
.
.
OLMC 20
.
.
.
.
.
20
19
S0-7806
S1-7818
S2-7830
S3-7842
4732
9
4784
.
.
.
.
.
.
OLMC 19
S0-7807
S1-7819
S2-7831
S3-7843
5512
10
11
5564
.
.
.
.
.
OLMC 18
18
17
S0-7808
S1-7820
S2-7832
S3-7844
6136
6188
.
.
.
.
OLMC 17
S0-7809
S1-7821
S2-7833
S3-7845
6760
12
13
14
6812
.
.
.
OLMC 16
16
15
S0-7810
S1-7822
S2-7834
S3-7846
7228
7280
.
.
.
OLMC 15
S0-7811
S1-7823
S2-7835
S3-7847
7696
SYNCH
PRESET
7748
0
4
8
12
16
20
24
28
32
36
40
44
48
L
S
B
M
S
B
B0
B1
B3
B4
B5
B6
B7
7848 7849...
...7910 7911
Electronic Signature
7
SpecificationsGAL26V12C
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING COND.
Commercial Devices:
Supply voltage VCC ....................................... -0.5 to +7V
Ambient Temperature (TA) ............................. 0 to +75°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.75 to +5.25V
Input voltage applied ........................... -2.5 to VCC +1.0V
Off-state output voltage applied........... -2.5 to VCC +1.0V
Storage Temperature..................................-65 to 150°C
Ambient Temperature with
Industrial Devices:
Ambient Temperature (TA) ........................... –40 to 85°C
Supply voltage (VCC)
Power Applied .........................................-55 to 125°C
1. Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
with Respect to Ground ......................... +4.5 to +5.5V
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.4
MAX. UNITS
VIL
VIH
IIL1
Input Low Voltage
Vss – 0.5
2.0
—
—
—
—
—
—
—
—
—
—
0.8
Vcc+1
–10
10
V
V
Input High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
Output Low Voltage
0V ≤ VIN ≤ VIL (MAX.)
3.5V ≤ VIN ≤ VCC
µA
µA
V
IIH
—
VOL
VOH
IOL
IOL = MAX. Vin = VIL or VIH
IOH = MAX. Vin = VIL or VIH
—
0.5
Output High Voltage
2.4
—
—
V
Low Level Output Current
High Level Output Current
Output Short Circuit Current
16
mA
mA
mA
IOH
IOS2
—
–3.2
–130
VCC = 5V VOUT = 0.5V TA = 25°C
–30
COMMERCIAL
ICC3
Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V
ftoggle = 15MHz
ftoggle = 15MHz
-7/-10
—
—
90
75
130
105
mA
mA
Outputs Open
-15/-20
INDUSTRIAL
ICC3
Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V
-10/-15/-20
—
110
150
mA
Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Icc specified for a ten-bit binary counter pattern.
4) Typical values are at Vcc = 5V and TA = 25 °C
8
SpecificationsGAL26V12C
Commercial
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
-7 -10
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
-15
-20
TEST
COND.1
DESCRIPTION
PARAM.
UNITS
tpd
tco
tcf2
tsu1
tsu2
th
A
A
Input or I/O to Combinatorial Output
Clock to Output Delay
—
—
—
6
7.5
4.5
2
—
—
—
7
10
7
—
—
—
10
10
15
8
—
—
—
12
12
20
12
10
—
—
ns
ns
ns
ns
ns
—
—
—
Clock to Feedback Delay
2.5
—
—
2.5
—
—
Setup Time, Input or Fdbk before Clk↑
Synch. Preset before Clk↑
—
—
5.5
6.5
—
Hold Time, Input or Feedback after Clock↑
0
—
—
0
—
—
0
—
—
0
—
—
ns
A
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
95.2
71.4
55.5
41.6
MHz
fmax3
A
A
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
125.0
142.8
—
—
105.2
125
—
—
80.0
83.3
—
—
45.4
62.5
—
—
MHz
MHz
Maximum Clock Frequency with
No Feedback
twh
twl
—
—
B
Clock Pulse Duration, High
3.5
3.5
—
—
—
6
—
—
7.5
7.5
9
4
4
—
—
10
10
13
—
—
—
6
—
—
15
15
20
—
—
—
8
—
—
20
20
20
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
Clock Pulse Duration, Low
6
8
ten
tdis
tar
Input or I/O to Output Enabled
—
—
—
8
—
—
—
10
10
10
—
—
—
15
15
12
C
Input or I/O to Output Disabled
Input or I/O to Asynch. Reset of Register
Asynchronous Reset Pulse Duration
Asynch. Reset to Clock Recovery Time
Synch. Preset to Clock Recovery Time
A
tarw
tarr
tspr
—
—
—
—
—
—
5
8
5
8
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
CAPACITANCE (TA = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
Input Capacitance
I/O Capacitance
MAXIMUM*
UNITS
pF
TEST CONDITIONS
VCC = 5.0V, VI = 2.0V
VCC = 5.0V, VI/O = 2.0V
CI
8
8
CI/O
pF
*Guaranteed but not 100% tested.
9
SpecificationsGAL26V12C
Commercial
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
-10
MIN. MAX. MIN. MAX. MIN. MAX.
-15
-20
TEST
COND.1
DESCRIPTION
PARAM.
UNITS
tpd
tco
tcf2
tsu1
tsu2
th
A
A
Input or I/O to Combinatorial Output
Clock to Output Delay
—
—
—
7
10
7
—
—
—
10
10
15
8
—
—
—
12
12
20
12
10
—
—
ns
ns
ns
ns
ns
—
—
—
Clock to Feedback Delay
2.5
—
—
2.5
—
—
Setup Time, Input or Fdbk before Clk↑
Synch. Preset before Clk↑
6.5
—
Hold Time, Input or Feedback after Clock↑
0
—
—
0
—
—
0
—
—
ns
A
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
71.4
55.5
41.6
MHz
fmax3
A
A
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
105.2
125.0
—
—
80.0
83.3
—
—
45.4
62.5
—
—
MHz
MHz
Maximum Clock Frequency with
No Feedback
twh
twl
—
—
B
Clock Pulse Duration, High
4
4
—
—
10
10
13
—
—
—
6
—
—
15
15
20
—
—
—
8
—
—
20
20
20
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
Clock Pulse Duration, Low
6
8
ten
tdis
tar
Input or I/O to Output Enabled
—
—
—
8
—
—
—
10
10
10
—
—
—
15
15
12
C
Input or I/O to Output Disabled
Input or I/O to Asynch. Reset of Register
Asynchronous Reset Pulse Duration
Asynch. Reset to Clock Recovery Time
Synch. Preset to Clock Recovery Time
A
tarw
tarr
tspr
—
—
—
8
8
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
CAPACITANCE (TA = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
Input Capacitance
I/O Capacitance
MAXIMUM*
UNITS
pF
TEST CONDITIONS
VCC = 5.0V, VI = 2.0V
VCC = 5.0V, VI/O = 2.0V
CI
8
8
CI/O
pF
*Guaranteed but not 100% tested.
10
Specifications GAL26V12
SWITCHING WAVEFORMS
INPUT or
I/O FEEDBACK
INPUT or
I/O FEEDBACK
VALID INPUT
VALID INPUT
t
s u
th
t
pd
CLK
COMBINATORIAL
OUTPUT
t
c o
REGISTERED
OUTPUT
Combinatorial Output
1/ fm a x
(external fdbk)
Registered Output
INPUT or
I/O FEEDBACK
t
dis
ten
OUTPUT
CLK
1/
fmax (internal fdbk )
Input or I/O to Output Enable/Disable
t
c f
t
su
REGISTERED
FEEDBACK
fmax with Feedback
t
w l
tw h
CLK
Clock Width
t
h
INPUT or
INPUT or
I/O FEEDBACK
DRIVING SP
I/O FEEDBACK
DRIVING AR
tsu
t
spr
t
arw
t
arr
CLK
REGISTERED
OUTPUT
t
c o
REGISTERED
OUTPUT
tar
CLK
Synchronous Preset
Asynchronous Reset
11
Specifications GAL26V12
fmax DESCRIPTIONS
C L K
C L K
L O G I C
L O G I C
A R R A Y
R E G I S T E R
A R R A Y
R E G I S T E R
t
s u
tc o
t
c f
p d
fmax with External Feedback 1/(tsu+tco)
t
Note: fmax with external feedback is cal-
culated from measured tsu and tco.
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by sub-
tracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to tcf + tpd.
C L K
L O G I C
R E G I S T E R
A R R A Y
fmax With No Feedback
Note: fmax with no feedback may be less
than 1/twh + twl. This is to allow for a clock
duty cycle of other than 50%.
SWITCHING TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
+5V
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
2ns 10% – 90%
1.5V
R
1
1.5V
See Figure
3-state levels are measured 0.5V from steady-state active
level.
FROM OUTPUT (O/Q)
UNDER TEST
TEST POINT
Output Load Conditions (see figure)
C L*
R
2
Test Condition
R1
R2
CL
A
300Ω
∞
390Ω
390Ω
390Ω
390Ω
390Ω
50pF
50pF
50pF
5pF
B
Active High
Active Low
Active High
Active Low
300Ω
∞
C
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
300Ω
5pF
12
Specifications GAL26V12
OUTPUT REGISTER PRELOAD
ELECTRONIC SIGNATURE
An electronic signature is provided in every GAL26V12 device.
It contains 64 bits of reprogrammable memory that can contain
user-defined data. Some uses include user ID codes, revision
numbers, or inventory control. The signature data is always
available to the user independent of the state of the security cell.
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state condi-
tions.
SECURITY CELL
A security cell is provided in every GAL26V12 device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the
device, so the original configuration can never be examined once
this cell is programmed. The Electronic Signature is always avail-
able to the user, regardless of the state of this control cell.
The GAL26V12 device includes circuitry that allows each regis-
tered output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If
necessary, approved GALprogrammers capable of executing test
vectors perform output register preload automatically.
INPUT BUFFERS
LATCH-UP PROTECTION
GAL26V12 devices are designed with TTL level compatible in-
put buffers. These buffers have a characteristically high imped-
ance, and present a much lighter load to the driving logic than bi-
polar TTL devices.
GAL26V12 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias minimizes the
potential for latch-up caused by negative input undershoots.
Additionally, outputs are designed with n-channel pull-ups instead
of the traditional p-channel pull-ups in order to eliminate latch-up
due to output overshoots.
DEVICE PROGRAMMING
GAL devices are programmed using a Lattice-approved Logic
Programmer, available from a number of manufacturers (see the
the GAL Development Tools section). Complete programming of
the device takes only a few seconds. Erasing of the device is
transparent to the user, and is done automatically as part of the
programming cycle.
13
Specifications GAL26V12
POWER-UP RESET
Circuitry within the GAL26V12 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (tpr, 1µs MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the
asynchronous nature of system power-up, some conditions must
be met to guarantee a valid power-up reset of the GAL26V12.
First, the VCC rise must be monotonic. Second, the clock input
must be at static TTL level as shown in the diagram during power
up. The registers will reset within a maximum of tpr time. As in nor-
mal system operation, avoid clocking the device until all input and
feedback path setup times have been met. The clock must also
meet the minimum pulse width requirements.
4.0 V
Vcc
CLK
tpr
INTERNAL
REGISTER
Q - OUTPUT
Internal Register
Reset to Logic "0"
ACTIVE LOW
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
Device Pin
Reset to Logic "0"
ACTIVE HIGH
OUTPUT REGISTER
INPUT/OUTPUT EQUIVALENT SCHEMATICS
O u t p u t
Da t a
P I N
PIN
F e e d b a c k
Vcc
V c c
Tri-S tat e
Cont rol
Vcc
Vcc
ESD
Protection
Circuit
O u t p u t
Da t a
P I N
PIN
ESD
Protection
Circuit
Feedback
(To Input Buffer)
Output
Input
14
Specifications GAL26V12
TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
Normalized Tco vs Vcc
Normalized Tsu vs Vcc
1.2
1.2
1.2
1.1
1.1
1
1.1
1
1
0.9
0.8
0.9
0.9
0.8
0.8
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
Supply Voltage (V)
Supply Voltage (V)
Supply Voltage (V)
Normalized Tsu vs Temp
Normalized Tpd vs Temp
Normalized Tco vs Temp
1.4
1.3
1.2
1.1
1
1.3
1.2
1.1
1
1.3
1.2
1.1
1
0.9
0.8
0.7
0.9
0.8
0.7
0.9
0.8
0.7
-55
-25
0
25
50
75
100 125
-55
-25
0
25
50
75
100 125
-55
-25
0
25
50
75
100 125
Temperature (deg. C)
Temperature (deg. C)
Temperature (deg. C)
Delta Tpd vs # of Outputs
Switching
Delta Tco vs # of Outputs
Switching
0
-0.25
-0.5
0
-0.25
-0.5
-0.75
-1
-0.75
-1
1
2
3
4
5
6
7
8
9
10 11 12
1
2
3
4
5
6
7
8
9
10 11 12
Number of Outputs Switching
Number of Outputs Switching
Delta Tpd vs Output Loading
Delta Tco vs Output Loading
12
10
8
12
10
8
RISE
FALL
RISE
FALL
6
6
4
4
2
2
0
0
-2
0
-2
0
50
100
150
200
250
300
50
100
150
200
250
300
Output Loading (pF)
Output Loading (pF)
15
Specifications GAL26V12
TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
Voh vs Ioh
Voh vs Ioh
3
2.5
2
5
4
3
2
1
0
4
3.75
3.5
3.25
3
1.5
1
0.5
0
0.00
20.00
40.00
60.00
80.00 100.00
0.00 10.00 20.00 30.00 40.00 50.00 60.00
0.00
1.00
2.00
3.00
4.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
Normalized Icc vs Temp
Normalized Icc vs Freq.
1.3
1.2
1.1
1
1.3
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
1.2
1.1
1
0.9
0.8
0.7
0.9
0.8
0.7
4.50
4.75
5.00
5.25
5.50
-55
-25
0
25
50
75
100 125
0
25
50
75
100
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
Input Clamp (Vik)
Delta Icc vs Vin (1 input)
10
0
10
20
30
40
50
60
8
6
4
2
0
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
-2.00
-1.50
-1.00
-0.50
0.00
Vin (V)
Vik (V)
16
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