ICE40HX1K-CM225 [LATTICE]
iCE40⢠HX-Series Ultra Low-Power mobileFPGA⢠Family; iCE40â ?? ¢ HX系列超低功耗mobileFPGAâ ?? ¢家族
| 型号： | ICE40HX1K-CM225 |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | iCE40⢠HX-Series Ultra Low-Power mobileFPGA⢠Family |
| 文件： | 总12页 (文件大小：861K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
iCE40™ HX-Series
Ultra Low-Power
mobileFPGA™ Family
March 30, 2012 (1.31)
Data Sheet
Figure 1: iCE40 HX-Series Family Architectural Features
HX-Series - Tablet targeted series
Programmable
optimized for high performance
Logic Block (PLB)
200 µA at f =0 kHz
Low cost package offerings
80% faster than iCE65
Tablet resolution HD video and imaging
(Typical)
I/O Bank 0
Programmable Interconnect
Proven, high-volume 40 nm, low-power
CMOS technology
Integrated Phase-Locked Loop (PLL)
Clock multiplication/division for display, SerDes,
and memory interface applications
Up to 533 MHz PLL Output
Reprogrammable from a variety of
methods and sources
Flexible programmable logic and
programmable interconnect fabric
NVCM
PLL
8K look-up tables (LUT4) and flip-flops
Low-power logic and interconnect
SPI
I/O Bank 2
Complete iCEcube™ development system
Windows® and Linux® support
Config
Carry logic
Four-input
Look-Up Table
(LUT4)
Phase-Locked
Loop
VHDL and Verilog logic synthesis
Place and route software
Nonvolatile Configuration
Memory (NVCM)
Flip-flop with enable
and reset controls
Design and IP core libraries
Low-cost iCEman40HX development board
Table 1: iCE40HX Ultra Low-Power Programmable Logic Family Summary
Part Number
Logic Cells (LUT + Flip-Flop)
RAM4K Memory Blocks
HX640
640
HX1K
1,280
16
HX4K
3,520
20
HX8K
7,680
32
8
RAM4K RAM bits
32K
1
120 Kb
200 µA
67
64K
1
245 Kb
267 µA
95
80K
2
533 Kb
667 µA
95
128K
2
1,057 Kb
1100 µA
206
Phase-Locked Loops (PLLs)
Configuration bits (maximum)
Core Operating Power 0 KHz1
Maximum Programmable I/O Pins
Maximum Differential Input Pairs
8
11
12
26
Package
225-ball BGA
132-ball BGA
284-ball BGA
256-ball BGA
Code Area mm Pitch mm Programmable I/O: Max I/O (LVDS)
CM225
CB132
CB284
CT256
VQ100
7x7
0.4
0.5
0.5
0.8
0.5
178(23)
8x8
95(11)
72(9)
95(12)
95(12)
12x12
14x14
14x14
206(26)
67(8)
100-pin quad flat pack
Note 1: At 1.2V VCC
© 2007-2012 by Lattice Semiconductor Corporation. All rights reserved.
www.latticesemi.com
(1.31, 30-MAR-2012)
1
iCE40 HX-Series Ultra-Low Power mobileFPGA™ Family
Ordering Information
Figure 2 describes the iCE40HX ordering codes for all packaged components. See the separate DiePlus data sheets
when ordering die-based products. See the separate iCE40 Pinout Excel files for package and pinout specifications.
Figure 2: iCE40HX Ordering Codes (packaged, non-die components)
iCE40HX 8K - CM 225
High Performance
Package Leads
Series
Package Style
CM= chip-scale ball grid (0.4 mm pitch)
CB= chip-scale ball grid (0.5 mm pitch)
CT= chip-scale ball grid (0.8 mm pitch)
VQ = Very Thin Quad flat pack (0.5 mm pitch)
TQ = Thin Quad flat pack (0.5 mm pitch)
QN= quad flat no-lead (0.5 mm pitch)
Logic Cells
640, 1K, 4K, 8K
iCE40HX8K-CM225
225-ball Chip-Scale BGA Package
(7x7 mm footprint, 0.4 mm pitch)
Lattice Semiconductor Corporation
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2
iCE40 HX-Series Ultra-Low Power mobileFPGA™ Family
Electrical Characteristics
All parameter limits are specified under worst-case supply voltage, junction temperature, and processing conditions.
Absolute Maximum Ratings
Stresses beyond those listed under Table 2 may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions beyond those listed under the Recommended
Operating Conditions is not implied. Exposure to absolute maximum conditions for extended periods of time
adversely affects device reliability.
Table 2: Absolute Maximum Ratings
Symbol
Description
Minimum Maximum
Units
VCC
VPP_2V5
VPP_FAST
VCCIO_0
VCCIO_1
VCCIO_2
VCCIO_3
SPI_VCC
VIN_0
Core supply Voltage
–0.5
1.42
V
V
V
V
VPP_2V5 NVCM programming and operating supply
Optional fast NVCM programming supply
I/O bank supply voltage (I/O Banks 0, 1, 2 and 3 plus SPI
interface)
–0.5
4.00
Voltage applied to PIO pin within a specific I/O bank (I/O
Banks 0, 1, 2 and 3 plus SPI interface)
–1.0
3.6
V
VIN_1
VIN_2
VIN_SPI
VIN_3
VCCPLL
IOUT
TJ
TSTG
Analog voltage supply to the Phase Locked Loop (PLL)
DC output current per pin
Junction temperature
–0.5
—
–55
–65
1.30
20
125
150
V
mA
°C
°C
Storage temperature, no bias
Recommended Operating Conditions
Table 3: Recommended Operating Conditions
Minimum Nominal Maximum Units
Symbol
VCC
Description
Core supply voltage
VPP_2V5 NVCM
High Performance, low-power
1.14
1.30
2.30
2.30
1.20
—
—
1.26
3.47
3.47
3.00
V
V
V
V
VPP_2V51
Release from Power-on Reset
Configure from NVCM
NVCM programming
programming and operating
supply
—
VPP_FAST2
SPI_VCC
VCCIO_0
VCCIO_1
VCCIO_2
VCCIO_3
SPI_VCC
VCCPLL3
TA
Optional fast NVCM programming supply
SPI interface supply voltage
Leave unconnected in application
1.71
2.70
2.38
—
3.30
2.50
3.47
3.47
2.63
V
V
V
I/O standards, all banks
LVCMOS33
LVCMOS25, LVDS
LVCMOS18, SubLVDS
1.71
1.43
1.80
1.50
1.89
1.58
V
V
LVCMOS15
Analog voltage supply to the Phase Locked Loop (PLL)
Ambient temperature
NVCM programming temperature
1.14
–40
10
1.20
—
25
1.26
85
30
V
°C
°C
TPROG
Notes:
1. VPP_2V5 must be connected to a valid voltage, when the iCE40HX device is active.
2. VPP_FAST, used only for fast production programming, must be left floating or unconnected in application.
3. VCCPLL must be tied to VCC when PLL is not used.
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iCE40 HX-Series Ultra-Low Power mobileFPGA™ Family
I/O Characteristics
Table 4: PIO Pin Electrical Characteristics
Symbol
Description
Conditions
Minimum
Nominal
Maximum
±10
Units
µA
µA
Il
IOZ
Input pin leakage current VIN = VCCIOmax to 0 V
Three-state I/O pin (Hi-Z) VO = VCCIOmax to 0 V
leakage current
±10
CPIO
CGBIN
PIO pin input capacitance
GBIN global buffer pin
6
6
pF
pF
input capacitance
RPULLUP Internal PIO pull-up
resistance during
VCCIO = 3.3V
VCCIO = 2.5V
VCCIO = 1.8V
60
80
120
160
50
kΩ
kΩ
kΩ
kΩ
mV
configuration
VCCIO = 1.5V
VHYST
Input hysteresis
VCCIO = 1.5V to 3.3V
NOTE: All characteristics are characterized and may or may not be tested on each pin on each device.
Single-ended I/O Characteristics
Table 5: I/O Characteristics
Nominal I/O
Output Current at
Voltage (mA)
Bank Supply
Voltage
3.3V
Input Voltage (V)
Output Voltage (V)
I/O Standard
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
IOH
VIL
VIH
VOL
0.4
0.4
0.4
0.4
VOH
2.40
2.00
1.40
1.20
IOL
0.80
0.70
2.00
1.70
8
8
2.5V
1.8V
1.5V
6
6
4
4
35% VCCIO 65% VCCIO
35% VCCIO 65% VCCIO
2
2
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iCE40 HX-Series Ultra-Low Power mobileFPGA™ Family
Differential Inputs
Figure 3: Differential Input Specifications
VCCIO_3
DPxxB
Differential
Input common mode voltage
input voltage
VIN_B
50%
VID
VIN_A
DPxxA
VICM
iC40 Differential
Input
GND
Input common mode voltage:
ꢁꢁꢀꢄꢅꢆ
ꢇ
ꢀꢁꢂꢃ
ꢀꢁ
ꢂꢃꢄ
Differential input voltage:
ꢀꢈꢃ| ꢀꢉꢅꢊꢋ
|
ꢀꢉꢅꢌ
Table 6: Recommended Operating Conditions for Differential Inputs
VCCIO_3 (V)
VID (mV)
Nom
VICM (V)
Nom
I/O
Standard
Min
Nom
Max
Min
Max
Min
Max
ꢁꢁꢀꢄꢅꢆ
ꢁꢁꢀꢄꢅꢆ
ꢁꢁꢀꢄꢅꢆ
LVDS
2.38
1.71
2.50
2.63
1.89
250
350
150
450
ꢇ ꢈꢉꢆꢈ
ꢊ ꢈꢉꢆꢈ
ꢇ
ꢇ
ꢇ
ꢁꢁꢀꢄꢅꢆ
ꢁꢁꢀꢄꢅꢆ
ꢁꢁꢀꢄꢅꢆ
SubLVDS
1.80
100
200
ꢇ ꢈꢉꢋꢌ
ꢊ ꢈꢉꢋꢌ
ꢇ
ꢇ
ꢇ
Differential Outputs
Figure 4: Differential Output Specifications
VCCIO_x
Differential
1%
RP
Output common mode voltage
output voltage
RS
RS
VOUT_B
50%
VOD
VOUT_A
VOCM
iC40 Differential
Output Pair
GND
Output common mode voltage:
Differential output voltage:
ꢁꢁꢀꢄꢅꢍ
ꢇ
ꢄꢁꢂꢃ
ꢀꢁꢍꢃꢄ
ꢄꢈꢃ| ꢄꢎꢏꢅꢊꢋ
|
ꢄꢎꢏꢅꢌ
Table 7: Recommended Operating Conditions for Differential Outputs
Ω
VCCIO_x (V)
VOD (mV)
Nom
VOCM (V)
I/O
Standard
Min
Nom
Max
Min
Max
Min
Nom
Max
RS
RP
ꢁꢁꢀꢄ
ꢁꢁꢀꢄ
ꢇ
ꢁꢁꢀꢄ
LVDS
2.38
1.71
2.50
2.63
1.89
150
140
300
350
150
400
ꢇ ꢈꢉꢎꢌ
ꢇ ꢈꢉꢎꢈ
ꢊ ꢈꢉꢎꢌ
ꢊ ꢈꢉꢎꢈ
ꢇ
ꢇ
ꢁꢁꢀꢄ
ꢇ
ꢁꢁꢀꢄ
ꢇ
ꢁꢁꢀꢄ
ꢇ
SubLVDS
1.80
270
120
100
200
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iCE40 HX-Series Ultra-Low Power mobileFPGA™ Family
AC Timing Guidelines
The following examples provide some guidelines of device performance. The actual performance depends on the
specific application and how it is physically implemented in the iCE65P FPGA using the Lattice iCEcube2 software.
The following guidelines assume typical conditions (VCC = 1.0 V or 1.2 V as specified, temperature = 25 ˚C). Apply
derating factors using the iCEcube2 timing analyzer to adjust to other operating regimes.
Programmable Logic Block (PLB) Timing
Table 8 provides timing information for the logic in a Programmable Logic Block (PLB), which includes the paths
shown in Figure 5 and Figure 6.
Figure 5 PLB Sequential Timing Circuit
PAD
PIO
DFF
PAD
PIO
D
Q
LUT4
Logic Cell
GBIN
PAD
GBUF
Figure 6 PLB Combinational Timing Circuit
PAD
PIO
PIO
LUT4
Logic Cell
Table 8: Typical Programmable Logic Block (PLB) Timing
Nominal VCC
1.2 V
Typ.
Description
units
MHz
ns
Sequential Logic Paths
Flip-flop toggle frequency. DFF flip-flop output fed back to LUT4 input with
4-input XOR, clocked on same clock edge
FTOGGLE
GBIN
input
DFF
GBIN
input
PIO
256
3.9
Logic cell flip-flop (DFF) clock-to-output time, measured from the DFF CLK
input to PIO output, including interconnect delay.
tCKO
clock
input
GBIN
input
output
Global Buffer Input (GBIN) delay, though Global Buffer (GBUF) clock network
to clock input on the logic cell DFF flip-flop.
tGBCKLC
DFF
clock
input
GBIN
input
PIO
1.5
ns
Minimum setup time on PIO input, through LUT4, to DFF flip-flop D-input
before active clock edge on the GBIN input, including interconnect delay.
tSULI
tHDLI
PIO
.67
0
ns
ns
input
GBIN
input
Minimum hold time on PIO input, through LUT4, to DFF flip-flop D-input
after active clock edge on the GBIN input, including interconnect delay.
input
Combinational Logic Paths
Asynchronous delay from PIO input pad to adjacent PLB interconnect.
tLUT4IN
PIO
input
LUT4
LUT4
input
LUT4
1.8
0.34
3.7
ns
ns
ns
Logic cell LUT4 combinational logic propagation delay, regardless of logic
complexity from input to output.
tILO
input output
LUT4 PIO
output output
Asynchronous delay from adjacent PLB interconnect to PIO output
pad.
tLUT4IN
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iCE40 HX-Series Ultra-Low Power mobileFPGA™ Family
Programmable Input/Output (PIO) Block
Table 9 provides timing information for the logic in a Programmable Logic Block (PLB), which includes the paths
shown in Figure 7 and Figure 8. The timing shown is for the LVCMOS25 I/O standard in all I/O banks. The
iCEcube2 development software reports timing adjustments for other I/O standards.
Figure 7: Programmable I/O (PIO) Pad-to-Pad Timing Circuit
PAD
PAD
PIO
PIO
Figure 8: Programmable I/O (PIO) Sequential Timing Circuit
PAD
PAD
PIO
PIO
INFF
OUTFF
D
Q
D
Q
GBIN
GBUF
Table 9: Typical Programmable Input/Output (PIO) Timing (LVCMOS25)
Nominal VCC
1.2 V
Description
units
Typ.
Synchronous Output Paths
OUTFF
Delay from clock input on OUTFF output flip-flop to PIO output
pad.
tOCKO
PIO
3.1
1.4
ns
clock
input
GBIN
input
output
OUTFF
clock
input
Global Buffer Input (GBIN) delay, though Global Buffer (GBUF)
clock network to clock input on the PIO OUTFF output flip-flop.
tGBCKIO
ns
Synchronous Input Paths
Setup time on PIO input pin to INFF input flip-flop before active
clock edge on GBIN input, including interconnect delay.
tSUPDIN
PIO
GBIN
input
PIO
0
ns
ns
input
GBIN
input
Hold time on PIO input to INFF input flip-flop after active clock
edge on the GBIN input, including interconnect delay.
tHDPDIN
1.6
input
Pad to Pad
tPADIN
Inter-
Asynchronous delay from PIO input pad to adjacent
PIO
1.8
3.4
ns
ns
connect interconnect.
input
Inter-
connect
Asynchronous delay from adjacent interconnect to PIO output
pad including interconnect delay.
tPADO
PIO
output
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iCE40 HX-Series Ultra-Low Power mobileFPGA™ Family
RAM4K Block
Table 10 provides timing information for the logic in a RAM4K block, which includes the paths shown in Figure 9.
Figure 9: RAM4K Timing Circuit
PAD
PAD
PIO
PIO
WDATA
RDATA
RAM4K
RAM Block
(256x16)
GBIN
GBIN
GBUF
GBUF
WCLK
RCLK
Table 10: Typical RAM4K Block Timing
Nominal VCC
1.2 V
Typ.
Description
Write Setup/Hold Time
Minimum write data setup time on PIO inputs before active clock
edge on GBIN input, include interconnect delay.
tSUWD
PIO
GBIN
input
0.44
0
ns
ns
input
GBIN
input
Minimum write data hold time on PIO inputs after active clock edge
on GBIN input, including interconnect delay.
tHDWD
PIO
input
Read Clock-Output-Time
Clock-to-output delay from RCLK input pin, through RAM4K RDATA
output flip-flop to PIO output pad, including interconnect delay.
tCKORD
RCLK
clock
input
GBIN
input
PIO
output
4.1
1.4
ns
ns
Global Buffer Input (GBIN) delay, though Global Buffer (GBUF)
clock network to the RCLK clock input.
tGBCKRM
RCLK
clock
input
Write and Read Clock Characteristics
WCLK
RCLK
WCLK
RCLK
Write clock High time
Write clock Low time
Write clock cycle time
Sustained write clock frequency
tRMWCKH
tRMWCKL
tRMWCYC
FWMAX
0.30
0.35
0.71
256
ns
ns
ns
MHz
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iCE40 HX-Series Ultra-Low Power mobileFPGA™ Family
Phase-Locked Loop (PLL) Block
Table 11 provides timing information for the Phase-Locked Loop (PLL) block shown in Figure 10.
Figure 10: Phase-Locked Loop (PLL)
PLL
LATCHINPUTVALUE
DYNAMICDELAY[3:0]
EXTFEEDBACK
BYPASS
RESET
LOCK
REFERENCECLK
PLLOUT
Table 11: Phase-Locked Loop (PLL) Block Timing
Nominal VCC 1.2 V
Min.
Typical
Max.
Symbol From
Frequency Range
FREF
To
Description
Units
Input clock frequency range
10
16
—
—
133
533
MHz
MHz
Output clock frequency range (cannot exceed
maximum frequency supported by global
buffers)
FOUT
Duty Cycle
PLLIJ
TwHI
TwLOW
PLLOJ
Input duty cycle
35
2.5
2.5
45
—
—
—
—
65
—
—
55
%
ns
ns
%
Input clock high time
Input clock low time
Output duty cycle
Fine Delay
tFDTAP
PLLTAPS
PLLFDAM
Jitter
Fine delay adjustment, per tap
Fine delay adjustment settings
Maximum delay adjustment
165
—
2.5
ps
taps
ns
0
15
Input clock period jitter
PLLOUT output period jitter
PLLIPJ
PLLOPJ
—
—
—
1% or
≤ 100
+/- 300
+/- 1.1%
output
ps
ps
period or
≥ꢐ110
Lock/Reset Time
tLOCK
PLL lock time after receive stable, monotonic
REFERENCECLK input
Minimum reset pulse width
—
—
—
50
μs
twRST
20
—
ns
Notes:
1. Output jitter performance is affected by input jitter. A clean reference clock < 100ps jitter must be used to ensure
best jitter performance.
2. The output jitter specification refers to the intrinsic jitter of the PLL.
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iCE40 HX-Series Ultra-Low Power mobileFPGA™ Family
Internal Configuration Oscillator Frequency
Table 12 shows the operating frequency for the iCE40’s internal configuration oscillator.
Table 12: Internal Oscillator Frequency at VCC = 1.2V
Frequency (MHz)
Oscillator
Mode
Symbol
fOSCD
Min.
Max.
Description
Default oscillator frequency. Slow enough to safely operate
with any SPI serial PROM.
Default
7
10
fOSCL
fOSCH
Low
Frequency
High
Frequency
Off
21
35
0
30
50
0
Supported by most SPI serial Flash PROMs
Supported by some high-speed SPI serial Flash PROMs
Oscillator turned off by default after configuration to save
power.
Configuration Timing
Table 13 shows the maximum time to configure an iCE40HX device, by oscillator mode. The calculations use the
slowest frequency for a given oscillator mode from Table 12 and the maximum configuration bitstream size from
Table 1, which includes full RAM4K block initialization. The configuration bitstream selects the desired oscillator
mode based on the performance of the configuration data source.
Table 13: Typical SPI Master or NVCM Configuration Timing by Oscillator Mode
Symbol
tCONFIGL
Description
Time from when minimum
Power-on Reset (POR)
threshold is reached until
user application starts.
Device
Default
53
Low Freq.
High Freq.
Units
ms
ms
ms
ms
iCE40HX640
iCE40HX1K
iCE40HX4K
iCE40HX8K
25
25
110
110
11
11
50
50
53
230
230
Table 14 provides timing for the CRESET_B and CDONE pins.
Table 14: General Configuration Timing
All Grades
Symbol
tCRESET_B
From
CREST_B
To
CREST_B
Description
Minimum CRESET_B Low pulse width required to restart
configuration, from falling edge to rising edge
Min.
200
Max.
—
Units
ns
CDONE
High
PIO pins Number of configuration clock cycles after CDONE goes
Clock
cycles
tDONE_IO
—
49
active
High before the PIO pins are activated.
SPI Peripheral Mode (Clock = SPI_SCK, cycles measured
rising-edge to rising-edge)
Depends on
SPI_SCK frequency
Table 15 provides various timing specifications for the SPI peripheral mode interface.
Table 15: SPI Peripheral Mode Timing
All Grades
Symbol
tCR_SCK
From
CRESET_B
To
Description
Min.
300
Max.
—
Units
µs
SPI_SCK Minimum time from a rising edge on CRESET_B until
the first SPI write operation, first SPI_SCK. During this
time, the iCE40HX FPGA is clearing its internal
configuration memory
SPI_SI
SPI_SCK Setup time on SPI_SI before the rising SPI_SCK clock
edge
tSUSPISI
12
—
ns
SPI_SCK
SPI_SI
Hold time on SPI_SI after the rising SPI_SCK clock edge
tHDSPISI
tSPISCKH
tSPISCKL
tSPISCKCYC
FSPI_SCK
12
20
20
40
1
—
—
—
1,000
25
ns
ns
ns
ns
MHz
SPI_SCK SPI_SCK SPI_SCK clock High time
SPI_SCK SPI_SCK SPI_SCK clock Low time
SPI_SCK SPI_SCK SPI_SCK clock period*
SPI_SCK SPI_SCK Sustained SPI_SCK clock frequency*
* = Applies after sending the synchronization pattern.
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10
iCE40 HX-Series Ultra-Low Power mobileFPGA™ Family
Power Consumption Characteristics
Core Power
Table 16 shows the power consumed on the internal VCC supply rail when the device is filled with 16-bit binary
counters, measured with a 32.768 kHz and at 32.0 MHz
Table 16: VCC Power Consumption for Device Filled with 16-Bit Binary Counters
iCE40HX640 iCE40HX1K iCE40HX4K iCE40HX8K
Symbol
ICC0K
ICC32K
ICC32M
Description
f =0
fꢐ≤ꢐꢆꢇ.768ꢐkHz
f = 32.0 MHz
VCC
1.2V
1.2V
1.2V
Units
µA
µA
Typical
200
222
4
Typical
267
297
4
Typical
667
741
12
Typical
1100
1222
13
mA
I/O Power
Table 17 provides the static current by I/O bank. The typical current for I/O Banks 0, 1, 2 and the SPI bank is not
measurable within the accuracy of the test environment. The PIOs in I/O Bank 3 use different circuitry and dissipate
a small amount of static current.
Table 17: I/O Bank Static Current (f = 0 MHz)
Symbol
ICCO_0
ICCO_1
ICCO_2
ICCO_3
Description
Typical
« 1
Maximum Units
I/O Bank 0
I/O Bank 1
I/O Bank 2
I/O Bank 3
SPI Bank
Static current consumption per I/O bank.
f = 0 MHz. No PIO pull-up resistors
enabled. All inputs grounded. All
outputs driving Low.
uA
uA
uA
uA
uA
« 1
« 1
« 1
« 1
ICCO_SPI
NOTE: The typical static current for I/O Banks 0, 1, 2, and the SPI bank is less than the accuracy of the device tester.
Power Estimator
To estimate the power consumption for a specific application, please download and use the iCE40HX Power Estimator
Spreadsheet our use the power estimator built into the iCEcube2 software.
Lattice Semiconductor Corporation
(1.31, 30-MAR-2012)
www.latticesemi.com/
11
iCE40 HX-Series Ultra-Low Power mobileFPGA™ Family
Revision History
Version
1.31
Date
30-MAR-2012
Description
Updated Table 1
1.3
22-MAR-2012
Production Release
Updated Notes on Table 3: Recommended Operating Conditions
Updated values in Table 4, Table 5 Table 12, Table 13 and Table 17
Updated Figure 3 and Figure 4 to specify iCE40
Updated company name
Moved package specifications to iCE40 Pinout Excel files.
Updated Table 1 maximum IOs.
1.21
1.2
1.1
5-MAR-2012
13-FEB-2012
15-DEC-2011
1.01
1.0
31-OCT-2011
11-JUL-2011
Added 640, 1K and 4K to Table 13 configuration times. Updated Table 1 maximum IOs.
Initial Release
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at
www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective
holders. The specifications and information herein are subject to change without notice.
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon 97124-6421
United States of America
Tel: +1 503 268 8000
Fax: +1 503 268 8347
cumentation services by Prevailing Technology, Inc. (www.prevailing-technology.com)
Lattice Semiconductor Corporation
(1.31, 30-MAR-2012)
www.latticesemi.com/
12
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