ICE40UP5K-UWG30ITR_技术文档

iCE40 UltraPlus™ Family

Data Sheet

FPGA-DS-02008 Version 1.4

August 2017

iCE40 UltraPlus™ Family

Data Sheet

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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

2

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

Contents

Acronyms in This Document.................................................................................................................................................6

1. General Description......................................................................................................................................................7

1.1.

2. Product Family..............................................................................................................................................................8

2.1. Overview .............................................................................................................................................................8

3. Architecture................................................................................................................................................................10

3.1. Architecture Overview ......................................................................................................................................10

Features ..............................................................................................................................................................7

3.1.1. PLB Blocks .....................................................................................................................................................11

3.1.2. Routing..........................................................................................................................................................12

3.1.3. Clock/Control Distribution Network .............................................................................................................12

3.1.4. sysCLOCK Phase Locked Loops (PLLs) ...........................................................................................................13

3.1.5. sysMEM Embedded Block RAM Memory .....................................................................................................14

3.1.6. sysMEM Single Port RAM Memory (SPRAM)................................................................................................16

3.1.7. sysDSP...........................................................................................................................................................18

3.1.8. sysIO Buffer Banks ........................................................................................................................................23

3.1.9. sysIO Buffer...................................................................................................................................................26

3.1.10.

3.1.11.

3.1.12.

3.1.13.

3.1.14.

3.1.15.

On-Chip Oscillator ....................................................................................................................................26

User I²C IP .................................................................................................................................................27

User SPI IP.................................................................................................................................................27

RGB High Current Drive I/O Pins...............................................................................................................27

RGB PWM IP .............................................................................................................................................27

Non-Volatile Configuration Memory........................................................................................................28

3.2.

iCE40 UltraPlus Programming and Configuration .............................................................................................28

3.2.1. Device Programming.....................................................................................................................................28

3.2.2. Device Configuration ....................................................................................................................................28

3.2.3. Power Saving Options...................................................................................................................................28

4. DC and Switching Characteristics ...............................................................................................................................29

4.1.

4.2.

4.3.

4.4.

4.5.

4.6.

4.7.

4.8.

4.9.

Absolute Maximum Ratings ..............................................................................................................................29

Recommended Operating Conditions...............................................................................................................29

Power Supply Ramp Rates ................................................................................................................................30

Power-On Reset ................................................................................................................................................30

Power-up Supply Sequence ..............................................................................................................................30

External Reset ...................................................................................................................................................30

Power-On-Reset Voltage Levels ........................................................................................................................31

ESD Performance ..............................................................................................................................................31

DC Electrical Characteristics..............................................................................................................................32

4.10. Supply Current ..................................................................................................................................................32

4.11. User I²C Specifications.......................................................................................................................................33

4.12. I²C 50 ns Delay...................................................................................................................................................33

4.13. I²C 50 ns Filter ...................................................................................................................................................33

4.14. User SPI Specifications ^{1, 2}.................................................................................................................................33

4.15. Internal Oscillators (HFOSC, LFOSC)..................................................................................................................34

4.16. sysI/O Recommended Operating Conditions....................................................................................................34

4.17. sysI/O Single-Ended DC Electrical Characteristics .............................................................................................34

4.18. Differential Comparator Electrical Characteristics............................................................................................35

4.19. Typical Building Block Function Performance ...................................................................................................35

4.19.1.

4.19.2.

Pin-to-Pin Performance (LVCMOS25).......................................................................................................35

Register-to-Register Performance............................................................................................................35

4.20. sysDSP Timing ...................................................................................................................................................36

4.21. SPRAM Timing...................................................................................................................................................36

4.22. Derating Logic Timing........................................................................................................................................36

4.23. Maximum sysIO Buffer Performance ................................................................................................................37

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

3

iCE40 UltraPlus™ Family

Data Sheet

4.24. iCE40 UltraPlus Family Timing Adders...............................................................................................................37

4.25. iCE40 UltraPlus External Switching Characteristics...........................................................................................38

4.26. sysCLOCK PLL Timing .........................................................................................................................................39

4.27. SPI Master or NVCM Configuration Time..........................................................................................................39

4.28. sysCONFIG Port Timing Specifications ..............................................................................................................40

4.29. RGB LED Drive ...................................................................................................................................................41

4.30. Switching Test Conditions .................................................................................................................................41

5. Pinout Information .....................................................................................................................................................42

5.1.

Signal Descriptions ............................................................................................................................................42

5.1.1. Power Supply Pins.........................................................................................................................................42

5.1.2. Configuration Pins.........................................................................................................................................42

5.1.3. Configuration SPI Pins...................................................................................................................................43

5.1.4. Global Pins ....................................................................................................................................................44

5.1.5. General I/O, LED Pins ....................................................................................................................................45

5.2.

5.3.

Pin Information Summary .................................................................................................................................46

iCE40UP Part Number Description....................................................................................................................47

5.3.1. Tape and Reel Quantity.................................................................................................................................47

5.4.

Ordering Part Numbers .....................................................................................................................................47

5.4.1. Industrial.......................................................................................................................................................47

Supplemental Information..................................................................................................................................................48

Technical Support ...............................................................................................................................................................49

Revision History ..................................................................................................................................................................50

Figures

Figure 3.1. iCE40UP5K Device, Top View ............................................................................................................................10

Figure 3.2. PLB Block Diagram ............................................................................................................................................11

Figure 3.3. PLL Diagram ......................................................................................................................................................13

Figure 3.4. sysMEM Memory Primitives .............................................................................................................................15

Figure 3.5. SPRAM Primitive ...............................................................................................................................................17

Figure 3.6. sysDSP Functional Block Diagram (16-bit x 16-bit Multiply-Accumulate).........................................................19

Figure 3.7. sysDSP 8-bit x 8-bit Multiplier...........................................................................................................................22

Figure 3.8. DSP 16-bit x 16-bit Multiplier............................................................................................................................23

Figure 3.9. I/O Bank and Programmable I/O Cell................................................................................................................24

Figure 3.10. iCE I/O Register Block Diagram .......................................................................................................................25

Figure 4.1. Power Up Sequence with SPE_VCCIO1 and VPP_2V5 Not Connected Together..............................................31

Figure 4.2. Power Up Sequence with All Supplies Connected Together to 1.8 V ...............................................................31

Figure 4.3. Output Test Load, LVCMOS Standards..............................................................................................................41

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

4

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

Tables

Table 2.1. iCE40 UltraPlus Family Selection Guide ...............................................................................................................8

Table 3.1. Logic Cell Signal Descriptions .............................................................................................................................11

Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks ...................................................................12

Table 3.3. PLL Signal Descriptions.......................................................................................................................................14

Table 3.4. sysMEM Block Configurations............................................................................................................................15

Table 3.5. EBR Signal Descriptions......................................................................................................................................16

Table 3.6. SPRAM Signal Descriptions ................................................................................................................................18

Table 3.7. Output Block Port Description ...........................................................................................................................19

Table 3.8. PIO Signal List.....................................................................................................................................................25

Table 3.9. Supported Input Standards................................................................................................................................26

Table 3.10. Supported Output Standards...........................................................................................................................26

Table 3.11. iCE40 UltraPlus Power Saving Features Description........................................................................................28

Table 4.1. Absolute Maximum Ratings ...............................................................................................................................29

Table 4.2. Recommended Operating Conditions................................................................................................................29

Table 4.3. Power Supply Ramp Rates .................................................................................................................................30

Table 4.4. Power-On-Reset Voltage Levels.........................................................................................................................31

Table 4.5. DC Electrical Characteristics...............................................................................................................................32

Table 4.6. Supply Current ^{1, 2, 3, 4, 5}.......................................................................................................................................32

Table 4.7. User I²C Specifications........................................................................................................................................33

Table 4.8. I²C 50 ns Delay....................................................................................................................................................33

Table 4.9. I²C 50 ns Filter ....................................................................................................................................................33

Table 4.10. User SPI Specifications .....................................................................................................................................33

Table 4.11. Internal Oscillators (HFOSC, LFOSC).................................................................................................................34

Table 4.12. sysI/O Recommended Operating Conditions...................................................................................................34

Table 4.13. sysI/O Single-Ended DC Electrical Characteristics............................................................................................34

Table 4.14. Differential Comparator Electrical Characteristics...........................................................................................35

Table 4.15. Pin-to-Pin Performance (LVCMOS25) ..............................................................................................................35

Table 4.16. Register-to-Register Performance ...................................................................................................................35

Table 4.17. sysDSP Timing ..................................................................................................................................................36

Table 4.18. Single Port RAM Timing ...................................................................................................................................36

Table 4.19. Maximum sysIO Buffer Performance...............................................................................................................37

Table 4.20. iCE40 UltraPlus Family Timing Adders .............................................................................................................37

Table 4.21. iCE40 UltraPlus External Switching Characteristics..........................................................................................38

Table 4.22. sysCLOCK PLL Timing........................................................................................................................................39

Table 4.23. SPI Master or NVCM Configuration Time.........................................................................................................39

Table 4.24. sysCONFIG Port Timing Specifications .............................................................................................................40

Table 4.25. RGB LED............................................................................................................................................................41

Table 4.26. Test Fixture Required Components, Non-Terminated Interfaces....................................................................41

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

5

iCE40 UltraPlus™ Family

Data Sheet

Acronyms in This Document

A list of acronyms used in this document.

Acronym

Definition

DFF

D-style Flip-Flop

DSP

EBR

HFOSC

I²C

Digital Signal Processor

Embedded Block RAM

High Frequency Oscillator

Inter-Integrated Circuit

Low Frequency Oscillator

Look Up Table

LFOSC

LUT

LVCMOS

NVCM

PCLK

PFU

Low-Voltage Complementary Metal Oxide Semiconductor

Non Volatile Configuration Memory

Primary Clock

Programmable Functional Unit

Programmable I/O Cells

Programmable Logic Blocks

Phase Locked Loops

PIC

PLB

PLL

SoC

System on a Chip

SPI

SPR

Serial Peripheral Interface

Single Port RAM

WLCSP

Wafer Level Chip Scale Packaging

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

6

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

1.1. Features

1. General Description



Flexible Logic Architecture

iCE40 UltraPlus™ family from Lattice Semiconductor is

an ultra-low power FPGA and sensor manager

designed for ultra-low power mobile applications, such

as smartphones, tablets and hand-held devices. iCE40

UltraPlus is compatible with Lattice's iCE40 Ultra family

devices, containing all the functions iCE40 Ultra family

has except the high current IR LED driver. In addition,

the iCE40 UltraPlus features an additional 1 Mb SRAM,

additional DSP blocks, with additional LUTs, all which

can be used to support an always-on Voice Recognition

function in the mobile devices, without the need to

keep the higher power consuming voice codec on all

the time.



Two devices with 2800 to 5280 LUTs

Offered in WLCS and QFN packages

Ultra-low Power Devices



Advanced 40 nm low power process

As low as 100 µA standby current typical

Embedded Memory



Up to 1024 kb Single Port SRAM

Up to 120 kb sysMEM™ Embedded Block RAM

Two Hardened I²C Interfaces



Two I/O pins to support I3C interface



Two Hardened SPI Interfaces

Two On-Chip Oscillators



Low Frequency Oscillator – 10 kHz

High Frequency Oscillator – 48 MHz

The iCE40 UltraPlus family includes integrated SPI and

I²C blocks to interface with virtually all mobile sensors

and application processors. In addition, the iCE40

UltraPlus family also features two I/O pins that can

support the interface to I3C devices. There are two

on-chip oscillators, 10 kHz and 48 MHz, the LFOSC

(10 kHz) is ideal for low power function in always-on

applications, while HFOSC (48 MHz) can be used for

awaken activities.



24 mA Current Drive RGB LED Outputs



On-chip DSP



Three drive outputs in each device

User selectable sink current up to 24 mA

Signed and unsigned 8-bit or 16-bit functions

Functions include Multiplier, Accumulator, and

Multiply-Accumulate (MAC)



Flexible On-Chip Clocking

The iCE40 UltraPlus family also features DSP functional

block to off-load Application Processor to pre-process

information sent from the mobile device, such as voice

data. The RGB PWM IP, with the three 24 mA constant

current RGB outputs on the iCE40 UltraPlus provides

all the necessary logic to directly drive the service LED,

without the need of external MOSFET or buffer.



Eight low skew global signal resource, six can

be directly driven from external pins



One PLL with dynamic interface per device

Flexible Device Configuration

SRAM is configured through:



Standard SPI Interface

Internal Nonvolatile Configuration

Memory (NVCM)

The iCE40 UltraPlus family of devices are targeting for

mobile applications to perform all the functions in

iCE40 Ultra devices, such as Service LED, GPIO

Expander, SDIO Level Shift, and other custom

functions. In addition, the iCE40 UltraPlus family

devices are also targeting for Voice Recognition

application.



Ultra-Small Form Factor

As small as 2.15 mm × 2.55 mm

Applications



Always-On Voice Recognition Application

Smartphones

Tablets and Consumer Handheld Devices

Handheld Commercial and Industrial Devices

Multi Sensor Management Applications

Sensor Pre-processing and Sensor Fusion

Always-On Sensor Applications

USB 3.1 Type C Cable Detect / Power Delivery

Applications

The iCE40 UltraPlus family features two device

densities, 2800 to 5280 Look Up Tables (LUTs) of logic

with programmable I/Os that can be used as either

SPI/I²C interface ports or general purpose I/O’s. Two of

the iCE40 UltraPlus I/Os can be used to interface to

higher performance I3C. It also has up to 120 kb of

Block RAMs, plus 1024 kb of Single Port SRAMs to work

with user logic.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

7

iCE40 UltraPlus™ Family

Data Sheet

2. Product Family

Table 2.1 lists device information and packages of the iCE40 UltraPlus family.

Table 2.1. iCE40 UltraPlus Family Selection Guide

Part Number

iCE40UP3K

iCE40UP5K

Logic Cells (LUT + Flip-Flop)

EBR Memory Blocks

2800

20

80

4

5280

30

120

4

EBR Memory Bits (Kbits)

SPRAM Memory Blocks

SPRAM Memory Bits (Kbits)

NVCM

1024

Yes

1

1024

Yes

1

PLL

DSP Blocks (MULT16 with 32-bit Accumulator

Hardened I²C, SPI

4

8

2, 2

1

2, 2

1

HF Oscillator (48 MHz)

LF Oscillator (10 KHz)

1

24 mA LED Sink

3

PWM IP Block

Yes

Packages, ball pitch, dimension

30-ball WLCSP, 0.4 mm, 2.15 mm x 2.55 mm

48-ball QFN, 0.5 mm, 7.0 mm x 7.0 mm

Total User I/O Count

21

-

21

39

2.1. Overview

The iCE40 UltraPlus family of ultra-low power FPGAs has three devices with densities ranging from 2800 to 5280 Look-

Up Tables (LUTs) fabricated in a 40 nm Low Power CMOS process. In addition to LUT-based, low-cost programmable

logic, these devices also feature Embedded Block RAM (EBR), Single Port RAM (SPRAM), on-chip Oscillators (LFOSC,

HFOSC), two hardened I²C Controllers, two hardened SPI Controllers, PWM IP, three 24 mA RGB LED open-drain

drivers, I3C interface pins, and DSP blocks. These features allow the devices to be used in low-cost, high-volume

consumer and mobile applications.

The iCE40 UltraPlus FPGAs are available in very small form factor packages, as small as 2.15 mm x 2.55 mm. The small

form factor allows the device to easily fit into a lot of mobile applications, where space can be limited. Table 2.1 lists

the LUT densities, package and I/O pin count.

The iCE40 UltraPlus devices offer I/O features such as pull-up resistors. Pull-up features are controllable on a “per pin”

basis. In addition, the iCE40 UltraPlus devices offer two I/Os with dynamic control on the pull-up resistors to support

I3C interface.

The RGB PWM IP in the iCE40 UltraPlus devices provides controls for driving the 24 mA LED Sink driver, including color

controls, LED ON/OFF time, and breathe rate.

The iCE40 UltraPlus devices also provide flexible, reliable and secure configuration from on-chip NVCM. These devices

can also configure themselves from external SPI Flash, or be configured by an external master such as a CPU.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

8

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the iCE40

UltraPlus family of devices. Popular logic synthesis tools provide synthesis library support for iCE40 UltraPlus. Lattice

design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route

the design in the iCE40 UltraPlus device. These tools extract the timing from the routing and back-annotate it into the

design for timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) modules, including a number of reference designs,

licensed free of charge, optimized for the iCE40 UltraPlus FPGA family. Lattice also can provide fully verified bitstream

for some of the widely used target functions in mobile device applications, such as ultra-low power sensor

management, gesture recognition, IR remote, barcode emulator functions. Users can use these functions as offered by

Lattice, or they can use the design to create their own unique required functions. For more information regarding

Lattice's reference designs or fully-verified bitstreams, contact your local Lattice representative.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

9

iCE40 UltraPlus™ Family

Data Sheet

3. Architecture

3.1. Architecture Overview

The iCE40 UltraPlus family architecture contains an array of Programmable Logic Blocks (PLB), two Oscillator

Generators, two user configurable I²C controllers, two user configurable SPI controllers, blocks of sysMEM™ Embedded

Block RAM (EBR) and Single Port RAM (SPRAM) surrounded by Programmable I/O (PIO). Figure 3.1 shows the block

diagram of the iCE40UP5K device.

PLB

I²C

I/O Bank 0

PLL

HFOSC

LFOSC

50 ns Delay

50 ns Filter

5 PLB Rows

config

256 Kb

SPRAM

256 Kb

SPRAM

256 Kb

SPRAM

256 Kb

SPRAM

config

Carry Logic

4-Input Look-up

Table (LUT)

I/O Bank 2

SPI

I/O Bank 1_SPI

Flip-flop with Enableand Reset Controls

Figure 3.1. iCE40UP5K Device, Top View

The Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional grid with rows and

columns. Each column has either PLB or EBR blocks. The PIO cells are located at the top and bottom of the device,

arranged in banks. The PLB contains the building blocks for logic, arithmetic, and register functions. The PIOs utilize a

flexible I/O buffer referred to as a sysIO buffer that supports operation with a variety of interface standards. The blocks

are connected with many vertical and horizontal routing channel resources. The place and route software tool

automatically allocates these routing resources.

In the iCE40 UltraPlus family, there are three sysIO banks, one on top and two at the bottom. User can connect some

V_CCIOs together, if all the I/Os are using the same voltage standard. See the Power-up Supply Sequence section. The

sysMEM EBRs are large 4 kb, dedicated fast memory blocks. These blocks can be configured as RAM, ROM or FIFO with

user logic using PLBs.

In addition to the EBR, the iCE40 UltraPlus devices also feature four 256 kb SPRAM blocks that can be cascaded to

create up to 1 Mb block. It is useful for temporary storage of large quantities of information.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

10

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

Every device in the family has two user SPI ports, one of these (right side) SPI ports also supports programming and

configuration of the device. The iCE40 UltraPlus also includes two user I²C ports, two oscillators, and high current RGB

LED sink.

3.1.1. PLB Blocks

The core of the iCE40 UltraPlus device consists of Programmable Logic Blocks (PLB) which can be programmed to

perform logic and arithmetic functions. Each PLB consists of eight interconnected Logic Cells (LC) as shown in

Figure 3.2. Each LC contains one LUT and one register.

Shared Block-Level Controls

Clock

Programmable

Logic Block (PLB)

Enable

FCOUT

1

Set/Reset

0

Logic Cell

Carry Logic

DFF

O

I0

D

Q

EN

I1

I2

I3

SR

LUT

FCIN

Four-input

Look-Up Table

(LUT)

Flip-flop with

optional enable and

set or reset controls

= Statically defined by configuration program

Figure 3.2. PLB Block Diagram

Logic Cells

Each Logic Cell includes three primary logic elements shown in Figure 3.2.



A four-input Look-Up Table (LUT) builds any combinational logic function, of any complexity, requiring up to four

inputs. Similarly, the LUT element behaves as a 16x1 Read-Only Memory (ROM). Combine and cascade multiple

LUTs to create wider logic functions.

A ‘D’-style Flip-Flop (DFF), with an optional clock-enable and reset control input, builds sequential logic functions.

Each DFF also connects to a global reset signal that is automatically asserted immediately following device

configuration.

Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders, subtracters,

comparators, binary counters and some wide, cascaded logic functions.

Table 3.1 lists the logic cell signals.

Table 3.1. Logic Cell Signal Descriptions

Function

Input

Type

Signal Name

I0, I1, I2, I3

Enable

Description

Data signal

Inputs to LUT

Input

Control signal

Clock enable shared by all LCs in the PLB

Asynchronous or synchronous local set/reset shared by

Clock one of the eight Global Buffers, or from the

Input

Set/Reset*

Clock

Input

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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iCE40 UltraPlus™ Family

Data Sheet

Function

Type

Signal Name

FCIN

Description

Input

Output

Inter-PLB signal

Data signals

Fast carry in

O

LUT or registered output

Fast carry out

Inter-PFU signal

FCOUT

*Note: If Set/Reset is not used, then the flip-flop is never set/reset, except when cleared immediately after configuration.

3.1.2. Routing

There are many resources provided in the iCE40 UltraPlus devices to route signals individually with related control

signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments.

The inter-PLB connections are made with three different types of routing resources: Adjacent (spans two PLBs), x4

(spans five PLBs) and x12 (spans thirteen PLBs). The Adjacent, x4 and x12 connections provide fast and efficient

connections in the diagonal, horizontal and vertical directions.

The design tool takes the output of the synthesis tool and places and routes the design.

3.1.3. Clock/Control Distribution Network

Each iCE40 UltraPlus device has six global inputs, two pins on the top bank and four pins on the bottom bank.

These global inputs can be used as high fanout nets, clock, reset or enable signals. The dedicated global pins are

identified as Gxx and each drives one of the eight global buffers. The global buffers are identified as GBUF[7:0]. These

six inputs may be used as general purpose I/O if they are not used to drive the clock nets.

Table 3.2 lists the connections between a specific global buffer and the inputs on a PLB. All global buffers optionally

connect to the PLB CLK input. Any four of the eight global buffers can drive logic inputs to a PLB. Even-numbered global

buffers optionally drive the Set/Reset input to a PLB. Similarly, odd-numbered buffers optionally drive the PLB clock-

enable input. GBUF[7:6, 3:0] can connect directly to G[7:6, 3:0] pins respectively. GBUF4 and GBUF5 can connect to the

two on-chip Oscillator Generators (GBUF4 connects to LFOSC, GBUF5 connects to HFOSC).

Table 3.2. Global Buffer (GBUF) Connections to Programmable Logic Blocks

Global Buffer

GBUF0

LUT Inputs

Clock



Reset



Clock Enable

—



—



—



—



GBUF1

—



GBUF2



GBUF3

—

Yes, any 4 of 8 GBUF

Inputs



GBUF4



GBUF5

—



GBUF6



GBUF7

—

The maximum frequency for the global buffers are listed in Table 4.21.

Global Hi-Z Control

The global high-impedance control signal, GHIZ, connects to all I/O pins on the iCE40 UltraPlus device. This GHIZ signal

is automatically asserted throughout the configuration process, forcing all user I/O pins into their high-impedance

state.

Global Reset Control

The global reset control signal connects to all PLB and PIO flip-flops on the iCE40 UltraPlus device. The global reset

signal is automatically asserted throughout the configuration process, forcing all flip-flops to their defined wake-up

state. For PLB flip-flops, the wake-up state is always reset, regardless of the PLB flip-flop primitive used in the

application.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

12

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iCE40 UltraPlus™ Family

Data Sheet

3.1.4. sysCLOCK Phase Locked Loops (PLLs)

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The iCE40 UltraPlus devices have one sysCLOCK

PLL. REFERENCECLK is the reference frequency input to the PLL and its source can come from an external I/O pin, the

internal Oscillator Generators from internal routing. EXTFEEDBACK is the feedback signal to the PLL which can come

from internal routing or an external I/O pin. The feedback divider is used to multiply the reference frequency and thus

synthesize a higher frequency clock output.

The PLLOUT output has an output divider, thus allowing the PLL to generate different frequencies for each output. The

output divider can have a value from 1 to 64 (in increments of 2X). The PLLOUT outputs can all be used to drive the

iCE40 UltraPlus global clock network directly or general purpose routing resources can be used.

The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected. A

block diagram of the PLL is shown in Figure 3.3.

The timing of the device registers can be optimized by programming a phase shift into the PLLOUT output clock which

will advance or delay the output clock with reference to the REFERENCECLK clock. This phase shift can be either

programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after a phase

adjustment on the output used as the feedback source and not relock until the tLOCK parameter has been satisfied.

There is an additional feature in the iCE40 UltraPlus PLL. There are two FPGA controlled inputs, SCLK and SDI, that

allows the user logic to serially shift in data thru SDI, clocked by SCLK clock. The data shifted in would change the

configuration settings of the PLL. This feature allows the PLL to be time multiplexed for different functions, with

different clock rates. After the data is shifted in, user would simply pulse the RESET input of the PLL block, and the PLL

will re-lock with the new settings. For more details, refer to TN1251, iCE40 sysCLOCK PLL Design and Usage Guide.

RESET

BYPASS

GNDPLL V_{CC PLL}

Phase

Detector

DIVQ

DIVR

RANGE

Low-Pass

Filter

Voltage

Controlled

Oscillator

(VCO)

REFERENCECLK

VCO

Input

Divider

SIMPLE

SCLK

SDI

DIVF

PLLOUTCORE

Feedback

Fine Delay

Adjustment

Output Port

Divider

Fine Delay

Adjustment

Feedback

Phase

Shifter

PLLOUTGLOBAL

Feedback_Path

LOCK

DYNAMICDELAY[7:0]

EXTFEEDBACK

EXTERNAL

LATCHINPUTVALUE

Low Powermode

Figure 3.3. PLL Diagram

Table 3.3 provides signal descriptions of the PLL block.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

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iCE40 UltraPlus™ Family

Data Sheet

Table 3.3. PLL Signal Descriptions

Signal Name

REFERENCECLK

BYPASS

Direction

Description

Input

Input reference clock

The BYPASS control selects which clock signal connects to the PLLOUT output.

0 – PLL generated signal

1 – REFERENCECLK

EXTFEEDBACK

Input

External feedback input to PLL. Enabled when the FEEDBACK_PATH attribute is set

to EXTERNAL.

DYNAMICDELAY[7:0]

LATCHINPUTVALUE

PLLOUTGLOBAL

PLLOUTCORE

Fine delay adjustment control inputs. Enabled when DELAY_ADJUSTMENT_MODE

is set to DYNAMIC.

Input

When enabled, puts the PLL into low-power mode; PLL output is held static at the

last input clock value. Set ENABLE ICEGATE_PORTA and PORTB to ‘1’ to enable.

Output

Output from the Phase-Locked Loop (PLL). Drives a global clock network on the

FPGA. The port has optimal connections to global clock buffers GBUF4 and GBUF5.

Output clock generated by the PLL, drives regular FPGA routing. The frequency

generated on this output is the same as the frequency of the clock signal generated

on the PLLOUTLGOBAL port.

LOCK

Output

When High, indicates that the PLL output is phase aligned or locked to the input

reference clock.

RESET

SCLK

SDI

Input

Active low reset.

Input, Serial Clock used for re-programming PLL settings.

Input, Serial Data used for re-programming PLL settings.

3.1.5. sysMEM Embedded Block RAM Memory

Larger iCE40 UltraPlus device includes multiple high-speed synchronous sysMEM Embedded Block RAMs (EBRs), each

4 kbit in size. This memory can be used for a wide variety of purposes including data buffering and FIFO.

sysMEM Memory Block

The sysMEM block can implement single port, pseudo dual port, or FIFO memories with programmable logic resources.

Each block can be used in a variety of depths and widths as listed in Table 3.4.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

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FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

Table 3.4. sysMEM Block Configurations

Block RAM

WADDR Port

Size (Bits)

WDATA Port

Size (Bits)

RADDR Port

Size (Bits)

RDATA Port

Size (Bits)

MASK Port

Size (Bits)

Configuration

and Size

SB_RAM256x16

SB_RAM256x16NR

SB_RAM256x16NW

SB_RAM256x16NRNW

256x16 (4 k)

8 [7:0]

9 [8:0]

16 [15:0]

8 [7:0]

4 [3:0]

2 [1:0]

8 [7:0]

9 [8:0]

16 [15:0]

SB_RAM512x8

SB_RAM512x8NR

512x8 (4 k)

8 [7:0]

4 [3:0]

2 [1:0]

No Mask Port

SB_RAM512x8NW

SB_RAM512x8NRNW

SB_RAM1024x4

SB_RAM1024x4NR

1024x4 (4 k)

10 [9:0]

11 [10:0]

10 [9:0]

11 [10:0]

SB_RAM1024x4NW

SB_RAM1024x4NRNW

SB_RAM2048x2

SB_RAM2048x2NR

SB_RAM2048x2NW

2048x2 (4 k)

SB_RAM2048x2NRNW

Note: For iCE40 UltraPlus, the primitive name without “Nxx” uses rising-edge Read and Write clocks. “NR” uses rising-edge Write

clock and falling-edge Read clock. “NW” uses falling-edge Write clock and rising-edge Read clock. “NRNW” uses failing-edge clocks

on both Read and Write.

RAM Initialization and ROM Operation

If desired, the contents of the RAM can be pre-loaded during device configuration.

By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block

can also be utilized as a ROM.

Memory Cascading

Larger and deeper blocks of RAM can be created using multiple EBR sysMEM Blocks.

RAM4k Block

Figure 3.4 shows the 256x16 memory configurations and their input/output names. In all the sysMEM RAM modes, the

input data and addresses for the ports are registered at the input of the memory array.

Write Port

Read Port

WDATA[15:0]

MASK[15:0]

RDATA[15:0]

RADDR[7:0]

WADDR[7:0]

RAM4K

RAM Block

(256x16)

WE

WCLKE

WCLK

RE

RCLKE

RCLK

Figure 3.4. sysMEM Memory Primitives

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

15

iCE40 UltraPlus™ Family

Data Sheet

Table 3.5 lists the EBR signals.

Table 3.5. EBR Signal Descriptions

Signal Name

WDATA[15:0]

MASK[15:0]

Direction

Description

Input

Write Data input.

Input

Masks write operations for individual data bit-lines.

0 – Write bit

1 – Do not write bit

WADDR[7:0]

WE

Input

Output

Input

Write Address input. Selects one of 256 possible RAM locations.

Write Enable input.

WCLKE

WCLK

Write Clock Enable input.

Write Clock input. Default rising-edge, but with falling-edge option.

Read Data output.

RDATA[15:0]

RADDR[7:0]

RE

Read Address input. Selects one of 256 possible RAM locations.

Read Enable input.

RCLKE

Read Clock Enable input.

RCLK

Read Clock input. Default rising-edge, but with falling-edge option.

For further information on the sysMEM EBR block, refer to TN1250, Memory Usage Guide for iCE40 Devices.

3.1.6. sysMEM Single Port RAM Memory (SPRAM)

The SPRAM block is implemented to be accessed only as single port. Each block of SPRAM is designed to be 16K x 16

(256 kbits) in size. See Figure 3.5.

SPRAM Data Width

The SPRAM is designed with fixed 16-bit data width. However, the block contains nibble mask control on the write

input that allows the user logic to operate the SPRAM as x4 or x8 with this control on the write side, and user logic to

select which nibble/byte in the read side.

SPRAM Initialization and ROM Operation

There is no pre-load into the SPRAM during device configuration, therefore, the SPRAM is not initialized after

configuration.

SPRAM Cascading

Deeper SPRAM can be created using multiple SPRAM blocks, up to four blocks (64K x 16)

SPRAM Power Modes

There are three power modes in the SPRAM that the users can select during normal operation. This reduces the SPRAM

block power when it Is not needed, allow lower power consumption in an always-on application. These modes are:



Standby Mode: SPRAM stops all activity, and SPRAM freezes in its current state. Memory contents are retained,

memory outputs are retained, and all register contents are retained.

Sleep Mode: SPRAM block is shut down on all peripheral circuit, except the memory core. Memory contents are

retained, memory outputs and register contents are clear and become unknown.

Power Off Mode: Power source to the SPRAM is disconnected. This is the lowest power state. Memory contents

are lost. Memory outputs are unknown.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

16

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

DATAOUT [15:0]

MASKWREN [3:0]

WREN

MASKWREN [3:0]

WREN

Single Port RAM Primitive

SB_SPRAM256KA

CHIPSELECT

CLOCK

STANDBY

SLEEP

POWEROFFN

Figure 3.5. SPRAM Primitive

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

17

iCE40 UltraPlus™ Family

Data Sheet

Table 3.6. SPRAM Signal Descriptions

Signal Name

ADDRESS[13:0]

DATAIN[15:0]

MASKWREN[3:0]

WREN

Direction

Input

Description

Address input

Input

Write Data input

Nibble WE control

Write Enable

CHIPSELECT

CLOCK

Input

Enable SPRAM

Clock input

STANDY

Input

Standby Mode

Sleep Mode

SLEEP

Input

POWEROFF

DATAOUT[15:0]

Input

Switch off power source to SPRAM

Output Data

Output

For further information on sysMEM SPRAM block, refer to TN1314, iCE40 SPRAM Usage Guide.

3.1.7. sysDSP

The iCE40 UltraPlus family provides an efficient sysDSP architecture that is very suitable for low-cost Digital Signal

Processing (DSP) functions for mobile applications. Typical functions used in these applications are Multiply,

Accumulate, and Multiply-Accumulate. The block can also be used for simple Add and Subtract functions.

iCE40 UltraPlus sysDSP Architecture Features

The iCE40 UltraPlus sysDSP supports many functions that include the following:



Single 16-bit x 16-bit Multiplier, or two independent 8-bit x 8-bit Multipliers

Optional independent pipeline control on Input Register, Output Register, and Intermediate Reg faster clock

performance



Single 32-bit Accumulator, or two independent 16-bit Accumulators

Single 32-bit, or two independent 16-bit Adder/Subtracter functions, registered or asynchronous

Cascadable to create wider Accumulator blocks

Figure 3.6 shows the block diagram of the sysDSP block. The block consists of the Multiplier section with a bypassable

Output register, Input Register, and Intermediate register between Multiplier and AC timing to achieve the highest

performance.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

18

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

CO

SIGNEXTOUT

COCAS

Input Registers

Multiplier

Accumulator

Q[31:16]

0

OHADS

W

0

1

C

Q

1

P

0

1

C [15:0]

CHLD

D

HLD

Q

±

1

D

Q

C 12

X

O[31:16]

C 0

HLD

2

3

R

16x16 Pipeline

Registers

R

X [15]

[15:0]

Hi

0

1

C 9

8x8=16

C 8

F

A

0

1

A [15:8]

B [15:8]

0

1

[15:0]

OHRST

OHHLD

OHLDA

2

3

[15:8]

D

HLD

Q

A [15:0]

AHLD

D

Q

HCI

P [31:24]

C 1

C 11

C 4

R

+

8x8

R

[7:0]

C 10

J

16x16

Pipeline

Register

A [7:0]

0

1

[15:0]

D

Q

B [15:8]

[15:8]

HLD

P [23:16]

C 6

R

^16xH¹⁶⁼³²

[15:8]

[31:16]

[15:0]

0

1

L

C 22

IHRST

8x8 PowerSave

LCO

D

Q

0

1

HLD

K

C 7

A [15:8]

B [7:0]

0

1

LCOCA

S

[15:0]

R

[7:0]

Q[15:0

D

HLD

Q

[7:0]

OLADS

P [15:8]

P [7:0]

C 6

0

1

+

8x8

Y

R

[15:8]

[7:0]

G

S

R

A [7:0]

B [7:0]

0

1

[15:0]

0

1

2

3

0

1

±

D

HLD

Q

C 19

D

R

Z

0

1

O[15:0]

8x8=16

C 5

D

HLD

Q

B [15:0]

BHLD

R

Z [15]

B

Lo

C 2

0

1

C 16

R

C 15

OLRST

OLHLD

OLLDA

2

3

LCI

C 18

0

1

D

C 17

D

HLD

Q

D[15:0]

DHLD

C 3

R

ASGND=C23

BSGND=C24

ILRST

CLK

0

1

ENA

SIGNEXTIN

CICAS CI

Figure 3.6. sysDSP Functional Block Diagram (16-bit x 16-bit Multiply-Accumulate)

Table 3.7. Output Block Port Description

Primitive

Input/

Output

Input

Signal

Width

Function

Default

Port Name

CLK

1

Clock Input. Applies to all clocked elements in the

sysDSP block

—

ENA

CE

1

Input

Clock Enable Input. Applies to all clocked elements

in the sysDSP block.

0 – Enabled

0 – Not enabled

1 – Enabled

A[15:0]

B[15:0]

C[15:0]

D[15:0]

AHLD

A[15:0]

B[15:0]

C[15:0]

D[15:0]

AHOLD

16

1

Input

Input to the A Register. Feeds the Multiplier or is a

direct input to the Adder Accumulator

Input to the B Register. Feeds the Multiplier or is a

direct input to the Adder Accumulator

Input to the C Register. It is a direct input to the

Adder Accumulator

Input to the D Register. It is a direct input to the

Adder Accumulator

16'b0

A Register Hold.

0 – Update

1 – Hold

0 – Update

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

19

iCE40 UltraPlus™ Family

Data Sheet

Table 3.7. Output Block Port Description (Continued)

Primitive

Port Name

Input/

Output

Input

Signal

Width

Function

Default

BHLD

BHOLD

CHOLD

DHOLD

IRSTTOP

1

B Register Hold.

0 – Update

1 – Hold

0 – Update

CHLD

DHLD

IHRST

1

Input

C Register Hold.

0 – Update

1 – Hold

0 – Update

0 – No reset

D Register Hold.

0 – Update

1 – Hold

Reset input to A and C input registers, and the

pipeline registers in the upper half of the Multiplier

Section.

0 – No reset

1 – Reset

ILRST

IRSTBOT

O[31:0]

1

Input

Reset input to B and D input registers, and the

pipeline registers in the lower half of the Multiplier

Section. It also resets the Multiplier result pipeline

register.

0 – No reset

1 – Reset

0 – No reset

O[31:0]

32

Output

Output of the sysDSP block. This output can be:

—



O[31:0] – 32-bit result of 16x16 Multiplier or

MAC

O[31:16] – 16-bit result of 8x8 upper half

Multiplier or MAC

O[15:0] – 16-bit result of 8x8 lower half

Multiplier or MAC

OHHLD

OHRST

OHOLDTOP

ORSTTOP

1

Input

High-order (upper half) Accumulator Register Hold.

0 – Update

1 – Hold

0 – Update

Reset input to high-order (upper half) bits of the

Accumulator Register.

0 – No reset

1 – Reset

OHLDA

OHADS

OLOADTOP

1

Input

High-order (upper half) Accumulator Register

Accumulate/Load control.

0 – Accumulate, register is loaded with

Adder/Subtracter results

0 –

Accumulate

1 – Load, register is loaded with Input C or C Register

ADDSUBTOP

High-order (upper half) Accumulator Add or Subtract

0 – Add

select.

0 – Add

1 – Subtract

OLHLD

OLRST

OHOLDBOT

ORSTBOT

1

Input

Low-order (lower half) Accumulator Register Hold.

0 – Update

1 – Hold

0 – Update

Reset input to Low-order (lower half) bits of the

Accumulator Register.

0 – No reset

0 –No reset

1 – Reset

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

20

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

Table 3.7. Output Block Port Description (Continued)

Primitive

Port Name

OLOADBOT

Input/

Output

Input

Signal

Width

Function

Default

OLLDA

1

Low-order (lower half) Accumulator Register

Accumulate/Load control.

0 –

Accumulate

0 – Accumulate, register is loaded with

Adder/Subtracter results

1 – Load, register is loaded with Input C or C Register

OLADS

CICAS

ADDSUBBOT

ACCUMCI

1

Input

Low-order (lower half) Accumulator Add or Subtract

select.

0 – Add

1 – Subtract

0 – Add

Cascade Carry/Borrow input from previous sysDSP

block

—

CI

1

Input

Output

Input

Carry/Borrow input from lower logic tile

—

COCAS

CO

ACCUMCO

CO

Cascade Carry/Borrow output to next sysDSP block

Carry/Borrow output to higher logic tile

SIGNEXTIN

SIGNEXTOUT

SIGNEXTIN

SIGNEXTOUT

Sign extension input from previous sysDSP block

Sing extension output to next sysDSP block

Output

The iCE40 UltraPlus sysDSP can support the following functions:



8-bit x 8-bit Multiplier

16-bit x 16-bit Multiplier

16-bit Adder/Subtracter

32-bit Adder/Subtracter

16-bit Accumulator

32-bit Accumulator

8-bit x 8-bit Multiply-Accumulate

16-bit x 16-bit Multiply-Accumulate

Figure 3.7 on the next page shows the path for an 8-bit x 8-bit Multiplier using the upper half of sysDSP block.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

21

iCE40 UltraPlus™ Family

Data Sheet

CO

SIGNEXTOUT

COCAS

Input Registers

Multiplier

Accumulator

Q

Q [31 :16 ]

OHADS

0

1

W

C

0

1

P

0

1

2

3

0

1

C[15 :0 ]

CHLD

D

Q

±

D

Q

C12

X

HLD

O [ 31 :16

]

C 0

HLD

R

16 x16 Pipeline

Registers

R

X [ 15 ]

High

[ 15 :0 ]

0

1

C 9

8 x8 =16

[15:8]

C 8

F

A

0

1

A[ 15 :8

B [ 15 :8

]

0

1

[

15 :0 ]

OHRST

2

3

OHHLD

OHLDA

D

Q

A[15 :0 ]

AHLD

D

Q

HCI

HLD

P [ 31 : 24 ]

C 1

C 11

C 4

+

R

8 x8

R

C 10

J

[7:0]

16 x 16

Pipeline

Register

0

1

A[ 7 :0

]

[15 :0

]

D

Q

[15:8]

B [ 15 :8

HLD

P [ 23 : 16 ]

C 6

16 x16 =32

[15:8]

[ 31 : 16

]

H

0

1

L

C 22

8 x8 PowerSave

0

LCO

IHRST

D

Q

[ 15 : 0 ]

0

1

HLD

K

C 7

A[ 15 :8

B [ 7 :0

]

[ 15 :

0

]

R

LCOCAS

Q [15:0]

[7:0]

1

D

Q

[7:0]

HLD

OLADS

P [ 15 : 8 ]

C 6

0

1

+

Y

8 x8

R

[ 15 :8

[7:0]

]

G

[ 15 : 0 ]

S

R

A[ 7 :0

B [ 7 :0

]

0

1

2

3

0

1

±

P [ 7: 0 ]

D

Q

1

C19

Z

D

Q

0

1

O [ 15 :0 ]

HLD

8 x8 = 16

C 5

B [15 :0 ]

BHLD

D

Q

R

HLD

Z [15 ]

B

Low

C 2

0

1

C 16

R

C 15

OLRST

OLHLD

OLLDA

2

3

LCI

C 18

D

0

1

C 17

D

Q

D[15 :0 ]

DHLD

HLD

C 3

R

ASGND=C23

BSGND=C24

ILRST

1

0

CLK

ENA

( 25 - FEB - 2012

)

SIGNEXTIN

CICAS CI

Figure 3.7. sysDSP 8-bit x 8-bit Multiplier

Figure 3.8 shows the path for an 16-bit x 16-bit Multiplier using the upper half of sysDSP block.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

22

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

CO

SIGNEXTOUT

COCAS

Input Registers

Multiplier

Accumulator

Q[31:16]

OHADS

0

1

W

0

1

C

Q

P

0

1

2

3

0

1

C[15:0]

CHLD

D

HLD

Q

±

C12

D

HLD

Q

X

O[31:16]

C0

R

16x16 Pipeline

Registers

R

X[15]

[15:0]

High

0

1

2

3

C9

8x8=16

[15:8]

C8

F

A

0

1

A[15:8]

B[15:8]

0

[ 15:0]

OHRST

OHHLD

OHLDA

D

HLD

Q

A[15:0]

AHLD

1

D

Q

HCI

:24

P[31

]

C1

[7:0]

C11

C4

R

+

8x8

R

C10

J

16x16

A[

7:0]

0

1

[ 15:0]

Pipeline

Register

D

Q

B[15:8]

[15:8]

:

]

HLD

P[23 16

C6

R

16x16=32

[15:8]

[31:16]

0

H

L

C22

IHRST

8x8 PowerSave

1

LCO

D

Q

[15:0]

HLD

0

1

K

C7

A[15:8]

B[7:0]

0

1

[15:0]

R

LCOCAS

[7:0]

Q[15:0

D

HLD

Q

[7:0]

OLADS

P[15:8]

P[7:0]

C6

0

1

8x8

+

Y

R

[15:8]

[7:0]

G

S

A[7:0]

R

0

1

0

1

2

3

[15:0]

0

1

±

C19

D

HLD

Q

D

R

Z

0

1

7:0]

B[

O[15:0]

8x8=16

C5

B[15:0]

BHLD

D

HLD

Q

R

Z[15]

B

Low

C2

0

1

C16

R

C15

OLRST

OLHLD

OLLDA

2

3

LCI

C18

0

1

D

C17

D

HLD

Q

D[15:0]

DHLD

ASGND=23

BSGND=24

C3

R

ILRST

CLK

0

1

ENA

(25-FEB-2012)

SIGNEXTIN

CICAS CI

Figure 3.8. DSP 16-bit x 16-bit Multiplier

3.1.8. sysIO Buffer Banks

iCE40 UltraPlus devices have up to three I/O banks with independent V_CCIOrails. The configuration SPI interface signals

are powered by SPI_V_CCIO1. Refer to the Pin Information Summary table.

Programmable I/O (PIO)

The programmable logic associated with an I/O is called a PIO. The individual PIOs are connected to their respective

sysIO buffers and pads. The PIOs are placed on the top and bottom of the devices.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

23

iCE40 UltraPlus™ Family

Data Sheet

V_CCIO

I/O Bank 0 or 2

Voltage Supply

0 = Hi-Z

1 = Output

Enabled

Enabled ‘1’

Disabled ‘0’

Pull-up

OE

50 ns Delay

50ns Delay

50ns Filter

Pull-up

Enable

OUTCLK

OUT

5 PLBRows

PAD

Latch inhibits

switchingfor

power saving

OUTCLK

iCEGATE

HOLD

HD

IN

Gxx pins optionally

connect directly to

an associated

GBUF global

buffer

INCLK

Figure 3.9. I/O Bank and Programmable I/O Cell

The PIO contains three blocks: an input register block, output register block iCEGate™ and tri-state register block. To

save power, the optional iCEGate^TMlatch can selectively freeze the state of individual, non-registered inputs within an

I/O bank. Note that the freeze signal is common to the bank. These blocks can operate in a variety of modes along with

the necessary clock and selection logic.

Input Register Block

The input register blocks for the PIOs on all edges contain registers that can be used to condition high-speed interface

signals before they are passed to the device core.

Output Register Block

The output register block can optionally register signals from the core of the device before they are passed to the sysIO

buffers.

Figure 3.10 shows the input/output register block for the PIOs.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

24

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

CLOCK_ENABLE

PIO Pair

OUTPUT_CLK

INPUT_CLK

(1,0)

LATCH_INPUT_VALUE

D_IN_1

D_IN_0

Pad

D_OUT_1

D_OUT_0

(1,0)

0

1

OUTPUT_ENABLE

(1,0)

LATCH_INPUT_VALUE

D_IN_1

D_IN_0

Pad

D_OUT_1

D_OUT_0

(1,0)

0

1

OUTPUT_ENABLE

= Statically defined by configuration program.

Figure 3.10. iCE I/O Register Block Diagram

Table 3.8. PIO Signal List

Pin Name

I/O Type

Input

Description

OUTPUT_CLK

CLOCK_ENABLE

INPUT_CLK

Output register clock

Clock enable

Input

Input register clock

Output enable

OUTPUT_ENABLE

D_OUT_0/1

Input

Data from the core

Data to the core

D_IN_0/1

Output

Input

LATCH_INPUT_VALUE

Latches/holds the Input Value

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

25

iCE40 UltraPlus™ Family

Data Sheet

3.1.9. sysIO Buffer

Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the

periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement a wide variety of

standards that are found in today’s systems with LVCMOS interfaces.

Typical I/O Behavior During Power-up

The internal power-on-reset (POR) signal is deactivated when V_CC, SPI_V_CCIO1and V_{PP_2V5}reach the level defined in Table

4.4. After the POR signal is deactivated, the FPGA core logic becomes active. You must ensure that all V

banks are

CCIO

active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the

application. The default configuration of the I/O pins in a device prior to configuration is tri-stated with a weak pull-up

to V

. The I/O pins maintain the pre-configuration state until V_CC, SPI_V_CCIO1and V_{PP_2V5}reach the defined levels. The

CCIO

I/Os take on the software user-configured settings only after POR signal is deactivated and the device performs a

proper download/configuration. Unused I/Os are automatically blocked and the pull-up termination is disabled.

Supported Standards

The iCE40 UltraPlus sysIO buffer supports both single-ended input/output standards, and used as differential

comparators. The buffer supports the LVCMOS 1.8 V, 2.5 V, and 3.3 V standards. The buffer has individually

configurable options for bus maintenance (weak pull-up or none).

Table 3.9 and Table 3.10 show the I/O standards (together with their supply and reference voltages) supported by the

iCE40 UltraPlus devices.

Differential Comparators

The iCE40 UltraPlus devices provide differential comparator on pairs of I/O pins. These comparators are useful in some

mobile applications. See the Pin Information Summary section on page 46 to locate the corresponding paired I/Os with

differential comparators.

Table 3.9. Supported Input Standards

V_CCIO(Typical)

I/O Standard

3.3 V

2.5 V

1.8 V

Single-Ended Interfaces

LVCMOS33

Yes

—

Yes

—

LVCMOS25

LVCMOS18

—

Yes

Table 3.10. Supported Output Standards

V_CCIO(Typical)

I/O Standard

Single-Ended Interfaces

LVCMOS33

3.3 V

2.5 V

1.8 V

LVCMOS25

LVCMOS18

3.1.10. On-Chip Oscillator

The iCE40 UltraPlus devices feature two different frequency Oscillator. One is tailored for low-power operation that

runs at low frequency (LFOSC). Both Oscillators are controlled with internally generated current.

The LFOSC runs at nominal frequency of 10 kHz. The high frequency oscillator (HFOSC) runs at a nominal frequency of

48 MHz, divisible to 24 MHz, 12 MHz, or 6 MHz by user option. The LFOSC can be used to perform all always-on

functions, with the lowest power possible. The HFOSC can be enabled when the always-on functions detect a condition

that would need to wake up the system to perform higher frequency functions.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

26

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

3.1.11. User I²C IP

The iCE40 UltraPlus devices have two I²C IP cores. Either of the two cores can be configured either as an I²C master or

as an I²C slave. The pins for the I²C interface are not pre-assigned. User can use any General Purpose I/O pins.

In each of the two cores, there are options to delay the either the input or the output, or both, by 50 ns nominal, using

dedicated on-chip delay elements. This provides an easier interface with any external I²C components.

When the IP core is configured as master, it will be able to control other devices on the I²C bus through the pre-

assigned pin interface. When the core is configured as the slave, the device will be able to provide I/O expansion to an

I²C Master. The I²C cores support the following functionality:



Master and Slave operation

7-bit and 10-bit addressing

Multi-master arbitration support

Clock stretching

Up to 400 kHz data transfer speed

General Call support

Optionally delaying input or output data, or both

Optional filter on SCL input

For further information on the User I²C, refer to TN1274, iCE40 SPI/I2C Hardened IP Usage Guide.

3.1.12. User SPI IP

The iCE40 UltraPlus devices have two SPI IP cores. The pins for the SPI interface are not pre-assigned. User can use any

General Purpose I/O pins. Both SPI IP cores can be configured as a SPI master or as a slave. When the SPI IP core is

configured as a master, it controls the other SPI enabled devices connected to the SPI Bus. When SPI IP core is

configured as a slave, the device will be able to interface to an external SPI master.

The SPI IP core supports the following functions:



Configurable Master and Slave modes

Full-Duplex data transfer

Mode fault error flag with CPU interrupt capability

Double-buffered data register

Serial clock with programmable polarity and phase

LSB First or MSB First Data Transfer

For further information on the User SPI, refer to TN1274, iCE40 SPI/I2C Hardened IP Usage Guide.

3.1.13. RGB High Current Drive I/O Pins

The iCE40 UltraPlus family devices offer multiple high current LED drive outputs in each device in the family to allow

the iCE40 UltraPlus product to drive LED signals directly on mobile applications.

There are three outputs on each device that can sink up to 24 mA current. These outputs are open-drain outputs, and

provides sinking current to an LED connecting to the positive supply. These three outputs are designed to drive the RBG

LEDs, such as the service LED found in a lot of mobile devices. This RGB drive current is user programmable from 4 mA

to 24 mA, in increments of 4 mA. This output functions as General Purpose I/O with open-drain when the high current

drive is not needed.

3.1.14. RGB PWM IP

To provide an easier usage of the RGB high current drivers to drive RGB LED, a Pulse-Width Modulator IP can be used in

the user design. This PWM IP provides the flexibility for user to dynamically change the modulation width of each of

the RGB LED driver, which changes the color. Also, the user can dynamically change the settings on the ON-time

duration, OFF-time duration, and ability to turn the LED lights on and off gradually with user set breath-on and breath-

off time.

For additional information on the PWM IP, refer to TN1288, iCE40 LED Driver Usage Guide.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

27

iCE40 UltraPlus™ Family

Data Sheet

3.1.15. Non-Volatile Configuration Memory

All iCE40 UltraPlus devices provide a Non-Volatile Configuration Memory (NVCM) block which can be used to configure

the device.

For more information on the NVCM, refer to TN1248, iCE40 Programming and Configuration.

3.2. iCE40 UltraPlus Programming and Configuration

This section describes the programming and configuration of the iCE40 UltraPlus family.

3.2.1. Device Programming

The NVCM memory can be programmed through the SPI port. The SPI port is located in Bank 1, using SPI_V

supply.

power

CCIO1

3.2.2. Device Configuration

There are various ways to configure the Configuration RAM (CRAM), using SPI port, including:



From a SPI Flash (Master SPI mode)

System microprocessor to drive a Serial Slave SPI port (SSPI mode)

For more details on configuring the iCE40 UltraPlus, refer to TN1248, iCE40 Programming and Configuration.

3.2.3. Power Saving Options

The iCE40 UltraPlus devices feature iCEGate and PLL low power mode to allow users to meet the static and dynamic

power requirements of their applications. Table 3.11 describes the function of these features.

Table 3.11. iCE40 UltraPlus Power Saving Features Description

Device Subsystem

Feature Description

PLL

When LATCHINPUTVALUE is enabled, puts the PLL into low-power mode; PLL output held static at last

input clock value.

iCEGate

To save power, the optional iCEGate latch can selectively freeze the state of individual, non-registered

inputs within an I/O bank. Registered inputs are effectively frozen by their associated clock or clock-

enable control.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

28

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

4. DC and Switching Characteristics

4.1. Absolute Maximum Ratings

Table 4.1. Absolute Maximum Ratings

Parameter

Min

Max

Unit

Supply Voltage V_CC

–0.5

1.42

V

Output Supply Voltage V_CCIO

–0.5

3.60

1.42

V

NVCM Supply Voltage V_{PP_2V5}

PLL Supply Voltage V_CCPLL

I/O Tri-state Voltage Applied

Dedicated Input Voltage Applied

Storage Temperature (Ambient)

Junction Temperature (T_J)

Notes:

–0.5

–65

3.60

150

125

V

°C

1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional

operation of the device at these or any other conditions above those indicated in the operational sections of this specification is

not implied.

2. Compliance with FPGA-TN-02044, Thermal Management document is required.

3. All voltages referenced to GND.

4.2. Recommended Operating Conditions

Table 4.2. Recommended Operating Conditions

Symbol

Parameter

Min

1.14

1.71⁴

Max

1.26

3.46

Unit

V

1

V_CC

Core Supply Voltage

Slave SPI Configuration

Master SPI Configuration

V

V_{PP_2V5}NVCM

Programming and

Operating Supply Voltage

2.30

1.71

1.14

0

3.46

3.00

3.46

1.26

85

V

V_{PP_2V5}

Configuration from NVCM

NVCM Programming

V

1, 2, 3

V_CCIO

V_CCPLL

t_JCOM

I/O Driver Supply Voltage

PLL Supply Voltage

V_{CCIO_0}, SPI_V_CCIO1, V_{CCIO_2}

V

Junction Temperature Commercial Operation

Junction Temperature, Industrial Operation

Junction Temperature NVCM Programming

°C

t_JIND

–40

100

t_PROG

10.00

30.00

Notes:

1. Like power supplies must be tied together if they are at the same supply voltage and they meet the power up sequence

requirement. See the Power-up Supply Sequence section. V_CCand V_CCPLLare recommended to be tied together to the same

supply with an RC-based noise filter between them. Refer to TN1252, iCE40 Hardware Checklist.

2. See recommended voltages by I/O standard in subsequent table.

3. V_CCIOpins of unused I/O banks should be connected to the V_CCpower supply on boards.

4. V_{PP_2V5}can, optionally, be connected to a 1.8 V (+/-5%) power supply in Slave SPI Configuration modes subject to the condition

that none of the HFOSC/LFOSC and RGB LED driver features are used. Otherwise, V_{PP_2V5}must be connected to a power supply

with a minimum 2.30 V level.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

29

iCE40 UltraPlus™ Family

Data Sheet

4.3. Power Supply Ramp Rates

Table 4.3. Power Supply Ramp Rates

Symbol

t_RAMP

Parameter

Min

Max

Unit

Power supply ramp rates for all power supplies

0.6

10

V/ms

Notes:

1. Assumes monotonic ramp rates.

2. Power up sequence must be followed. See the Power-up Supply Sequence section below.

4.4. Power-On Reset

All iCE40 UltraPlus devices have on-chip Power-On-Reset (POR) circuitry to ensure proper initialization of the device.

Only three supply rails are monitored by the POR circuitry as follows: (1) VCC, (2) SPI_VCCIO1 and (3) VPP_2V5. All other

supply pins have no effect on the power-on reset feature of the device. Note that all supply voltage pins must be

connected to power supplies for normal operation (including device configuration).

4.5. Power-up Supply Sequence

It is recommended to bring up the power supplies in the following order. Note that there is no specified timing delay

between the power supplies, however, there is a requirement for each supply to reach a level of 0.5 V, or higher,

before any subsequent power supplies in the sequence are applied.

1. VCC and VCCPLL should be the first two supplies to be applied. Note that these two supplies can be tied together

subject to the recommendation to include a RC-based noise filter on the VCCPLL. Refer to TN1252, iCE40 Hardware

Checklist.

2. SPI_VCCIO1 should be the next supply, and can be applied any time after the previous supplies (VCC and VCCPLL) have

reached as level of 0.5 V or higher.

3. VPP_2V5 should be the next supply, and can be applied any time after previous supplies (VCC, VCCPLL and SPI_VCCIO1)

have reached a level of 0.5 V or higher.

4. Other Supplies (VCCIO0 and VCCIO2) do not affect device power-up functionality, and they can be applied any time

after the initial power supplies (VCC and VCCPLL) have reached a level of 0.5 V or greater. There is no power down

sequence required. However, when partial power supplies are powered down, it is required the above sequence to

be followed when these supplies are re-powered up again.

4.6. External Reset

When all power supplies have reached their minimum operating voltage defined in Table 4.2, it is required to either

keep CRESET_B LOW, or toggle CRESET_B from HIGH to LOW, for a duration of tCRESET_B, and release it to go HIGH, to

start configuration download from either the internal NVCM or the external Flash memory. Figure 4.1 shows Power-Up

sequence when SPI_VCCIO1 and VPP_2V5 are not connected together, and the CRESET_B signal triggers configuration

download. Figure 4.2 shows when SPI_VCCIO1 and VPP_2V5 connected together. All power supplies should be powered

up during configuration. Before and during configuration, the I/Os are held in tri-state. I/Os are released to user

functionality once the device has finished configuration.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

30

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

Figure 4.1. Power Up Sequence with SPE_VCCIO1 and VPP_2V5 Not Connected Together

Figure 4.2. Power Up Sequence with All Supplies Connected Together to 1.8 V

4.7. Power-On-Reset Voltage Levels

Table 4.4. Power-On-Reset Voltage Levels

Min

Max

Unit

Symbol

Parameter

V_CC

0.62

0.92

V

Power-On-Reset ramp up trip point (circuit

SPI_V_CCIO1

V_{PP_2V5}

V_CC

V_PORUP

0.87

0.90

—

1.50

1.53

0.79

1.50

1.53

V

monitoring V_CC, SPI_V_CCIO1, and

)

PP_2V5

Power-On-Reset ramp down trip point (circuit

SPI_V_CCIO1

V_{PP_2V5}

V_PORDN

—

V

monitoring V_CC, SPI_V_CCIO1, and

)

PP_2V5

—

Note: These POR trip points are only provided for guidance. Device operation is only characterized for power supply voltages

specified under recommended operating conditions.

4.8. ESD Performance

Please contact Lattice Semiconductor for additional information.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

31

iCE40 UltraPlus™ Family

Data Sheet

4.9. DC Electrical Characteristics

Over recommended operating conditions.

Table 4.5. DC Electrical Characteristics

Symbol

Parameter

Min

Typ

Max

Unit

Condition

1, 3, 4

Input or I/O Leakage

—

±10

µA

I_IL, I_IH

0 V < V_IN< V_CCIO+ 0.2 V

V_CCIO= 3.3 V, 2.5 V, 1.8 V

V_CC= Typ, V_IO= 0 to V_CCIO+ 0.2 V

I/O Capacitance, excluding

LED Drivers²

C₁

—

6

—

pf

V_CCIO= 3.3 V, 2.5 V, 1.8 V

Global Input Buffer

Capacitance²

C₂

V_CC= Typ, V_IO= 0 to V_CCIO+ 0.2 V

V_CC= Typ, V_IO= 0 to 3.5 V

V_CCIO= 1.8 V, 2.5 V, 3.3 V

C₃

RGB Pin Capacitance²

IRLED Pin Capacitance²

Input Hysteresis

—

15

53

200

—

pf

C₄

V_HYST

—

mV

µA

−3

−8

−11

−31

−72

−128

V_CCIO= 1.8 V, 0 ≤ V_IN≤ 0.65 * V_CCIO

V_CCIO= 2.5 V, 0 ≤ V_IN≤ 0.65 * V_CCIO

V_CCIO= 3.3 V, 0 ≤ V_IN≤ 0.65 * V_CCIO

Internal PIO Pull-up Current

—

I_PU

—

Notes:

1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is

not measured with the output driver active. Internal pull-up resistors are disabled.

2. T_J25 ^oC, f = 1.0 MHz.

3. Refer to V_ILand V_IHin Table 4.13 on page 34.

4. Input pins are clamped to V_CCIOand GND by a diode. When input is higher than V_CCIOor lower than GND, the Input Leakage

current will be higher than the I_ILand I_IH.

4.10. Supply Current

Table 4.6. Supply Current ^{1, 2, 3, 4, 5}

Typ

V_CC=1.2 V

Symbol

Parameter

Unit

I_CCSTDBY

I_PP2V5STDBY

I_{SPI_VCCIO1STDBY}

I_CCIOSTDBY

I_CCPEAK

Core Power Supply Static Current

75

µA

V_{PP_2V5}Power Supply Static Current

0.55

0.5

SPI_V_CCIO1Power Supply Static Current

V_CCIOPower Supply Static Current

µA

0.5

µA

Core Power Supply Startup Peak Current

V_{PP_2V5}Power Supply Startup Peak Current

SPI_V_CCIO1Power Supply Startup Peak Current

V_CCIOPower Supply Startup Peak Current

12

mA

I_{PP_2V5PEAK}

I_{SPI_VCCIO1PEAK}

I_CCIOPEAK

2.5

9.0

2.0

Notes:

1. Assumes blank pattern with the following characteristics: all outputs are tri-stated, all inputs are configured as LVCMOS and

held at V_CCIOor GND, on-chip PLL is off. For more detail with your specific design, use the Power Calculator tool. Power specified

with master SPI configuration mode. Other modes may be up to 25% higher.

2. Frequency = 0 MHz.

3. T_J= 25 °C, power supplies at nominal voltage, on devices processed in nominal process conditions.

4. Does not include pull-up.

5. Startup Peak Currents are measured with decoupling capacitances of 0.1 uF, 10 nF, and 1 nF to the power supply. Higher

decoupling capacitance causes higher current.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

32

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

4.11. User I²C Specifications

Table 4.7. User I²C Specifications

Spec (STD Mode)

Spec (FAST Mode)

Symbol

Parameter

Unit

Min

Typ

—

Max

Min

—

Typ

—

Max

400

—

f_SCL

Maximum SCL clock frequency

SCL clock HIGH Time

—

4

100

—

kHz

µs

ns

µs

t_HI

0.6

1.3

100

0

t_LO

SCL clock LOW Time

4.7

250

0

—

t_SU,DAT

t_HD,DAT

t_SU,STA

t_HD,STA

t_SU,STO

t_BUF

Setup time (DATA)

—

Hold time (DATA)

—

Setup time (START condition)

Hold time (START condition)

Setup time (STOP condition)

Bus free time between STOP and START

SCL LOW to DATAOUT valid

4.7

4

—

0.6

1.3

—

4

—

4.7

—

t_CO,DAT

3.4

0.9

4.12. I²C 50 ns Delay

Table 4.8. I²C 50 ns Delay

Spec

Symbol

Parameter

Unit

Min

Typ

Max

T_DELAY

Delay through 50 ns Delay Block

—

50

—

ns

4.13. I²C 50 ns Filter

Table 4.9. I²C 50 ns Filter

Spec

Typ

50

Symbol

Parameter

Unit

Min

—

Max

—

T_FILTER-H

T_FILTER-L

HIGH Pulse Filter through 50 ns Filter Block

LOW Pulse Filter through 50 ns Filter Block

ns

—

50

—

4.14. User SPI Specifications ^{1, 2}

Table 4.10. User SPI Specifications

Symbol

Parameter

Min

Typ

Max

Unit

f_MAX

Maximum SCK clock frequency

—

45

MHz

Notes:

1. All setup and hold time parameters on external SPI interface are design-specific and, therefore, generated by the Lattice Design

Software too. These parameters include the following:

-

t_SUmaster

t_HOLDmaster

t_SUslave

t_HOLDslave

t_SCK2OUT

master Setup Time (master mode)

master Hold time (master mode)

slave Setup Time (slave mode)

slave Hold time (slave mode)

SCK to Out Delay (slave mode)

2. The SCLK duty cycle needs to be specified in the Lattice Design Software as a timing constraint in order to ensure proper timing

check on SCLK HIGH and LOW (t_HI, t_LO) time.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

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Data Sheet

4.15. Internal Oscillators (HFOSC, LFOSC)

Table 4.11. Internal Oscillators (HFOSC, LFOSC)

Parameter

Spec/Recommended

Parameter Description

Unit

Symbol

Conditions

Commercial Temp HFOSC clock frequency (t_J= 0 °C–85 °C)

Min

Typ

48

10

50

—

Max

-10%

-20%

-10%

45

10%

20%

10%

55

MHz

kHz

%

f_CLKHF

Industrial Temp

HFOSC clock frequency (t_J= –40 °C–100 °C)

f_CLKLF

—

LFOSC CLKK clock frequency

Commercial Temp HFOSC Duty Cycle (t_J= 0 °C–85 °C)

DCH_CLKHF

Industrial Temp

HFOSC Duty Cycle (t_J= –40 °C–100 °C)

LFOSC Duty Cycle (Clock High Period)

Oscillator output synchronizer delay

Oscillator output disable delay

40

60

%

DCH_CLKLF

—

45

55

%

Tsync_on

Tsync_off

—

5

Cycles

—

5

Note: Glitchless enabling and disabling OSC clock outputs.

4.16. sysI/O Recommended Operating Conditions

Table 4.12. sysI/O Recommended Operating Conditions

V_CCIO(V)

Typ

Standard

Min

Max

3.46

2.62

1.89

LVCMOS 3.3

LVCMOS 2.5

LVCMOS 1.8

3.14

2.37

1.71

3.3

2.5

1.8

4.17. sysI/O Single-Ended DC Electrical Characteristics

Table 4.13. sysI/O Single-Ended DC Electrical Characteristics

V_{OH Min}

(V)

V_{OL Max}

(V)

V_IL

V_IH

I_OL

(mA)

I_OHMax

(mA)

Input/Output

Standard

Min (V)

Max (V)

Min (V)

0.4

0.2

0.4

0.2

0.4

0.2

V_CCIO− 0.4

V_CCIO− 0.2

V_CCIO− 0.4

V_CCIO− 0.2

V_CCIO− 0.4

V_CCIO− 0.2

8

0.1

6

–8

–0.1

–6

LVCMOS 3.3

LVCMOS 2.5

LVCMOS 1.8

–0.3

0.8

2.0

V_CCIO+0.2 V

–0.3

0.7

1.7

V_CCIO+0.2 V

0.1

4

–0.1

–4

0.35 V_CCIO

0.65 V_CCIO

0.1

–0.1

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

34

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Data Sheet

4.18. Differential Comparator Electrical Characteristics

Table 4.14. Differential Comparator Electrical Characteristics

Parameter

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

V_REF

Reference Voltage to compare, on V_INM

V_CCIO= 2.5 V

0.25

250

—

V_CCIO- 0.25 V

V

V_{DIFFIN_H}

V_{DIFFIN_L}

I_IN

Differential input HIGH (V_INP- V_INM

)

—

–250

10

mV

µA

Differential input LOW (V_INP- V_INM

Input Current, V_INPand V_INM

)

–10

4.19. Typical Building Block Function Performance

4.19.1. Pin-to-Pin Performance (LVCMOS25)

Table 4.15. Pin-to-Pin Performance (LVCMOS25)

Function

Basic Functions

16-Bit Decoder

4:1 Mux

Timing

Unit

16.5

18.0

19.5

ns

16:1 Mux

Notes:

1. The above timing numbers are generated using the Lattice Design Software tool. Exact performance may vary with device and

tool version. The tool uses internal parameters that have been characterized but are not tested on every device.

2. Using a V_CCof 1.14 V at Junction Temperature 85 °C.

4.19.2. Register-to-Register Performance

Table 4.16. Register-to-Register Performance

Function

Timing

Unit

Basic Functions

16:1 Mux

110

100

40

MHz

16-Bit Adder

16-Bit Counter

64-Bit Counter

Embedded Memory Functions

256 x 16 Pseudo-Dual Port RAM

Notes:

150

MHz

1. The above timing numbers are generated using the Lattice Design Software tool. Exact performance may vary with device and

tool version. The tool uses internal parameters that have been characterized but are not tested on every device.

2. Under worst case operating conditions.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

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iCE40 UltraPlus™ Family

Data Sheet

4.20. sysDSP Timing

Over recommended operating conditions.

Table 4.17. sysDSP Timing

Parameter

f_MAX8x8SMULT

f_{MAX16x16SMULT}

Description

Min

50

Max

—

Unit

MHz

Max frequency signed MULT8x8 bypassing pipeline register

Max frequency signed MULT16x16 bypassing pipeline register

50

—

4.21. SPRAM Timing

Over recommended operating conditions.

Table 4.18. Single Port RAM Timing

Parameter

Description

Min

Max

Unit

f_MAXSRAM

Max frequency SPRAM (4/8/16-bit Read and Write)

70

—

MHz

4.22. Derating Logic Timing

Logic timing provided in the following sections of the data sheet and the Lattice design tools are worst case numbers in

the operating range. Actual delays may be much faster. Lattice design tools can provide logic timing numbers at a

particular temperature and voltage.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

36

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Data Sheet

4.23. Maximum sysIO Buffer Performance

Table 4.19. Maximum sysIO Buffer Performance

I/O Standard

Inputs

Max Speed

Unit

LVCMOS33

250

MHz

LVCMOS25

LVCMOS18

Outputs

LVCMOS33

250

155

70

MHz

LVCMOS25

LVCMOS18

LVCMOS12

Note: Measured with a toggling pattern.

4.24. iCE40 UltraPlus Family Timing Adders

Over recommended commercial operating conditions.

Table 4.20. iCE40 UltraPlus Family Timing Adders

Buffer Type

Input Adjusters

LVCMOS33

LVCMOS25

LVCMOS18

Output Adjusters

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS12

Notes:

Description

Timing (Typ)

Units

LVCMOS, V_CCIO= 3.3 V

LVCMOS, V_CCIO= 2.5 V

LVCMOS, V_CCIO= 1.8 V

0.18

0

ns

0.19

LVCMOS, V_CCIO= 3.3 V

LVCMOS, V_CCIO= 2.5 V

LVCMOS, V_CCIO= 1.8 V

LVCMOS, V_CCIO= 1.2 V

-0.12

0

ns

1.32

5.38

1. Timing adders are relative to LVCMOS25 and characterized but not tested on every device.

2. LVCMOS timing measured with the load specified in Switching Test Condition table.

3. Commercial timing numbers are shown.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

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iCE40 UltraPlus™ Family

Data Sheet

4.25. iCE40 UltraPlus External Switching Characteristics

Over recommended commercial operating conditions.

Table 4.21. iCE40 UltraPlus External Switching Characteristics

Parameter

Clocks

Description

Device

Min

Max

Unit

Global Clock

f_{MAX_GBUF}

t_{W_GBUF}

Frequency for Global Buffer Clock network

Clock Pulse Width for Global Buffer

Global Buffer Clock Skew Within a Device

All Devices

—

2

—

185

—

530

MHz

ns

ps

t_{ISKEW_GBUF}

Pin-LUT-Pin Propagation Delay

Best case propagation delay through one

LUT logic

General I/O Pin Parameters (Using Global Buffer Clock without PLL)*

t_PD

All Devices

—

9.0

ns

t_{SKEW_IO}

t_CO

t_SU

Data bus skew across a bank of IOs

Clock to Output – PIO Output Register

Clock to Data Setup – PIO Input Register

Clock to Data Hold – PIO Input Register

All Devices

—

−0.5

5.55

510

10.0

—

ps

ns

t_H

—

General I/O Pin Parameters (Using Global Buffer Clock with PLL)

t_COPLL

t_SUPLL

t_HPLL

Clock to Output – PIO Output Register

Clock to Data Setup – PIO Input Register

Clock to Data Hold – PIO Input Register

All Devices

—

7.3

−1.1

2.4

—

ns

*Note: All the data is from the worst case.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

38

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

4.26. sysCLOCK PLL Timing

Over recommended operating conditions.

Table 4.22. sysCLOCK PLL Timing

Parameter

Descriptions

Conditions

Min

Max

Unit

Input Clock Frequency (REFERENCECLK,

EXTFEEDBACK)

f_IN

—

10

133

MHz

Output Clock Frequency (PLLOUT)

PLL VCO Frequency

16

533

10

275

1066

133

f_OUT

f_VCO

—

MHz

3

f_PFD

Phase Detector Input Frequency

AC Characteristics

t_DT

t_PH

Output Clock Duty Cycle

—

40

—

60

±12

450

0.05

750

0.10

275

0.05

—

%

deg

Output Phase Accuracy

—

f_OUT>= 100 MHz

—

ps p-p

UIPP

ps p-p

UIPP

ps p-p

UIPP

ns

Output Clock Period Jitter

f_OUT< 100 MHz

—

f_OUT>= 100 MHz

—

1, 5, 6

Output Clock Cycle-to-Cycle Jitter

Output Clock Phase Jitter

t_OPJIT

f_OUT< 100 MHz

—

f_PFD>= 25 MHz

—

f_PFD< 25 MHz

t_W

Output Clock Pulse Width

PLL Lock-in Time

At 90% or 10%

1.33

—

2, 3

t_LOCK

—

50

µs

t_UNLOCK

PLL Unlock Time

—

50

ns

f_PFD≥ 20 MHz

—

1000

0.02

500

—

ps p-p

UIPP

ns

4

t_IPJIT

Input Clock Period Jitter

f_PFD< 20 MHz

—

3

t_STABLE

LATCHINPUTVALUE LOW to PLL Stable

LATCHINPUTVALUE Pulse Width

RESET Pulse Width

—

3

t_{STABLE_PW}

t_RST

100

10

100

ns

—

ns

t_RSTREC

RESET Recovery Time

—

µs

t_{DYNAMIC_WD}

DYNAMICDELAY Pulse Width

—

VCO Cycles

Notes:

1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is

taken over 1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B.

2. Output clock is valid after t_LOCKfor PLL reset and dynamic delay adjustment.

3. At minimum f_PFD. As the f_PFDincreases the time will decrease to approximately 60% the value listed.

4. Maximum limit to prevent PLL unlock from occurring. Does not imply the PLL will operate within the output specifications listed

in this table.

5. The jitter values will increase with loading of the PLD fabric and in the presence of SSO noise.

4.27. SPI Master or NVCM Configuration Time

Table 4.23. SPI Master or NVCM Configuration Time

Symbol

Parameter

Conditions

Max

140

50

Unit

ms

All devices – Low Frequency (Default)

All devices – Medium frequency

All devices – High frequency

t_CONFIG

POR/CRESET_B to Device I/O Active

ms

26

ms

Notes:

1. Assumes sysMEM Block is initialized to an all zero pattern if they are used.

2. The NVCM download time is measured with a fast ramp rate starting from the maximum voltage of POR trip point.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

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iCE40 UltraPlus™ Family

Data Sheet

4.28. sysCONFIG Port Timing Specifications

Over recommended operating conditions.

Table 4.24. sysCONFIG Port Timing Specifications

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

All Configuration Mode

Minimum CRESET_B LOW pulse width

tCRESET_B

required to restart configuration, from

falling edge to rising edge

—

200

49

—

ns

t_{DONE_IO}

Number of configuration clock cycles after

CDONE goes HIGH before the PIO pins are

activated

Clock

Cycles

Slave SPI

t_{CR_SCK}

Minimum time from a rising edge on

CRESET_B until the first SPI WRITE

operation, first SPI_XCK clock. During this

time, the iCE40 UltraPlus device is clearing

its internal configuration memory

—

1200

—

µs

f_MAX

Write

Read¹

—

1

—

15

—

25

—

MHz

ns

CCLK clock frequency

—

20

12

13

t_CCLKH

t_CCLKL

CCLK clock pulsewidth HIGH

CCLK clock pulsewidth LOW

CCLK setup time

—

ns

t_STSU

—

ns

t_STH

ns

CCLK hold time

—

t_STCO

ns

CCLK falling edge to valid output

—

Master SPI³

f_MCLK

MCLK clock frequency

Low Frequency

Medium Frequency²

High Frequency²

7.0

21.0

33.0

1200

6.16

1

12.0

33.0

53.0

—

17.0

45.0

71.0

—

MHz

µs

t_MCLK

t_SU

CRESET_B HIGH to first MCLK edge

CCLK setup time

—

ns

t_HD

CCLK hold time

—

ns

Notes:

1. Supported with 1.2 V V_CCand at 25 °C.

2. Extended range f_MAXWrite operations support up to 53 MHz with 1.2 V V_CCand at 25 °C.

3. t_SUand t_HDtiming must be met for all MCLK frequency choices.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

40

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

4.29. RGB LED Drive

Table 4.25. RGB LED

Symbol

ILED_ACCURACY RGB0, RGB1, RGB2 Sink Current Accuracy to selected current @ V_LEDOUT>= 0.5 V

ILED_MATCH

RGB0, RGB1, RGB2 Sink Current Matching among the 3 outputs @ V_LEDOUT>= 0.5

Parameter

Min

–12

–5

Max

+12

+5

Unit

%

4.30. Switching Test Conditions

Figure 4.3 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,

voltage, and other test conditions are listed in Table 4.26.

V_T

R1

Test Point

DUT

CL

Figure 4.3. Output Test Load, LVCMOS Standards

Table 4.26. Test Fixture Required Components, Non-Terminated Interfaces

Test Condition

R₁

C_L

Timing Reference

LVCMOS 3.3 = 1.5 V

LVCMOS 2.5 = V_CCIO/2

LVCMOS 1.8 = V_CCIO/2

1.5 V

V_T

—

LVCMOS settings (L ≥ H, H ≥ L)

0 pF

∞

—

LVCMOS 3.3 (Z ≥ H)

LVCMOS 3.3 (Z ≥ L)

Other LVCMOS (Z ≥ H)

Other LVCMOS (Z ≥ L)

LVCMOS (H ≥ Z)

V_OL

V_OH

V_OL

V_OH

V_OL

V_OH

1.5 V

V_CCIO/2

188

0 pF

V_CCIO/2

V_OH– 0.15 V

LVCMOS (L ≥ Z)

V_OL– 0.15 V

Note: Output test conditions for all other interfaces are determined by the respective standards.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

41

iCE40 UltraPlus™ Family

Data Sheet

5. Pinout Information

5.1. Signal Descriptions

5.1.1. Power Supply Pins

Signal Name

Function

Power

I/O

—

Description

V_CC

Core Power Supply

V_{CCIO_0}, SPI_V_CCIO1, V_{CCIO_2}

Power

Power for I/Os in Bank 0, 1, and 2.

Power for NVCM programming and operations.

Power for PLL.

V_{PP_2V5}

V_CCPLL

Power

GND

GROUND

Ground

GND_LED

Ground for LED drivers. Should connect to GND on board.

5.1.2. Configuration Pins

Signal Name

Function

I/O

Description

General I/O

Shared

Function

CRESET_B

—

Configuration

I

Configuration Reset, active LOW. No internal pull-up resistor.

Either actively driven externally or connect an 10 kΩ pull-up to

SPI_V_CCIO1

.

IOB_xxx

CDONE

Configuration

General I/O

I/O

Configuration Done. Includes a weak pull-up resistor to

SPI_V_CCIO1

.

In user mode, after configuration, this pin can be programmed

as general I/O in user function. In 30-pin WLCSP, this pin

connects to IOB_12a, which also is shared as global signal G4

in user mode.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

42

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

5.1.3. Configuration SPI Pins

Signal Name

Function

I/O

Description

General I/O

Shared

Function

IOB_34a

SPI_SCK

SPI_SO

SPI_SI

Configuration

I/O

This pin is shared with device configuration. During

configuration:

In Master SPI mode, this pin outputs the clock to external SPI

memory.

In Slave SPI mode, this pin inputs the clock from external

In user mode, after configuration, this pin can be programmed as

general I/O in user function.

General I/O

I/O

IOB_32a

IOB_33b

IOB_35b

Configuration

Output

This pin is shared with device configuration. During

configuration:

In Master SPI mode, this pin outputs the command data to

external SPI memory.

In Slave SPI mode, this pin connects to the MISO pin of the

In user mode, after configuration, this pin can be programmed as

general I/O in user function.

General I/O

I/O

Configuration

Input

This pin is shared with device configuration. During

configuration:

In Master SPI mode, this pin receives data from external SPI

memory.

In Slave SPI mode, this pin connects to the MOSI pin of the

General I/O

I/O

In user mode, after configuration, this pin can be programmed as

general I/O in user function.

SPI_SS_B

Configuration

This pin is shared with device configuration. During

configuration:

In Master SPI mode, this pin outputs to the external SPI memory.

General I/O

I/O

In user mode, after configuration, this pin can be programmed as

general I/O in user function.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

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iCE40 UltraPlus™ Family

Data Sheet

5.1.4. Global Pins

Signal Name

Function

General I/O

Global

I/O

Description

General I/O

Shared

Function

G0

IOT_46b

In user mode, after configuration, this pin can be

programmed as general I/O in user function.

Input

I/O

Global input used for high fanout, or clock/ reset net. The

G0 pin drives the GBUF0 global buffer.

IOT_45a

IOB_25b

IOB_12a

IOB_11b

IOB_3b

G1

G3

G4

G5

G6

General I/O

Global

In user mode, after configuration, this pin can be

programmed as general I/O in user function.

Input

I/O

Global input used for high fanout, or clock/ reset net. The

G1 pin drives the GBUF1 global buffer.

General I/O

Global

In user mode, after configuration, this pin can be

programmed as general I/O in user function.

Input

I/O

Global input used for high fanout, or clock/ reset net. The

G3 pin drives the GBUF3 global buffer.

General I/O

Global

In user mode, after configuration, this pin can be

programmed as general I/O in user function.

Input

I/O

Global input used for high fanout, or clock/ reset net. The

G4 pin drives the GBUF4 global buffer.

General I/O

Global

In user mode, after configuration, this pin can be

programmed as general I/O in user function.

Input

I/O

Global input used for high fanout, or clock/ reset net. The

G5 pin drives the GBUF5 global buffer.

General I/O

Global

In user mode, after configuration, this pin can be

programmed as general I/O in user function.

Input

Global input used for high fanout, or clock/ reset net. The

G6 pin drives the GBUF6 global buffer.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

44

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

5.1.5. General I/O, LED Pins

Signal Name

Function

I/O

Description

General I/O

Shared Function

RGB0

—

General I/O

Open-

Drain I/O

In user mode, when RGB function is not used, this pin can

be connected to any user logic and used as open-drain I/O.

This pin is located in Bank 0.

LED

Open-

Drain

Output

In user mode, when using RGB function, this pin can be

programmed as open drain 24 mA output to drive external

LED.

RGB1

RGB2

—

General I/O

LED

Open-

Drain I/O

In user mode, when RGB function is not used, this pin can

be connected to any user logic and used as open-drain I/O.

This pin is located in Bank 0.

Open-

Drain

Output

In user mode, when using RGB function, this pin can be

programmed as open drain 24 mA output to drive external

LED.

General I/O

LED

Open-

Drain I/O

In user mode, when RGB function is not used, this pin can

be connected to any user logic and used as open-drain I/O.

This pin is located in Bank 0.

Open-

Drain

Output

In user mode, when using RGB function, this pin can be

programmed as open drain 24 mA output to drive external

LED.

PIOT_xx

PIOB_xx

—

General I/O

I/O

In user mode, with user's choice, this pin can be

programmed as I/O in user function in the top (xx = I/O

location). These pins are located in Bank 0.

In user mode, with user's choice, this pin can be

programmed as I/O in user function in the bottom (xx = I/O

location). Pins with xx <= 9 are located in Bank 2, pins with

xx> are located in Bank 1.

I/O

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

45

iCE40 UltraPlus™ Family

Data Sheet

5.2. Pin Information Summary

iCE40UP3K

iCE40UP5K

Pin Type

UWG30

SG48

17

14

8

General Purpose

I/O Per Bank

Bank 0

Bank 1

Bank 2

7

10

4

7

10

4

Total General Purpose I/Os

V_CC

21

1

21

1

39

2

V_CCIO

Bank 0

1

Bank 1

Bank 2

1

V_CCPLL

1

V_{PP_2V5}

1

Dedicated Config Pins

GND

1

2

0¹

2

Total Balls

30

48

Note:

1. 48-pin QFN package (SG48) requires the package paddle to be connected to GND.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

46

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

5.3. iCE40UP Part Number Description

iCE40UP XX-XX XX XI TR

Device Family

iCE40UP FPGA

TR

<blank> = Default Tape and Reel

for SG48 (See quantity below)

TR = Tape and Reel (See quantity below)

TR50 = Tape and Reel, 50 units

TR1K = Tape and Reel, 1,000 units

Logic Cells

3K = 2,800 Logic Cells

5K = 5,280 Logic Cells

Grade

I = Industrial

Package

UWG30 = 30-Ball WLCSP (0.40 mm Ball Pitch)

SG48 = 48-Pin QFN (0.50 mm Pin Pitch)

All parts are shipped in tape-and-reel.

5.3.1. Tape and Reel Quantity

Package

UWG30

SG48

TR Quantity

5,000

2,000

5.4. Ordering Part Numbers

5.4.1. Industrial

Part Number

LUTs

2800

5280

Supply Voltage

1.2 V

Package

Pins

30

48

30

Temperature

IND

iCE40UP3K-UWG30ITR

iCE40UP3K-UWG30ITR1K

iCE40UP3K-UWG30ITR50

iCE40UP5K-SG48I

Halogen-Free WLCSP

Halogen-Free QFN

Halogen-Free WLCSP

1.2 V

IND

1.2 V

IND

1.2 V

IND

iCE40UP5K-SG48ITR50

iCE40UP5K-UWG30ITR

iCE40UP5K-UWG30ITR1K

iCE40UP5K-UWG30ITR50

1.2 V

IND

1.2 V

IND

1.2 V

IND

1.2 V

IND

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

47

iCE40 UltraPlus™ Family

Data Sheet

Supplemental Information

For Further Information

A variety of technical documents for the iCE40 UltraPlus family are available on the Lattice web site.



TN1248, iCE40 Programming and Configuration

TN1274, iCE40 SPI/I2C Hardened IP Usage Guide

TN1276, Advanced iCE40 SPI/I2C Hardened IP Usage Guide

TN1250, Memory Usage Guide for iCE40 Devices

TN1251, iCE40 sysCLOCK PLL Design and Usage Guide

TN1252, iCE40 Hardware Checklist

TN1288, iCE40 LED Driver Usage Guide

TN1295, DSP Function Usage Guide for iCE40 Devices

TN1296, iCE40 Oscillator Usage Guide

TN1314, iCE40 SPRAM Usage Guide

iCE40 UltraPlus Pinout Files

iCE40 UltraPlus Pin Migration Files

FPGA-TN-02044, Thermal Management

Package Diagrams

Lattice design tools

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

48

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

Technical Support

For assistance, submit a technical support case at www.latticesemi.com/techsupport.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

49

iCE40 UltraPlus™ Family

Data Sheet

Revision History

Date

Version

Section

Change Summary

August 2017

1.4

All

— Changed document number from DS1056 to FPGA-DS-02008.

— Removed Preliminary from document cover page and header.

1.3

All

— Changed document status from Advance to Preliminary.

— Updated footer.

Architecture

— Corrected link to FPGA-TN-02021, iCE40 LED Driver Usage Guide.

— Added link to FPGA-TN-02022, iCE40 SPRAM Usage Guide.

DC and

Switching

Characteristics

— Updated Typ V_CC=1.2 V values for I_{PP_2VSPEAK}and I_COOPEAKin Table 4.6.

Supply Current.

— Added Min value for f_MAXSRAMto Table 4.18. Single Port RAM Timing.

— Added LVCMOS12 information to Table 4.19. Maximum sysIO Buffer

Performance and Table 4.20. iCE40 UltraPlus Family Timing Adders.

— Updated Table 4.21. iCE40 UltraPlus External Switching

Characteristics. Revised Max values for t_{ISKEW_GBUF}, t_{SKEW_IO}, t_CO, t_COPLL, and

Min values for t_SUPLL, t_HPLL

.

— Added Max values to Table 4.23. SPI Master or NVCM Configuration

Time.

Pinout

Information

— Updated TR description in the iCE40UP Part Number Description

section.

— Updated part number information in the Ordering Part Numbers

section.

Supplemental

Information

— Corrected link to FPGA-TN-02021, iCE40 LED Driver Usage Guide.

— Added link to FPGA-TN-02022, iCE40 SPRAM Usage Guide.

— Added link to Package Diagrams.

June 2016

1.2

All

Updated template.

Introduction

Added QFN package in features list.

Product

Family

Added packages to Table 2.1 iCE40 UltraPlus Family Selection Guide.

Added information on RGB PWM IP in Overview.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

50

FPGA-DS-02008-1.4

iCE40 UltraPlus™ Family

Data Sheet

Date

Version

Section

Change Summary

Architecture

— Performed minor editorial changes.

— Added information on 256 kb SPRAM blocks.

— Changed headings in Table 3.2. Global Buffer (GBUF) Connections to

Programmable Logic Blocks.

— Corrected VCCPLL format in Figure 3.3. PLL Diagram.

— Updated note in Table 3.4. sysMEM Block Configurations.

— Added reference to FPGA-TN-02022, iCE40 SPRAM Usage Guide.

— Revised sysIO Buffer Banks information.

— Corrected VCCIO format in Figure 3.9. I/O Bank and Programmable

I/O Cell.

— Revised Typical I/O Behavior During Power-up information.

— Revised Supported Standards information.

— Revised heading in Table 3.9. Supported Input Standards.

— Revised heading and removed LVCMOS12 in Table 3.10. Supported

Output Standards.

— Revised HFOSC information in On-Chip Oscillator section.

— Removed "An RGB PWM IP is also offered in the family." in RGB High

Current Drive I/O Pins section.

DC and

Switching

Characteristics

— Added the following figures:



Figure 4.1. Power Up Sequence with SPE_VCCIO1 and

VPP_2V5 Not Connected Together.



Figure 4.2. Power Up Sequence with All Supplies Connected

Together to 1.8 V.

— Updated note in Table 4.5. DC Electrical Characteristics.

— Added note in Table 4.6. Supply Current.

— Revised User SPI Specifications 1, 2 section.



Removed symbols.

Added notes.

— Revised Table 4.11. Internal Oscillators (HFOSC, LFOSC).

— Removed note in Table 4.13. sysI/O Single-Ended DC Electrical

Characteristics.

— Changed to Lattice Design Software tool in Table 4.15. Pin-to-Pin

Performance (LVCMOS25).

— Changed to Lattice Design Software tool and revised note in Table

4.16. Register-to-Register Performance.

— Added sysDSP Timing section.

— Added SPRAM Timing section.

— Removed LVCMOS12 and added timing values in Table 4.19.

Maximum IO Buffer Performance.

— Removed LVCMOS12 and added timing values in Table 4.20. iCE40

UltraPlus Family Timing Adders.

— Revised max values in Table 4.23. SPI Master or NVCM Configuration

Time.

— Removed TBD conditions in Table 4.24. sysCONFIG Port Timing

Specifications. Revised t_HDparameter.

— Revised Table 4.25. High Current RGB LED and IR LED Drive.

Pinout

Information

— General update to Signal Descriptions section.

— Updated the iCE40UP Part Number Description section. Added

FGW49 package.

— Added OPNs.

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02008-1.4

51

iCE40 UltraPlus™ Family

Data Sheet

Date

Version

Section

Change Summary

Supplemental Added reference to FPGA-TN-02022, iCE40 SPRAM Usage Guide.

Information

September 2015

1.1

Architecture

Updated Architecture section. Replaced iCE5UP with iCE40UP.

Updated Pin Information Summary section.

— Replaced iCE5UP with iCE40UP.

Pinout

Information

— Replaced SWG30 with UWG30.

Ordering

Information

Updated iCE40UP Part Number Description section.

— Replaced iCE5UP with iCE40UP.

— Replaced SWG30 with UWG30.

Updated Ordering Part Numbers section. Replaced the table of part

Further

Information

Removed reference to Schematic Symbols.

Initial release.

August 2015

1.0

All

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

52

FPGA-DS-02008-1.4

7^thFloor, 111 SW 5^thAvenue

Portland, OR 97204, USA

T 503.268.8000

www.latticesemi.com


型号：	ICE40UP5K-UWG30ITR
厂家：	LATTICE SEMICONDUCTOR
描述：	iCE40 UltraPlusâ¢ Family
文件：	总53页 (文件大小：1953K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICE40UP5K-UWG30ITR [LATTICE]

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