ISPLSI1016EA-125LT44

®

ispLSI 1016EA

In-System Programmable High Density PLD

Features

Functional Block Diagram

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 2000 PLD Gates

— 32 I/O Pins, One Dedicated Input

— 96 Registers

— High-Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— Functionally Compatible with ispLSI 1016E

A0

A1

A2

A3

A4

A5

A6

A7

B7

D

Q

B6

B5

B4

B3

B2

B1

B0

Logic

Array

GLB

• NEW FEATURES

— 100% IEEE 1149.1 Boundary Scan Testable

— ispJTAG™ In-System Programmable via IEEE 1149.1

(JTAG) Test Access Port

— User-Selectable 3.3V or 5V I/O Supports Mixed-

Voltage Systems (V^CCIOPin)

Global Routing Pool (GRP)

CLK

— Open-Drain Output Option

• HIGH-PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 200 MHz Maximum Operating Frequency

— tpd = 4.5 ns Propagation Delay

0139C/1016EA

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

Description

The ispLSI 1016EA is a High Density Programmable

Logic Device containing 96 Registers, 32 Universal I/O

pins, one Dedicated Input pin, two Dedicated Clock Input

pins, one Global OE input pin and a Global Routing Pool

(GRP). The GRP provides complete interconnectivity

between all of these elements. The ispLSI 1016EA fea-

tures5Vin-systemprogrammability(ISP™)andin-system

diagnostic capabilities via an IEEE 1149.1 Test Access

Port. The ispLSI 1016EA offers non-volatile

reprogrammability of the logic, as well as the intercon-

nect to provide truly reconfigurable systems. A functional

superset of the ispLSI 1016 architecture, the ispLSI

1016EA device adds user-selectable 3.3V or 5V I/O and

open-drain output options.

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Device for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

The basic unit of logic on the ispLSI 1016EA device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1...B7 (Figure 1). There are a total of 16 GLBs in the

ispLSI 1016EA device. Each GLB has 18 inputs, a

programmable AND/OR/Exclusive OR array, and four

outputs which can be configured to be either combinato-

rial or registered. Inputs to the GLB come from the GRP

and a dedicated input. All of the GLB outputs are brought

back into the GRP so that they can be connected to the

inputs of any other GLB on the device.

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

to change without notice.

June 2000

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

1016ea_01

1

Specifications ispLSI 1016EA

Functional Block Diagram

Figure 1. ispLSI 1016EA Functional Block Diagram

VCCIO

Generic

Logic Blocks

(GLBs)

GOE 0

I/O 31

I/O 30

B7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 29

A0

B6

B5

B4

I/O 28

A1

A2

A3

A4

A5

A6

A7

I/O 27

I/O 26

I/O 25

I/O 4

I/O 5

I/O 6

I/O 7

I/O 24

Global

Routing

Pool

I/O 23

I/O 22

I/O 21

I/O 20

B3

B2

B1

B0

(GRP)

I/O 8

I/O 9

I/O 10

I/O 11

I/O 19

I/O 18

I/O 17

I/O 16

I/O 12

I/O 13

I/O 14

I/O 15

CLK 0

TDI

CLK 1

CLK 2

Clock

Distribution

Network

Megablock

TDO

IOCLK 0

IOCLK 1

TMS

TCK

0139/1016EA

*Note: Y1 and RESET are multiplexed on the same pin

Clocks in the ispLSI 1016EA device are selected using

the Clock Distribution Network. Two dedicated clock pins

(Y0 and Y1) are brought into the distribution network, and

five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and

IOCLK 1) are provided to route clocks to the GLBs and

I/O cells. The Clock Distribution Network can also be

driven from a special clock GLB (B0 on the ispLSI

1016EA device). The logic of this GLB allows the user to

create an internal clock from a combination of internal

signals within the device.

The device also has 32 I/O cells, each of which is directly

connected to an I/O pin. Each I/O cell can be individually

programmed to be a combinatorial input, registered

input, latched input, output or bi-directional

I/O pin with 3-state control. The signal levels are TTL

compatible voltages and the output drivers can source

2 mA or sink 8 mA. Each output can be programmed

independently for fast or slow output slew rate to mini-

mize overall output switching noise. By conneting the

VCCIO pin to a common 5V or 3.3V power supply, I/O

output levels can be matched to 5V or 3.3V-compatible

voltages.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the

outputs of the ispLSI 1016EA are individually program-

mable, either as a standard totem-pole output or an

open-drain output. The totem-pole output drives the

specified Voh and Vol levels, whereas the open-drain

output drives only the specified Vol. The Voh level on the

open-drain output depends on the external loading and

Eight GLBs, 16 I/O cells, a dedicated input (if available)

and one ORP are connected together to make a

Megablock (see Figure 1). The outputs of the eight GLBs

are connected to a set of 16 universal I/O cells by the

ORP. Each ispLSI 1016EA device contains two

Megablocks.

The GRP has, as its inputs, the outputs from all of the pull-up. This output configuration is controlled by a pro-

GLBs andallof theinputs from thebi-directionalI/O cells. grammable fuse. The default configuration when the

All of these signals are made available to the inputs of the device is in bulk erased state is totem-pole configuration.

GLBs. Delays through the GRP have been equalized to The open-drain/totem-pole option is selectable through

minimize timing skew.

the ispDesignEXPERT software tools.

2

Specifications ispLSI 1016EA

Boundary Scan

Figure 2. Boundary Scan Waveforms and Timing Specifications

TMS

TDI

T

bth

btsu

T

btcp

btch

btcl

TCK

TDO

T

btoz

btvo

btco

Valid Data

T

btcpsu

T

btcph

Data to be

captured

Data Captured

T

btuoz

btuov

btuco

Data to be

driven out

Valid Data

Symbol

Parameter

Min

100

50

20

25

50

–

Max Units

t

TCK [BSCAN test] clock pulse width

TCK [BSCAN test] pulse width high

TCK [BSCAN test] pulse width low

TCK [BSCAN test] setup time

–

ns

btcp

t

btch

–

ns

btcl

t

–

ns

btsu

bth

TCK [BSCAN test] hold time

–

ns

TCK [BSCAN test] rise and fall time

–

mV/ns

ns

rf

TAP controller falling edge of clock to valid output

TAP controller falling edge of clock to data output disable

TAP controller falling edge of clock to data output enable

BSCAN test Capture register setup time

25

–

btco

btoz

btvo

btcpsu

btcph

btuco

btuoz

btuov

–

ns

–

ns

40

25

–

ns

BSCAN test Capture register hold time

–

ns

BSCAN test Update reg, falling edge of clock to valid output

BSCAN test Update reg, falling edge of clock to output disable

BSCAN test Update reg, falling edge of clock to output enable

50

ns

–

ns

–

ns

3

Specifications ispLSI 1016EA

1

Absolute Maximum Ratings

Supply Voltage V

................................ -0.5 to +7.0V

CC

Input Voltage Applied........................ -2.5 to V +1.0V

CC

Off-State Output Voltage Applied ..... -2.5 to V +1.0V

CC

Storage Temperature................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (T ) with Power Applied ... 150°C

J

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional

operation of the device at these or at any other conditions above those indicated in the operational sections of this specification

is not implied (while programming, follow the programming specifications).

DC Recommended Operating Conditions

SYMBOL

PARAMETER

Commercial

MIN.

4.75

3.0

MAX.

5.25

3.6

UNITS

V

CC

Supply Voltage

V

T = 0°C to + 70°C

A

5V

Supply Voltage: Output Drivers

V

CCIO

3.3V

Input Low Voltage

Input High Voltage

0

0.8

V

IL

2.0

V +1

cc

V

IH

Table 2-0005/1016EA

Capacitance (T_A=25^oC, f=1.0 MHz)

SYMBOL

PARAMETER

TYPICAL

UNITS

TEST CONDITIONS

V_CC= 5.0V, V_PIN= 2.0V

Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance

(Commercial)

8

pf

C₁

10

pf

V_CC= 5.0V, V_PIN= 2.0V

Y0 Clock Capacitance

C₂

Table 2-0006/1016EA

Erase/Reprogram Specifications

PARAMETER

MINIMUM

MAXIMUM

UNITS

Erase/Reprogram Cycles

10000

—

Cycles

Table 2-0008/1016EA

4

Specifications ispLSI 1016EA

Switching Test Conditions

Figure 3. Test Load

Input Pulse Levels

GND to 3.0V

1.5ns

Input Rise and Fall Time 10% to 90%

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

+ 5V

1.5V

R

1

2

See Figure 3

Table 2-0003/1016EA

3-state levels are measured 0.5V from

steady-state active level.

Device

Output

Test

Point

R

C *

L

Output Load Conditions (see Figure 3)

TEST CONDITION

R1

470Ω

∞

R2

CL

A

B

390Ω

35pF

*C includes Test Fixture and Probe Capacitance.

L

0213a

Active High

Active Low

470Ω

Active High to Z

∞

390Ω

5pF

at V_OH-0.5V

C

Active Low to Z

at V_OL+0.5V

470Ω

Table 2-0004/1016E

DC Electrical Characteristics

Over Recommended Operating Conditions

SYMBOL

PARAMETER

Output Low Voltage

CONDITION

I_OL= 8 mA

MIN.

—

TYP.³MAX. UNITS

—

0.4

—

V

VOL

I_OH= -2 mA, V_CCIO= 3.0V

2.4

—

Output High Voltage

VOH

I

_OH= -4 mA, V_CCIO= 4.75V

—

V

Input or I/O Low Leakage Current

0V ≤ V_IN≤ V_IL(Max.)

-10

µA

I

IL

IH

(V_CCIO- 0.2)V ≤ V_IN≤ V_CCIO

—

10

µA

Input or I/O High Leakage Current

V

_CCIO≤ V_IN≤ 5.25V

0V ≤ V_IN≤ V_IL

_CCIO= 5.0V or 3.3V, V_OUT= 0.5V

V_IL= 0.0V, V_IH= 3.0V

_TOGGLE= 1 MHz

-200

-240

—

I

IL-PU

OS¹

µA

I/O Active Pull-Up Current

Output Short Circuit Current

—

V

mA

91

CC^{2, 4, 5}

Operating Power Supply Current

I

f

Table 2-0007/1016EA

1. One output at a time for a maximum duration of one second. V_OUT= 0.5V was selected to avoid test

problems by tester ground degradation. Characterized but not 100% tested.

2. Measured using four 16-bit counters.

3. Typical values are at V_CC= 5V and T_A= 25°C.

4. Unused inputs held at 0.0V.

5. Maximum I_CCvaries widely with specific device configuration and operating frequency. Refer to the

Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor

Data Book CD-ROM to estimate maximum I_CC

.

5

Specifications ispLSI 1016EA

External Timing Parameters

Over Recommended Operating Conditions

TEST ⁴

-200

-125

-100

DESCRIPTION¹

UNITS

2

PARAMETER

#

COND.

MIN. MAX.

MIN. MAX. MIN. MAX.

A

1

Data Propagation Delay, 4PT Bypass, ORP Bypass

Data Propagation Delay, Worst Case Path

Clock Frequency with Internal Feedback ³

—

4.5

6.0

—

ns

—

7.5

10.0

—

10.0

12.5

—

t

pd1

2

3

4

5

6

7

8

9

t

f

t

pd2

A

200

143

250

3.0

—

MHz

ns

125

100

167

4.5

—

100

77

max (Int.)

max (Ext.)

max (Tog.)

su1

1

—

A

Clock Frequency with External Feedback

(

)

—

tsu2 + tco1

1

Clock Frequency, Max. Toggle

(

)

—

125

6.0

—

twh + twl

GLB Reg. Setup Time before Clock,4 PT Bypass

GLB Reg. Clock to Output Delay, ORP Bypass

GLB Reg. Hold Time after Clock, 4 PT Bypass

GLB Reg. Setup Time before Clock

—

3.5

ns

4.5

6.0

co1

—

A

0.0

3.5

—

ns

0.0

5.5

—

0.0

7.0

—

t

h1

su2

10 GLB Reg. Clock to Output Delay

11 GLB Reg. Hold Time after Clock

12 Ext. Reset Pin to Output Delay

13 Ext. Reset Pulse Duration

4.0

—

5.5

—

7.0

—

co2

0.0

—

0.0

—

0.0

—

h2

5.5

—

10.0

—

13.5

—

r1

—

B

3.5

—

5.0

—

6.5

—

rw1

14 Input to Output Enable

7.0

4.5

—

12.0

7.0

—

15.0

9.0

—

ptoeen

ptoedis

goeen

goedis

wh

C

15 Input to Output Disable

—

B

16 Global OE Output Enable

—

C

17 Global OE Output Disable

—

18 External Synchronous Clock Pulse Duration, High

19 External Synchronous Clock Pulse Duration, Low

20 I/O Reg. Setup Time before Ext. Sync Clock (Y1)

2.0

3.0

4.0

3.5

—

wl

—

su3

—

21 I/O Reg. Hold Time after Ext. Sync. Clock (Y1)

0.0

—

ns

0.0

—

0.0

—

th3

Table 2-0030A/1016EA

v.2.6

1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-bit counter using GRP feedback.

4. Reference Switching Test Conditions section.

6

Specifications ispLSI 1016EA

1

Internal Timing Parameters

-200

-125

-100

2

PARAM.

#

DESCRIPTION

UNITS

MIN. MAX. MIN. MAX. MIN. MAX.

Inputs

tiobp

tiolat

tiosu

tioh

tioco

tior

tdin

22 I/O Register Bypass

23 I/O Latch Delay

ns

—

0.3

4.0

—

0.4

4.0

—

0.3

4.0

—

24 I/O Register Setup Time before Clock

25 I/O Register Hold Time after Clock

26 I/O Register Clock to Out Delay

27 I/O Register Reset to Out Delay

28 Dedicated Input Delay

3.0

0.0

—

3.0

0.0

—

3.4

0.0

—

4.6

1.9

5.0

2.2

4.0

1.1

—

GRP

tgrp1

tgrp4

tgrp8

tgrp16

GLB

t4ptbpc

t4ptbpr

t1ptxor

t20ptxor

txoradj

tgbp

tgsu

tgh

tgco

tgro

tptre

tptoe

tptck

29 GRP Delay, 1 GLB Load

30 GRP Delay, 4 GLB Loads

31 GRP Delay, 8 GLB Loads

32 GRP Delay, 16 GLB Loads

ns

—

1.7

1.9

2.1

2.5

—

2.1

2.3

2.5

2.9

1.3

1.5

1.7

2.1

33 4 ProductTerm Bypass Path Delay (Combinatorial)

34 4 Product Term Bypass Path Delay (Registered)

35 1 ProductTerm/XOR Path Delay

ns

—

3.4

3.1

3.6

1.2

—

0.3

4.0

—

4.9

4.3

2.1

—

1.7

1.8

1.9

0.6

—

36 20 Product Term/XOR Path Delay

37 XOR Adjacent Path Delay ³

—

38 GLB Register Bypass Delay

—

39 GLB Register Setup Time before Clock

40 GLB Register Hold Time after Clock

41 GLB Register Clock to Output Delay

42 GLB Register Reset to Output Delay

43 GLB Product Term Reset to Register Delay

44 GLB Product Term Output Enable to I/O Cell Delay

45 GLB Product Term Clock Delay

0.2

1.0

—

0.3

3.5

—

1.4

4.9

3.8

5.7

1.7

5.0

4.5

7.2

4.7

0.3

1.4

3.8

2.5

2.1

2.5

0.0

—

1.5

—

2.8

—

3.9 3.5

46 GLB Feedback Delay

tgfb

0.3

—

ORP

torp

torpbp

47 ORP Delay

ns

—

0.8

0.1

—

1.3

0.2

—

1.4

0.4

48 ORP Bypass Delay

Table 2-0036A/1016EA

v.2.6

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

7

Specifications ispLSI 1016EA

1

Internal Timing Parameters

-125

MIN. MAX. MIN. MAX.

-100

-200

PARAM.

#

DESCRIPTION

UNITS

MIN. MAX.

Outputs

tob

tsl

toen

todis

tgoe

49 Output Buffer Delay

—

0.9

5.0

3.1

1.4

—

1.7

5.0

4.0

3.0

—

2.0

5.0

5.1

3.9

ns

50 Output Buffer Delay, Slew Limited Adder

51 I/O Cell OE to Output Enabled

52 I/O Cell OE to Output Disabled

53 Global OE

Clocks

54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clk)

55 Clock Delay, Y1 to Global GLB Clock Line

0.9

0.8

0.0

0.8

0.9

1.8

0.0

1.1 1.1

0.9 0.9

0.8 1.8

0.0 0.0

1.9 1.9

1.5 1.5

0.8 1.8

0.0 0.0

0.8 2.8

ns

tgy0

tgy1

tgcp

tioy1

tiocp

56 Clock Delay, Clock GLB to Global GLB Clock Line

57 Clock Delay, Y1 to I/O Cell Global Clock Line

58 Clock Delay, Clock GLB to I/O Cell Global Clock Line

2.8 0.8 2.8

Global Reset

59 Global Reset to GLB and I/O Registers

—

0.0

—

2.1

—

5.1

ns

tgr

Table 2-0037A/1016EA

v.2.6

1. Internal Timing Parameters are not tested and are for reference only.

8

Specifications ispLSI 1016EA

ispLSI 1016EA Timing Model

I/O Cell

GRP

GLB

Feedback

#33 Comb 4 PT Bypass

ORP

I/O Cell

#46

Ded. In

#28

I/O Reg Bypass

#22

GRP4

#30

Reg 4 PT Bypass

#34

GLB Reg Bypass

#38

ORP Bypass

#48

#49, 50

I/O Pin

(Input)

I/O Pin

(Output)

Input

Register

20 PT

XOR Delays

GLB Reg

Delay

ORP

Delay

GRP Loading

Delay

Q

D

#51, 52

RST

D

Q

#47

#35 - 37

#59

#29, 31 - 32

#59

#23 - 27

RST

Reset

#39 - 42

Clock

Control

PTs

RE

OE

CK

Distribution

0491/1016EA

Y1

#55 - 58

#43 - 45

#54

#53

Y0

GOE 0

Derivations of

su = Logic + Reg su - Clock (min)

= ( iobp + grp4 + 20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min))

tsu, th and t

co from the Product Term Clock¹

t

= (#22 + #30 + #36) + (#39) - (#22 + #30 + #45)

0.9 = (0.3 + 1.5 + 1.9) + (0.2) - (0.3 + 1.5 + 1.2)

th

= Clock (max) + Reg h - Logic

= (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)

= (#22 + #30 + #45) + (#40) - (#22 + #30 + #36)

1.6 = (0.3 + 1.5 + 2.5) + (1.0) - (0.3 + 1.5 + 1.9)

tco

= Clock (max) + Reg co + Output

= (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)

= (#22 + #30 + #45) + (#41) + (#47 + #49)

= (0.3 + 1.5 + 2.5) + (1.4) + (0.8 + 0.9)

7.2

Derivations of

1

tsu,

th and tco from the Clock GLB

t

su

= Logic + Reg (setup) - Clock (min)

= ( iobp + grp4 + 20ptxor) + ( gsu) - (tgy0(min) + tgco + tgcp(min))

t

= (#22 + #30 + #36) + (#39) - (#54 + #41 + #56)

= (0.3 + 1.5 + 1.9) + (0.2) - (0.9 + 1.4 + 0.8)

1.1

1.4

7.2

h

= Clock (max) + Reg (hold) - Logic

= (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)

= (#54 + #41 + #56) + (#40) - (#22 + #30 + #36)

= (0.9 + 1.4 + 1.8) + (1.0) - (0.3 + 1.5 + 1.9)

co

= Clock (max) + Reg (clock-to-out) + Output

= (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)

= (#54 + #41 + #56) + (#41) + (#47 + #49)

= (0.9 + 1.4 + 1.8) + (1.4) + (0.8 + 0.9)

1. Calculations are based upon timing specifications for the ispLSI 1016EA-200.

Table 2-0042a/1016EA

v.2.6

9

Specifications ispLSI 1016EA

Maximum GRP Delay vs GLB Loads

4

3

2

1

ispLSI 1016EA-100

ispLSI 1016EA-125

ispLSI 1016EA-200

1

4

8

16

GLB Load

GRP/GLB/1016EA

Power Consumption

used. Figure 4 shows the relationship between power

and operating speed.

Power consumption in the ispLSI 1016EA device de-

pends on two primary factors: the speed at which the

device is operating and the number of Product Terms

Figure 4. Typical Device Power Consumption vs fmax

150

140

ispLSI 1016EA

130

120

110

100

90

80

0

50

100

150

200

250

f

max (MHz)

Notes: Configuration of four 16-bit counters

Typical current at 5V, 25°C

I

can be estimated for the ispLSI 1016EA using the following equation:

CC

(mA) = 23 + (# of PTs 0.52) + (# of nets max freq 0.004)

*

Where:

# of PTs = Number of product terms used in design

# of nets = Number of signals used in device

Max freq = Highest clock frequency to the device (in MHz)

The I

estimate is based on typical conditions (V

= 5.0V, room temperature) and an assumption of four GLB loads

CC

on average exists and the device is filled with four 16-bit counters. These values are for estimates only. Since the

value of I

is sensitive to operating conditions and the program in the device, the actual I

CC

should be verified.

CC

0127/1016EA

10

Specifications ispLSI 1016EA

Pin Description

TQFP

PIN NUMBERS

PLCC

PIN NUMBERS

DESCRIPTION

NAME

9, 10, 11, 12,

13, 14, 15, 16,

19, 20, 21, 22,

23, 24, 25, 26,

31, 32, 33, 34,

35, 36, 37, 38,

41, 42, 43, 44,

I/O 0 - I/O 3

I/O 4 - I/O 7

15, 16, 17, 18,

19, 20, 21, 22,

25, 26, 27, 28,

29, 30, 31, 32,

37, 38, 39, 40,

41, 42, 43, 44,

3, 4, 5, 6,

7, 8, 9, 10

Input/Output Pins - These are the general purpose I/O pins used by the logic

array.

I/O 8 - I/O 11

I/O 12 - I/O 15

I/O 16 - I/O 19

I/O 20 - I/O 23

I/O 24 - I/O 27

I/O 28 - I/O 31

1, 2, 3,

4

GOE 0/IN 3¹

2

40

This is a dual function pin. It can be used either as Global Output Enable for

all I/O cells or it can be used as a dedicated input pin.

14

36

24

33

8

TDI

Input - Functions as an input pin to load programming data into the device and

also used as one of the two control pins for the ispJTAG state machine.

30

18

27

Input - Controls the operation of the ISP state machine.

TMS

TDO

TCK

Output - Functions as an output pin to read serial shift register data.

Input - Functions as a clock pin for the Serial Shift Register.

Dedicated Clock input. This clock input is connected to one of the clock inputs

of all of the GLBs on the device.

11

35

5

Y0

Y1/RESET¹

29

This pin performs two functions:

Dedicated Clock input. This clock input is brought into the clock distribution

network, and can optionally be routed to any GLB on the device.

Active Low (0) Reset pin which resets all of the GLB and I/O registers in the

device.

GND

VCC

1, 23

12, 34

17, 39

6, 28

Ground (GND)

VCC

VCCIO

13

7

Supply voltage for output drivers, 5V or 3.3V.

Table 2-0002C/1016EA

1. Pins have dual function capability which is software selectable.

11

Specifications ispLSI 1016EA

Pin Configurations

ispLSI 1016EA 44-Pin PLCC Pinout Diagram

6

5

4

3

2

1

44 43 42 41 40

I/O 28

I/O 29

I/O 30

I/O 31

Y0

7

39

38

37

36

35

34

33

32

31

30

29

I/O 18

I/O 17

I/O 16

TMS

8

9

10

11

12

13

14

15

16

17

Y1/RESET¹

ispLSI 1016EA

VCC

Top View

VCCIO

TDI

TCK

I/O 15

I/O 14

I/O 13

I/O 12

I/O 0

I/O 1

I/O 2

18 19 20 21 22 23 24 25 26 27 28

1. Pins have dual function capability which is software selectable.

0123A-isp1016EA

ispLSI 1016EA 44-Pin TQFP Pinout Diagram

44 43 42 41 40 39 38 37 36 35 34

I/O 28

I/O 29

I/O 30

I/O 31

Y0

1

33

I/O 18

I/O 17

I/O 16

TMS

2

32

31

30

29

28

27

26

25

24

23

3

4

Y1/RESET¹

5

ispLSI 1016EA

VCC

6

VCC

Top View

VCCIO

TDI

7

TCK

8

I/O 15

I/O 14

I/O 13

I/O 12

I/O 0

I/O 1

I/O 2

9

10

11

12 13 14 15 16 17 18 19 20 21 22

1. Pins have dual function capability which is software selectable.

44 TQFP/1016EA

12

Specifications ispLSI 1016EA

Part Number Description

—

1016EA XXX

X

XXX

ispLSI

X

Grade

Blank = Commercial

Device Family

Device Number

Package

J44 = PLCC

T44 = TQFP

Speed

200 = 200 MHz

125 = 125 MHz

fmax

Power

L = Low

100

= 100 MHz

0212/1016EA

ispLSI 1016EA Ordering Information

COMMERCIAL

FAMILY

fmax (MHz)

200

tpd (ns)

4.5

ORDERING NUMBER

ispLSI 1016EA-200LJ44

ispLSI 1016EA-200LT44

ispLSI 1016EA-125LJ44

ispLSI 1016EA-125LT44

ispLSI 1016EA-100LJ44

ispLSI 1016EA-100LT44

PACKAGE

44-Pin PLCC

44-Pin TQFP

44-Pin PLCC

44-Pin TQFP

44-Pin PLCC

44-Pin TQFP

200

4.5

125

100

7.5

10

ispLSI

10

Table 2-0041A/1016EA

13


型号：	ISPLSI1016EA-125LT44
厂家：	LATTICE SEMICONDUCTOR
描述：	In-System Programmable High Density PLD 在系统可编程高密度PLD
文件：	总13页 (文件大小：164K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISPLSI1016EA-125LT44 [LATTICE]

相关型号：

ISPLSI1016EA-200LJ44

ISPLSI1016EA-200LT44

ISPLSI1016EA_07

ISPLSI1016E_02

ISPLSI1016E_06

ISPLSI1024-50LJ

ISPLSI1024-60LH/883

ISPLSI1024-60LJ

ISPLSI1024-60LJI

ISPLSI1024-60LT

ISPLSI1024-60LTI

ISPLSI1024-80LJ