ISPLSI1024EA-200LT100 [LATTICE]
In-System Programmable High Density PLD; 在系统可编程高密度PLD
| 型号： | ISPLSI1024EA-200LT100 |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | In-System Programmable High Density PLD |
| 文件： | 总13页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ispLSI 1024EA
In-System Programmable High Density PLD
Features
Functional Block Diagram
• HIGH DENSITY PROGRAMMABLE LOGIC
— 4000 PLD Gates
— 48 I/O Pins, Two Dedicated Inputs
— 144 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
A0
A1
A2
A3
A4
A5
A6
A7
C7
C6
C5
C4
C3
C2
C1
C0
D
D
D
D
Q
Q
Q
Q
Logic
Array
GLB
• NEW FEATURES
— 100% IEEE 1149.1 Boundary Scan Testable
— ispJTAG™ In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
— User Selectable 3.3V or 5V I/O Supports Mixed-
Voltage Systems (VCCIO Pin)
Global Routing Pool (GRP)
— Open-Drain Output Option
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool
CLK
— fmax = 200 MHz Maximum Operating Frequency
— tpd = 4.5 ns Propagation Delay
0139/1024EA
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
Description
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
The ispLSI 1024EA is a High Density Programmable
Logic Device containing 144 Registers, 48 Universal I/O
pins, two Dedicated Input pins, four Dedicated Clock
Input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 1024EA features 5V in-system
diagnosticcapabilitiesviaIEEE1149.1TestAccessPort.
The ispLSI 1024EA device offers non-volatile
reprogrammability of the logic, as well as the intercon-
nectstoprovidetrulyreconfigurablesystems.Afunctional
superset of the ispLSI 1024 architecture, the ispLSI
1024EA device adds user selectable 3.3V or 5V I/O and
open-drain output options.
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
The basic unit of logic on the ispLSI 1024EA device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…D7 (Figure 1). There are a total of 24 GLBs in the
ispLSI 1024EA device. Each GLB has 18 inputs, a
programmable AND/OR/Exclusive OR array, and four
outputs which can be configured to be either combinato-
rial or registered. Inputs to the GLB come from the GRP
and dedicated inputs. All of the GLB outputs are brought
back into the GRP so that they can be connected to the
inputs of any other GLB on the device.
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Copyright©2000LatticeSemiconductorCorp.Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
June 2000
1024ea_01
1
Specifications ispLSI 1024EA
Functional Block Diagram
Figure 1. ispLSI 1024EA Functional Block Diagram
RESET
VCCIO
Generic
Logic Blocks
(GLBs)
GOE 1/IN 5
GOE 0/IN 4
I/O 47
C7
I/O 46
I/O 0
I/O 45
A0
I/O 1
C6
C5
C4
C3
C2
C1
C0
I/O 44
I/O 2
I/O 3
A1
A2
A3
A4
A5
A6
A7
I/O 43
I/O 42
I/O 41
I/O 40
I/O 4
I/O 5
I/O 6
I/O 7
Global
Routing
Pool
I/O 39
I/O 38
I/O 37
I/O 36
I/O 8
I/O 9
(GRP)
I/O 10
I/O 11
I/O 35
I/O 34
I/O 33
I/O 32
I/O 12
I/O 13
I/O 14
I/O 15
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
B0
B1
B2
B3
B4
B5
B6
B7
Clock
Distribution
Network
TDI
Megablock
Output Routing Pool (ORP)
Input Bus
TDO
TMS
TCK
0139B/1024EA
The device also has 48 I/O cells, each of which is directly Clocks in the ispLSI 1024EA device are selected using
connected to an I/O pin. Each I/O cell can be individually theClockDistributionNetwork.Fourdedicatedclockpins
programmed to be a combinatorial input, registered in- (Y0, Y1, Y2 and Y3) are brought into the distribution
put, latched input, output or bi-directional network, and five clock outputs (CLK 0, CLK 1, CLK 2,
I/O pin with 3-state control. The signal levels are TTL IOCLK 0 and IOCLK 1) are provided to route clocks to the
compatible voltages and the output drivers can source 4 GLBs and I/O cells. The Clock Distribution Network can
mA or sink 8 mA. Each output can be programmed also be driven from a special clock GLB (C0 on the ispLSI
independently for fast or slow output slew rate to mini- 1024EA device). The logic of this GLB allows the user to
mize overall output switching noise. By connecting the create an internal clock from a combination of internal
VCCIO pin to a common 5V or 3.3V power supply, I/O signals within the device.
output levels can be matched to 5V or 3.3V-compatible
voltages.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 1024EA are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.
Eight GLBs, 16 I/O cells, dedicated inputs (if available)
and one ORP are connected together to make a
Megablock (Figure 1). The outputs of the eight GLBs are
connected to a set of 16 universal I/O cells by the ORP.
Each ispLSI 1024EA device contains three Megablocks.
The GRP has, as its inputs, the outputs from all of the
GLBsandallof theinputsfromthebi-directionalI/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
2
Specifications ispLSI 1024EA
Boundary Scan
Figure 2. Boundary Scan Waveforms and Timing Specifications
TMS
TDI
T
T
bth
btsu
T
T
T
btcp
btch
btcl
TCK
TDO
T
T
T
btoz
btvo
btco
Valid Data
Valid Data
T
btcpsu
T
btcph
Data to be
captured
Data Captured
T
T
T
btuoz
btuov
btuco
Data to be
driven out
Valid Data
Valid Data
Symbol
Parameter
Min
100
50
50
20
25
50
–
Max Units
t
TCK [BSCAN test] clock pulse width
TCK [BSCAN test] pulse width high
TCK [BSCAN test] pulse width low
TCK [BSCAN test] setup time
–
–
ns
ns
btcp
t
t
btch
–
ns
btcl
t
t
t
t
t
t
t
t
t
t
t
–
ns
btsu
bth
TCK [BSCAN test] hold time
–
ns
TCK [BSCAN test] rise and fall time
–
mV/ns
ns
rf
TAP controller falling edge of clock to valid output
25
25
25
–
btco
btoz
btvo
btcpsu
btcph
btuco
btuoz
btuov
TAP controller falling edge of clock to data output disable
TAP controller falling edge of clock to data output enable
BSCAN test Capture register setup time
–
ns
–
ns
40
25
–
ns
BSCAN test Capture register hold time
–
ns
BSCAN test Update reg, falling edge of clock to valid output
BSCAN test Update reg, falling edge of clock to output disable
BSCAN test Update reg, falling edge of clock to output enable
50
50
50
ns
–
ns
–
ns
3
Specifications ispLSI 1024EA
1
Absolute Maximum Ratings
Supply Voltage V .................................. -0.5 to +7.0V
cc
Input Voltage Applied........................ -2.5 to V +1.0V
CC
Off-State Output Voltage Applied ..... -2.5 to V +1.0V
CC
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T ) with Power Applied ... 150°C
J
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL
PARAMETER
Commercial
MIN.
4.75
4.75
3.0
MAX.
5.25
5.25
3.6
UNITS
VCC
Supply Voltage
V
V
V
V
V
T = 0°C to + 70°C
A
5V
Supply Voltage: Output Drivers
VCCIO
3.3V
Input Low Voltage
Input High Voltage
0
0.8
VIL
VIH
2.0
V +1
cc
Table 2-0005/1024EA
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL
PARAMETER
TYPICAL
UNITS
TEST CONDITIONS
VCC = 5.0V, VPIN = 2.0V
Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
(Commercial/Industrial)
8
pf
C1
10
pf
VCC= 5.0V, VPIN = 2.0V
Y0 Clock Capacitance
C2
Table 2-0006/1024EA
Erase/Reprogram Specifications
PARAMETER
MINIMUM
MAXIMUM
UNITS
Erase/Reprogram Cycles
10000
—
Cycles
Table 2-0008/1024EA
4
Specifications ispLSI 1024EA
Switching Test Conditions
Figure 3. Test Load
Input Pulse Levels
GND to 3.0V
1.5ns
Input Rise and Fall Time 10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
+ 5V
1.5V
1.5V
R
1
2
See Figure 3
Table 2-0003/1024EA
Device
Output
Test
Point
3-state levels are measured 0.5V from
steady-state active level.
R
C *
L
Output Load Conditions (see Figure 3)
TEST CONDITION
R1
470Ω
∞
R2
CL
*C includes Test Fixture and Probe Capacitance.
L
A
B
390Ω
390Ω
390Ω
35pF
35pF
35pF
0213a
Active High
Active Low
470Ω
Active High to Z
at VOH-0.5V
∞
390Ω
5pF
C
Active Low to Z
at VOL+0.5V
470Ω
390Ω
5pF
Table 2-0004/1024EA
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
PARAMETER
Output Low Voltage
CONDITION
MIN.
—
TYP.3 MAX. UNITS
IOL = 8 mA
—
—
0.4
V
V
VOL
I
I
OH = -2 mA, VCCIO = 3.0V
OH = -4 mA, VCCIO = 4.75V
2.4
—
Output High Voltage
VOH
2.4
—
—
—
V
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
0V ≤ VIN ≤ VIL (Max.)
—
-10
µA
I
I
IL
IH
(VCCIO - 0.2)V ≤ VIN ≤ VCCIO
—
—
—
—
—
—
—
10
10
µA
µA
V
CCIO ≤ VIN ≤ 5.25V
-200
-240
—
I
I
IL-PU
OS1
0V ≤ VIN ≤ VIL
µA
I/O Active Pull-Up Current
Output Short Circuit Current
—
—
VCCIO = 5.0V or 3.3V, VOUT = 0.5V
VIL = 0.0V, VIH = 3.0V
mA
mA
152
CC2, 4, 5
Operating Power Supply Current
I
f
TOGGLE = 1 MHz
Table 2-0007/1024EA
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using eight 16-bit counters.
3. Typical values are at VCC = 5V and TA = 25°C.
4. Unused inputs held at 0.0V.
5. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the
Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book CD-ROM to estimate maximum ICC
.
5
Specifications ispLSI 1024EA
External Timing Parameters
Over Recommended Operating Conditions
TEST 4
-200
-125
-100
DESCRIPTION1
UNITS
2
PARAMETER
#
COND.
MIN. MAX.
MIN. MAX. MIN. MAX.
A
A
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback 3
—
—
4.5
6.0
—
ns
ns
—
—
7.5
10.0
—
—
—
10.0
12.5
—
t
pd1
2
3
4
5
6
7
8
9
t
f
f
f
t
t
pd2
A
200
143
250
3.0
—
MHz
MHz
MHz
ns
125
100
167
4.5
—
100
77
max (Int.)
max (Ext.)
max (Tog.)
su1
1
—
—
—
A
Clock Frequency with External Feedback
(
)
—
—
—
tsu2 + tco1
1
Clock Frequency, Max. Toggle
(
)
—
—
125
6.0
—
—
twh + twl
GLB Reg. Setup Time before Clock,4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
—
—
—
3.5
ns
4.5
6.0
co1
—
—
—
—
A
0.0
3.5
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.0
5.5
—
—
—
0.0
7.0
—
—
—
t
t
t
t
t
t
t
t
t
t
t
t
t
h1
su2
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
4.0
—
5.5
—
7.0
—
co2
0.0
—
0.0
—
0.0
—
h2
5.5
—
10.0
—
13.5
—
r1
—
B
3.5
—
5.0
—
6.5
—
rw1
14 Input to Output Enable
7.0
7.0
4.5
4.5
—
12.0
12.0
7.0
7.0
—
15.0
15.0
9.0
9.0
—
ptoeen
ptoedis
goeen
goedis
wh
C
15 Input to Output Disable
—
—
—
B
16 Global OE Output Enable
—
—
—
C
17 Global OE Output Disable
—
—
—
—
—
—
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
2.0
2.0
3.0
3.0
3.0
4.0
4.0
3.5
—
—
—
wl
20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.0
21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 0.0
—
—
—
su3
—
—
ns
0.0
—
0.0
—
th3
Table 2-0030A/1024EA
v.2.5
1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
6
Specifications ispLSI 1024EA
1
Internal Timing Parameters
-200
-125
-100
2
PARAM.
#
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
22 I/O Register Bypass
23 I/O Latch Delay
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
0.3
4.0
—
—
—
0.4
4.0
—
0.3
4.0
—
24 I/O Register Setup Time before Clock
25 I/O Register Hold Time after Clock
26 I/O Register Clock to Out Delay
27 I/O Register Reset to Out Delay
28 Dedicated Input Delay
3.0
0.0
—
3.0
0.0
—
3.4
0.0
—
—
—
—
4.6
4.6
1.9
5.0
5.0
2.2
4.0
4.0
1.1
—
—
—
—
—
—
GRP
tgrp1
tgrp4
tgrp8
tgrp16
tgrp24
GLB
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
29 GRP Delay, 1 GLB Load
30 GRP Delay, 4 GLB Loads
31 GRP Delay, 8 GLB Loads
32 GRP Delay, 16 GLB Loads
33 GRP Delay, 24 GLB Loads
ns
ns
ns
ns
ns
—
—
—
—
—
—
—
—
—
—
1.7
1.9
2.1
2.5
2.9
—
—
—
—
—
2.1
2.3
2.5
2.9
3.3
1.3
1.5
1.7
2.1
2.5
34 4 ProductTerm Bypass Path Delay (Combinatorial)
35 4 Product Term Bypass Path Delay (Registered)
36 1 ProductTerm/XOR Path Delay
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
3.4
3.1
3.6
3.6
3.6
1.2
—
—
—
—
—
—
—
1.4
4.0
—
—
—
—
4.9
3.8
4.3
4.3
4.3
2.1
—
1.7
1.8
1.9
1.9
1.9
0.6
—
—
—
37 20 Product Term/XOR Path Delay
38 XOR Adjacent Path Delay 3
—
—
—
—
39 GLB Register Bypass Delay
—
—
40 GLB Register Setup Time before Clock
41 GLB Register Hold Time after Clock
42 GLB Register Clock to Output Delay
43 GLB Register Reset to Output Delay
44 GLB Product Term Reset to Register Delay
45 GLB Product Term Output Enable to I/O Cell Delay
46 GLB Product Term Clock Delay
0.2
1.0
—
0.3
3.5
—
—
—
—
1.4
4.9
3.8
5.7
1.7
5.0
4.5
7.2
4.7
0.3
1.4
3.8
2.5
2.1
2.5
0.0
—
—
—
—
—
—
1.5
—
2.8
—
3.9 3.5
47 GLB Feedback Delay
tgfb
0.3
—
ORP
torp
torpbp
48 ORP Delay
ns
ns
—
—
0.8
0.1
—
—
1.3
0.2
—
—
1.4
0.4
49 ORP Bypass Delay
Table 2-0036A/1024EA
v.2.5
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
Specifications ispLSI 1024EA
1
Internal Timing Parameters
-125
MIN. MAX. MIN. MAX.
-100
-200
PARAM.
#
DESCRIPTION
UNITS
MIN. MAX.
Outputs
tob
tsl
toen
todis
50 Output Buffer Delay
—
—
—
—
—
0.9
5.0
3.1
3.1
1.4
—
—
—
—
—
1.7
5.0
4.0
4.0
3.0
—
—
—
—
—
2.0
5.0
5.1
5.1
3.9
ns
ns
ns
ns
ns
51 Output Buffer Delay, Slew Limited Adder
52 I/O Cell OE to Output Enabled
53 I/O Cell OE to Output Disabled
54 Global OE
tgoe
Clocks
55 Clock Delay, Y0 to Global GLB Clock Line (Ref. clk)
56 Clock Delay, Y1 or Y2 to Global GLB Clock Line
57 Clock Delay, Clock GLB to Global GLB Clock Line
58 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
59 Clock Delay, Clock GLB to I/O Cell Global Clock Line
0.9
0.9
0.8
0.0
0.8
0.9
0.9
1.8
0.0
1.1 1.1
0.9 0.9
0.8 1.8
0.0 0.0
1.9 1.9
1.5 1.5
0.8 1.8
0.0 0.0
0.8 2.8
ns
ns
ns
ns
ns
tgy0
tgy1/2
tgcp
tioy2/3
tiocp
2.8 0.8 2.8
Global Reset
60 Global Reset to GLB and I/O Registers
—
0.0
—
2.1
—
5.1
ns
tgr
Table 2-0037A/1024EA
v.2.5
1. Internal Timing Parameters are not tested and are for reference only.
8
Specifications ispLSI 1024EA
ispLSI 1024EA Timing Model
I/O Cell
GRP
GLB
Feedback
#34 Comb 4 PT Bypass
ORP
I/O Cell
#47
Ded. In
#28
I/O Reg Bypass
#22
GRP4
#30
Reg 4 PT Bypass
#35
GLB Reg Bypass
#39
ORP Bypass
#49
#50, 51
I/O Pin
(Input)
I/O Pin
(Output)
Input
Register
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
GRP Loading
Delay
Q
D
#52, 53
RST
D
Q
#48
#36 - 38
#60
#29, 31 - 33
#60
#23 - 27
RST
Reset
#40 - 43
Clock
Control
PTs
RE
OE
CK
Distribution
0491/1032EA
Y1,2,3
#56 - 59
#44 - 46
#55
#54
Y0
GOE 0,1
Derivations of tsu, th and t
co from the Product Term Clock1
tsu
= Logic + Reg su - Clock (min)
= ( iobp + grp4 + 20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min))
t
t
t
= (#22 + #30 + #37) + (#40) - (#22 + #30 + #46)
0.6 = (0.3 + 1.5 + 1.9) + (0.2) - (0.3 + 1.5 + 1.5)
th
= Clock (max) + Reg h - Logic
= (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
1.6 = (0.3 + 1.5 + 2.5) + (1.0) - (0.3 + 1.5 + 1.9)
tco
= Clock (max) + Reg co + Output
= (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
= (#22 + #30 + #46) + (#42) + (#48 + #50)
= (0.3 + 1.5 + 2.5) + (1.4) + (0.8 + 0.9)
7.4
1
Derivations of tsu, th and tco from the Clock GLB
t
t
t
su
= Logic + Reg (setup) - Clock (min)
= ( iobp + grp4 + 20ptxor) + ( gsu) - (tgy0(min) + tgco + tgcp(min))
= (#22 + #30 + #37) + (#40) - (#55 + #42 + #57)
t
t
t
t
= (0.3 + 1.5 + 1.9) + (0.2) - (0.9 + 1.4 + 0.8)
0.8
1.4
7.2
h
= Clock (max) + Reg (hold) - Logic
= (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#55 + #42 + #57) + (#41) - (#22 + #30 + #37)
= (0.9 + 1.4 + 1.8) + (1.0) - (0.3 + 1.5 + 1.9)
co
= Clock (max) + Reg (clock-to-out) + Output
= (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
= (#55 + #42 + #57) + (#42) + (#48 + #50)
= (0.9 + 1.4 + 1.8) + (1.4) + (0.8 + 0.9)
1. Calculations are based upon timing specifications for the ispLSI 1024EA-200.
Table 2-0042a/1024EA
v.2.5
9
Specifications ispLSI 1024EA
Maximum GRP Delay vs GLB Loads
4
ispLSI 1024EA-100
ispLSI 1024EA-125
ispLSI 1024EA-200
3
2
1
1
4
8
16
24
GLB Load
GRP/GLB/1024EA
Power Consumption
Power consumption in the ispLSI 1024EA device de- used. Figure 4 shows the relationship between power
pends on two primary factors: the speed at which the and operating speed.
device is operating, and the number of product terms
Figure 4. Typical Device Power Consumption vs fmax
260
ispLSI 1024EA
240
220
200
180
160
140
120
100
0
50
100
150
200
250
fmax (MHz)
Notes: Configuration of eight 16-bit counters
Typical current at 5V, 25°C
Icc can be estimated for the ispLSI 1024EA using the following equation:
Icc = 17mA + (# of PTs * .726) + (# of nets * Max Freq * .0043)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The Icc estimate is based on typical conditions (Vcc = 5.0V, room temperature) and an assumption of four GLB
loads on average exists. These values are for estimates only. Since the value of Icc is sensitive to operating
conditions and the program in the device, the actual Icc should be verified.
0127/1024EA
10
Specifications ispLSI 1024EA
Pin Description
TQFP PIN
NUMBERS
NAME
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
19, 20, 21, 22,
23, 28, 29, 30,
31, 32, 33, 34,
I/O 12 - I/O 15 42, 43, 44, 45,
I/O 16 - I/O 19 46, 47, 48, 53,
I/O 20 - I/O 23 54, 55, 56, 57,
I/O 24 - I/O 27 69, 70, 71, 72,
I/O 28 - I/O 31 73, 78, 79, 80,
I/O 32 - I/O 35 81, 82, 83, 84,
I/O 36 - I/O 39 92, 93, 94, 95,
I/O 40 - I/O 43 96, 97, 98, 3,
I/O 44 - I/O 47 4,
5,
6,
7
GOE 0/IN 41
This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be
used as a dedicated input pin.
91
GOE 1/IN 51
This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be
used as a dedicated input pin.
8
Input - Functions as an input pin to load programming data into the device and also used as one of
the two control pins for the ispJTAG state machine.
TDI
18
68
Input - Controls the operation of the ISP state machine.
TMS
Output - Functions as an output pin to read serial shift register data.
Input - Functions as a clock pin for the Serial Shift Register.
TDO
TCK
35
58
Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device.
RESET
17
9
Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on
the device.
Y0
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any GLB on the device.
Y1
Y2
Y3
67
60
59
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any GLB and/or any I/O cell on the device.
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any I/O cell on the device.
GND
VCC
14, 15, 36, 37, Ground (GND)
61, 62, 89, 90
10, 11, 40, 41, Vcc
65, 66, 85, 86
16
VCCIO
Supply voltage for output drivers, 5V or 3.3V.
No Connect
2
NC
1,
2,
12, 13,
24, 25, 26, 27,
38, 39, 49, 50,
51, 52, 63, 64,
74, 75, 76, 77,
87, 88, 99, 100
Table 2-0002A/1024EA
1. Pins have dual function capability which is software selectable.
2. NC pins are not to be connected to any active signals, Vcc or GND.
11
Specifications ispLSI 1024EA
Pin Configurations
ispLSI 1024EA 100-Pin TQFP Pinout Diagram
2NC
2NC
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC2
NC2
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
1GOE 1/IN 5
Y0
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
TMS
Y1
9
VCC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VCC
VCC
NC2
VCC
2NC
ispLSI 1024EA
2NC
NC2
GND
GND
VCCIO
RESET
TDI
GND
GND
Y2
Top View
Y3
TCK
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
NC2
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
2NC
2NC
NC2
1. Pins have dual function capability which is software selectable.
2. NC pins are not to be connected to any active signal, VCC or GND.
100-TQFP/1024EA
12
Specifications ispLSI 1024EA
Part Number Description
ispLSI
1024EA - XXX
X
XXXX X
Device Family
Grade
Blank = Commercial
Package
T100 = 100-Pin TQFP
Device Number
Power
L = Low
Speed
200 = 200 MHz
125 = 125 MHz
100 = 100 MHz
f
f
f
max
max
max
0212/1024EA
ispLSI 1024EA Ordering Information
COMMERCIAL
FAMILY
ispLSI
fmax (MHz)
200
tpd (ns)
4.5
ORDERING NUMBER
PACKAGE
100-Pin TQFP
100-Pin TQFP
100-Pin TQFP
ispLSI 1024EA-200LT100
ispLSI 1024EA-125LT100
ispLSI 1024EA-100LT100
125
7.5
100
10
Table 2-0041A/1024EA
13
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