ISPLSI1048C_技术文档

®

ispLSI 1048C/883

In-System Programmable High Density PLD

Features

Functional Block Diagram

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 8000 PLD Gates

— 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output

Enables

— 288 Registers

— High-Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— Security Cell Prevents Unauthorized Copying

Output Routing Pool

F7 F6 F5 F4 F3 F2 F1 F0

E7 E6 E5 E4 E3 E2 E1 E0

A0

A1

A2

A3

A4

A5

A6

A7

D7

D6

D5

D4

D3

D2

D1

D0

D

Q

Logic

Array

Global Routing Pool (GRP)

GLB

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

C0 C1 C2 C3 C4 C5 C6 C7

Output Routing Pool

CLK

— fmax = 50 MHz Maximum Operating Frequency

— tpd = 22 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile E²CMOSTechnology

0139G1A-isp

Description

— 100% Tested at Time of Manufacture

• IN-SYSTEM PROGRAMMABLE

The ispLSI 1048C/883 is a High-Density Programmable

Logic Device processed in full compliance to MIL-STD-

883. This military grade device contains 288 Registers,

96 Universal I/O pins, 12 Dedicated Input pins, two

Global Output Enables (GOE), four Dedicated Clock

Input pins and a Global Routing Pool (GRP). The GRP

provides complete interconnectivity between all of these

elements. The ispLSI 1048C/883 features 5-Volt in-

system programming and in-system diagnostic

capabilities. It is the first device which offers non-volatile

reprogrammability of the logic, and the interconnect to

provide truly reconfigurable systems. Compared to the

ispLSI 1048, the ispLSI 1048C/883 offers two additional

dedicatedinputsandtwonewGlobalOutputEnablepins.

— In-System Programmable™ (ISP™) 5-Volt Only

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• COMBINES EASE OF USE AND THE FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEX-

IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

The basic unit of logic on the ispLSI 1048C/883 device is

theGenericLogicBlock(GLB).TheGLBsarelabeledA0,

A1 .. F7 in figure 1. There are a total of 48 GLBs in the

ispLSI 1048C/883 devices. Each GLB has 18 inputs, a

programmable AND/OR/XOR array, and four outputs

which can be configured to be either combinatorial or

registered. Inputs to the GLB come from the GRP and

dedicated inputs. All of the GLB outputs are brought back

into the GRP so that they can be connected to the inputs

of any other GLB on the device.

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

September 2000

1048CMIL_01

1

Specifications ispLSI 1048C/883

Functional Block Diagram

Figure 1. ispLSI 1048C/883 Functional Block Diagram

I/O I/O I/OI/O

95 94 93 92

I/O I/OI/OI/O

91 90 89 88

I/O I/O I/O I/O

87 86 85 84

I/O I/O I/O I/O

83 82 81 80

IN IN

11 10

I/O I/O I/OI/O

79 78 77 76

I/O I/OI/OI/O

75 74 73 72

I/O I/O I/O I/O

71 70 69 68

I/O I/O I/O I/O

67 66 65 64

IN IN

9

8

RESET

GOE0

Input Bus

Output Routing Pool (ORP)

Input Bus

Output Routing Pool (ORP)

Generic

Logic Blocks

(GLBs)

GOE1

IN 7

IN 6

F7

F6

F5

F4

F3

F2

F1

F0

E7

E6

E5

E4

E3

E2

E1

E0

I/O 63

I/O 62

I/O 61

I/O 60

D7

D6

D5

D4

I/O 0

I/O 1

I/O 2

I/O 3

A0

A1

A2

A3

I/O 59

I/O 58

I/O 57

I/O 4

I/O 5

I/O 6

I/O 7

Global

Routing

Pool

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

D3

D2

D1

D0

I/O 8

A4

A5

A6

A7

(GRP)

I/O 9

I/O 10

I/O 11

I/O 51

I/O 50

I/O 49

I/O 48

I/O 12

I/O 13

I/O 14

I/O 15

SDI/IN 0

CLK 0

B0

B1

B2

B3

B4

B5

B6

B7

C0

C1

C2

C3

C4

C5

C6

C7

CLK 1

CLK 2

MODE/IN 1

Clock

Distribution

Network

IOCLK 0

IOCLK 1

Output Routing Pool (ORP)

Input Bus

Output Routing Pool (ORP)

Input Bus

Megablock

ispEN

IN2

SDO/ I/O I/O I/O I/O

IN3

16 17 18 19

I/O I/O I/O I/O

20 21 22 23

I/O I/O I/O I/O

24 25 26 27

I/O I/O I/O I/O

28 29 30 31

IN SCLK/ I/O I/O I/O I/O

IN 5 32 33 34 35

I/O I/O I/O I/O

36 37 38 39

I/O I/O I/O I/O

40 41 42 43

I/O I/O I/O I/O

44 45 46 47

Y

0

Y

1

Y

2

Y

3

4

0139F(2)-48B-isp

The device also has a 96 I/O cells, each of which is The GRP has, as its inputs, the outputs from all of the

directly connected to an I/O pin. Each I/O cell can be GLBs and all of the inputs from the bi-directional I/O cells.

individually programmed to be a combinatorial input, All of these signals are made available to the inputs of the

registered input, latched input, output or bi-directional GLBs. Delays through the GRP have been equalized to

I/O pin with 3-state control. Additionally, all outputs have minimize timing skew.

selectable polarity, active high or active low. The signal

Clocks in the ispLSI 1048C/883 device are selected

voltagelevelsareTTL-compatible, andtheoutputdrivers

using the Clock Distribution Network. Four dedicated

can source 4 mA or sink 8 mA.

clock pins (Y0, Y1, Y2 and Y3) are brought into the

Eight GLBs, 16 I/O cells, two dedicated inputs and one distribution network, and five clock outputs (CLK 0, CLK

ORP are connected together to make a Megablock as 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route

shown in figure 1. The outputs of the eight GLBs are clocks to the GLBs and I/O cells. The Clock Distribution

connected to a set of 16 universal I/O cells by the ORP. Network can also be driven from a special clock GLB (D0

Each ispLSI 1048C/883 device contains six Megablocks. on the ispLSI 1048C/883 device). The logic of this GLB

allows the user to create an internal clock from a combi-

nation of internal signals.

2

Specifications ispLSI 1048C/883

1

Absolute Maximum Ratings

Supply Voltage V ...................................-0.5 to +7.0V

cc

Input Voltage Applied........................ -2.5 to V +1.0V

CC

Off-State Output Voltage Applied ..... -2.5 to V +1.0V

CC

Storage Temperature................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (T ) with Power Applied ... 150°C

J

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional

operation of the device at these or at any other conditions above those indicated in the operational sections of this specification

is not implied (while programming, follow the programming specifications).

DC Recommended Operating Conditions

SYMBOL

PARAMETER

MIN.

MAX.

5.5

UNITS

Supply Voltage

Input Low Voltage

Input High Voltage

Military/883

T_C= -55°C to +125°C

V

CC

IL

4.5

0

V

0.8

IH

2.0

Vcc + 1

0005A mil.eps

Capacitance (T_A=25^oC, f=1.0 MHz)

1

SYMBOL PARAMETER

MAXIMUM

UNITS

TEST CONDITIONS

_CC=5.0V, V_IN=2.0V

Dedicated Input Capacitance

10

pf

V

C₁

C₂

I/O and Clock Capacitance

V_CC=5.0V, V_I/O, V_Y=2.0V

Table 2- 0006mil

1. Characterized but not 100% tested.

Data Retention Specifications

PARAMETER

Data Retention

MINIMUM

20

MAXIMUM

UNITS

—

Years

Erase/Reprogram Cycles

10000

Cycles

Table 2- 0008B

3

Specifications ispLSI 1048C/883

Switching Test Conditions

Input Pulse Levels

GND to 3.0V

Figure 2. Test Load

Input Rise and Fall Time

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

≤ 3ns 10% to 90%

1.5V

+ 5V

1.5V

R

1

See figure 2

Device

Output

Test

Point

3-state levels are measured 0.5V from steady-state

active level.

Table 2- 0003

R

2

C *

L

Output Load Conditions (see figure 2)

*

C includes Test Fixture and Probe Capacitance.

L

Test Condition

R1

R2

CL

A

470Ω

390Ω

35pF

5pF

B

Active High

Active Low

∞

470Ω

Active High to Z

at V_OH- 0.5V

∞

C

Active Low to Z

470Ω

390Ω

5pF

at V_OL+ 0.5V

Table 2- 0004A

DC Electrical Characteristics

Over Recommended Operating Conditions

3

CONDITION

I_OL=8 mA

PARAMETER

Output Low Voltage

MIN. TYP.

MAX.

0.4

UNITS

SYMBOL

VOL

VOH

IIL

IIH

IIL-isp

IIL-PU

–

2.4

–

V

I_OH=-4 mA

Output High Voltage

–

0V ≤ V_IN≤ V_IL(MAX.)

3.5V ≤ V_IN≤ V_CC

Input or I/O Low Leakage Current

Input or I/O High Leakage Current

isp Input Low Leakage Current

I/O Active Pull-Up Current

-10

10

µA

–

µA

mA

0V ≤ V_IN≤ V_IL(MAX.)

0V ≤ V_IN≤ V_IL

–

-150

–

1

V_CC= 5V, V_OUT= 0.5V

V_IL= 0.5V, V_IH= 3.0V

f_TOGGLE= 1 MHz

Output Short Circuit Current

Operating Power Supply Current

–

IOS

ICC

-200

260

2,4

–

165

1. One output at a time for a maximum duration of one second. V_out= 0.5V was selected to avoid test problems by tester ground

degradation. Characterized but not 100% tested.

2. Measured using twelve 16-bit counters.

3. Typical values are at V_CC= 5V and T_A= 25^oC.

4. Maximum I_CCvaries widely with specific device configuration and operating frequency. Refer to the Power Consumption sec-

tion of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum

I_CC.

0007A-48C mil

4

Specifications ispLSI 1048C/883

External Timing Parameters

Over Recommended Operating Conditions

-50

4

2

DESCRIPTION¹

TEST

PARAMETER

#

UNITS

COND.

MIN. MAX.

t

f

t

pd1

1

Data Propagation Delay, 4PT bypass, ORP bypass

Data Propagation Delay

22.0

26.0

–

ns

A

–

A

–

A

–

B

C

B

C

–

2

3

4

5

6

7

8

9

pd2

Clock Frequency with Internal Feedback³

MHz

ns

50.3

34.5

58.8

13.0

–

max (Int.)

max (Ext.)

max (Tog.)

su1

1

(

)

Clock Frequency with External Feedback

–

tsu2 + tco1

1

(

)

Clock Frequency, Max Toggle

–

twh + tw1

GLB Reg. Setup Time before Clock, 4PT bypass

GLB Reg. Clock to Output Delay, ORP bypass

GLB Reg. Hold Time after Clock, 4 PT bypass

GLB Reg. Setup Time before Clock

–

14.0

–

ns

co1

ns

0

h1

–

ns

15.0

–

su2

10 GLB Reg. Clock to Output Delay

11 GLB Reg. Hold Time after Clock

12 Ext. Reset Pin to Output Delay

13 Ext. Reset Pulse Duration

16.0

–

ns

co2

ns

0

h2

20.5

–

ns

–

r1

ns

13.5

–

rw1

14 Input to Output Enable

27.5

20.5

–

ns

ptoeen

ptoedis

goeen

goedis

wh

15 Input to Output Disable

ns

–

16 Global OE Output Enable

ns

–

17 Global OE Output Disable

ns

–

20 Ext. Sync. Clock Pulse Duration, High

21 Ext. Sync. Clock Pulse Duration, Low

ns

8.5

3.0

9.0

–

ns

wl

22 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)

23 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)

–

ns

su3

–

ns

h3

Table 2- 0030-48C/50 mil

1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-Bit counter using GRP feedback.

4. Reference Switching Test Conditions section.

5

Specifications ispLSI 1048C/883

1

Internal Timing Parameters

-50

2

PARAMETER

DESCRIPTION

UNITS

#

MIN. MAX.

Inputs

24 I/O Register Bypass

–

4.3

5.5

–

ns

t

iobp

iolat

iosu

ioh

25 I/O Latch Delay

26 I/O Register Setup Time before Clock

27 I/O Register Hold Time after Clock

28 I/O Register Clock to Out Delay

29 I/O Register Reset to Out Delay

30 Dedicated Input Delay

9.1

0.3

–

4.6

5.1

7.4

ioco

ior

–

din

GRP

31 GRP Delay, 1 GLB Load

32 GRP Delay, 4 GLB Loads

33 GRP Delay, 8 GLB Loads

34 GRP Delay, 16 GLB Loads

35 GRP Delay, 48 GLB Loads

t

grp1

–

6.2

6.7

ns

grp4

grp8

8.0

grp16

grp48

10.5

22.7

GLB

36 4 Product Term Bypass Path Delay

37 1 Product Term/XOR Path Delay

38 20 Product Term/XOR Path Delay

39 XOR Adjacent Path Delay³

t

4ptbp

1ptxor

20ptxor

xoradj

gbp

–

5.5

6.7

7.5

8.9

1.2

–

ns

–

40 GLB Register Bypass Delay

–

41 GLB Register Setup Time before Clock

42 GLB Register Hold Time after Clock

43 GLB Register Clock to Output Delay

44 GLB Register Reset to Output Delay

45 GLB Product Term Reset to Register Delay

46 GLB Product Term Output Enable to I/O Cell Delay

47 GLB Product Term Clock Delay

gsu

3.9

7.3

–

gh

–

gco

2.3

2.8

11.1

9.6

gro

–

ptre

–

ptoe

ptck

–

3.4 8.2

ORP

48 ORP Delay

t

orp

–

3.4

1.4

ns

49 ORP Bypass Delay

torpbp

Table 2- 0036-48C/50MIL

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

6

Specifications ispLSI 1048C/883

1

Internal Timing Parameters

-50

2

PARAMETER

DESCRIPTION

UNITS

#

MIN. MAX.

Outputs

–

2.9

6.9

ns

t

ob

50

51

52

53

Output Buffer Delay

oen

odis

goe

I/O Cell OE to Output Enabled

I/O Cell OE to Output Disabled

Global OE

6.9

13.6

Clocks

ns

7.4

8.7

t

gy0

54

55

56

57

58

Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)

Clock Delay, Y1 or Y2 to Global GLB Clock Line

Clock Delay, Clock GLB to Global GLB Clock Line

Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line

Clock Delay, Clock GLB to I/O Cell Global Clock Line

7.4

6.1

gy1/2

gcp

2.6 7.6

6.1 8.7

ioy2/3

iocp

7.6

2.6

Global Reset

11.4

ns

tgr

59

Global Reset to GLB and I/O Registers

–

Table 2- 0037-48C/50mil

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

7

Specifications ispLSI 1048C/883

ispLSI 1048C/883 Timing Model

I/O Cell

GRP

GLB

ORP

I/O Cell

Feedback

Ded. In

#30

I/O Reg Bypass

#24

GRP 4

#32

4 PT Bypass

#36

GLB Reg Bypass

#40

ORP Bypass

#49

#50

I/O Pin

(Input)

I/O Pin

(Output)

#51, 52

Input

Register

GRP

Loading

Delay

20 PT

XOR Delays

GLB Reg

Delay

ORP

Delay

Q

D

RST

D

Q

#48

#37, 38, 39

#59

#31, 33,

34, 35

#59

#25 - 29

RST

#

41, 42,

Reset

43, 44

Clock

Control

PTs

RE

OE

CK

Distribution

Y1,2,3

#55, 56,

57, 58

#45, 46,

47

#54

#53

Y0

GOE0, 1

0491A/48

1

Derivations of tsu, th and tco from the Product Term Clock

tsu

=

Logic + Reg su - Clock (min)

= (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min))

= (#24 + #32 + #38) + (#41) - (#24 + #32 + #47)

8.0 ns= (4.3 + 6.7 + 7.5) + (3.9) - (4.3 + 6.7 + 3.4)

th

= Clock (max) + Reg h - Logic

= (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)

= (#24 + #32 + #47) + (#42) - (#24 + #32 + #38 )

8.0 ns= (4.3 + 6.7 + 8.2) + (7.3) - (4.3 + 6.7 + 7.5)

tco

= Clock (max) + Reg co + Output

= (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)

= (#24 + #32 + #47) + (#43) + (#48 + #50)

32.8 ns = (4.3 + 6.7 + 8.2) + (7.3) + (3.4 + 2.9)

1

Derivations of tsu, th and tco from the Clock GLB

tsu

= Logic + Reg su - Clock (min)

= (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min))

= (#24 + #32 + #38) + (#41) - (#54 + #43 + #56)

10.1 ns= (4.3 + 6.7 + 7.5) + (3.9) - (7.4 + 2.3 + 2.6)

th

= Clock (max) + Reg h - Logic

= (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)

= (#54 + #43 + #56) + (#42) - (#24 + #32 + #38)

6.1 ns= (7.4 + 2.3 + 7.6) + (7.3) - (4.3 + 6.7 + 7.5)

tco

= Clock (max) + Reg co + Output

= (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)

= (#54 + #43 + #56) + (#43) + (#48 + #50)

30.9 ns = (7.4 + 2.3 + 7.6) + (7.3) + (3.4 + 2.9)

1. Calculations are based upon timing specifications for the ispLSI 1048C-50

8

Specifications ispLSI 1048C/883

Maximum GRP Delay vs GLB Loads

11

10

9

ispLSI 1048C-50

8

7

6

5

4

3

1

4

8

12

16

GLB Loads

0126A-48C-80-ispmil

Power Consumption

Power consumption in the ispLSI 1048C/883 device used. Figure 3 shows the relationship between power

depends on two primary factors: the speed at which the and operating speed.

device is operating, and the number of Product Terms

Figure 3. Typical Device Power Consumption vs fmax

250

ispLSI 1048C

200

150

100

50

0

10

20 30

40 50 60 70 80

max (MHz)

f

Notes: Configuration of Twelve 16-bit Counters

Typical Current at 5V, 25˚C

I

can be estimated for the ispLSI 1048C using the following equation:

= 73 + (# of PTs * 0.23) + (# of nets * Max. freq * 0.010) where:

CC

# of PTs = Number of Product Terms used in design

# of nets = Number of Signals used in device

Max. freq = Highest Clock Frequency to the device

The I

CC

estimate is based on typical conditions (V = 5.0V, room temperature) and an assumption of 2 GLB

CC

loads on average exists. These values are for estimates only. Since the value of I

CC

is sensitive to operating

conditions and the program in the device, the actual I

CC

should be verified.

0127A-48C-80-isp

9

Specifications ispLSI 1048C/883

Pin Description

NAME

CPGA PIN NUMBERS

DESCRIPTION

I/O 0 - I/O 5

J2, J3, K1, L1, K2, M1, Input/Output Pins - These are the general purpose I/O pins used

L2, K3, N1, M2, L3, P1, by the logic array.

M3, P2, N3, M4, P3, N4,

P4, M5, N5, P5, M6, N6,

N9, M9, P10, P11, N10, P12,

N11, M10, P13, N12, M11, P14,

M12, N14, M13, L12, M14, L13,

L14, K12, K13, K14, J12, J13,

F13, F12, E14, D14, E13, C14,

D13, E12, B14, C13, D12, A14,

C12, A13, B12, C11, A12, B11,

A11, C10, B10, A10, C9, B9,

B6, C6, A5, A4, B5, A3,

B4, C5, A2, B3, C4, A1,

C3, B1, C2, D3, C1, D2,

I/O 6 - I/O 11

I/O 12 - I/O 17

I/O 18 - I/O 23

I/O 24 - I/O 29

I/O 30 - I/O 35

I/O 36 - I/O 41

I/O 42 - I/O 47

I/O 48 - I/O 53

I/O 54 - I/O 59

I/O 60 - I/O 65

I/O 66 - I/O 71

I/O 72 - I/O 77

I/O 78 - I/O 83

I/O 84 - I/O 89

I/O 90 - I/O 95

D1, E3, E2, E1, F3,

N13, B7,

F2

Global output enables for all I/Os.

Dedicated input pins to the device.

GOE0, GOE1

IN 2, IN 4

P7,

P9

IN 6 - IN 11

F14, A9, A8, A7, A6,

F1

ispEN

H2

Input – Dedicated in-system programming enable input pin. This

pin is brought low to enable the programming mode. The MODE,

SDI, SDO and SCLK options become active.

SDI/IN 0¹

J1

Input – This pin performs two functions. It is a dedicated input pin

when ispEN is logic high. When ispEN is logic low, it functions as

an input pin to load programming data into the device. SDI/IN 0

alsoisusedasoneofthetwocontrolpinsfortheispstatemachine.

MODE/IN 1¹

P6

Input – This pin performs two functions. It is a dedicated input pin

when ispEN is logic high. When ispEN is logic low, it functions as

a pin to control the operation of the isp state machine.

SDO/IN 3¹

SCLK/IN 5¹

P8

Input/Output – This pin performs two functions. It is a dedicated

input pin when ispEN is logic high. When ispEN is logic low, it

functions as an output pin to read serial shift register data.

J14

Input – This pin performs two functions. It is a dedicated input

when ispEN is logic high. When ispEN is logic low, it functions as

a clock pin for the Serial Shift Register.

Active Low (0) Reset pin which resets all of the GLB and I/O

registers in the device.

RESET

Y0

H1

G1

Dedicated Clock input. This clock input is connected to one of the

clock inputs of all of the GLBs on the device.

Y1

G14

Dedicated clock input. This clock input is brought into the clock

distribution network, and can optionally be routed to any GLB on

the device.

Dedicated clock input. This clock input is brought into the clock

distributionnetwork, andcanoptionallyberoutedto anyGLBand/

or any I/O cell on the device.

Y2

Y3

H13

H14

Dedicated clock input. This clock input is brought into the clock

distributionnetwork, andcanoptionallyberoutedtoanyI/Ocellon

the device.

GND

VCC

B2, B8, B13, C8, H3, H12, Ground (GND)

M8, N2, N8

C7, G2, G3, G12, G13, M7, V_CC

N7

Table 2- 0002C-48C/CPGA

1. Pins have dual function capability.

10

Specifications ispLSI 1048C/883

Pin Configuration

ispLSI 1048C/883 133-Pin CPGA Pinout Diagram

PIN A1

14

13

12

11

10

9

8

7

6

5

4

3

2

1

A

I/O59

I/O61

I/O64

I/O66

I/O69

IN7

IN8

IN9

IN10

I/O74

I/O75

I/O77

I/O80

I/O83

I/O56

I/O53

GND

I/O62

I/O60

I/O65

I/O63

I/O68

I/O67

I/O71

I/O70

GND

GOE1

Vcc

I/O72

I/O73

I/O76

I/O79

I/O78

I/O82

I/O81

GND

I/O86

I/O89

I/O85

I/O88

I/O90

B

C

D

E

F

I/O57

I/O84

I/O87

I/O58

I/O51

I/O54

I/O52

I/O48

INDEX

I/O50

IN6

I/O55

I/O49

I/O91

I/O94

Vcc

I/O92

I/O95

Vcc

I/O93

IN11

Y0

G

H

Y1

Vcc

Y2

Vcc

ispLSI 1048C/883

Bottom View

Y3

GND

RESET

SDI/

ispEN

SCLK/

I/O47

I/O44

I/O46

I/O43

I/O1

I/O7

I/O0

I/O4

I/O6

J

K

L

1

IN0

IN5

I/O45

I/O42

I/O2

I/O3

I/O10

I/O39

I/O41

I/O36

I/O33

I/O29

I/O34

I/O30

I/O27

I/O22

I/O40

I/O37

I/O35

I/O38

GOE0

I/O32

I/O31

I/O28

I/O26

I/O25

I/O24

IN4

GND

I/O19

I/O20

I/O21

I/O15

I/O17

I/O18

I/O12

I/O14

I/O16

I/O9

GND

I/O13

I/O5

I/O8

M

N

P

Vcc

I/O23

SDO/

MODE/

I/O11

IN2

1

IN3

IN1

133 CPGA Pinout.eps

1. Pins have dual function capability.

11

Specifications ispLSI 1048C/883

Part Number Description

–

1048C XX

X

ispLSI

Device Family

Grade

/883 = 883 Military Process

Device Number

Speed

Package

G = CPGA

50 = 50 MHz fmax

Power

L = Low

0212-80B-isp1048C mil

Ordering Information

MILITARY

Ordering Number

ispLSI 1048C-50LG/883

Family

ispLSI

fmax (MHz) tpd (ns)

50 22

Package

SMD Number

5962-9558701MXC

133-Pin CPGA

Table 2- 0041A-48C-ispmil

12


型号：	ISPLSI1048C
厂家：	LATTICE SEMICONDUCTOR
描述：	In-System Programmable High Density PLD 在系统可编程高密度PLD
文件：	总12页 (文件大小：181K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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