ISPLSI1048E50LT_技术文档

Lead-

ee

Fr

Package

®

ispLSI 1048E

Options

vailable!

A

In-System Programmable High Density PLD

Features

Functional Block Diagram

• HIGH DENSITY PROGRAMMABLE LOGIC

— 8,000 PLD Gates

Output Routing Pool

F7 F6 F5 F4 F3 F2 F1 F0

E7 E6 E5 E4 E3 E2 E1 E0

— 96 I/O Pins, Twelve Dedicated Inputs

— 288 Registers

A0

A1

A2

A3

A4

A5

A6

A7

D7

D6

D5

D4

D3

D2

D1

D0

D

Q

— High-Speed Global Interconnects

Logic

Array

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

Global Routing Pool (GRP)

GLB

— Small Logic Block Size for Random Logic

— Functionally and Pin-out Compatible to ispLSI 1048C

B0 B1 B2 B3 B4 B5 B6 B7

Output Routing Pool

C0 C1 C2 C3 C4 C5 C6 C7

Output Routing Pool

CLK

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 125 MHz Maximum Operating Frequency

0139G1A-isp

— tpd = 7.5 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Eraseable and Reprogrammable

— Non-Volatile

Description

The ispLSI 1048E is a High Density Programmable Logic

Device containing 288 Registers, 96 Universal I/O pins,

12 Dedicated Input pins, four Dedicated Clock Input pins,

twodedicatedGlobalOEinputpins,andaGlobalRouting

Pool(GRP).TheGRPprovidescompleteinterconnectivity

between all of these elements. The ispLSI 1048E offers

5Vnon-volatilein-systemprogrammabilityofthelogic,as

well as the interconnect to provide truly reconfigurable

systems. A functional superset of the ispLSI 1048 archi-

tecture, the ispLSI 1048E device adds two new global

output enable pins and two additional dedicated inputs.

— 100% Tested at Time of Manufacture

• IN-SYSTEM PROGRAMMABLE

— In-System Programmable (ISP™) 5V Only

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

The basic unit of logic on the ispLSI 1048E device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1…F7(seeFigure1). Thereareatotalof48GLBsinthe

ispLSI 1048E device. Each GLB has 18 inputs, a pro-

grammableAND/OR/ExclusiveORarray,andfouroutputs

which can be configured to be either combinatorial or

registered. Inputs to the GLB come from the GRP and

dedicated inputs. All of the GLB outputs are brought back

into the GRP so that they can be connected to the inputs

of any other GLB on the device.

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

— Lead-Free Package Options

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

August 2006

1048e_12

1

Specifications ispLSI 1048E

Functional Block Diagram

Figure 1. ispLSI 1048E Functional Block Diagram

I/O I/O I/OI/O

95 94 93 92

I/O I/OI/OI/O

91 90 89 88

I/O I/O I/O I/O

87 86 85 84

I/O I/O I/O I/O

83 82 81 80

IN IN

11 10

I/O I/O I/OI/O

79 78 77 76

I/O I/OI/OI/O

75 74 73 72

I/O I/O I/O I/O

71 70 69 68

I/O I/O I/O I/O

67 66 65 64

IN IN

9

8

RESET

Input Bus

Output Routing Pool (ORP)

Input Bus

Output Routing Pool (ORP)

GOE 0

Generic

Logic Blocks

(GLBs)

GOE 1

IN 7

IN 6

F7

F6

F5

F4

F3

F2

F1

F0

E7

E6

E5

E4

E3

E2

E1

E0

I/O 63

I/O 62

I/O 61

I/O 60

D7

D6

D5

D4

I/O 0

I/O 1

I/O 2

I/O 3

A0

A1

A2

A3

I/O 59

I/O 58

I/O 57

I/O 4

I/O 5

I/O 6

I/O 7

Global

Routing

Pool

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

D3

D2

D1

D0

I/O 8

A4

A5

A6

A7

(GRP)

I/O 9

I/O 10

I/O 11

I/O 51

I/O 50

I/O 49

I/O 48

I/O 12

I/O 13

I/O 14

I/O 15

SDI/IN 0

MODE/IN 1

CLK 0

CLK 1

CLK 2

IOCLK 0

IOCLK 1

B0

B1

B2

B3

B4

B5

B6

B7

C0

C1

C2

C3

C4

C5

C6

C7

Clock

Distribution

Network

Output Routing Pool (ORP)

Input Bus

Output Routing Pool (ORP)

Input Bus

Megablock

ispEN

IN 2 SDO/ I/O I/O I/O I/O

IN 3

16 17 18 19

I/O I/O I/O I/O

20 21 22 23

I/O I/O I/O I/O

24 25 26 27

I/O I/O I/O I/O

28 29 30 31

IN SCLK/ I/O I/O I/O I/O

IN 5 32 33 34 35

I/O I/O I/O I/O

36 37 38 39

I/O I/O I/O I/O

40 41 42 43

I/O I/O I/O I/O

44 45 46 47

Y

0

Y

1

Y

2

Y

3

4

0139F(2)-48B-isp

The device also has 96 I/O cells, each of which is directly The GRP has, as its inputs, the outputs from all of the

connected to an I/O pin. Each I/O cell can be individually GLBs and all of the inputs from the bi-directional I/O cells.

programmed to be a combinatorial input, registered in- All of these signals are made available to the inputs of the

put, latched input, output or bi-directional GLBs. Delays through the GRP have been equalized to

I/O pin with 3-state control. The signal levels are TTL minimize timing skew.

compatible voltages and the output drivers can source 4

Clocks in the ispLSI 1048E device are selected using the

mA or sink 8 mA. Each output can be programmed

Clock Distribution Network. Four dedicated clock pins

independently for fast or slow output slew rate to mini-

(Y0, Y1, Y2 and Y3) are brought into the distribution

mize overall output switching noise.

network, and five clock outputs (CLK 0, CLK 1, CLK 2,

Eight GLBs, 16 I/O cells, two dedicated inputs and one IOCLK 0 and IOCLK 1) are provided to route clocks to the

ORP are connected together to make a Megablock (see GLBs and I/O cells. The Clock Distribution Network can

figure 1). The outputs of the eight GLBs are connected to also be driven from a special clock GLB (D0). The logic

a set of 16 universal I/O cells by the ORP. Each ispLSI of this GLB allows the user to create an internal clock

1048E device contains six Megablocks.

from a combination of internal signals within the device.

2

Specifications ispLSI 1048E

1

Absolute Maximum Ratings

Supply Voltage V . ................................. -0.5 to +7.0V

cc

Input Voltage Applied........................ -2.5 to V +1.0V

CC

Off-State Output Voltage Applied ..... -2.5 to V +1.0V

CC

Storage Temperature................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (T ) with Power Applied ... 150°C

J

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional

operation of the device at these or at any other conditions above those indicated in the operational sections of this specification

is not implied (while programming, follow the programming specifications).

DC Recommended Operating Conditions

SYMBOL

PARAMETER

Commercial

Industrial

MIN.

4.75

4.5

0

MAX.

5.25

5.5

UNITS

V

T = 0°C to + 70°C

A

VCC

Supply Voltage

T = -40°C to + 85°C

A

Input Low Voltage

Input High Voltage

0.8

VIL

2.0

V +1

cc

VIH

Table 2-0005/1048E

Capacitance (T_A=25^oC, f=1.0 MHz)

SYMBOL

PARAMETER

TYPICAL

UNITS

TEST CONDITIONS

_CC= 5.0V, V_PIN= 2.0V

V_CC= 5.0V, V_PIN= 2.0V

8

pf

V

Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance

Y0 Clock Capacitance

C₁

C₂

15

Table 2-0006/1048E

Data Retention Specifications

PARAMETER

Data Retention

MINIMUM

20

MAXIMUM

UNITS

Years

Cycles

–

Erase/Reprogram Cycles

10000

Table 2-0008/1048E

3

Specifications ispLSI 1048E

Switching Test Conditions

Figure 2. Test Load

Input Pulse Levels

GND to 3.0V

≤ 3 ns 10% to 90%

1.5V

+ 5V

Input Rise and Fall Time

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

R

1

2

1.5V

See Figure 2

Device

Output

Test

Point

Table 2-0003/1048E

3-state levels are measured 0.5V from

steady-state active level.

R

C

*

L

Output Load Conditions (see Figure 2)

*

C includes Test Fixture and Probe Capacitance.

L

0213a

TEST CONDITION

R1

470Ω

∞

R2

CL

A

B

390Ω

35pF

Active High

Active Low

470Ω

Active High to Z

∞

390Ω

5pF

at V_OH-0.5V

C

Active Low to Z

at V_OL+0.5V

470Ω

5pF

Table 2-0004a

DC Electrical Characteristics

Over Recommended Operating Conditions

3

SYMBOL

PARAMETER

Output Low Voltage

Output High Voltage

CONDITION

I_OL= 8 mA

MIN.

–

TYP. MAX. UNITS

–

0.4

–

V

VOL

VOH

IIL

I_OH= -4 mA

2.4

–

V

Input or I/O Low Leakage Current 0V ≤ V ≤ V (Max.)

–

-10

10

μA

mA

IN

IL

Input or I/O High Leakage Current 3.5V ≤ V ≤ V

–

IIH

IN

CC

ispEN Input Low Leakage Current 0V ≤ V ≤ V

–

-150

-200

–

IIL-isp

IIL-PU

IOS¹

ICC^{2, 4}

IN

IL

I/O Active Pull-Up Current

Output Short Circuit Current

0V ≤ V ≤ V

–

IN

IL

V = 5V, V_OUT= 0.5V

–

CC

–

175

Commercial

Industrial

V = 0.0V, V = 3.0V

IL

IH

Operating Power Supply Current

–

f_CLOCK= 1 MHz

Table 2-0007/1048E

1. One output at a time for a maximum duration of one second. V_OUT= 0.5V was selected to avoid test problems

by tester ground degradation. Characterized but not 100% tested.

2. Measured using twelve 16-bit counters.

3. Typical values are at V_CC= 5V and T = 25°C.

A

4. Maximum I_CCvaries widely with specific device configuration and operating frequency. Refer to the Power Consumption

section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to

estimate maximum I_CC

.

4

Specifications ispLSI 1048E

External Timing Parameters

Over Recommended Operating Conditions

TEST ⁴

COND.

-125

-100

-90

DESCRIPTION¹

UNITS

2

PARAMETER

#

MIN. MAX. MIN. MAX. MIN. MAX.

A

–

1

Data Propagation Delay, 4PT Bypass, ORP Bypass

Data Propagation Delay, Worst Case Path

Clock Frequency with Internal Feedback ³

–

7.5

10.0

–

10.0

12.5

–

10.0

12.5

–

ns

tpd1

tpd2

fmax (Int.)

fmax (Ext.)

fmax (Tog.)

tsu1

tco1

th1

tsu2

tco2

th2

tr1

trw1

tptoeen

tptoedis

tgoeen

tgoedis

twh

twl

tsu3

2

3

4

5

6

7

8

9

125.0

100.0

71.0

125.0

6.5

90.9

71.0

125.0

6.5

–

MHz

ns

1

^{Clock Frequency with External Feedback}(_{tsu2 + tco1}) ^91.0

–

1

–

^{Clock Frequency, Max. Toggle}(_{twh + twl}

)

167.0

5.5

–

GLB Reg. Setup Time before Clock,4 PT Bypass

GLB Reg. Clock to Output Delay, ORP Bypass

GLB Reg. Hold Time after Clock, 4 PT Bypass

GLB Reg. Setup Time before Clock

–

A

4.5

–

6.5

ns

–

0.0

6.5

–

0.0

7.5

–

0.0

7.5

–

ns

–

10 GLB Reg. Clock to Output Delay

11 GLB Reg. Hold Time after Clock

12 Ext. Reset Pin to Output Delay

13 Ext. Reset Pulse Duration

5.5

–

7.5

–

7.5

–

0.0

–

0.0

–

0.0

–

A

–

10.0

–

13.5

–

13.5

–

5.0

–

6.5

–

6.5

–

B

C

B

C

–

14 Input to Output Enable

12.0

7.0

–

15.0

9.0

–

15.0

9.0

–

15 Input to Output Disable

–

16 Global OE Output Enable

–

17 Global OE Output Disable

–

18 External Synchronous Clock Pulse Duration, High

19 External Synchronous Clock Pulse Duration, Low

3.0

4.0

3.5

4.0

–

20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.0

21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 0.0

–

0.0

–

0.0

–

ns

th3

Table 2-0030A/1048E

1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-bit counter using GRP feedback.

4. Reference Switching Test Conditions section.

5

Specifications ispLSI 1048E

External Timing Parameters

Over Recommended Operating Conditions

TEST ⁴

COND.

-70

-50

DESCRIPTION¹

UNITS

2

PARAMETER

#

MIN. MAX. MIN. MAX.

A

–

1

Data Propagation Delay, 4PT Bypass, ORP Bypass

Data Propagation Delay, Worst Case Path

Clock Frequency with Internal Feedback ³

–

15.0

18.5

–

20.0

24.5

–

ns

tpd1

tpd2

fmax (Int.)

fmax (Ext.)

fmax (Tog.)

tsu1

tco1

th1

tsu2

tco2

th2

tr1

trw1

tptoeen

tptoedis

tgoeen

tgoedis

twh

twl

tsu3

2

3

4

5

6

7

8

9

70.0

56.0

100.0

9.0

–

50.0

42.0

77.0

12.0

–

MHz

ns

1

^{Clock Frequency with External Feedback}(_{tsu2 + tco1}

)

–

1

–

^{Clock Frequency, Max. Toggle}(_{twh + twl}

)

–

GLB Reg. Setup Time before Clock,4 PT Bypass

GLB Reg. Clock to Output Delay, ORP Bypass

GLB Reg. Hold Time after Clock, 4 PT Bypass

GLB Reg. Setup Time before Clock

–

A

7.0

9.5

ns

–

0.0

11.0

–

0.0

14.5

–

ns

–

10 GLB Reg. Clock to Output Delay

11 GLB Reg. Hold Time after Clock

12 Ext. Reset Pin to Output Delay

13 Ext. Reset Pulse Duration

9.0

–

12.0

–

0.0

–

0.0

–

A

–

15.0

–

20.5

–

10.0

–

13.0

–

B

C

B

C

–

14 Input to Output Enable

18.0

12.0

–

24.0

16.0

–

15 Input to Output Disable

–

16 Global OE Output Enable

–

17 Global OE Output Disable

–

18 External Synchronous Clock Pulse Duration, High

19 External Synchronous Clock Pulse Duration, Low

20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3)

5.0

4.0

6.5

–

21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)

0.0

–

0.0

–

ns

th3

Table 2-0030B/1048E

1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-bit counter using GRP feedback.

4. Reference Switching Test Conditions section.

6

Specifications ispLSI 1048E

1

Internal Timing Parameters

-125

-100

-90

2

PARAMETER

Inputs

#

UNITS

DESCRIPTION

MIN. MAX. MIN. MAX. MIN. MAX.

22 I/O Register Bypass

23 I/O Latch Delay

–

0.3

1.9

–

0.3

2.3

–

0.5

2.5

–

ns

t

iobp

iolat

iosu

ioh

24 I/O Register Setup Time before Clock

25 I/O Register Hold Time after Clock

26 I/O Register Clock to Out Delay

27 I/O Register Reset to Out Delay

28 Dedicated Input Delay

3.0

0.0

–

3.5

0.0

–

4.0

-0.5

–

4.6

2.3

5.0

2.7

5.0

2.9

ioco

ior

–

din

GRP

29 GRP Delay, 1 GLB Load

–

1.8

–

1.9

–

2.2

ns

t

grp1

30 GRP Delay, 4 GLB Loads

31 GRP Delay, 8 GLB Loads

–

2.0

2.3

2.8

4.9

–

2.4

2.6

3.0

5.4

–

2.4

2.7

3.3

5.7

ns

t

grp4

grp8

GRP Delay, 16 GLB Loads

32

grp16

grp48

33 GRP Delay, 48 GLB Loads

GLB

34 4 Product Term Bypass Path Delay (Combinatorial)

35 4 Product Term Bypass Path Delay (Registered)

–

3.9

4.0

–

5.3

–

5.4

6.3

ns

t

4ptbpc

4ptbpr

36 1 Product Term/XOR Path Delay

37 20 Product Term/XOR Path Delay

38 XOR Adjacent Path Delay³

–

3.6

5.0

0.4

–

4.6

5.8

6.3

1.0

–

6.5

7.3

0.4

–

ns

t

1ptxor

20ptxor

xoradj

gbp

–

39 GLB Register Bypass Delay

–

40 GLB Register Setup Time before Clock

41 GLB Register Hold Time after Clock

42 GLB Register Clock to Output Delay

43 GLB Register Reset to Output Delay

44 GLB Product Term Reset to Register Delay

45 GLB Product Term Output Enable to I/O Cell Delay

46 GLB Product Term Clock Delay

0.1

4.5

–

0.5

5.3

–

0.1

6.4

–

gsu

–

gh

2.3

4.9

3.9

5.4

2.5

6.2

4.5

7.2

2.0

6.3

5.0

5.7

gco

–

gro

–

ptre

–

ptoe

ptck

2.9 4.0

3.5 4.7

4.0 5.2

ORP

47 ORP Delay

–

1.0

0.0

–

1.0

0.0

–

1.0

0.0

ns

t

orp

48 ORP Bypass Delay

orpbp

Table 2-0036A/1048E

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

7

Specifications ispLSI 1048E

1

Internal Timing Parameters

-70

-50

2

PARAMETER

Inputs

#

UNITS

DESCRIPTION

MIN. MAX. MIN. MAX.

22 I/O Register Bypass

23 I/O Latch Delay

–

0.6

3.6

–

0.7

4.7

–

ns

t

iobp

iolat

iosu

ioh

24 I/O Register Setup Time before Clock

25 I/O Register Hold Time after Clock

26 I/O Register Clock to Out Delay

27 I/O Register Reset to Out Delay

28 Dedicated Input Delay

4.1

-0.6

–

6.5

-0.7

–

6.0

4.3

7.0

6.1

ioco

ior

–

din

GRP

29 GRP Delay, 1 GLB Load

–

3.5

–

5.1

ns

t

grp1

30 GRP Delay, 4 GLB Loads

31 GRP Delay, 8 GLB Loads

–

3.7

4.1

4.8

7.5

–

5.4

5.8

6.6

9.8

ns

t

grp4

grp8

GRP Delay, 16 GLB Loads

32

grp16

grp48

33 GRP Delay, 48 GLB Loads

GLB

34 4 Product Term Bypass Path Delay (Combinatorial)

35 4 Product Term Bypass Path Delay (Registered)

–

8.5

7.4

–

10.7

9.2

ns

t

4ptbpc

4ptbpr

36 1 Product Term/XOR Path Delay

37 20 Product Term/XOR Path Delay

38 XOR Adjacent Path Delay³

–

8.4

9.4

1.6

–

10.5

11.7

2.2

–

ns

t

1ptxor

20ptxor

xoradj

gbp

–

39 GLB Register Bypass Delay

–

40 GLB Register Setup Time before Clock

41 GLB Register Hold Time after Clock

42 GLB Register Clock to Output Delay

43 GLB Register Reset to Output Delay

44 GLB Product Term Reset to Register Delay

45 GLB Product Term Output Enable to I/O Cell Delay

46 GLB Product Term Clock Delay

0.1

8.5

–

0.0

11.5

–

gsu

–

gh

2.0

6.3

6.1

6.8

3.0

7.3

7.9

10.0

gco

–

gro

–

ptre

–

ptoe

ptck

5.1 6.4

6.9 8.3

ORP

47 ORP Delay

–

2.0

0.0

–

2.5

0.0

ns

t

orp

48 ORP Bypass Delay

orpbp

Table 2-0036B/1048E

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

8

Specifications ispLSI 1048E

1

Internal Timing Parameters

-125

-100

-90

#

UNITS

PARAMETER

Outputs

DESCRIPTION

MIN. MAX. MIN. MAX. MIN. MAX.

49 Output Buffer Delay

–

1.3

10.0

4.3

–

2.0

10.0

5.1

–

1.7

12.0

6.4

ns

t

ob

50 Output Slew Limited Delay Adder

51 I/O Cell OE to Output Enabled

52 I/O Cell OE to Output Disabled

53 Global OE

sl

oen

odis

goe

4.3

5.1

6.4

2.7

3.9

2.6

Clocks

54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)

55 Clock Delay, Y1 or Y2 to Global GLB Clock Line

56 Clock Delay, Clock GLB to Global GLB Clock Line

57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line

58 Clock Delay, Clock GLB to I/O Cell Global Clock Line

0.9 0.9 2.0

0.8 1.8 0.8

0.0 0.0 0.0

0.8 1.8 0.8

2.0 2.8 2.8

1.8 0.8 1.8

0.0 0.0 0.5

1.8 0.8 1.8

ns

t

gy0

gy1/2

gcp

ioy2/3

iocp

Global Reset

59 Global Reset to GLB and I/O Registers

–

2.8

–

4.3

–

4.5

ns

t

gr

Table 2-0037A/1048E

1. Internal timing parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

9

Specifications ispLSI 1048E

1

Internal Timing Parameters

-70

-50

#

UNITS

PARAMETER

Outputs

DESCRIPTION

MIN. MAX. MIN. MAX.

49 Output Buffer Delay

–

2.2

12.0

6.9

–

3.2

12.0

7.9

ns

t

ob

50 Output Slew Limited Delay Adder

51 I/O Cell OE to Output Enabled

52 I/O Cell OE to Output Disabled

53 Global OE

sl

oen

odis

goe

6.9

7.9

5.1

8.1

Clocks

54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)

55 Clock Delay, Y1 or Y2 to Global GLB Clock Line

56 Clock Delay, Clock GLB to Global GLB Clock Line

57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line

58 Clock Delay, Clock GLB to I/O Cell Global Clock Line

2.8

0.8

0.1

0.8

2.8 3.3 3.3

1.8 0.8 1.8

0.6 0.0 0.7

1.8 0.8 1.8

ns

t

gy0

gy1/2

gcp

ioy2/3

iocp

Global Reset

59 Global Reset to GLB and I/O Registers

–

4.5

–

7.5

ns

t

gr

Table 2-0037B/1048E

1. Internal timing parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

10

Specifications ispLSI 1048E

ispLSI 1048E Timing Model

I/O Cell

GRP

GLB

ORP

I/O Cell

Feedback

#34

Ded. In

Comb 4 PT Bypass

#28

I/O Reg Bypass

#22

GRP4

#30

Reg 4 PT Bypass

#35

GLB Reg Bypass

#39

ORP Bypass

#48

#49, 50

I/O Pin

(Input)

I/O Pin

(Output)

Input

20 PT

XOR Delays

GLB Reg

Delay

ORP

Delay

GRP Loading

Delay

Register

Q

D

#51, 52

RST

D

Q

#29, 31-33

#47

#36 - 38

#59

#23 - 27

RST

Reset

#40 - 43

Clock

Control

PTs

RE

OE

CK

Distribution

0491

Y1,2,3

#55 - 58

#44 - 46

#54

#53

Y0

GOE 0,1

Derivations of

su = Logic + Reg su - Clock (min)

= ( iobp + grp4 + 20ptxor) + (

tsu, th and t

co from the Product Term Clock¹

t

tgsu) – (tiobp +

tgrp4 +

tptck(min))

= (#22 + #30 + #37) + (#40) – (#22 + #30 + #46)

2.2 ns = (0.3 + 2.0 + 5.0) + (0.1) – (0.3 + 2.0 + 2.9)

th

= Clock (max) + Reg h - Logic

= (tiobp + tgrp4 + tptck(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)

= (#22 + #30 + #46) + (#41) - (#22 + #30 + #37)

3.5 ns

= (0.3 + 2.0 + 4.0) + (4.5) – (0.3 + 2.0 + 5.0)

t

co

= Clock (max) + Reg co + Output

= (

= (#22 + #30 + #46) + (#42) + (#47 + #49)

10.9 ns = (0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3)

tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)

1

Derivations of

tsu,

th and tco from the Clock GLB

t

su

= Logic + Reg su - Clock (min)

= ( iobp + grp4 + 20ptxor) + (tgsu) – (tgy0(min) + tgco + tgcp(min))

t

= (#22 + #30 + #37) + (#40) – (#54 + #42 + #56)

3.4 ns = (0.3 + 2.0 + 5.0) + (0.1) – (0.9 + 2.3 + 0.8)

h

= Clock (max) + Reg h - Logic

= (tgy0(max) + tgco + tgcp(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)

= (#54 + #42 + #56) + (#41) – (#22 + #30 + #37)

= (0.9 + 2.3 + 1.8) + (4.5) – (0.3 + 2.0 + 5.0)

2.2 ns

co

= Clock (max) + Reg co + Output

= (

= (#54 + #42 + #56) + (#42) + (#47 + #49)

9.6 ns = (0.9 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3)

tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)

1. Calculations are based upon timing specifications for the ispLSI 1048E-125.

Table 2-0042/1048E

11

Specifications ispLSI 1048E

Maximum GRP Delay vs. GLB Loads

10

9

ispLSI 1048E-50

ispLSI 1048E-70

8

7

6

5

4

ispLSI 1048E-90/100

ispLSI 1048E-125

3

2

1

4

8

16

32

48

GLB Loads

0127A/1048E

Power Consumption

Power consumption in the ispLSI 1048E device depends Figure 3 shows the relationship between power and

on two primary factors: the speed at which the device is operating speed.

operating and the number of Product Terms used.

Figure3. TypicalDevicePowerConsumptionvsfmax

380

ispLSI 1048E

340

300

260

220

180

0

20

40

60

80

100 120 140

fmax (MHz)

Notes: Configuration of twelve 16-bit counters,

Typical current at 5V, 25°C

I

can be estimated for the ispLSI 1048E using the following equation:

= 20 + (# of PTs * 0.42) + (# of nets * Max. freq * 0.010)

CC

Where:

# of PTs = Number of Product Terms used in design

# of nets = Number of Signals used in device

Max. freq = Highest Clock Frequency to the device

The I

estimate is based on typical conditions (V

= 5.0V, room temperature) and an assumption of 4 GLB loads on

CC

average exists. These values are for estimates only. Since the value of I

program in the device, the actual I

is sensitive to operating conditions and the

CC

should be verified.

CC

0127B/1048E

12

Specifications ispLSI 1048E

Pin Description

NAME

PQFP / TQFP PIN NUMBERS

DESCRIPTION

I/O 0 - I/O 5

22,

28,

35,

41,

53,

59,

67,

73,

86,

92,

99,

23,

29,

36,

42,

54,

60,

68,

74,

87,

93,

100,

106,

119,

125,

4,

24,

30,

37,

43,

55,

61,

69,

75,

88,

94,

101,

107,

120,

126,

5,

25,

31,

38,

44,

56,

62,

70,

76,

89,

95,

102,

108,

121,

127,

6,

Input/Output Pins - These are the general purpose I/O pins used by the

logic array.

21,

27,

34,

40,

52,

58,

66,

72,

85,

91,

98,

26,

32,

39,

45,

57,

63,

71,

77,

90,

96,

103,

109,

122,

128,

7,

I/O 6 - I/O 11

I/O 12 - I/O 17

I/O 18 - I/O 23

I/O 24 - I/O 29

I/O 30 - I/O 35

I/O 36 - I/O 41

I/O 42 - I/O 47

I/O 48 - I/O 53

I/O 54 - I/O 59

I/O 60 - I/O 65

I/O 66 - I/O 71

I/O 72 - I/O 77

I/O 78 - I/O 83

I/O 84 - I/O 89

I/O 90 - I/O 95

104, 105,

117, 118,

123, 124,

2,

8,

3,

9,

10,

11,

12,

13

GOE0, GOE1

Global Output Enable input pins.

Dedicated input pins to the device.

64,

114

47,

84,

51

110,

IN 2, IN 4

IN 6 - IN 11

111, 115,

116, 14

ispEN

18

Input - Dedicated in-system programming enable input pin. This pin is

brought low to enable the programming mode. When low, the MODE,

SDI, SDO and SCLK controls become active.

Input - This pin performs two functions. When ispEN is logic low, it

functions as an input pin to load programming data into the device.

SDI/IN 0 also is used as one of the two control pins for the ISP state

machine. When ispEN is high, it functions as a dedicated input pin.

SDI/IN 0¹

20

MODE/IN 1¹

SDO/IN 3¹

SCLK/IN 5¹

46

50

78

Input - This pin performs two functions. When ispEN is logic low, it

functions as pin to control the operation of the isp state machine. When

ispEN is high, it functions as a dedicated input pin.

Output/Input - This pin performs two functions. When ispEN is logic low,

it functions as an output pin to read serial shift register data. When

ispEN is high, it functions as a dedicated input pin.

Input - This pin performs two functions. When ispEN is logic low, it

functions as a clock pin for the Serial Shift Register. When ispEN is

high, it functions as a dedicated input pin.

RESET

Y0

19

15

83

Active Low (0) Reset pin which resets all of the GLB and I/O registers in

the device.

Dedicated Clock input. This clock input is connected to one of the clock

inputs of all of the GLBs on the device.

Y1

Dedicated Clock input. This clock input is brought into the clock

distribution network, and can optionally be routed to any GLB on the

device.

Y2

Y3

80

79

Dedicated Clock input. This clock input is brought into the clock

distribution network, and can optionally be routed to any GLB and/or

any I/O cell on the device.

Dedicated Clock input. This clock input is brought into the clock

distribution network, and can optionally be routed to any I/O cell on the

device.

1,

17,

33,

82,

49,

65,

81,

GND

VCC

Ground (GND)

V_CC

97,

112

16,

48,

113

Table 2 - 0002C-48E

1. Pins have dual function capability.

13

Specifications ispLSI 1048E

Pin Configuration

ispLSI 1048E 128-Pin PQFP Pinout Diagram

GND

I/O 84

I/O 85

I/O 86

I/O 87

I/O 88

I/O 89

I/O 90

I/O 91

I/O 92

I/O 93

I/O 94

I/O 95

IN 11

Y0

1

2

3

4

5

96

95

94

93

92

91

90

89

88

87

86

85

84

I/O 59

I/O 58

I/O 57

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

I/O 49

I/O 48

IN 6

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

Y1

VCC

GND

Y2

83

82

ispLSI 1048E

VCC

GND

ispEN

RESET

¹SDI/IN 0

I/O 0

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

Top View

Y3

SCLK/IN 5¹

I/O 47

I/O 46

I/O 45

I/O 44

I/O 43

I/O 42

I/O 41

I/O 40

I/O 39

I/O 38

I/O 37

I/O 36

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

22

23

24

25

26

27

28

29

30

31

32

I/O 9

I/O 10

I/O 11

GND

0124-48C

1. Pins have dual function capability.

14

Specifications ispLSI 1048E

Pin Configuration

ispLSI 1048E 128-Pin TQFP Pinout Diagram

GND

I/O 84

I/O 85

I/O 86

I/O 87

I/O 88

I/O 89

I/O 90

I/O 91

I/O 92

I/O 93

I/O 94

I/O 95

IN 11

Y0

1

2

3

4

5

96

95

94

93

92

91

90

89

88

87

86

85

84

I/O 59

I/O 58

I/O 57

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

I/O 49

I/O 48

IN 6

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

Y1

VCC

GND

Y2

83

82

ispLSI 1048E

VCC

GND

ispEN

RESET

¹SDI/IN 0

I/O 0

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

Top View

Y3

SCLK/IN 5¹

I/O 47

I/O 46

I/O 45

I/O 44

I/O 43

I/O 42

I/O 41

I/O 40

I/O 39

I/O 38

I/O 37

I/O 36

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

22

23

24

25

26

27

28

29

30

31

32

I/O 9

I/O 10

I/O 11

GND

1. Pins have dual function capability.

0124-48/TQFP

15

Specifications ispLSI 1048E

Package Thermal Characteristics

For the ispLSI 1048E-125LT, it is strongly recommended

that the actual Icc be verified to ensure that the maximum

mum allowable junction temperature (T ) specification.

Please refer to the Thermal Management section of the

Lattice Semiconductor Data Book or CD-ROM for addi-

J

junction temperature (T ) with power supplied is not

J

exceeded. Depending on the specific logic design and

clock speed, airflow may be required to satisfy the maxi-

tional information on calculating T .

J

Part Number Description

–

1048E XXX X

X

ispLSI

Device Family

Device Number

Speed

Grade

Blank = Commercial

I = Industrial

Package

Q = PQFP

T = TQFP

QN = Lead-Free PQFP

TN = Lead-Free TQFP

125 = 125 MHz

100 = 100 MHz

90 = 90 MHz

70 = 70 MHz

50 = 50 MHz

f

max

f

max

Power

L = Low

ispLSI 1048E Ordering Information

Conventional Packaging

COMMERCIAL

FAMILY

fmax (MHz)

tpd (ns)

ORDERING NUMBER

ispLSI 1048E-125LQ

ispLSI 1048E-125LT

ispLSI 1048E-100LQ

ispLSI 1048E-100LT

PACKAGE

128-Pin PQFP

128-Pin TQFP

128-Pin PQFP

128-Pin TQFP

125

7.5

10

100

10

90

70

50

10

15

20

ispLSI 1048E-90LQ

ispLSI 1048E-90LT

ispLSI 1048E-70LQ

ispLSI 1048E-70LT

ispLSI 1048E-50LQ

ispLSI 1048E-50LT

128-Pin PQFP

128-Pin TQFP

128-Pin PQFP

128-Pin TQFP

128-Pin PQFP

128-Pin TQFP

ispLSI

50

20

Table 2-0041A/1048E

INDUSTRIAL

FAMILY

ispLSI

fmax (MHz)

tpd (ns)

15

ORDERING NUMBER

ispLSI 1048E-70LQI*

ispLSI 1048E-50LQI*

PACKAGE

128-Pin PQFP

70

50

20

Table 2-0041B/1048E

*Use 1048E-70 for new 1048E-50 designs.

16

Specifications ispLSI 1048E

ispLSI 1048E Ordering Information (Cont.)

Lead-Free Packaging

COMMERCIAL

FAMILY

fmax (MHz)

125

tpd (ns)

ORDERING NUMBER

ispLSI 1048E-125LQN

ispLSI 1048E-125LTN

ispLSI 1048E-100LQN

ispLSI 1048E-100LTN

PACKAGE

7.5

10

Lead-Free 128-Pin PQFP

Lead-Free 128-Pin TQFP

Lead-Free 128-Pin PQFP

Lead-Free 128-Pin TQFP

125

100

10

90

10

ispLSI 1048E-90LQN

ispLSI 1048E-90LTN

ispLSI 1048E-70LQN

ispLSI 1048E-70LTN

ispLSI 1048E-50LQN

ispLSI 1048E-50LTN

Lead-Free 128-Pin PQFP

Lead-Free 128-Pin TQFP

Lead-Free 128-Pin PQFP

Lead-Free 128-Pin TQFP

Lead-Free 128-Pin PQFP

Lead-Free 128-Pin TQFP

ispLSI

70

50

15

20

50

20

INDUSTRIAL

FAMILY

ispLSI

fmax (MHz)

tpd (ns)

ORDERING NUMBER

PACKAGE

70

15

ispLSI 1048E-70LQNI

Lead-Free 128-Pin PQFP

Revision History

Date

—

Version

Change Summary

Previous Lattice release.

Updated for lead-free package options.

11

12

August 2006

17


型号：	ISPLSI1048E50LT
厂家：	LATTICE SEMICONDUCTOR
描述：	In-System Programmable High Density PLD 在系统可编程高密度PLD
文件：	总17页 (文件大小：280K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISPLSI1048E50LT [LATTICE]

相关型号：

ISPLSI1048E50LTI

ISPLSI1048E50LTN

ISPLSI1048E50LTNI

ISPLSI1048E70LQ

ISPLSI1048E70LQI

ISPLSI1048E70LQN

ISPLSI1048E70LQNI

ISPLSI1048E70LT

ISPLSI1048E70LTI

ISPLSI1048E70LTN

ISPLSI1048E70LTNI

ISPLSI1048E90LQ