ISPLSI2032E-135LT48 [LATTICE]
In-System Programmable SuperFAST High Density PLD; 在系统可编程超快高密度可编程逻辑器件
| 型号： | ISPLSI2032E-135LT48 |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | In-System Programmable SuperFAST High Density PLD |
| 文件： | 总14页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ispLSI 2032E
In-System Programmable
SuperFAST™ High Density PLD
Features
Functional Block Diagram
• SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 1000 PLD Gates
— 32 I/O Pins, Two Dedicated Inputs
— 32 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functionally and JEDEC Upward Compatible
with ispLSI 2032 Devices
Global Routing Pool
(GRP)
A0
A1
A2
A7
A6
A5
A4
D
D
D
D
Q
Q
Q
Q
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 225 MHz Maximum Operating Frequency
— tpd = 3.5 ns Propagation Delay
Logic
Array
GLB
— TTL Compatible Inputs and Outputs
— 5V Programmable Logic Core
A3
— ispJTAG™ In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
— User-Selectable 3.3V or 5V I/O (48-Pin Package Only)
Supports Mixed Voltage Systems
0139Bisp/2000
— PCI Compatible Outputs (48-Pin Package Only)
— Open-Drain Output Option
— Electrically Erasable and Reprogrammable
— Non-Volatile
Description
The ispLSI 2032E is a High Density Programmable Logic
Device. The device contains 32 Registers, 32 Universal
I/O pins, two Dedicated Input Pins, three Dedicated
Clock Input Pins, one dedicated Global OE input pin and
a Global Routing Pool (GRP). The GRP provides com-
plete interconnectivity between all of these elements.
The ispLSI 2032E features 5V in-system programmabil-
ity and in-system diagnostic capabilities. The ispLSI
2032E offers non-volatile reprogrammability of the logic,
as well as the interconnect to provide truly reconfigurable
systems.
— Unused Product Term Shutdown Saves Power
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
The basic unit of logic on the ispLSI 2032E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. A7 (see Figure 1). There are a total of eight GLBs in the
ispLSI 2032E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/ExclusiveORarray, andfouroutputswhichcan
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
Copyright©1999LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject
to change without notice.
June 1999
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2032e_03
1
Specifications ispLSI 2032E
Functional Block Diagram
Figure 1. ispLSI 2032E Functional Block Diagram
GOE 0
I/O 31
I/O 0
I/O 1
I/O 30
A0
A7
I/O 29
I/O 28
I/O 2
I/O 3
I/O 27
I/O 26
I/O 4
I/O 5
Global Routing Pool
(GRP)
A1
A6
A5
A4
I/O 6
I/O 25
I/O 24
I/O 7
I/O 23
I/O 22
I/O 21
I/O 20
I/O 8
I/O 9
I/O 10
A2
I/O 11
I/O 12
I/O 13
I/O 19
I/O 18
I/O 17
I/O 16
I/O 14
A3
I/O 15
TDI/IN 0
TDO/IN 1
TMS
BSCAN
Y0
Y1*
TCK/Y2
Notes:
*Y1 and RESET are multiplexed on the same pin
0139/2032E
programmed to be a combinatorial input, output or bi- Clocks in the ispLSI 2032E device are selected using the
directional I/O pin with 3-state control. The signal levels dedicatedclockpins. Threededicatedclockpins(Y0, Y1,
are TTL compatible voltages and the output drivers can Y2) or an asynchronous clock can be selected on a GLB
source 4 mA or sink 8 mA. Each output can be pro- basis. The asynchronous or Product Term clock can be
grammed independently for fast or slow output slew rate generated in any GLB for its own clock.
tominimizeoveralloutputswitchingnoise. Byconnecting
Programmable Open-Drain Outputs
the VCCIO pins to a common 5V or 3.3V power supply,
I/O output levels can be matched to 5V or 3.3V compat-
ible voltages. When connected to a 5V supply, the I/O
pins provide PCI-compatible output drive (48-pin device
only).
In addition to the standard output configuration, the
outputs of the ispLSI 2032E are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the ORP. Each ispLSI
2032E device contains one Megablock.
The GRP has as its inputs, the outputs from all of the
GLBsandallof theinputsfromthebi-directionalI/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
2
Specifications ispLSI 2032E
1
Absolute Maximum Ratings
Supply Voltage V .................................. -0.5 to +7.0V
cc
Input Voltage Applied........................ -2.5 to V +1.0V
CC
Off-State Output Voltage Applied ..... -2.5 to V +1.0V
CC
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T ) with Power Applied ... 150°C
J
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
4.75
5.25
V
Supply Voltage: Logic Core, Input Buffers
T = 0°C to +70°C
A
VCC
5V
Supply Voltage: Output Drivers
3.3V
4.75
3.0
5.25
3.6
V
V
V
CCIO1
Input Low Voltage
Input High Voltage
0
0.8
V
V
V
IL
2.0
V +1
cc
VIH
Table 2-0005/2032E
1. 3.3V I/O operation not available for 44-pin packages.
Capacitance (TA=25°C, f=1.0 MHz)
SYMBOL
PARAMETER
Dedicated Input Capacitance
TYP
6
UNITS
TEST CONDITIONS
VCC = 5.0V, V = 2.0V
pf
pf
pf
C1
C2
C3
IN
7
VCC= 5.0V, VI/O = 2.0V
I/O Capacitance
10
VCC= 5.0V, VY = 2.0V
Clock Capacitance
Table 2-0006/2032E
Erase/Reprogram Specification
PARAMETER
MINIMUM
MAXIMUM
UNITS
Erase/Reprogram Cycles
10,000
–
Cycles
Table 2-0008/2032E
3
Specifications ispLSI 2032E
Switching Test Conditions
Figure 2. Test Load
Input Pulse Levels
GND to 3.0V
1.5 ns
+ 5V
Input Rise and Fall Time 10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
1.5V
R
1
2
1.5V
Device
Output
Test
Point
See Figure 2
Table 2-0003/2032E
3-state levels are measured 0.5V from
steady-state active level.
R
C *
L
Output Load Conditions (see Figure 2)
*
C includes Test Fixture and Probe Capacitance.
L
TEST CONDITION
R1
470Ω
∞
R2
CL
0213A
A
B
390Ω
390Ω
390Ω
35pF
35pF
35pF
Active High
Active Low
470Ω
Active High to Z
∞
390Ω
390Ω
5pF
at VOH-0.5V
C
Active Low to Z
at VOL+0.5V
470Ω
5pF
Table 2 - 0004A
DC Electrical Characteristics
Over Recommended Operating Conditions1
SYMBOL
PARAMETER
Output Low Voltage
Output High Voltage
CONDITION
IOL = 8 mA
MIN. TYP.3 MAX. UNITS
–
2.4
–
–
–
–
–
–
–
0.4
–
V
VOL
VOH
IIL
IOH = -4 mA
V
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (Max.)
-10
10
µA
µA
µA
µA
(VCCIO - 0.2)V ≤ VIN ≤ VCCIO
–
IIH
Input or I/O High Leakage Current
V
CCIO ≤ VIN ≤ 5.25V
–
10
I/O Active Pull-Up Current, non-PCI
I/O Active Pull-Up Current, PCI5
0V ≤ VIN ≤ 2.0V
0V ≤ VIN ≤ 2.0V
-10
-150
IIL-PU
IOS1
-10
–
–
–
-250
-200
-240
–
µA
mA
mA
mA
Output Short Circuit Current, non-PCI VCCIO = 5V, VOUT = 0.5V
Output Short Circuit Current, PCI5
VCCIO = 5.0V or 3.3V, VOUT = 0.5V
–
–
-225/-200
–
85
VIL = 0.0V, VIH = 3.0V
fTOGGLE = 1 MHz
ICC2,4,6
Operating Power Supply Current
Others
–
65
–
mA
1. One output at a time for a maximum duration of one second (VOUT = 0.5V). Characterized, but not 100% tested. Table 2-0007/2032E
2. Meaured using two 16-bit counters.
3. Typical values are at VCC = 5V and TA = 25°C.
4. Unused inputs held at 0.0V.
5. Available in 48-pin package only.
6. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the
Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor
Data Book or CD-ROM to estimate maximum ICC
.
4
Specifications ispLSI 2032E
External Timing Parameters
Over Recommended Operating Conditions
-225
-200
-180
TEST
COND.
DESCRIPTION1
UNITS
2
PARAMETER
#
4
MIN. MAX. MIN. MAX. MIN. MAX.
A
A
A
–
1
Data Prop. Delay, 4PT Bypass, ORP Bypass
Data Prop. Delay
–
3.5
5.5
–
–
–
3.5
5.5
–
–
–
5.0
7.5
–
ns
ns
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
2
3
4
5
6
7
8
9
–
Clk Frequency with Int. Feedback3
225
167
250
200
167
250
2.5
–
180
125
200
3.0
–
MHz
MHz
MHz
ns
1
Clk Frequency with Ext. Feedback (tsu2 + tco1
)
–
–
–
–
Clk Frequency, Max. Toggle
–
–
–
–
GLB Reg. Setup Time before Clk, 4 PT Bypass 2.5
–
–
–
A
–
GLB Reg. Clk to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clk, 4 PT Bypass
GLB Reg. Setup Time before Clk
–
0.0
3.5
–
2.5
–
2.5
–
4.0
–
ns
0.0
3.5
–
0.0
4.0
–
ns
–
–
–
–
ns
–
10 GLB Reg. Clk to Output Delay
11 GLB Reg. Hold Time after Clk
12 Ext. Reset Pin to Output Delay, ORP Bypass
13 Ext. Reset Pulse Duration
3.5
–
3.5
–
4.5
–
ns
–
0.0
–
0.0
–
0.0
–
ns
A
–
5.0
–
5.0
–
6.5
–
ns
3.5
–
3.5
–
4.0
–
ns
B
C
B
C
–
14 Input to Output Enable
7.0
7.0
3.5
3.5
–
7.0
7.0
3.5
3.5
–
10.0
10.0
5.0
5.0
–
ns
15 Input to Output Disable
–
–
–
ns
16 Global OE Output Enable
–
–
–
ns
17 Global OE Output Disable
–
–
–
ns
18 Ext. Synch. Clk Pulse Duration, High
19 Ext. Synch. Clk Pulse Duration, Low
2.0
2.0
2.0
2.0
2.5
2.5
ns
–
–
–
–
ns
twl
Table 2-0030A/2032E
1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
5
Specifications ispLSI 2032E
External Timing Parameters
Over Recommended Operating Conditions
-135
-110
TEST
COND.
DESCRIPTION1
UNITS
2
PARAMETER
#
4
MIN. MAX. MIN. MAX.
A
A
A
–
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
–
–
7.5
10.0
–
–
–
10.0
13.0
–
ns
ns
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
2
3
4
5
6
7
8
9
Clock Frequency with Internal Feedback3
137
100
167
4.0
–
111
77.0
125
5.5
–
MHz
MHz
MHz
ns
1
Clock Frequency with External Feedback (tsu2 + tco1
)
–
–
–
Clock Frequency, Max. Toggle
–
–
–
GLB Register Setup Time before Clock, 4 PT Bypass
GLB Register Clock to Output Delay, ORP Bypass
GLB Register Hold Time after Clock, 4 PT Bypass
GLB Register Setup Time before Clock
–
–
A
–
4.5
–
5.5
–
ns
0.0
5.5
–
0.0
7.5
–
ns
–
–
–
ns
–
10 GLB Register Clock to Output Delay
11 GLB Register Hold Time after Clock
12 External Reset Pin to Output Delay, ORP Bypass
13 External Reset Pulse Duration
5.5
–
6.5
–
ns
–
0.0
–
0.0
–
ns
A
–
9.0
–
12.5
–
ns
5.0
–
6.5
–
ns
B
C
B
C
–
14 Input to Output Enable
12.0
12.0
6.0
6.0
–
14.5
14.5
7.0
7.0
–
ns
15 Input to Output Disable
–
–
ns
16 Global OE Output Enable
–
–
ns
17 Global OE Output Disable
–
–
ns
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
3.0
3.0
4.0
4.0
ns
–
–
–
ns
twl
Table 2-0030B/2032E
1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
6
Specifications ispLSI 2032E
Internal Timing Parameters1
Over Recommended Operating Conditions
-225
MIN. MAX. MIN. MAX. MIN. MAX.
-200
-180
2
PARAMETER
Inputs
#
DESCRIPTION
UNITS
20 Input Buffer Delay
–
–
0.6
1.3
–
–
0.4
1.3
–
–
0.6
1.3
ns
ns
t
io
21 Dedicated Input Delay
tdin
GRP
grp
GLB
22 GRP Delay
–
0.7
–
0.7
–
0.7
ns
t
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
25 1 Product Term/XOR Path Delay
–
–
1.2
1.2
2.2
2.2
2.2
0.0
–
–
–
1.8
1.8
2.8
2.8
2.8
0.0
–
–
–
1.8
2.8
3.8
3.8
3.8
0.0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
4ptbpc
4ptbpr
1ptxor
20ptxor
xoradj
gbp
–
–
–
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay3
–
–
–
–
–
–
28 GLB Register Bypass Delay
–
–
–
29 GLB Register Setup Time before Clock
30 GLB Register Hold Time after Clock
31 GLB Register Clock to Output Delay
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
0.8
1.7
–
0.8
1.7
–
0.3
2.7
–
gsu
–
–
–
gh
0.7
1.3
2.5
4.2
0.7
2.9
2.5
4.4
0.7
1.1
2.9
5.9
gco
–
–
–
gro
–
–
–
ptre
–
–
–
ptoe
ptck
0.3 2.8
0.7 3.2 1.5 3.7
ORP
36 ORP Delay
–
–
1.0
0.0
–
–
1.0
0.0
–
–
1.1
0.6
ns
ns
t
orp
37 ORP Bypass Delay
torpbp
Outputs
38 Output Buffer Delay
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1.3
1.5
2.8
2.8
2.2
ns
ns
ns
ns
ns
t
t
t
t
t
ob
1.0
1.5
1.5
1.5
2.0
0.6
1.5
1.5
1.5
2.0
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
sl
oen
odis
goe
Clocks
43
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
0.8
1.0
1.2
1.4
1.4 1.4
1.6 1.6
ns
ns
t
gy0
0.8
1.0
1.2
1.4
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
tgy1/2
Global Reset
gr
–
–
–
3.5
ns
2.7
2.7
45
Global Reset to GLB
t
Table 2-0036A/2032E
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
7
Specifications ispLSI 2032E
Internal Timing Parameters1
-135
-110
2
PARAMETER
Inputs
#
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX.
20 Input Buffer Delay
–
–
1.1
2.4
–
–
1.7
3.4
ns
ns
t
io
21 Dedicated Input Delay
tdin
GRP
grp
GLB
22 GRP Delay
–
1.3
–
1.7
ns
t
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
25 1 Product Term/XOR Path Delay
–
–
3.6
3.6
5.0
5.1
5.6
0.0
–
–
–
4.9
4.8
6.2
6.8
7.5
0.1
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
4ptbpc
4ptbpr
1ptxor
20ptxor
xoradj
gbp
–
–
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay3
–
–
–
–
28 GLB Register Bypass Delay
–
–
29 GLB Register Setup Time before Clock
30 GLB Register Hold Time after Clock
31 GLB Register Clock to Output Delay
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
0.3
3.0
–
0.5
4.0
–
gsu
–
–
gh
0.7
1.1
4.4
6.4
0.6
1.8
5.9
7.1
gco
–
–
gro
–
–
ptre
–
–
ptoe
ptck
2.9 5.2 4.0 7.0
ORP
36 ORP Delay
–
–
1.3
0.3
–
–
1.5
0.5
ns
ns
t
orp
37 ORP Bypass Delay
torpbp
Outputs
38 Output Buffer Delay
–
–
–
–
–
–
–
–
–
–
1.2
10.0
4.0
ns
ns
ns
ns
ns
t
t
t
t
t
ob
1.2
10.0
3.2
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
sl
oen
odis
goe
4.0
3.2
3.0
2.8
Clocks
43
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
2.3
2.3
3.2 3.2
3.2 3.2
ns
ns
t
gy0
2.3
2.3
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
tgy1/2
Global Reset
–
–
9.0
ns
6.4
45
Global Reset to GLB
tgr
Table 2-0036B/2032E
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
8
Specifications ispLSI 2032E
ispLSI 2032E Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
Comb 4 PT Bypass #23
Ded. In
#21
I/O Delay
#20
GRP
#22
Reg 4 PT Bypass
GLB Reg Bypass
#28
ORP Bypass
#37
#38,
#39
I/O Pin
I/O Pin
(Input)
#24
(Output)
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
D
Q
#36
#25, 26, 27
RST
#45
#29, 30,
31, 32
Reset
Control
PTs
RE
OE
CK
#33, 34,
35
#40, 41
#43, 44
#42
Y0,1,2
GOE 0
0491/2032E
Derivations of tsu, th and tco from the Product Term Clock
t
t
t
su
= Logic + Reg su - Clock (min)
= ( io + grp + 20ptxor) + ( gsu) - (tio + tgrp + tptck(min))
= (#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
t
t
t
t
= (0.6 + 0.7 + 2.2) + (0.8) - (0.6 + 0.7 + 0.3)
2.7
2.3
6.8
h
= Clock (max) + Reg h - Logic
= (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
= (#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
= (0.6 + 0.7 + 2.8) + (1.7) - (0.6 + 0.7 + 2.2)
co
= Clock (max) + Reg co + Output
= (tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
= (#20 + #22 + #35) + (#31) + (#36 + #38)
= (0.6 + 0.7 + 2.8) + (0.7) + (1.0 + 1.0)
Note: Calculations are based upon timing specifications for the ispLSI 2032E-225L
Table 2-0042/2032E
9
Specifications ispLSI 2032E
Power Consumption
Figure 3 shows the relationship between power and
operating speed.
Power consumption in the ispLSI 2032E device depends
on two primary factors: the speed at which the device is
operating and the number of Product Terms used.
Figure 3. Typical Device Power Consumption vs fmax
ispLSI 2032E-225 and -200
150
140
130
120
110
ispLSI 2032E-180
and Slower
100
90
80
70
60
50
40
1
20
40 60
80 100 120 140 160 180 200 220 240
max (MHz)
f
Notes: Configuration of two 16-bit counters
Typical current at 5V, 25°C
ICC can be estimated for the ispLSI 2032E using the following equation:
For 2032E-225 and -200: I = 4.5 + (# of PTs 1.3) + (# of nets Max freq 0.0035)
*
*
*
CC
For 2032E-180 and Slower: I
= 4.5 + (# of PTs 1.02) + (# of nets Max freq 0.0035)
* * *
CC
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB
loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating
conditions and the program in the device, the actual ICC should be verified.
0127A/2032E
10
Specifications ispLSI 2032E
Pin Description
48-PIN TQFP
44-PIN PLCC
44-PIN TQFP
PIN NUMBERS
PIN NUMBERS
PIN NUMBERS
NAME
DESCRIPTION
9, 10, 11, 13,
14, 15, 16, 17,
20, 21, 22, 23,
25, 26, 27, 28,
33, 34, 35, 37,
38, 39, 40, 41,
44, 45, 46, 47,
I/O 0 - I/O 3
I/O 4 - I/O 7
15, 16, 17, 18,
19, 20, 21, 22,
25, 26, 27, 28,
29, 30, 31, 32,
37, 38, 39, 40,
41, 42, 43, 44,
3, 4, 5, 6,
7, 8, 9, 10
9, 10, 11, 12,
13, 14, 15, 16,
19, 20, 21, 22,
23, 24, 25, 26,
31 32, 33, 34,
35, 36, 37, 38,
41, 42, 43, 44,
Input/Output Pins — These are the general purpose
I/O pins used by the logic array.
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
1, 2, 3,
4
1, 2, 3,
4
40
5
GOE 0
Y0
2
Global Output Enable input pin.
43
5
11
Dedicated Clock input. This clock input is connected to
one of the clock inputs of all the GLBs on the device.
RESET/Y1
35
This pin performs two functions:
29
31
- Dedicated clock input. This clock input is brought
into the Clock Distribution Network, and can optionally
be routed to any GLB and/or I/O cell on the device.
- Active Low (0) Reset pin which resets all of the GLB
and I/O registers in the device.
7
8
BSCAN
13
14
7
8
Input — Dedicated in-system programming enable
input pin. This pin is brought low to enable the
programming mode. The TMS, TDI, TDO and TCK
controls become active.
1
TDI/IN 0
Input — This pin performs two functions. When
BSCAN is logic low, it functions as an input pin to load
programming data into the device. TDI/IN0 also is used
as one of the two control pins for the ISP state
machine. When BSCAN is high, it functions as a
dedicated input pin.
2
32
19
TMS/NC
36
24
30
18
Input — When in ISP mode, controls operation of ISP
state machine.
1
TDO/IN 1
Output/Input — This pin performs two functions. When
BSCAN is logic low, it functions as an output pin to
read serial shift register data. When BSCAN is high, it
functions as a dedicated input pin.
1
TCK/Y2
33
27
29
Input — This pin performs two functions. When
BSCAN is logic low, it functions as a clock pin for the
Serial Shift Register. When BSCAN is high, it
functions as a dedicated clock input. This clock input
is brought into the Clock Distribution Network and
can be routed to any GLB and/or I/O cell on the
device.
GND
1, 23
12, 34
17, 39
6, 28
Ground (GND)
12, 18, 36, 42
VCC
V
6, 30
24, 48
CC
VCCIO
Supply voltage for output drivers, 5V or 3.3V. All
VCCIO pins must be connected to the same voltage
level.
Table 2-0002/2032E
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, VCC or GND.
11
Specifications ispLSI 2032E
Pin Configuration
ispLSI 2032E 44-Pin PLCC Pinout Diagram
6
5 4 3 2 1 44 43 42 41 40
I/O 28
I/O 29
I/O 30
I/O 31
Y0
7
39
38
37
36
35
34
33
32
31
30
29
I/O 18
8
I/O 17
I/O 16
9
10
11
12
13
14
15
16
17
TMS/NC2
RESET/Y11
VCC
ispLSI 2032E
VCC
BSCAN
1TDI/IN 0
I/O 0
TCK/Y21
Top View
I/O 15
I/O 14
I/O 1
I/O 13
I/O 2
I/O 12
18 19 20 21 22 23 24 25 26 27 28
44PLCC/2032E
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, V or GND.
CC
ispLSI 2032E 44-Pin TQFP Pinout Diagram
44 43 42 41 40 39 38 37 36 35 34
I/O 28
I/O 29
I/O 30
1
2
33
32
31
I/O 18
I/O 17
I/O 16
TMS/NC2
RESET/Y11
VCC
3
4
5
6
7
I/O 31
Y0
30
29
28
27
ispLSI 2032E
VCC
Top View
BSCAN
TCK/Y21
1TDI/IN 0
8
26
25
24
23
I/O 15
I/O 14
I/O 13
I/O 12
I/O 0
9
I/O 1
10
11
I/O 2
12 13 14 15 16 17 18 19 20 21 22
44TQFP/2032E
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, VCC or GND.
12
Specifications ispLSI 2032E
Pin Configuration
ispLSI 2032E 48-Pin TQFP Pinout Diagram
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
GND
I/O 28
I/O 29
I/O 30
I/O 31
Y0
1
2
3
4
5
6
7
I/O 18
I/O 17
I/O 16
TMS/NC2
RESET/Y11
VCC
ispLSI 2032E
VCC
BSCAN
1TDI/IN 0
Top View
TCK/Y21
8
I/O 15
I/O 0
9
I/O 1
10
11
12
I/O 14
I/O 2
I/O 13
GND
I/O 12
13 14 15 16 17 18 19 20 21 22 23 24
48TQFP/2032E
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, VCC or GND.
13
Specifications ispLSI 2032E
Part Number Description
ispLSI 2032E – XXX X XXX X
Device Family
Grade
Blank = Commercial
Device Number
Speed
Package
J44 = PLCC
T44 = TQFP
T48 = TQFP
225 = 225 MHz
200 = 200 MHz
180 = 180 MHz
135 = 135 MHz
110 = 110 MHz
f
max
max
max
max
max
f
f
f
f
Power
L = Low
0212/2032E
ispLSI 2032E Ordering Information
COMMERCIAL
FAMILY
fmax (MHz)
225
tpd (ns)
3.5
ORDERING NUMBER
ispLSI 2032E-225LJ44
ispLSI 2032E-225LT44
ispLSI 2032E-225LT48
ispLSI 2032E-200LJ44*
ispLSI 2032E-200LT44*
ispLSI 2032E-200LT48*
PACKAGE
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
225
3.5
225
3.5
200
3.5
200
3.5
200
3.5
180
180
180
135
135
5.0
5.0
5.0
7.5
7.5
ispLSI 2032E-180LJ44
ispLSI 2032E-180LT44
ispLSI 2032E-180LT48
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
ispLSI
ispLSI 2032E-135LJ44
ispLSI 2032E-135LT44
ispLSI 2032E-135LT48
ispLSI 2032E-110LJ44
ispLSI 2032E-110LT44
ispLSI 2032E-110LT48
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
44-Pin PLCC
44-Pin TQFP
48-Pin TQFP
135
110
110
110
7.5
10.0
10.0
10.0
Table 2-0041/2032E
*2032E-225 recommended for new designs.
14
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