ISPLSI2128E-100LT176

®

ispLSI 2128E

In-System Programmable

SuperFAST™ High Density PLD

Features

Functional Block Diagram

• SUPERFAST HIGH DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

Output Routing Pool (ORP)

D7 D6

D5

D4

Output Routing Pool (ORP)

D2

D1

D0

D3

— 6000 PLD Gates

— 128 I/O Pins, Eight Dedicated Inputs

— 128 Registers

A0

A1

C7

C6

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100% Functional/JEDEC Upward Compatible with

ispLSI 2128 Devices

D

Q

A2

A3

C5

C4

D

Logic

Array

A4

A5

C3

C2

GLB

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— fmax = 180 MHz Maximum Operating Frequency

— tpd = 5.0 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— 5V Programmable Logic Core

A6

A7

C1

C0

Global Routing Pool (GRP)

— ispJTAG™ In-System Programmable via IEEE 1149.1

(JTAG) Test Access Port

B0

B1

B2

B3

B5

B6

B7

B4

Output Routing Pool (ORP)

— User-Selectable 3.3V or 5V I/O Supports Mixed-

Voltage Systems

0139(9A)/2128

— PCI Compatible Outputs

— Open-Drain Output Option

Description

— Electrically Erasable and Reprogrammable

— Non-Volatile

— Unused Product Term Shutdown Saves Power

The ispLSI 2128E is a High Density Programmable Logic

Device. The device contains 128 Registers, 128 Univer-

sal I/O pins, eight Dedicated Input pins, three Dedicated

Clock Input pins, two dedicated Global OE input pins and

a Global Routing Pool (GRP). The GRP provides com-

plete interconnectivity between all of these elements.

The ispLSI 2128E features 5V in-system programmabil-

ity and in-system diagnostic capabilities. The ispLSI

2128E offers non-volatile reprogrammability of all logic,

as well as the interconnect to provide truly reconfigurable

systems.

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

The basic unit of logic on the ispLSI 2128E device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. D7 (see Figure 1). There are a total of 32 GLBs in the

ispLSI 2128E device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/ExclusiveORarray, andfouroutputswhichcan

be configured to be either combinatorial or

registered.Inputs to the GLB come from the GRP and

dedicated inputs. All of the GLB outputs are brought back

into the GRP so that they can be connected to the inputs

of any GLB on the device.

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

The device also has 128 I/O cells, each of which is

directly connected to an I/O pin. Each I/O cell can be

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

November 1998

2128e_02

1

Specifications ispLSI 2128E

Functional Block Diagram

Figure 1. ispLSI 2128E Functional Block Diagram

RESET

Input Bus

GOE 0

GOE 1

Output Routing Pool (ORP)

D6

D5

Output Routing Pool (ORP)

D2

D1

D3

Megablock

Generic Logic

IN 5

IN 4

D7

D0

D4

Blocks (GLBs)

I/O 95

I/O 94

I/O 93

I/O 92

C7

C6

I/O 0

I/O 1

I/O 2

I/O 3

A0

I/O 91

I/O 90

I/O 89

I/O 88

I/O 4

I/O 5

I/O 6

I/O 7

I/O 87

I/O 86

I/O 85

I/O 84

A1

C5

C4

I/O 8

I/O 9

I/O 10

I/O 11

I/O 83

I/O 82

I/O 81

I/O 80

A2

A3

Global

Routing

Pool

I/O 12

I/O 13

I/O 14

I/O 15

I/O 79

I/O 78

I/O 77

I/O 76

C3

C2

(GRP)

I/O 16

I/O 17

I/O 18

I/O 19

I/O 75

I/O 74

I/O 73

I/O 72

A4

A5

I/O 20

I/O 21

I/O 22

I/O 23

I/O 71

I/O 70

I/O 69

I/O 68

C1

C0

I/O 24

I/O 25

I/O 26

I/O 27

I/O 67

I/O 66

I/O 65

I/O 64

A6

A7

I/O 28

I/O 29

I/O 30

I/O 31

TCK/ IN 0

TMS/IN 1

B0

B1

B2

B5

B6

B7

B3

B4

Output Routing Pool (ORP)

Input Bus

BSCAN

0139/2128E

individually programmed to be a combinatorial input,

output or bi-directional I/O pin with 3-state control. The

signal levels are TTL compatible voltages and the output

drivers can source 4 mA or sink 8 mA. Each output can

be programmed independently for fast or slow output

slew rate to minimize overall output switching noise. By

connecting the VCCIO pins to a common 5V or 3.3V

power supply, I/O output levels can be matched to 5V or

3.3V compatible voltages. When connected to a 5V

supply, the I/O pins provide PCI-compatible output drive.

Clocks in the ispLSI 2128E device are selected using the

dedicatedclockpins. Threededicatedclockpins(Y0, Y1,

Y2) or an asynchronous clock can be selected on a GLB

basis. The asynchronous or Product Term clock can be

generated in any GLB for its own clock.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the

outputs of the ispLSI 2128E are individually program-

mable, either as a standard totem-pole output or an

open-drain output. The totem-pole output drives the

specified Voh and Vol levels, whereas the open-drain

output drives only the specified Vol. The Voh level on the

open-drain output depends on the external loading and

pull-up. This output configuration is controlled by a pro-

grammable fuse. The default configuration when the

device is in bulk erased state is totem-pole configuration.

The open-drain/totem-pole option is selectable through

the ispDesignEXPERT software tools.

Eight GLBs, 32 I/O cells, two dedicated inputs and two

ORPs are connected together to make a Megablock (see

Figure 1). The outputs of the eight GLBs are connected

to a set of 32 universal I/O cells by the two ORPs. Each

ispLSI 2128E device contains four Megablocks.

The GRP has as its inputs, the outputs from all of the

GLBsandallof theinputsfromthebi-directionalI/O cells.

All of these signals are made available to the inputs of the

GLBs. Delays through the GRP have been equalized to

minimize timing skew.

2

Specifications ispLSI 2128E

1

Absolute Maximum Ratings

Supply Voltage V .................................. -0.5 to +7.0V

cc

Input Voltage Applied........................ -2.5 to V +1.0V

CC

Off-State Output Voltage Applied ..... -2.5 to V +1.0V

CC

Storage Temperature................................ -65 to 150°C

Case Temp. with Power Applied .............. -55 to 125°C

Max. Junction Temp. (T ) with Power Applied ... 150°C

J

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional

operation of the device at these or at any other conditions above those indicated in the operational sections of this specification

is not implied (while programming, follow the programming specifications).

DC Recommended Operating Condition

SYMBOL

PARAMETER

MIN.

MAX.

UNITS

4.75

5.25

V

Supply Voltage: Logic Core, Input Buffers

T = 0°C to +70°C

A

VCC

5V

Supply Voltage: Output Drivers

3.3V

4.75

3.0

5.25

3.6

V

VCCIO

Input Low Voltage

Input High Voltage

0

0.8

V

IL

2.0

V +1

cc

VIH

Table 2-0005/2128E

Capacitance (T_A=25°C, f=1.0 MHz)

SYMBOL

PARAMETER

TYP

8

UNITS

TEST CONDITIONS

V_CC= 5.0V, V = 2.0V

Dedicated Input Capacitance

I/O Capacitance

pf

C₁

C₂

C₃

IN

8

V_CC= 5.0V, V_I/O= 2.0V

10

V_CC= 5.0V, V_Y= 2.0V

Clock Capacitance

Table 2-0006/2128E

Erase/Reprogram Specification

PARAMETER

MINIMUM

MAXIMUM

UNITS

Erase/Reprogram Cycles

10,000

–

Cycles

Table 2-0008/2128E

3

Specifications ispLSI 2128E

Switching Test Conditions

Input Pulse Levels

GND to 3.0V

1.5 ns

Figure 2. Test Load

Input Rise and Fall Time 10% to 90%

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

1.5V

+ 5V

1.5V

See Figure 2

R

Table 2-0003/2128E

1

2

3-state levels are measured 0.5V from

steady-state active level.

Device

Output

Test

Point

Output Load Conditions (see Figure 2)

TEST CONDITION

R1

470Ω

∞

R2

CL

R

C *

L

A

B

390Ω

35pF

Active High

Active Low

470Ω

*

C includes Test Fixture and Probe Capacitance.

L

Active High to Z

at V_OH-0.5V

∞

390Ω

5pF

0213A

C

Active Low to Z

at V_OL+0.5V

470Ω

390Ω

5pF

Table 2 - 0004A/2000

DC Electrical Characteristics

Over Recommended Operating Conditions

SYMBOL

PARAMETER

Output Low Voltage

Output High Voltage

CONDITION

I_OL= 8 mA

MIN.

–

TYP.³MAX. UNITS

–

0.4

–

V

VOL

I_OH= -4 mA

2.4

–

V

VOH

Input or I/O Low Leakage Current

0V ≤ V_IN≤ V_IL(Max.)

-10

10

µA

mA

I

IL

(V_CCIO- 0.2)V ≤ V_IN≤ V_CCIO

–

Input or I/O High Leakage Current

IH

V_CCIO≤ V_IN≤ 5.25V

–

10

-10

–

-250

-240

–

I

IL-PU

OS¹

0V ≤ V_IN≤ 2.0V

I/O Active Pull-Up Current

Output Short Circuit Current

–

V_CCIO= 5.0V or 3.3V, V_OUT= 0.5V

V_IL= 0.0V, V_IH= 3.0V

–

165

CC^3,4

Operating Power Supply Current

I

f_TOGGLE= 1 MHz

Table 2-0007/2128E

1. One output at a time for a maximum duration of one second. V_OUT= 0.5V was selected to avoid test

problems by tester ground degradation. Characterized but not 100% tested.

2. Meaured using eight 16-bit counters.

3. Typical values are at V_CC= 5V and T_A= 25°C.

4. Unused inputs held at 0.0V.

5. Maximum I_CCvaries widely with specific device configuration and operating frequency. Refer to the

Power Consumption section of this data sheet and the Thermal Management section of the Lattice Semiconductor

Data Book or CD-ROM to estimate maximum I_CC

.

4

Specifications ispLSI 2128E

External Timing Parameters

Over Recommended Operating Conditions

-180

-135

-100

TEST

COND.

2

PARAMETER

#

DESCRIPTION¹

UNITS

4

MIN. MAX. MIN. MAX.

MIN. MAX.

A

–

1

Data Prop Delay, 4PT Bypass, ORP Bypass

Data Prop Delay

–

5.0

7.5

–

7.5

10.0

–

ns

t

pd1

–

10.0

13.0

–

2

3

4

5

6

7

8

9

–

t

f

t

pd2

Clk Freq with Internal Feedback³

180

125

200

135

100

143

5.0

–

MHz

ns

max

100

77.0

100

6.5

–

1

Clk Freq with External Feedback

Clk Frequency, Max. Toggle

(

)

–

max (Ext.)

max (Tog.)

su1

–

tsu2 + tco1

–

GLB Reg Setup Time before Clk, 4 PT Bypass 4.0

–

A

–

GLB Reg Clk to Output Delay, ORP Bypass

GLB Reg Hold Time after Clk, 4 PT Bypass

GLB Reg Setup Time before Clk

–

0.0

5.0

–

3.0

–

4.0

–

ns

co1

5.0

–

0.0

6.0

–

ns

h1

0.0

8.0

–

ns

su2

–

10 GLB Reg Clk to Output Delay

11 GLB Reg Hold Time after Clk

12 External Reset Pin to Output Delay

13 External Reset Pulse Duration

14 Input to Output Enable

3.5

–

4.5

–

ns

co2

6.0

–

0.0

–

0.0

–

ns

h2

0.0

–

A

–

7.0

–

10.0

–

ns

r1

13.5

–

4.0

–

5.0

–

ns

rw1

6.5

–

B

C

B

C

–

10.0

5.0

–

12.0

7.0

–

ns

ptoeen

ptoedis

goeen

goedis

wh

15.0

9.0

–

15 Input to Output Disable

–

ns

–

16 Global OE Output Enable

–

ns

–

17 Global OE Output Disable

–

ns

–

18 External Synch Clk Pulse Duration, High

19 External Synch Clk Pulse Duration, Low

2.5

3.5

ns

5.0

–

ns

wl

–

Table 2-0030A/2128E

1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.

2. Refer to Timing Model in this data sheet for further details.

3. Standard 16-bit counter using GRP feedback.

4. Reference Switching Test Conditions section.

5

Specifications ispLSI 2128E

Internal Timing Parameters¹

Over Recommended Operating Conditions

-180

MIN. MAX. MIN. MAX.

-100

-135

2

PARAMETER

#

DESCRIPTION

UNITS

MIN. MAX.

Inputs

tio

tdin

–

0.5

2.2

20 Input Buffer Delay

–

0.5

1.1

–

0.5

1.7

ns

21 Dedicated Input Delay

GRP

–

1.7

22 GRP Delay

–

0.6

–

1.2

ns

tgrp

GLB

–

5.8

6.8

7.3

8.0

0.5

–

23 4 Product Term Bypass Path Delay (Combinatorial)

24 4 Product Term Bypass Path Delay (Registered)

25 1 Product Term/XOR Path Delay

–

1.9

2.9

3.9

0.0

–

3.7

4.2

5.2

0.5

–

ns

t4ptbpc

t4ptbpr

t1ptxor

t20ptxor

txoradj

tgbp

tgsu

tgh

tgco

tgro

–

26 20 Product Term/XOR Path Delay

27 XOR Adjacent Path Delay³

–

28 GLB Register Bypass Delay

–

1.2

4.0

–

29 GLB Register Setup Time before Clock

30 GLB Register Hold Time after Clock

31 GLB Register Clock to Output Delay

32 GLB Register Reset to Output Delay

33 GLB Product Term Reset to Register Delay

34 GLB Product Term Output Enable to I/O Cell Delay

35 GLB Product Term Clock Delay

0.7

3.3

–

0.7

4.3

–

0.3

1.3

6.1

8.6

0.3

0.6

4.8

5.9

0.3

1.1

6.0

6.9

–

tptre

–

tptoe

tptck

ORP

4.1 7.1

1.0 4.0

2.5 5.5

–

1.4

0.4

36 ORP Delay

–

0.9

0.4

–

1.0

0.5

ns

torp

37 ORP Bypass Delay

torpbp

Outputs

tob

tsl

toen

–

38 Output Buffer Delay

–

1.6

1.5

3.4

3.6

1.6

10.0

4.2

ns

1.6

1.5

3.0

2.0

39 Output Slew Limited Delay Adder

40 I/O Cell OE to Output Enabled

41 I/O Cell OE to Output Disabled

42 Global Output Enable

4.2

todis

tgoe

4.8

Clocks

2.7

0.7

0.9

1.6 1.6

1.8 1.8

2.7

43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)

44 Clock Delay, Y1 or Y2 to Global GLB Clock Line

ns

0.7

0.9

tgy0

tgy1/2

Global Reset

tgr

–

45 Global Reset to GLB

–

6.3

9.2

ns

4.4

Table 2-0036A/2128E

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

6

Specifications ispLSI 2128E

ispLSI 2128E Timing Model

I/O Cell

GRP

GLB

ORP

I/O Cell

Feedback

Comb 4 PT Bypass #23

Ded. In

#21

I/O Delay

#20

GRP

#22

Reg 4 PT Bypass

GLB Reg Bypass

#28

ORP Bypass

#37

#38,

#39

I/O Pin

(Input)

#24

(Output)

20 PT

XOR Delays

GLB Reg

Delay

ORP

Delay

D

Q

#36

#25 - 27

RST

#45

#29 - 32

Reset

Control

PTs

RE

OE

CK

#33 - 35

#40, 41

#43, 44

#42

Y0,1,2

GOE0, 1

0491/2128E

Derivations of tsu, th and tco from the Product Term Clock

tsu

= Logic + Reg su - Clock (min)

= ( io + grp + 20ptxor) + ( gsu) - (tio + tgrp + tptck(min))

t

= (#20 + #22 + #26) + (#29) - (#20 + #22 + #35)

3.6 = (0.5 + 0.6 + 3.9) + (0.7) - (0.5 + 0.6 + 1.0)

th

= Clock (max) + Reg h - Logic

= (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)

= (#20 + #22 + #35) + (#30) - (#20 + #22 + #26)

= (0.5 + 0.6 + 4.0) + (3.3) - (0.5 + 0.6 + 3.9)

3.4

7.9

tco

= Clock (max) + Reg co + Output

= (tio + tgrp + tptck(max)) + (tgco) + (torp + tob)

= (#20 + #22 + #35) + (#31) + (#36 + #38)

= (0.5 + 0.6 + 4.0) + (0.3) + (0.9 + 0.6)

Table 2-0042/2128E

Note: Calculations are based upon timing specifications for the ispLSI 2128E-180L.

7

Specifications ispLSI 2128E

Power Consumption

Figure 3 shows the relationship between power and

operating speed.

Power consumption in the ispLSI 2128E device depends

on two primary factors: the speed at which the device is

operating and the number of Product Terms used.

Figure 3. Typical Device Power Consumption vs fmax

500

450

400

350

300

250

200

ispLSI 2128E

150

100

0

20

40 60

80 100 120 140 160 180

max (MHz)

f

Notes: Configuration of eight 16-bit counters

Typical current at 5V, 25° C

I

can be estimated for the ispLSI 2128E using the following equation:

CC

=

27 + (# of PTs 0.55) + (# of nets max freq 0.0058)

* * *

CC

Where:

# of PTs = Number of Product Terms used in design

# of nets = Number of Signals used in device

Max freq = Highest Clock Frequency to the device (in MHz)

The I

estimate is based on typical conditions (V

= 5.0V, room temperature) and an assumption of two GLB loads

CC

on average exists. These values are for estimates only. Since the value of I

and the program in the device, the actual I

is sensitive to operating conditions

CC

should be verified.

CC

0127/2128E

8

Specifications ispLSI 2128E

Pin Description

TQFP PIN NUMBERS

NAME

DESCRIPTION

27, 28, 31, 32, 33,

35, 36, 37, 38, 39,

41, 42, 43, 44, 45,

46, 47, 48, 50, 51,

52, 53, 55, 57, 58,

59, 60, 61, 62, 63,

65, 66, 67, 68, 70,

71, 72, 73, 75, 76,

77, 79, 80, 81, 82,

83, 85, 86, 87, 88,

90, 91, 92, 93, 94,

95, 96, 97, 99, 101,

102, 103, 104, 105, 115,

116, 119, 120, 121, 123,

124, 125, 126, 127, 129,

130, 131, 132, 133, 134,

135, 136, 138, 139, 140,

141, 143, 145, 146, 147,

148, 149, 150, 151, 153,

154, 155, 156, 158, 159,

160, 161, 163, 164, 165,

167, 168, 169, 170, 171,

173, 174, 175, 176, 2,

Input/Output Pins - These are the general purpose I/O pins used by the logic array.

I/O 0 - I/O 4

I/O 5 - I/O 9

I/O 10 - I/O 14

I/O 15 - I/O 19

I/O 20 - I/O 24

I/O 25 - I/O 29

I/O 30 - I/O 34

I/O 35 - I/O 39

I/O 40 - I/O 44

I/O 45 - I/O 49

I/O 50 - I/O 54

I/O 55 - I/O 59

I/O 60 - I/O 64

I/O 65 - I/O 69

I/O 70 - I/O 74

I/O 75 - I/O 79

I/O 80 - I/O 84

I/O 85 - I/O 89

I/O 90 - I/O 94

I/O 95 - I/O 99

I/O 100 - I/O 104

I/O 105 - I/O 109

I/O 110 - I/O 114

I/O 115 - I/O 119

I/O 120 - I/O 124

I/O 125 - I/O 127

3, 4,

8, 9,

5,

6,

7,

12, 14, 15,

16, 17, 18

106, 107, 112, 113

110, 109,

IN 2 - IN 5

Dedicated input pins to the device.

GOE 0, GOE 1

Global Output Enable input pins.

22

Active Low (0) Reset pin which resets all of the GLB registers in the device.

RESET

19, 21, 111

Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all

the GLBs on the device.

Y0, Y1, Y2

23

24

Input - Dedicated in-system programming enable input pin. This pin is brought low to

enable the programming mode. The TMS, TDI, TDO and TCK options become active.

BSCAN

TDI/IN 7¹

Input - This pin performs two functions. When BSCAN is logic low, it functions as an input

pin to load programming data into the device. SDI is also used as one of the two control

pins for the ISP state machine. When BSCAN is high, it functions as a dedicated input pin.

TCK/IN 0¹

TMS/IN 1¹

Input - This pin performs two functions. When BSCAN is logic low, it functions as a clock

pin for the Serial Shift Register. When BSCAN is high, it functions as a dedicated input pin.

25

26

Input - This pin performs two functions. When BSCAN is logic low, it functions as pin to

control the operation of the programming state machine. When BSCAN is high, it

functions as a dedicated input pin.

TDO/IN 6¹

GND

Output/Input - This pin performs two functions. When BSCAN is logic low, it functions as

the pin to read the isp data. When BSCAN is high, it functions as a dedicated input pin.

114

1, 11, 29, 40, 49,

64, 69, 84, 89, 108,

117, 128, 137, 152, 157,

172

Ground (GND)

13, 34, 56, 78, 100,

122, 144, 166

VCC

V_CC

10, 30, 54, 74, 98,

118, 142, 162

Supply voltage for output drivers, 5V or 3.3V. All VCCIO pins must be connected to the

same voltage level.

VCCIO

20

No Connect

NC

Table 2-0002/2128E

1. Pins have dual function capability.

9

Specifications ispLSI 2128E

Pin Configuration

ispLSI 2128E 176-Pin TQFP Pinout Diagram

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

I/O 77

I/O 76

I/O 75

I/O 74

GND

I/O 73

I/O 72

I/O 71

I/O 70

I/O 69

VCC

I/O 68

I/O 67

I/O 66

VCCIO

GND

I/O 65

I/O 64

TDO/IN 6²

IN 5

1

2

3

4

5

6

7

8

GND

I/O 114

I/O 115

I/O 116

I/O 117

I/O 118

I/O 119

I/O 120

I/O 121

VCCIO

GND

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

I/O 122

VCC

I/O 123

I/O 124

I/O 125

I/O 126

I/O 127

Y0

¹NC

Y1

IN 4

Y2

GOE 0

GOE 1

GND

ispLSI 2128E

RESET

BSCAN

²TDI/IN 7

²TCK/IN 0

²TMS/IN 1

I/O 0

I/O 1

GND

VCCIO

I/O 2

I/O 3

Top View

IN 3

IN 2

I/O 63

I/O 62

I/O 61

I/O 60

I/O 59

VCC

I/O 58

VCCIO

I/O 57

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

GND

I/O 4

VCC

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

GND

I/O 10

I/O 11

I/O 12

I/O 13

98

97

96

95

94

93

92

91

90

89

176-TQFP/2128E

1. NC pins are not to be connected to any active signals, VCC or GND.

2. Pins have dual function capability.

10

Specifications ispLSI 2128E

Part Number Description

ispLSI 2128E– XXX X XXXX X

Device Family

Grade

Blank = Commercial

Device Number

Speed

Package

T176 = TQFP

Power

180 = 180 MHz

135 = 135 MHz

100 = 100 MHz

f

max

L = Low

0212/2128E

ispLSI 2128E Ordering Information

FAMILY

ispLSI

fmax (MHz)

180

tpd (ns)

5.0

ORDERING NUMBER

PACKAGE

176-Pin TQFP

ispLSI 2128E-180LT176

ispLSI 2128E-135LT176

ispLSI 2128E-100LT176

135

7.5

100

10.0

Table 2-0041/2128E

11


型号：	ISPLSI2128E-100LT176
厂家：	LATTICE SEMICONDUCTOR
描述：	In-System Programmable SuperFAST⑩ High Density PLD 在系统可编程SuperFAST⑩高密度PLD 可编程逻辑器件输入元件时钟
文件：	总11页 (文件大小：144K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISPLSI2128E-100LT176 [LATTICE]

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